LoongArchISelLowering.cpp File Reference

#include "LoongArchISelLowering.h"
#include "LoongArch.h"
#include "LoongArchMachineFunctionInfo.h"
#include "LoongArchRegisterInfo.h"
#include "LoongArchSubtarget.h"
#include "LoongArchTargetMachine.h"
#include "MCTargetDesc/LoongArchBaseInfo.h"
#include "MCTargetDesc/LoongArchMCTargetDesc.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/RuntimeLibcallUtil.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicsLoongArch.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "LoongArchGenAsmMatcher.inc"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "loongarch-isel-lowering"
#define	IOCSRRD_CASE(NAME, NODE)
#define	IOCSRWR_CASE(NAME, NODE)
#define	ASRT_LE_GT_CASE(NAME)
#define	CRC_CASE_EXT_BINARYOP(NAME, NODE)
#define	CRC_CASE_EXT_UNARYOP(NAME, NODE)
#define	CSR_CASE(ID)
#define	IOCSRRD_CASE(NAME, NODE)
#define	NODE_NAME_CASE(node)
#define	GET_REGISTER_MATCHER

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
template<typename ValType >
static bool	fitsRegularPattern (typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)
	Determine whether a range fits a regular pattern of values.
static SDValue	lowerVECTOR_SHUFFLE_VREPLVEI (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VREPLVEI (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VSHUF4I (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VSHUF4I (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VPACKEV (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VPACKEV (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VPACKOD (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VPACKOD (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VILVH (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VILVH (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VILVL (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VILVL (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VPICKEV (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VPICKEV (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VPICKOD (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VPICKOD (if possible).
static SDValue	lowerVECTOR_SHUFFLE_VSHUF (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into VSHUF.
static SDValue	lower128BitShuffle (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Dispatching routine to lower various 128-bit LoongArch vector shuffles.
static SDValue	lowerVECTOR_SHUFFLE_XVREPLVEI (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVREPLVEI (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVSHUF4I (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVSHUF4I (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVPACKEV (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVPACKEV (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVPACKOD (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVPACKOD (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVILVH (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVILVH (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVILVL (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVILVL (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVPICKEV (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVPICKEV (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVPICKOD (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVPICKOD (if possible).
static SDValue	lowerVECTOR_SHUFFLE_XVSHUF (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Lower VECTOR_SHUFFLE into XVSHUF (if possible).
static void	canonicalizeShuffleVectorByLane (const SDLoc &DL, MutableArrayRef< int > Mask, MVT VT, SDValue &V1, SDValue &V2, SelectionDAG &DAG)
	Shuffle vectors by lane to generate more optimized instructions.
static SDValue	lower256BitShuffle (const SDLoc &DL, ArrayRef< int > Mask, MVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG)
	Dispatching routine to lower various 256-bit LoongArch vector shuffles.
static bool	isConstantOrUndef (const SDValue Op)
static bool	isConstantOrUndefBUILD_VECTOR (const BuildVectorSDNode *Op)
static SDValue	getTargetNode (GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (BlockAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (ConstantPoolSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (JumpTableSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
template<unsigned N>
static SDValue	checkIntrinsicImmArg (SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
static SDValue	emitIntrinsicWithChainErrorMessage (SDValue Op, StringRef ErrorMsg, SelectionDAG &DAG)
static SDValue	emitIntrinsicErrorMessage (SDValue Op, StringRef ErrorMsg, SelectionDAG &DAG)
static LoongArchISD::NodeType	getLoongArchWOpcode (unsigned Opcode)
static SDValue	customLegalizeToWOp (SDNode *N, SelectionDAG &DAG, int NumOp, unsigned ExtOpc=ISD::ANY_EXTEND)
static SDValue	customLegalizeToWOpWithSExt (SDNode *N, SelectionDAG &DAG)
static void	emitErrorAndReplaceIntrinsicResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, StringRef ErrorMsg, bool WithChain=true)
template<unsigned N>
static void	replaceVPICKVE2GRResults (SDNode *Node, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget, unsigned ResOp)
static void	replaceVecCondBranchResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget, unsigned ResOp)
static void	replaceINTRINSIC_WO_CHAINResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
static SDValue	performANDCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performSRLCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performORCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static bool	checkValueWidth (SDValue V, ISD::LoadExtType &ExtType)
static SDValue	performSETCCCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performBITREV_WCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
template<unsigned N>
static SDValue	legalizeIntrinsicImmArg (SDNode *Node, unsigned ImmOp, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget, bool IsSigned=false)
template<unsigned N>
static SDValue	lowerVectorSplatImm (SDNode *Node, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
static SDValue	truncateVecElts (SDNode *Node, SelectionDAG &DAG)
static SDValue	lowerVectorBitClear (SDNode *Node, SelectionDAG &DAG)
template<unsigned N>
static SDValue	lowerVectorBitClearImm (SDNode *Node, SelectionDAG &DAG)
template<unsigned N>
static SDValue	lowerVectorBitSetImm (SDNode *Node, SelectionDAG &DAG)
template<unsigned N>
static SDValue	lowerVectorBitRevImm (SDNode *Node, SelectionDAG &DAG)
static SDValue	performINTRINSIC_WO_CHAINCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static MachineBasicBlock *	insertDivByZeroTrap (MachineInstr &MI, MachineBasicBlock *MBB)
static MachineBasicBlock *	emitVecCondBranchPseudo (MachineInstr &MI, MachineBasicBlock *BB, const LoongArchSubtarget &Subtarget)
static MachineBasicBlock *	emitPseudoXVINSGR2VR (MachineInstr &MI, MachineBasicBlock *BB, const LoongArchSubtarget &Subtarget)
static bool	CC_LoongArchAssign2GRLen (unsigned GRLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
static bool	CC_LoongArch (const DataLayout &DL, LoongArchABI::ABI ABI, unsigned ValNo, MVT ValVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy)
static SDValue	convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static SDValue	unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const ISD::InputArg &In, const LoongArchTargetLowering &TLI)
static SDValue	unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static SDValue	convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static bool	CC_LoongArch_GHC (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static Align	getPrefTypeAlign (EVT VT, SelectionDAG &DAG)
static Intrinsic::ID	getIntrinsicForMaskedAtomicRMWBinOp (unsigned GRLen, AtomicRMWInst::BinOp BinOp)

Variables
static cl::opt< bool >	ZeroDivCheck ("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false))
const MCPhysReg	ArgGPRs []
const MCPhysReg	ArgFPR32s []
const MCPhysReg	ArgFPR64s []
const MCPhysReg	ArgVRs []
const MCPhysReg	ArgXRs []

Macro Definition Documentation

ASRT_LE_GT_CASE

#define ASRT_LE_GT_CASE

(

NAME

)

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    return !Subtarget.is64Bit()                                                \
               ? emitIntrinsicErrorMessage(Op, ErrorMsgReqLA64, DAG)           \
               : Op;                                                           \
  }

CRC_CASE_EXT_BINARYOP

#define CRC_CASE_EXT_BINARYOP	(		NAME,
			NODE
	)

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    SDValue NODE = DAG.getNode(                                                \
        LoongArchISD::NODE, DL, {MVT::i64, MVT::Other},                        \
        {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),               \
         DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3))});       \
    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NODE.getValue(0)));   \
    Results.push_back(NODE.getValue(1));                                       \
    break;                                                                     \
  }

CRC_CASE_EXT_UNARYOP

#define CRC_CASE_EXT_UNARYOP	(		NAME,
			NODE
	)

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    SDValue NODE = DAG.getNode(                                                \
        LoongArchISD::NODE, DL, {MVT::i64, MVT::Other},                        \
        {Chain, Op2,                                                           \
         DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3))});       \
    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NODE.getValue(0)));   \
    Results.push_back(NODE.getValue(1));                                       \
    break;                                                                     \
  }

CSR_CASE

#define CSR_CASE

(

ID

)

Value:

  case Intrinsic::loongarch_##ID: {                                            \
    if (!Subtarget.is64Bit())                                                  \
      emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgReqLA64);   \
    break;                                                                     \
  }

DEBUG_TYPE

#define DEBUG_TYPE   "loongarch-isel-lowering"

Definition at line 37 of file LoongArchISelLowering.cpp.

GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 5992 of file LoongArchISelLowering.cpp.

IOCSRRD_CASE [1/2]

#define IOCSRRD_CASE	(		NAME,
			NODE
	)

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    return DAG.getNode(LoongArchISD::NODE, DL, {GRLenVT, MVT::Other},          \
                       {Chain, Op.getOperand(2)});                             \
  }

IOCSRRD_CASE [2/2]

#define IOCSRRD_CASE	(		NAME,
			NODE
	)

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    SDValue IOCSRRDResults =                                                   \
        DAG.getNode(LoongArchISD::NODE, DL, {MVT::i64, MVT::Other},            \
                    {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2)}); \
    Results.push_back(                                                         \
        DAG.getNode(ISD::TRUNCATE, DL, VT, IOCSRRDResults.getValue(0)));       \
    Results.push_back(IOCSRRDResults.getValue(1));                             \
    break;                                                                     \
  }

IOCSRWR_CASE

#define IOCSRWR_CASE	(		NAME,
			NODE
	)

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    SDValue Op3 = Op.getOperand(3);                                            \
    return Subtarget.is64Bit()                                                 \
               ? DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Chain,        \
                             DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),  \
                             DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op3))  \
               : DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Chain, Op2,   \
                             Op3);                                             \
  }

NODE_NAME_CASE

#define NODE_NAME_CASE

(

node

)

Value:

  case LoongArchISD::node:                                                     \
    return "LoongArchISD::" #node;

Function Documentation

canonicalizeShuffleVectorByLane()

static void canonicalizeShuffleVectorByLane ( const SDLoc &  DL, MutableArrayRef< int >  Mask, MVT  VT, SDValue &  V1, SDValue &  V2, SelectionDAG &  DAG  )

static

Shuffle vectors by lane to generate more optimized instructions.

256-bit shuffles are always considered as 2-lane 128-bit shuffles.

Therefore, except for the following four cases, other cases are regarded as cross-lane shuffles, where optimization is relatively limited.

• Shuffle high, low lanes of two inputs vector <0, 1, 2, 3> + <4, 5, 6, 7> — <0, 5, 3, 6>
• Shuffle low, high lanes of two inputs vector <0, 1, 2, 3> + <4, 5, 6, 7> — <3, 6, 0, 5>
• Shuffle low, low lanes of two inputs vector <0, 1, 2, 3> + <4, 5, 6, 7> — <3, 6, 3, 6>
• Shuffle high, high lanes of two inputs vector <0, 1, 2, 3> + <4, 5, 6, 7> — <0, 5, 0, 5>

The first case is the closest to LoongArch instructions and the other cases need to be converted to it for processing.

This function may modify V1, V2 and Mask

Definition at line 1151 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::None, and llvm::LoongArchISD::XVPERMI.

Referenced by lower256BitShuffle().

CC_LoongArch()

static bool CC_LoongArch ( const DataLayout &  DL, LoongArchABI::ABI  ABI, unsigned  ValNo, MVT  ValVT, CCValAssign::LocInfo  LocInfo, ISD::ArgFlagsTy  ArgFlags, CCState &  State, bool  IsFixed, bool  IsRet, Type *  OrigTy  )

static

Definition at line 4715 of file LoongArchISelLowering.cpp.

References llvm::LoongArchABI::ABI_ILP32D, llvm::LoongArchABI::ABI_ILP32F, llvm::LoongArchABI::ABI_ILP32S, llvm::LoongArchABI::ABI_LP64D, llvm::LoongArchABI::ABI_LP64F, llvm::LoongArchABI::ABI_LP64S, llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), ArgFPR32s, ArgFPR64s, ArgGPRs, ArgVRs, ArgXRs, assert(), llvm::CCValAssign::BCvt, CC_LoongArchAssign2GRLen(), llvm::SmallVectorImpl< T >::clear(), DL, llvm::SmallVectorBase< Size_T >::empty(), llvm::CCValAssign::Full, llvm::CCState::getFirstUnallocated(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getPending(), llvm::CCState::getPendingArgFlags(), llvm::CCState::getPendingLocs(), llvm::CCValAssign::getReg(), llvm::CCValAssign::Indirect, llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::isFloatingPoint(), llvm::MVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::report_fatal_error(), and llvm::SmallVectorBase< Size_T >::size().

Referenced by llvm::LoongArchTargetLowering::CanLowerReturn(), llvm::LoongArchTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerFormalArguments(), and llvm::LoongArchTargetLowering::LowerReturn().

CC_LoongArch_GHC()

static bool CC_LoongArch_GHC ( unsigned  ValNo, MVT  ValVT, MVT  LocVT, CCValAssign::LocInfo  LocInfo, ISD::ArgFlagsTy  ArgFlags, CCState &  State  )

static

Definition at line 5004 of file LoongArchISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCValAssign::getReg(), and llvm::report_fatal_error().

Referenced by llvm::LoongArchTargetLowering::LowerCall(), and llvm::LoongArchTargetLowering::LowerFormalArguments().

CC_LoongArchAssign2GRLen()

static bool CC_LoongArchAssign2GRLen ( unsigned  GRLen, CCState &  State, CCValAssign  VA1, ISD::ArgFlagsTy  ArgFlags1, unsigned  ValNo2, MVT  ValVT2, MVT  LocVT2, ISD::ArgFlagsTy  ArgFlags2  )

static

Definition at line 4679 of file LoongArchISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), ArgGPRs, llvm::CCValAssign::Full, llvm::CCValAssign::getLocVT(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getReg(), llvm::CCValAssign::getValNo(), and llvm::CCValAssign::getValVT().

Referenced by CC_LoongArch().

checkIntrinsicImmArg()

template<unsigned N>

static SDValue checkIntrinsicImmArg ( SDValue  Op, unsigned  ImmOp, SelectionDAG &  DAG, bool  IsSigned = false  )

static

Definition at line 1933 of file LoongArchISelLowering.cpp.

References llvm::LLVMContext::emitError(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), and llvm::ISD::UNDEF.

checkValueWidth()

static bool checkValueWidth ( SDValue  V, ISD::LoadExtType &  ExtType  )

static

Definition at line 3449 of file LoongArchISelLowering.cpp.

References llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::LoadSDNode::getExtensionType(), llvm::MemSDNode::getMemoryVT(), llvm::VTSDNode::getVT(), llvm::ISD::LOAD, llvm::ISD::NON_EXTLOAD, llvm::ISD::SEXTLOAD, and llvm::ISD::ZEXTLOAD.

convertLocVTToValVT()

static SDValue convertLocVTToValVT ( SelectionDAG &  DAG, SDValue  Val, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 4909 of file LoongArchISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm_unreachable, and llvm::LoongArchISD::MOVGR2FR_W_LA64.

convertValVTToLocVT()

static SDValue convertValVTToLocVT ( SelectionDAG &  DAG, SDValue  Val, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 4985 of file LoongArchISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm_unreachable, and llvm::LoongArchISD::MOVFR2GR_S_LA64.

customLegalizeToWOp()

static SDValue customLegalizeToWOp ( SDNode *  N, SelectionDAG &  DAG, int  NumOp, unsigned  ExtOpc = ISD::ANY_EXTEND  )

static

Definition at line 2646 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), getLoongArchWOpcode(), llvm::SelectionDAG::getNode(), llvm_unreachable, N, llvm::ISD::ROTL, llvm::ISD::SUB, and llvm::ISD::TRUNCATE.

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

customLegalizeToWOpWithSExt()

static SDValue customLegalizeToWOpWithSExt ( SDNode *  N, SelectionDAG &  DAG  )

static

Definition at line 2680 of file LoongArchISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), N, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::TRUNCATE.

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

emitErrorAndReplaceIntrinsicResults()

static void emitErrorAndReplaceIntrinsicResults ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, StringRef  ErrorMsg, bool  WithChain = true  )

static

Definition at line 2692 of file LoongArchISelLowering.cpp.

References llvm::LLVMContext::emitError(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getUNDEF(), N, and Results.

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults(), and replaceVPICKVE2GRResults().

emitIntrinsicErrorMessage()

static SDValue emitIntrinsicErrorMessage ( SDValue  Op, StringRef  ErrorMsg, SelectionDAG &  DAG  )

static

Definition at line 2350 of file LoongArchISelLowering.cpp.

References llvm::LLVMContext::emitError(), and llvm::SelectionDAG::getContext().

emitIntrinsicWithChainErrorMessage()

static SDValue emitIntrinsicWithChainErrorMessage ( SDValue  Op, StringRef  ErrorMsg, SelectionDAG &  DAG  )

static

Definition at line 2227 of file LoongArchISelLowering.cpp.

References llvm::LLVMContext::emitError(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getMergeValues(), and llvm::SelectionDAG::getUNDEF().

emitPseudoXVINSGR2VR()

static MachineBasicBlock * emitPseudoXVINSGR2VR ( MachineInstr &  MI, MachineBasicBlock *  BB, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 4426 of file LoongArchISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::LoongArchSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), Idx, llvm_unreachable, MI, MRI, and TII.

emitVecCondBranchPseudo()

static MachineBasicBlock * emitVecCondBranchPseudo ( MachineInstr &  MI, MachineBasicBlock *  BB, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 4301 of file LoongArchISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::LoongArchSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm_unreachable, MI, MRI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

fitsRegularPattern()

template<typename ValType >

static bool fitsRegularPattern ( typename SmallVectorImpl< ValType >::const_iterator  Begin, unsigned  CheckStride, typename SmallVectorImpl< ValType >::const_iterator  End, ValType  ExpectedIndex, unsigned  ExpectedIndexStride  )

static

Determine whether a range fits a regular pattern of values.

This function accounts for the possibility of jumping over the End iterator.

Definition at line 435 of file LoongArchISelLowering.cpp.

References End, and I.

getIntrinsicForMaskedAtomicRMWBinOp()

static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp ( unsigned  GRLen, AtomicRMWInst::BinOp  BinOp  )

static

Definition at line 5665 of file LoongArchISelLowering.cpp.

References llvm::AtomicRMWInst::Add, llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.

Referenced by llvm::LoongArchTargetLowering::emitMaskedAtomicRMWIntrinsic(), and llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic().

getLoongArchWOpcode()

static LoongArchISD::NodeType getLoongArchWOpcode ( unsigned  Opcode )

static

Definition at line 2617 of file LoongArchISelLowering.cpp.

References llvm::LoongArchISD::CLZ_W, llvm::ISD::CTLZ, llvm::ISD::CTTZ, llvm::LoongArchISD::CTZ_W, llvm::LoongArchISD::DIV_WU, llvm_unreachable, llvm::LoongArchISD::MOD_WU, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::LoongArchISD::ROTR_W, llvm::ISD::SHL, llvm::LoongArchISD::SLL_W, llvm::ISD::SRA, llvm::LoongArchISD::SRA_W, llvm::ISD::SRL, llvm::LoongArchISD::SRL_W, llvm::ISD::UDIV, and llvm::ISD::UREM.

Referenced by customLegalizeToWOp().

getPrefTypeAlign()

static Align getPrefTypeAlign ( EVT  VT, SelectionDAG &  DAG  )

static

Definition at line 5256 of file LoongArchISelLowering.cpp.

References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), and llvm::EVT::getTypeForEVT().

Referenced by llvm::SelectionDAG::CreateStackTemporary(), llvm::LoongArchTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerCall().

getTargetNode() [1/4]

static SDValue getTargetNode ( BlockAddressSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 1674 of file LoongArchISelLowering.cpp.

References llvm::SelectionDAG::getTargetBlockAddress(), and N.

getTargetNode() [2/4]

static SDValue getTargetNode ( ConstantPoolSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 1680 of file LoongArchISelLowering.cpp.

References llvm::SelectionDAG::getTargetConstantPool(), and N.

getTargetNode() [3/4]

static SDValue getTargetNode ( GlobalAddressSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 1669 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.

getTargetNode() [4/4]

static SDValue getTargetNode ( JumpTableSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 1686 of file LoongArchISelLowering.cpp.

References llvm::SelectionDAG::getTargetJumpTable(), and N.

insertDivByZeroTrap()

static MachineBasicBlock * insertDivByZeroTrap ( MachineInstr &  MI, MachineBasicBlock *  MBB  )

static

Definition at line 4251 of file LoongArchISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getBasicBlock(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), llvm::MachineOperand::isKill(), MBB, MI, llvm::MachineOperand::setIsKill(), TII, and ZeroDivCheck.

Referenced by llvm::MipsTargetLowering::EmitInstrWithCustomInserter().

isConstantOrUndef()

static bool isConstantOrUndef ( const SDValue  Op )

static

Definition at line 1354 of file LoongArchISelLowering.cpp.

Referenced by isConstantOrUndefBUILD_VECTOR(), isVMerge(), llvm::PPC::isVPKUDUMShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), and llvm::PPC::isVSLDOIShuffleMask().

isConstantOrUndefBUILD_VECTOR()

static bool isConstantOrUndefBUILD_VECTOR ( const BuildVectorSDNode *  Op )

static

Definition at line 1364 of file LoongArchISelLowering.cpp.

References llvm::DWARFExpression::Operation::getNumOperands(), and isConstantOrUndef().

legalizeIntrinsicImmArg()

template<unsigned N>

static SDValue legalizeIntrinsicImmArg ( SDNode *  Node, unsigned  ImmOp, SelectionDAG &  DAG, const LoongArchSubtarget &  Subtarget, bool  IsSigned = false  )

static

Definition at line 3628 of file LoongArchISelLowering.cpp.

References DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), and llvm::ISD::UNDEF.

lower128BitShuffle()

static SDValue lower128BitShuffle ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Dispatching routine to lower various 128-bit LoongArch vector shuffles.

This routine breaks down the specific type of 128-bit shuffle and dispatches to the lowering routines accordingly.

Definition at line 829 of file LoongArchISelLowering.cpp.

References assert(), DL, llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorNumElements(), lowerVECTOR_SHUFFLE_VILVH(), lowerVECTOR_SHUFFLE_VILVL(), lowerVECTOR_SHUFFLE_VPACKEV(), lowerVECTOR_SHUFFLE_VPACKOD(), lowerVECTOR_SHUFFLE_VPICKEV(), lowerVECTOR_SHUFFLE_VPICKOD(), lowerVECTOR_SHUFFLE_VREPLVEI(), lowerVECTOR_SHUFFLE_VSHUF(), lowerVECTOR_SHUFFLE_VSHUF4I(), and llvm::MVT::SimpleTy.

Referenced by lowerVECTOR_SHUFFLE().

lower256BitShuffle()

static SDValue lower256BitShuffle ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Dispatching routine to lower various 256-bit LoongArch vector shuffles.

This routine breaks down the specific type of 256-bit shuffle and dispatches to the lowering routines accordingly.

Definition at line 1254 of file LoongArchISelLowering.cpp.

References assert(), canonicalizeShuffleVectorByLane(), DL, llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorNumElements(), lowerVECTOR_SHUFFLE_XVILVH(), lowerVECTOR_SHUFFLE_XVILVL(), lowerVECTOR_SHUFFLE_XVPACKEV(), lowerVECTOR_SHUFFLE_XVPACKOD(), lowerVECTOR_SHUFFLE_XVPICKEV(), lowerVECTOR_SHUFFLE_XVPICKOD(), lowerVECTOR_SHUFFLE_XVREPLVEI(), lowerVECTOR_SHUFFLE_XVSHUF(), lowerVECTOR_SHUFFLE_XVSHUF4I(), and llvm::MVT::SimpleTy.

Referenced by lowerVECTOR_SHUFFLE().

lowerVECTOR_SHUFFLE_VILVH()

static SDValue lowerVECTOR_SHUFFLE_VILVH ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into VILVH (if possible).

VILVH interleaves consecutive elements from the left (highest-indexed) half of each vector.

It is possible to lower into VILVH when the mask consists of two of the following forms interleaved: <x, x+1, x+2, ...> <n+x, n+x+1, n+x+2, ...> where n is the number of elements in the vector and x is half n. For example: <x, x, x+1, x+1, x+2, x+2, ...> <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.

Definition at line 649 of file LoongArchISelLowering.cpp.

References DL, End, llvm::SelectionDAG::getNode(), and llvm::LoongArchISD::VILVH.

Referenced by lower128BitShuffle().

lowerVECTOR_SHUFFLE_VILVL()

static SDValue lowerVECTOR_SHUFFLE_VILVL ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into VILVL (if possible).

VILVL interleaves consecutive elements from the right (lowest-indexed) half of each vector.

It is possible to lower into VILVL when the mask consists of two of the following forms interleaved: <0, 1, 2, ...> <n, n+1, n+2, ...> where n is the number of elements in the vector. For example: <0, 0, 1, 1, 2, 2, ...> <0, n, 1, n+1, 2, n+2, ...>

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.

Definition at line 692 of file LoongArchISelLowering.cpp.

References DL, End, llvm::SelectionDAG::getNode(), and llvm::LoongArchISD::VILVL.

Referenced by lower128BitShuffle().

lowerVECTOR_SHUFFLE_VPACKEV()

static SDValue lowerVECTOR_SHUFFLE_VPACKEV ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into VPACKEV (if possible).

VPACKEV interleaves the even elements from each vector.

It is possible to lower into VPACKEV when the mask consists of two of the following forms interleaved: <0, 2, 4, ...> <n, n+2, n+4, ...> where n is the number of elements in the vector. For example: <0, 0, 2, 2, 4, 4, ...> <0, n, 2, n+2, 4, n+4, ...>

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.

Definition at line 568 of file LoongArchISelLowering.cpp.

References DL, End, llvm::SelectionDAG::getNode(), and llvm::LoongArchISD::VPACKEV.

Referenced by lower128BitShuffle(), and lowerVECTOR_SHUFFLE_XVPACKEV().

lowerVECTOR_SHUFFLE_VPACKOD()

static SDValue lowerVECTOR_SHUFFLE_VPACKOD ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into VPACKOD (if possible).

VPACKOD interleaves the odd elements from each vector.

It is possible to lower into VPACKOD when the mask consists of two of the following forms interleaved: <1, 3, 5, ...> <n+1, n+3, n+5, ...> where n is the number of elements in the vector. For example: <1, 1, 3, 3, 5, 5, ...> <1, n+1, 3, n+3, 5, n+5, ...>

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.

Definition at line 608 of file LoongArchISelLowering.cpp.

References DL, End, llvm::SelectionDAG::getNode(), and llvm::LoongArchISD::VPACKOD.

Referenced by lower128BitShuffle(), and lowerVECTOR_SHUFFLE_XVPACKOD().

lowerVECTOR_SHUFFLE_VPICKEV()

static SDValue lowerVECTOR_SHUFFLE_VPICKEV ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into VPICKEV (if possible).

VPICKEV copies the even elements of each vector into the result vector.

It is possible to lower into VPICKEV when the mask consists of two of the following forms concatenated: <0, 2, 4, ...> <n, n+2, n+4, ...> where n is the number of elements in the vector. For example: <0, 2, 4, ..., 0, 2, 4, ...> <0, 2, 4, ..., n, n+2, n+4, ...>

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.

Definition at line 732 of file LoongArchISelLowering.cpp.

References DL, End, llvm::SelectionDAG::getNode(), and llvm::LoongArchISD::VPICKEV.

Referenced by lower128BitShuffle().

lowerVECTOR_SHUFFLE_VPICKOD()

static SDValue lowerVECTOR_SHUFFLE_VPICKOD ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into VPICKOD (if possible).

VPICKOD copies the odd elements of each vector into the result vector.

It is possible to lower into VPICKOD when the mask consists of two of the following forms concatenated: <1, 3, 5, ...> <n+1, n+3, n+5, ...> where n is the number of elements in the vector. For example: <1, 3, 5, ..., 1, 3, 5, ...> <1, 3, 5, ..., n+1, n+3, n+5, ...>

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.

Definition at line 774 of file LoongArchISelLowering.cpp.

References DL, End, llvm::SelectionDAG::getNode(), and llvm::LoongArchISD::VPICKOD.

Referenced by lower128BitShuffle().

lowerVECTOR_SHUFFLE_VREPLVEI()

static SDValue lowerVECTOR_SHUFFLE_VREPLVEI ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into VREPLVEI (if possible).

VREPLVEI performs vector broadcast based on an element specified by an integer immediate, with its mask being similar to: <x, x, x, ...> where x is any valid index.

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above form.

Definition at line 463 of file LoongArchISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), and llvm::LoongArchISD::VREPLVEI.

Referenced by lower128BitShuffle().

lowerVECTOR_SHUFFLE_VSHUF()

static SDValue lowerVECTOR_SHUFFLE_VSHUF ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into VSHUF.

This mostly consists of converting the shuffle mask into a BUILD_VECTOR and adding it as an operand to the resulting VSHUF.

Definition at line 804 of file LoongArchISelLowering.cpp.

References llvm::MVT::changeVectorElementTypeToInteger(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::LoongArchISD::VSHUF.

Referenced by lower128BitShuffle().

lowerVECTOR_SHUFFLE_VSHUF4I()

static SDValue lowerVECTOR_SHUFFLE_VSHUF4I ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into VSHUF4I (if possible).

VSHUF4I splits the vector into blocks of four elements, then shuffles these elements according to a <4 x i2> constant (encoded as an integer immediate).

It is therefore possible to lower into VSHUF4I when the mask takes the form: <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...> When undef's appear they are treated as if they were whatever value is necessary in order to fit the above forms.

For example: %2 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> is lowered to: (VSHUF4I_H $v0, $v1, 27) where the 27 comes from: 3 + (2 << 2) + (1 << 4) + (0 << 6)

Definition at line 505 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), Idx, and llvm::LoongArchISD::VSHUF4I.

Referenced by lower128BitShuffle(), and lowerVECTOR_SHUFFLE_XVSHUF4I().

lowerVECTOR_SHUFFLE_XVILVH()

static SDValue lowerVECTOR_SHUFFLE_XVILVH ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into XVILVH (if possible).

Definition at line 939 of file LoongArchISelLowering.cpp.

References DL, End, llvm::SelectionDAG::getNode(), and llvm::LoongArchISD::VILVH.

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVILVL()

static SDValue lowerVECTOR_SHUFFLE_XVILVL ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into XVILVL (if possible).

Definition at line 978 of file LoongArchISelLowering.cpp.

References DL, End, llvm::SelectionDAG::getNode(), and llvm::LoongArchISD::VILVL.

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVPACKEV()

static SDValue lowerVECTOR_SHUFFLE_XVPACKEV ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into XVPACKEV (if possible).

Definition at line 925 of file LoongArchISelLowering.cpp.

References DL, and lowerVECTOR_SHUFFLE_VPACKEV().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVPACKOD()

static SDValue lowerVECTOR_SHUFFLE_XVPACKOD ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into XVPACKOD (if possible).

Definition at line 932 of file LoongArchISelLowering.cpp.

References DL, and lowerVECTOR_SHUFFLE_VPACKOD().

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVPICKEV()

static SDValue lowerVECTOR_SHUFFLE_XVPICKEV ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into XVPICKEV (if possible).

Definition at line 1012 of file LoongArchISelLowering.cpp.

References DL, End, llvm::SelectionDAG::getNode(), and llvm::LoongArchISD::VPICKEV.

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVPICKOD()

static SDValue lowerVECTOR_SHUFFLE_XVPICKOD ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into XVPICKOD (if possible).

Definition at line 1047 of file LoongArchISelLowering.cpp.

References DL, End, llvm::SelectionDAG::getNode(), and llvm::LoongArchISD::VPICKOD.

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVREPLVEI()

static SDValue lowerVECTOR_SHUFFLE_XVREPLVEI ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into XVREPLVEI (if possible).

It is a XVREPLVEI when the mask is: <x, x, x, ..., x+n, x+n, x+n, ...> where the number of x is equal to n and n is half the length of vector.

When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above form.

Definition at line 882 of file LoongArchISelLowering.cpp.

References assert(), DL, End, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), and llvm::LoongArchISD::VREPLVEI.

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVSHUF()

static SDValue lowerVECTOR_SHUFFLE_XVSHUF ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into XVSHUF (if possible).

Definition at line 1083 of file LoongArchISelLowering.cpp.

References assert(), llvm::MVT::changeVectorElementTypeToInteger(), DL, End, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorBase< Size_T >::size(), and llvm::LoongArchISD::VSHUF.

Referenced by lower256BitShuffle().

lowerVECTOR_SHUFFLE_XVSHUF4I()

static SDValue lowerVECTOR_SHUFFLE_XVSHUF4I ( const SDLoc &  DL, ArrayRef< int >  Mask, MVT  VT, SDValue  V1, SDValue  V2, SelectionDAG &  DAG  )

static

Lower VECTOR_SHUFFLE into XVSHUF4I (if possible).

Definition at line 914 of file LoongArchISelLowering.cpp.

References DL, and lowerVECTOR_SHUFFLE_VSHUF4I().

Referenced by lower256BitShuffle().

lowerVectorBitClear()

static SDValue lowerVectorBitClear ( SDNode *  Node, SelectionDAG &  DAG  )

static

Definition at line 3672 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::ISD::SHL, and truncateVecElts().

Referenced by performINTRINSIC_WO_CHAINCombine().

lowerVectorBitClearImm()

template<unsigned N>

static SDValue lowerVectorBitClearImm ( SDNode *  Node, SelectionDAG &  DAG  )

static

Definition at line 3684 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), and llvm::ISD::UNDEF.

lowerVectorBitRevImm()

template<unsigned N>

static SDValue lowerVectorBitRevImm ( SDNode *  Node, SelectionDAG &  DAG  )

static

Definition at line 3719 of file LoongArchISelLowering.cpp.

References DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::ISD::UNDEF, and llvm::ISD::XOR.

lowerVectorBitSetImm()

template<unsigned N>

static SDValue lowerVectorBitSetImm ( SDNode *  Node, SelectionDAG &  DAG  )

static

Definition at line 3702 of file LoongArchISelLowering.cpp.

References DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::ISD::OR, and llvm::ISD::UNDEF.

lowerVectorSplatImm()

template<unsigned N>

static SDValue lowerVectorSplatImm ( SDNode *  Node, unsigned  ImmOp, SelectionDAG &  DAG, bool  IsSigned = false  )

static

Definition at line 3645 of file LoongArchISelLowering.cpp.

References DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), and llvm::ISD::UNDEF.

performANDCombine()

static SDValue performANDCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 3102 of file LoongArchISelLowering.cpp.

References llvm::LoongArchISD::BSTRPICK, DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), N, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::SDNode::use_size().

performBITREV_WCombine()

static SDValue performBITREV_WCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 3613 of file LoongArchISelLowering.cpp.

References llvm::LoongArchISD::BITREV_4B, llvm::SelectionDAG::getNode(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, and llvm::LoongArchISD::REVB_2W.

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performINTRINSIC_WO_CHAINCombine()

static SDValue performINTRINSIC_WO_CHAINCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 3736 of file LoongArchISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::CTLZ, llvm::ISD::CTPOP, DL, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMA, llvm::ISD::FMUL, llvm::ISD::FSUB, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::INSERT_VECTOR_ELT, lowerVectorBitClear(), llvm::ISD::MUL, N, llvm::ISD::OR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SUB, truncateVecElts(), llvm::ISD::UDIV, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UREM, llvm::LoongArchISD::VREPLVE, and llvm::ISD::XOR.

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performORCombine()

static SDValue performORCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 3229 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, llvm::LoongArchISD::BSTRINS, llvm::SelectionDAG::computeKnownBits(), llvm::dbgs(), DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), llvm::APInt::isSubsetOf(), LLVM_DEBUG, N, llvm::ISD::SHL, llvm::ISD::SRL, std::swap(), and llvm::KnownBits::Zero.

performSETCCCombine()

static SDValue performSETCCCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 3544 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, CC, checkValueWidth(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ConstantSDNode::getSExtValue(), llvm::SDNode::getValueType(), N, llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::SEXTLOAD, llvm::ISD::TRUNCATE, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

performSRLCombine()

static SDValue performSRLCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 3188 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, llvm::LoongArchISD::BSTRPICK, DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), and N.

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine(), and llvm::MipsSETargetLowering::PerformDAGCombine().

replaceINTRINSIC_WO_CHAINResults()

static void replaceINTRINSIC_WO_CHAINResults ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 2739 of file LoongArchISelLowering.cpp.

References llvm_unreachable, N, replaceVecCondBranchResults(), Results, llvm::LoongArchISD::VALL_NONZERO, llvm::LoongArchISD::VALL_ZERO, llvm::LoongArchISD::VANY_NONZERO, llvm::LoongArchISD::VANY_ZERO, llvm::LoongArchISD::VPICK_SEXT_ELT, and llvm::LoongArchISD::VPICK_ZEXT_ELT.

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().

replaceVecCondBranchResults()

static void replaceVecCondBranchResults ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, const LoongArchSubtarget &  Subtarget, unsigned  ResOp  )

static

Definition at line 2725 of file LoongArchISelLowering.cpp.

References DL, llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), N, Results, and llvm::ISD::TRUNCATE.

Referenced by replaceINTRINSIC_WO_CHAINResults().

replaceVPICKVE2GRResults()

template<unsigned N>

static void replaceVPICKVE2GRResults ( SDNode *  Node, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, const LoongArchSubtarget &  Subtarget, unsigned  ResOp  )

static

Definition at line 2704 of file LoongArchISelLowering.cpp.

References DL, emitErrorAndReplaceIntrinsicResults(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementType(), Results, and llvm::ISD::TRUNCATE.

STATISTIC()

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"
	)

truncateVecElts()

static SDValue truncateVecElts ( SDNode *  Node, SelectionDAG &  DAG  )

static

Definition at line 3664 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), and llvm::SDValue::getScalarValueSizeInBits().

Referenced by lowerMSABitClear(), lowerVectorBitClear(), and performINTRINSIC_WO_CHAINCombine().

unpackFromMemLoc()

static SDValue unpackFromMemLoc ( SelectionDAG &  DAG, SDValue  Chain, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 4960 of file LoongArchISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::CCValAssign::Full, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getStoreSize(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm_unreachable, and llvm::ISD::NON_EXTLOAD.

unpackFromRegLoc()

static SDValue unpackFromRegLoc ( SelectionDAG &  DAG, SDValue  Chain, const CCValAssign &  VA, const SDLoc &  DL, const ISD::InputArg &  In, const LoongArchTargetLowering &  TLI  )

static

Definition at line 4927 of file LoongArchISelLowering.cpp.

References llvm::LoongArchMachineFunctionInfo::addSExt32Register(), llvm::BitWidth, convertLocVTToValVT(), DL, llvm::Function::getArg(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::Type::getIntegerBitWidth(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::EVT::getSimpleVT(), llvm::Value::getType(), and llvm::Type::isIntegerTy().

Variable Documentation

ArgFPR32s

const MCPhysReg ArgFPR32s[]

Initial value:

= {LoongArch::F0, LoongArch::F1, LoongArch::F2,
                               LoongArch::F3, LoongArch::F4, LoongArch::F5,
                               LoongArch::F6, LoongArch::F7}

Definition at line 4661 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch(), and llvm::RISCV::CC_RISCV().

ArgFPR64s

const MCPhysReg ArgFPR64s[]

Initial value:

= {
    LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64,
    LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64}

Definition at line 4665 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch(), and llvm::RISCV::CC_RISCV().

ArgGPRs

const MCPhysReg ArgGPRs[]

Initial value:

= {LoongArch::R4,  LoongArch::R5, LoongArch::R6,
                             LoongArch::R7,  LoongArch::R8, LoongArch::R9,
                             LoongArch::R10, LoongArch::R11}

Definition at line 4656 of file LoongArchISelLowering.cpp.

Referenced by llvm::CC_CSKY_ABIV2_SOFT_64(), CC_LoongArch(), CC_LoongArchAssign2GRLen(), llvm::RISCV::CC_RISCV(), CC_RISCVAssign2XLen(), llvm::LoongArchTargetLowering::LowerFormalArguments(), and llvm::Ret_CSKY_ABIV2_SOFT_64().

ArgVRs

const MCPhysReg ArgVRs[]

Initial value:

= {LoongArch::VR0, LoongArch::VR1, LoongArch::VR2,
                            LoongArch::VR3, LoongArch::VR4, LoongArch::VR5,
                            LoongArch::VR6, LoongArch::VR7}

Definition at line 4669 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch().

ArgXRs

const MCPhysReg ArgXRs[]

Initial value:

= {LoongArch::XR0, LoongArch::XR1, LoongArch::XR2,
                            LoongArch::XR3, LoongArch::XR4, LoongArch::XR5,
                            LoongArch::XR6, LoongArch::XR7}

Definition at line 4673 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch().

ZeroDivCheck

cl::opt< bool > ZeroDivCheck("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false)) ( "loongarch-check-zero-division"  , cl::Hidden  , cl::desc("Trap on integer division by zero.")  , cl::init(false)    )

static

Referenced by insertDivByZeroTrap().