| LLVM 22.0.0git
    | 
#include "LoongArchISelLowering.h"#include "LoongArch.h"#include "LoongArchMachineFunctionInfo.h"#include "LoongArchRegisterInfo.h"#include "LoongArchSubtarget.h"#include "MCTargetDesc/LoongArchBaseInfo.h"#include "MCTargetDesc/LoongArchMCTargetDesc.h"#include "MCTargetDesc/LoongArchMatInt.h"#include "llvm/ADT/SmallSet.h"#include "llvm/ADT/Statistic.h"#include "llvm/ADT/StringExtras.h"#include "llvm/CodeGen/ISDOpcodes.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/RuntimeLibcallUtil.h"#include "llvm/CodeGen/SelectionDAGNodes.h"#include "llvm/IR/IRBuilder.h"#include "llvm/IR/IntrinsicInst.h"#include "llvm/IR/IntrinsicsLoongArch.h"#include "llvm/Support/CodeGen.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/KnownBits.h"#include "llvm/Support/MathExtras.h"#include <llvm/Analysis/VectorUtils.h>#include "LoongArchGenAsmMatcher.inc"Go to the source code of this file.
| Macros | |
| #define | DEBUG_TYPE "loongarch-isel-lowering" | 
| #define | IOCSRRD_CASE(NAME, NODE) | 
| #define | IOCSRWR_CASE(NAME, NODE) | 
| #define | ASRT_LE_GT_CASE(NAME) | 
| #define | CRC_CASE_EXT_BINARYOP(NAME, NODE) | 
| #define | CRC_CASE_EXT_UNARYOP(NAME, NODE) | 
| #define | CSR_CASE(ID) | 
| #define | IOCSRRD_CASE(NAME, NODE) | 
| #define | NODE_NAME_CASE(node) | 
| #define | GET_REGISTER_MATCHER | 
| Enumerations | |
| enum | MaterializeFPImm { NoMaterializeFPImm = 0 , MaterializeFPImm2Ins = 2 , MaterializeFPImm3Ins = 3 , MaterializeFPImm4Ins = 4 , MaterializeFPImm5Ins = 5 , MaterializeFPImm6Ins = 6 } | 
| Variables | |
| static cl::opt< MaterializeFPImm > | MaterializeFPImmInsNum ("loongarch-materialize-float-imm", cl::Hidden, cl::desc("Maximum number of instructions used (including code sequence " "to generate the value and moving the value to FPR) when " "materializing floating-point immediates (default = 3)"), cl::init(MaterializeFPImm3Ins), cl::values(clEnumValN(NoMaterializeFPImm, "0", "Use constant pool"), clEnumValN(MaterializeFPImm2Ins, "2", "Materialize FP immediate within 2 instructions"), clEnumValN(MaterializeFPImm3Ins, "3", "Materialize FP immediate within 3 instructions"), clEnumValN(MaterializeFPImm4Ins, "4", "Materialize FP immediate within 4 instructions"), clEnumValN(MaterializeFPImm5Ins, "5", "Materialize FP immediate within 5 instructions"), clEnumValN(MaterializeFPImm6Ins, "6", "Materialize FP immediate within 6 instructions " "(behaves same as 5 on loongarch64)"))) | 
| static cl::opt< bool > | ZeroDivCheck ("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false)) | 
| const MCPhysReg | ArgGPRs [] | 
| const MCPhysReg | ArgFPR32s [] | 
| const MCPhysReg | ArgFPR64s [] | 
| const MCPhysReg | ArgVRs [] | 
| const MCPhysReg | ArgXRs [] | 
| #define ASRT_LE_GT_CASE | ( | NAME | ) | 
| #define CRC_CASE_EXT_BINARYOP | ( | NAME, | |
| NODE ) | 
Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().
| #define CRC_CASE_EXT_UNARYOP | ( | NAME, | |
| NODE ) | 
Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().
| #define CSR_CASE | ( | ID | ) | 
Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().
| #define DEBUG_TYPE "loongarch-isel-lowering" | 
Definition at line 41 of file LoongArchISelLowering.cpp.
| #define GET_REGISTER_MATCHER | 
Definition at line 9329 of file LoongArchISelLowering.cpp.
| #define IOCSRRD_CASE | ( | NAME, | |
| NODE ) | 
Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().
| #define IOCSRRD_CASE | ( | NAME, | |
| NODE ) | 
| #define IOCSRWR_CASE | ( | NAME, | |
| NODE ) | 
| #define NODE_NAME_CASE | ( | node | ) | 
| enum MaterializeFPImm | 
| Enumerator | |
|---|---|
| NoMaterializeFPImm | |
| MaterializeFPImm2Ins | |
| MaterializeFPImm3Ins | |
| MaterializeFPImm4Ins | |
| MaterializeFPImm5Ins | |
| MaterializeFPImm6Ins | |
Definition at line 45 of file LoongArchISelLowering.cpp.
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Shuffle vectors by lane to generate more optimized instructions.
256-bit shuffles are always considered as 2-lane 128-bit shuffles.
Therefore, except for the following four cases, other cases are regarded as cross-lane shuffles, where optimization is relatively limited.
The first case is the closest to LoongArch instructions and the other cases need to be converted to it for processing.
This function will return true for the last three cases above and will modify V1, V2 and Mask. Otherwise, return false for the first case and cross-lane shuffle cases.
Definition at line 2486 of file LoongArchISelLowering.cpp.
References DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::isUndef(), llvm::None, and llvm::LoongArchISD::XVPERMI.
Referenced by lower256BitShuffle().
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Definition at line 7653 of file LoongArchISelLowering.cpp.
References llvm::LoongArchABI::ABI_ILP32D, llvm::LoongArchABI::ABI_ILP32F, llvm::LoongArchABI::ABI_ILP32S, llvm::LoongArchABI::ABI_LP64D, llvm::LoongArchABI::ABI_LP64F, llvm::LoongArchABI::ABI_LP64S, ArgFPR32s, ArgFPR64s, ArgGPRs, ArgVRs, ArgXRs, assert(), llvm::CCValAssign::BCvt, CC_LoongArchAssign2GRLen(), llvm::SmallVectorImpl< T >::clear(), DL, llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::CCValAssign::Full, llvm::CCValAssign::getCustomMem(), llvm::CCValAssign::getCustomReg(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getPending(), llvm::CCValAssign::getReg(), llvm::CCValAssign::Indirect, llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::isFloatingPoint(), llvm::MVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), llvm::ISD::ArgFlagsTy::isVarArg(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Reg, and llvm::SmallVectorTemplateCommon< T, typename >::size().
Referenced by llvm::LoongArchTargetLowering::CanLowerReturn(), llvm::LoongArchTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerFormalArguments(), and llvm::LoongArchTargetLowering::LowerReturn().
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Definition at line 8005 of file LoongArchISelLowering.cpp.
References llvm::CCValAssign::getReg(), Reg, and llvm::report_fatal_error().
Referenced by llvm::LoongArchTargetLowering::LowerCall(), and llvm::LoongArchTargetLowering::LowerFormalArguments().
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Definition at line 7617 of file LoongArchISelLowering.cpp.
References ArgGPRs, llvm::CCValAssign::Full, llvm::CCValAssign::getLocVT(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getReg(), llvm::CCValAssign::getValNo(), llvm::CCValAssign::getValVT(), and Reg.
Referenced by CC_LoongArch().
Definition at line 5182 of file LoongArchISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::BUILD_VECTOR, checkBitcastSrcVectorSize(), llvm::Depth, llvm::ISD::FREEZE, llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::SelectionDAG::MaxRecursionDepth, llvm::ISD::OR, llvm::ISD::SELECT, llvm::ISD::SETCC, Size, llvm::ISD::TRUNCATE, llvm::ISD::VSELECT, and llvm::ISD::XOR.
Referenced by checkBitcastSrcVectorSize(), checkBitcastSrcVectorSize(), combineBitcastvxi1(), and performBITCASTCombine().
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Definition at line 3765 of file LoongArchISelLowering.cpp.
References llvm::cast(), llvm::LLVMContext::emitError(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::isInt(), llvm::isUInt(), SDValue(), and llvm::ISD::UNDEF.
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Definition at line 5629 of file LoongArchISelLowering.cpp.
References llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::cast(), llvm::LoadSDNode::getExtensionType(), llvm::MemSDNode::getMemoryVT(), llvm::VTSDNode::getVT(), llvm::ISD::NON_EXTLOAD, llvm::ISD::SEXTLOAD, and llvm::ISD::ZEXTLOAD.
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Definition at line 5808 of file LoongArchISelLowering.cpp.
References llvm::ISD::AND, llvm::cast(), llvm::ISD::Constant, DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), llvm::SelectionDAG::MaskedValueIsZero(), RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and translateSetCCForBranch().
Referenced by performBR_CCCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), and performSELECT_CCCombine().
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Definition at line 790 of file LoongArchISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::cast(), DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::isa(), llvm::isAllOnesConstant(), llvm::isNullConstant(), LHS, matchSetCC(), N, llvm::ISD::OR, RHS, SDValue(), llvm::ISD::SETCC, and llvm::ISD::XOR.
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Compute whether each element of a shuffle is zeroable.
A "zeroable" vector shuffle element is one which can be lowered to zero.
Definition at line 1347 of file LoongArchISelLowering.cpp.
References assert(), llvm::SDValue::getNode(), llvm::SDValue::getValueSizeInBits(), llvm::APInt::getZero(), llvm::ISD::isBuildVectorAllZeros(), llvm::peekThroughBitcasts(), llvm::APInt::setBit(), and Size.
Referenced by lower128BitShuffle(), lower256BitShuffle(), and lowerVECTOR_SHUFFLE().
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Definition at line 7878 of file LoongArchISelLowering.cpp.
References llvm::CCValAssign::BCvt, DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm_unreachable, and llvm::LoongArchISD::MOVGR2FR_W_LA64.
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Definition at line 7986 of file LoongArchISelLowering.cpp.
References llvm::CCValAssign::BCvt, DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm_unreachable, and llvm::LoongArchISD::MOVFR2GR_S_LA64.
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Definition at line 4483 of file LoongArchISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getConstant(), getLoongArchWOpcode(), llvm::SelectionDAG::getNode(), llvm_unreachable, N, llvm::ISD::ROTL, llvm::ISD::SUB, and llvm::ISD::TRUNCATE.
Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 4517 of file LoongArchISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), N, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::TRUNCATE.
Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
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Definition at line 7192 of file LoongArchISelLowering.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::RegState::Kill, MI, MRI, and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 4529 of file LoongArchISelLowering.cpp.
References llvm::LLVMContext::emitError(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getUNDEF(), N, and Results.
Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults(), and replaceVPICKVE2GRResults().
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Definition at line 4181 of file LoongArchISelLowering.cpp.
References llvm::LLVMContext::emitError(), and llvm::SelectionDAG::getContext().
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Definition at line 4058 of file LoongArchISelLowering.cpp.
References llvm::LLVMContext::emitError(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getMergeValues(), and llvm::SelectionDAG::getUNDEF().
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Definition at line 7019 of file LoongArchISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::LoongArchSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::LoongArchSubtarget::is64Bit(), MI, MRI, and TII.
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Definition at line 7058 of file LoongArchISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::LoongArchSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::LoongArchSubtarget::getRegisterInfo(), llvm::Hi, llvm::LoongArchSubtarget::is64Bit(), llvm::RegState::Kill, llvm_unreachable, llvm::Lo, MI, MRI, TII, and TRI.
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Definition at line 6949 of file LoongArchISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::LoongArchSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::Register::isVirtual(), llvm_unreachable, MI, MRI, and TII.
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Definition at line 7225 of file LoongArchISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::any_of(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineInstr::collectDebugValues(), llvm::SmallSet< T, N, C >::count(), DL, E(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::getImm(), llvm::LoongArchSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), I, llvm::SmallSet< T, N, C >::insert(), isSelectPseudo(), LHS, MI, llvm::Next, llvm::MachineBasicBlock::push_back(), RHS, llvm::MachineBasicBlock::setCallFrameSize(), llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
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Definition at line 7172 of file LoongArchISelLowering.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), MI, and TII.
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Definition at line 6824 of file LoongArchISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::LoongArchSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm_unreachable, MI, MRI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
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Definition at line 2909 of file LoongArchISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, assert(), DL, fillVector(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorNumElements(), and llvm::Vector.
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Definition at line 2890 of file LoongArchISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorNumElements(), llvm::ISD::INSERT_VECTOR_ELT, llvm::SDValue::isUndef(), llvm::ISD::SCALAR_TO_VECTOR, and llvm::Vector.
Referenced by fillSubVectorFromBuildVector().
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Determine whether a range fits a regular pattern of values.
This function accounts for the possibility of jumping over the End iterator.
Definition at line 1325 of file LoongArchISelLowering.cpp.
References I.
Referenced by isVECTOR_SHUFFLE_SPLATI(), lowerVECTOR_SHUFFLE_ILVEV(), lowerVECTOR_SHUFFLE_ILVL(), lowerVECTOR_SHUFFLE_ILVOD(), lowerVECTOR_SHUFFLE_ILVR(), lowerVECTOR_SHUFFLE_PCKEV(), lowerVECTOR_SHUFFLE_PCKOD(), lowerVECTOR_SHUFFLE_VILVH(), lowerVECTOR_SHUFFLE_VILVL(), lowerVECTOR_SHUFFLE_VPACKEV(), lowerVECTOR_SHUFFLE_VPACKOD(), lowerVECTOR_SHUFFLE_VPICKEV(), lowerVECTOR_SHUFFLE_VPICKOD(), lowerVECTOR_SHUFFLE_VREPLVEI(), lowerVECTOR_SHUFFLE_XVILVH(), lowerVECTOR_SHUFFLE_XVILVL(), lowerVECTOR_SHUFFLE_XVPICKEV(), lowerVECTOR_SHUFFLE_XVPICKOD(), and lowerVECTOR_SHUFFLE_XVREPLVEI().
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Definition at line 864 of file LoongArchISelLowering.cpp.
References DL, llvm::dyn_cast(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSelect(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::isa(), llvm::APInt::isAllOnes(), llvm::ConstantSDNode::isOpaque(), llvm::APInt::isZero(), SDValue(), llvm::ISD::SELECT, and std::swap().
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Definition at line 9098 of file LoongArchISelLowering.cpp.
References llvm::EVT::getScalarType().
Referenced by llvm::LoongArchTargetLowering::getRecipEstimate(), and llvm::LoongArchTargetLowering::getSqrtEstimate().
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Definition at line 8919 of file LoongArchISelLowering.cpp.
References llvm::AtomicRMWInst::Add, llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.
Referenced by llvm::LoongArchTargetLowering::emitMaskedAtomicRMWIntrinsic(), and llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic().
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Definition at line 4450 of file LoongArchISelLowering.cpp.
References llvm::LoongArchISD::CLZ_W, llvm::ISD::CTLZ, llvm::ISD::CTTZ, llvm::LoongArchISD::CTZ_W, llvm::LoongArchISD::DIV_W, llvm::LoongArchISD::DIV_WU, llvm_unreachable, llvm::LoongArchISD::MOD_W, llvm::LoongArchISD::MOD_WU, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::LoongArchISD::ROTR_W, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::LoongArchISD::SLL_W, llvm::ISD::SRA, llvm::LoongArchISD::SRA_W, llvm::ISD::SREM, llvm::ISD::SRL, llvm::LoongArchISD::SRL_W, llvm::ISD::UDIV, and llvm::ISD::UREM.
Referenced by customLegalizeToWOp().
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Definition at line 8265 of file LoongArchISelLowering.cpp.
References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), and llvm::EVT::getTypeForEVT().
Referenced by llvm::SelectionDAG::CreateStackTemporary(), llvm::LoongArchTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerCall().
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Definition at line 3502 of file LoongArchISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetBlockAddress(), and N.
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Definition at line 3508 of file LoongArchISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetConstantPool(), and N.
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Definition at line 3497 of file LoongArchISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.
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Definition at line 3514 of file LoongArchISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetJumpTable(), and N.
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Definition at line 6773 of file LoongArchISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), llvm::MachineOperand::isKill(), MBB, MI, llvm::MachineOperand::setIsKill(), TII, and ZeroDivCheck.
Referenced by llvm::MipsTargetLowering::EmitInstrWithCustomInserter().
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Test whether a shuffle mask is equivalent within each sub-lane.
The specific repeated shuffle mask is populated in RepeatedMask, as it is non-trivial to compute in the face of undef lanes. The representation is suitable for use with existing 128-bit shuffles as entries from the second vector have been remapped to [LaneSize, 2*LaneSize). 
Definition at line 1383 of file LoongArchISelLowering.cpp.
References assert(), llvm::SmallVectorImpl< T >::assign(), llvm::MVT::getScalarSizeInBits(), and Size.
Referenced by is128BitLaneRepeatedShuffleMask(), is128BitLaneRepeatedShuffleMask(), is256BitLaneRepeatedShuffleMask(), and matchShuffleAsByteRotate().
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Definition at line 7215 of file LoongArchISelLowering.cpp.
References MI.
Referenced by emitSelectPseudo().
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Definition at line 5947 of file LoongArchISelLowering.cpp.
References llvm::cast(), DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::isInt(), llvm::isUInt(), and llvm::ISD::UNDEF.
Referenced by performINTRINSIC_WO_CHAINCombine().
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Dispatching routine to lower various 128-bit LoongArch vector shuffles.
This routine breaks down the specific type of 128-bit shuffle and dispatches to the lowering routines accordingly.
Definition at line 2024 of file LoongArchISelLowering.cpp.
References assert(), computeZeroableShuffleElements(), DL, llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorNumElements(), llvm::SDValue::isUndef(), lowerVECTOR_SHUFFLE_IsReverse(), lowerVECTOR_SHUFFLE_VILVH(), lowerVECTOR_SHUFFLE_VILVL(), lowerVECTOR_SHUFFLE_VPACKEV(), lowerVECTOR_SHUFFLE_VPACKOD(), lowerVECTOR_SHUFFLE_VPICKEV(), lowerVECTOR_SHUFFLE_VPICKOD(), lowerVECTOR_SHUFFLE_VREPLVEI(), lowerVECTOR_SHUFFLE_VSHUF(), lowerVECTOR_SHUFFLE_VSHUF4I(), lowerVECTOR_SHUFFLEAsByteRotate(), lowerVECTOR_SHUFFLEAsShift(), lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(), SDValue(), llvm::MVT::SimpleTy, and widenShuffleMask().
Referenced by lowerVECTOR_SHUFFLE().
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Dispatching routine to lower various 256-bit LoongArch vector shuffles.
This routine breaks down the specific type of 256-bit shuffle and dispatches to the lowering routines accordingly.
Definition at line 2636 of file LoongArchISelLowering.cpp.
References assert(), canonicalizeShuffleVectorByLane(), computeZeroableShuffleElements(), DL, llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorNumElements(), llvm::SDValue::isUndef(), lower256BitShuffle(), lowerVECTOR_SHUFFLE_IsReverse(), lowerVECTOR_SHUFFLE_XVILVH(), lowerVECTOR_SHUFFLE_XVILVL(), lowerVECTOR_SHUFFLE_XVINSVE0(), lowerVECTOR_SHUFFLE_XVPACKEV(), lowerVECTOR_SHUFFLE_XVPACKOD(), lowerVECTOR_SHUFFLE_XVPERM(), lowerVECTOR_SHUFFLE_XVPERMI(), lowerVECTOR_SHUFFLE_XVPICKEV(), lowerVECTOR_SHUFFLE_XVPICKOD(), lowerVECTOR_SHUFFLE_XVREPLVEI(), lowerVECTOR_SHUFFLE_XVSHUF(), lowerVECTOR_SHUFFLE_XVSHUF4I(), lowerVECTOR_SHUFFLEAsByteRotate(), lowerVECTOR_SHUFFLEAsLanePermuteAndShuffle(), lowerVECTOR_SHUFFLEAsShift(), SDValue(), llvm::MVT::SimpleTy, and widenShuffleMask().
Referenced by lower256BitShuffle(), and lowerVECTOR_SHUFFLE().
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Definition at line 2846 of file LoongArchISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::cast(), DL, llvm::ISD::EXTLOAD, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::SDNode::getSimpleValueType(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::SDNode::isOnlyUserOf(), llvm::ISD::NON_EXTLOAD, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), and llvm::LoongArchISD::VLDREPL.
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Lower VECTOR_SHUFFLE whose result is the reversed source vector.
It is possible to do optimization for VECTOR_SHUFFLE performing vector reverse whose mask likes: <7, 6, 5, 4, 3, 2, 1, 0>
When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.
Definition at line 1719 of file LoongArchISelLowering.cpp.
References DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::ShuffleVectorInst::isReverseMask(), SDValue(), and llvm::LoongArchISD::VSHUF4I.
Referenced by lower128BitShuffle(), and lower256BitShuffle().
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Lower VECTOR_SHUFFLE into VILVH (if possible).
VILVH interleaves consecutive elements from the left (highest-indexed) half of each vector.
It is possible to lower into VILVH when the mask consists of two of the following forms interleaved: <x, x+1, x+2, ...> <n+x, n+x+1, n+x+2, ...> where n is the number of elements in the vector and x is half n. For example: <x, x, x+1, x+1, x+2, x+2, ...> <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.
Definition at line 1843 of file LoongArchISelLowering.cpp.
References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), SDValue(), and llvm::LoongArchISD::VILVH.
Referenced by lower128BitShuffle().
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Lower VECTOR_SHUFFLE into VILVL (if possible).
VILVL interleaves consecutive elements from the right (lowest-indexed) half of each vector.
It is possible to lower into VILVL when the mask consists of two of the following forms interleaved: <0, 1, 2, ...> <n, n+1, n+2, ...> where n is the number of elements in the vector. For example: <0, 0, 1, 1, 2, 2, ...> <0, n, 1, n+1, 2, n+2, ...>
When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.
Definition at line 1886 of file LoongArchISelLowering.cpp.
References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), SDValue(), and llvm::LoongArchISD::VILVL.
Referenced by lower128BitShuffle().
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Lower VECTOR_SHUFFLE into VPACKEV (if possible).
VPACKEV interleaves the even elements from each vector.
It is possible to lower into VPACKEV when the mask consists of two of the following forms interleaved: <0, 2, 4, ...> <n, n+2, n+4, ...> where n is the number of elements in the vector. For example: <0, 0, 2, 2, 4, 4, ...> <0, n, 2, n+2, 4, n+4, ...>
When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.
Definition at line 1762 of file LoongArchISelLowering.cpp.
References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), SDValue(), and llvm::LoongArchISD::VPACKEV.
Referenced by lower128BitShuffle(), and lowerVECTOR_SHUFFLE_XVPACKEV().
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Lower VECTOR_SHUFFLE into VPACKOD (if possible).
VPACKOD interleaves the odd elements from each vector.
It is possible to lower into VPACKOD when the mask consists of two of the following forms interleaved: <1, 3, 5, ...> <n+1, n+3, n+5, ...> where n is the number of elements in the vector. For example: <1, 1, 3, 3, 5, 5, ...> <1, n+1, 3, n+3, 5, n+5, ...>
When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.
Definition at line 1802 of file LoongArchISelLowering.cpp.
References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), SDValue(), and llvm::LoongArchISD::VPACKOD.
Referenced by lower128BitShuffle(), and lowerVECTOR_SHUFFLE_XVPACKOD().
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Lower VECTOR_SHUFFLE into VPICKEV (if possible).
VPICKEV copies the even elements of each vector into the result vector.
It is possible to lower into VPICKEV when the mask consists of two of the following forms concatenated: <0, 2, 4, ...> <n, n+2, n+4, ...> where n is the number of elements in the vector. For example: <0, 2, 4, ..., 0, 2, 4, ...> <0, 2, 4, ..., n, n+2, n+4, ...>
When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.
Definition at line 1926 of file LoongArchISelLowering.cpp.
References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), SDValue(), and llvm::LoongArchISD::VPICKEV.
Referenced by lower128BitShuffle().
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Lower VECTOR_SHUFFLE into VPICKOD (if possible).
VPICKOD copies the odd elements of each vector into the result vector.
It is possible to lower into VPICKOD when the mask consists of two of the following forms concatenated: <1, 3, 5, ...> <n+1, n+3, n+5, ...> where n is the number of elements in the vector. For example: <1, 3, 5, ..., 1, 3, 5, ...> <1, 3, 5, ..., n+1, n+3, n+5, ...>
When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above forms.
Definition at line 1968 of file LoongArchISelLowering.cpp.
References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), SDValue(), and llvm::LoongArchISD::VPICKOD.
Referenced by lower128BitShuffle().
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Lower VECTOR_SHUFFLE into VREPLVEI (if possible).
VREPLVEI performs vector broadcast based on an element specified by an integer immediate, with its mask being similar to: <x, x, x, ...> where x is any valid index.
When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above form.
Definition at line 1613 of file LoongArchISelLowering.cpp.
References assert(), DL, fitsRegularPattern(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), SDValue(), and llvm::LoongArchISD::VREPLVEI.
Referenced by lower128BitShuffle().
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Lower VECTOR_SHUFFLE into VSHUF.
This mostly consists of converting the shuffle mask into a BUILD_VECTOR and adding it as an operand to the resulting VSHUF.
Definition at line 1998 of file LoongArchISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::MVT::changeVectorElementTypeToInteger(), DL, llvm::SelectionDAG::getBuildVector(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSignedConstant(), and llvm::LoongArchISD::VSHUF.
Referenced by lower128BitShuffle().
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Lower VECTOR_SHUFFLE into VSHUF4I (if possible).
VSHUF4I splits the vector into blocks of four elements, then shuffles these elements according to a <4 x i2> constant (encoded as an integer immediate).
It is therefore possible to lower into VSHUF4I when the mask takes the form: <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...> When undef's appear they are treated as if they were whatever value is necessary in order to fit the above forms.
For example: %2 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> is lowered to: (VSHUF4I_H $v0, $v1, 27) where the 27 comes from: 3 + (2 << 2) + (1 << 4) + (0 << 6)
Definition at line 1655 of file LoongArchISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), SDValue(), and llvm::LoongArchISD::VSHUF4I.
Referenced by lower128BitShuffle(), and lowerVECTOR_SHUFFLE_XVSHUF4I().
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Lower VECTOR_SHUFFLE into XVILVH (if possible).
Definition at line 2225 of file LoongArchISelLowering.cpp.
References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), SDValue(), and llvm::LoongArchISD::VILVH.
Referenced by lower256BitShuffle().
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Lower VECTOR_SHUFFLE into XVILVL (if possible).
Definition at line 2264 of file LoongArchISelLowering.cpp.
References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), SDValue(), and llvm::LoongArchISD::VILVL.
Referenced by lower256BitShuffle().
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Lower VECTOR_SHUFFLE into XVINSVE0 (if possible).
Definition at line 2370 of file LoongArchISelLowering.cpp.
References assert(), llvm::sampleprof::Base, DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorNumElements(), SDValue(), and llvm::LoongArchISD::XVINSVE0.
Referenced by lower256BitShuffle().
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Lower VECTOR_SHUFFLE into XVPACKEV (if possible).
Definition at line 2211 of file LoongArchISelLowering.cpp.
References DL, and lowerVECTOR_SHUFFLE_VPACKEV().
Referenced by lower256BitShuffle().
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Lower VECTOR_SHUFFLE into XVPACKOD (if possible).
Definition at line 2218 of file LoongArchISelLowering.cpp.
References DL, and lowerVECTOR_SHUFFLE_VPACKOD().
Referenced by lower256BitShuffle().
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Lower VECTOR_SHUFFLE into XVPERM (if possible).
Definition at line 2168 of file LoongArchISelLowering.cpp.
References DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorNumElements(), inRange(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), and llvm::LoongArchISD::XVPERM.
Referenced by lower256BitShuffle().
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Lower VECTOR_SHUFFLE into XVPERMI (if possible).
Definition at line 2149 of file LoongArchISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), SDValue(), and llvm::LoongArchISD::XVPERMI.
Referenced by lower256BitShuffle().
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Lower VECTOR_SHUFFLE into XVPICKEV (if possible).
Definition at line 2298 of file LoongArchISelLowering.cpp.
References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), SDValue(), and llvm::LoongArchISD::VPICKEV.
Referenced by lower256BitShuffle().
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Lower VECTOR_SHUFFLE into XVPICKOD (if possible).
Definition at line 2333 of file LoongArchISelLowering.cpp.
References DL, fitsRegularPattern(), llvm::SelectionDAG::getNode(), SDValue(), and llvm::LoongArchISD::VPICKOD.
Referenced by lower256BitShuffle().
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Lower VECTOR_SHUFFLE into XVREPLVEI (if possible).
It is a XVREPLVEI when the mask is: <x, x, x, ..., x+n, x+n, x+n, ...> where the number of x is equal to n and n is half the length of vector.
When undef's appear in the mask they are treated as if they were whatever value is necessary in order to fit the above form.
Definition at line 2103 of file LoongArchISelLowering.cpp.
References assert(), DL, fitsRegularPattern(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), SDValue(), and llvm::LoongArchISD::VREPLVEI.
Referenced by lower256BitShuffle().
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Lower VECTOR_SHUFFLE into XVSHUF (if possible).
Definition at line 2416 of file LoongArchISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementTypeToInteger(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and llvm::LoongArchISD::VSHUF.
Referenced by lower256BitShuffle().
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Lower VECTOR_SHUFFLE into XVSHUF4I (if possible).
Definition at line 2137 of file LoongArchISelLowering.cpp.
References DL, lowerVECTOR_SHUFFLE_VSHUF4I(), and SDValue().
Referenced by lower256BitShuffle().
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Lower VECTOR_SHUFFLE as byte rotate (if possible).
For example: shuffle = shufflevector <2 x i64> a, <2 x i64> b, <2 x i32> <i32 3, i32 0> is lowered to: (VBSRL_V $v1, $v1, 8) (VBSLL_V $v0, $v0, 8) (VOR_V $v0, $V0, $v1)
Definition at line 1487 of file LoongArchISelLowering.cpp.
References DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorVT(), llvm::Hi, llvm::Lo, matchShuffleAsByteRotate(), llvm::ISD::OR, SDValue(), llvm::LoongArchISD::VBSLL, and llvm::LoongArchISD::VBSRL.
Referenced by lower128BitShuffle(), and lower256BitShuffle().
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Lower VECTOR_SHUFFLE as lane permute and then shuffle (if possible).
Only for 256-bit vector.
For example: %2 = shufflevector <4 x i64> %0, <4 x i64> posion, <4 x i64> <i32 0, i32 3, i32 2, i32 0> is lowerded to: (XVPERMI $xr2, $xr0, 78) (XVSHUF $xr1, $xr2, $xr0) (XVORI $xr0, $xr1, 0)
Definition at line 2597 of file LoongArchISelLowering.cpp.
References assert(), llvm::SmallVectorImpl< T >::assign(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::is256BitVector(), SDValue(), and Size.
Referenced by lower256BitShuffle().
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Lower VECTOR_SHUFFLE as shift (if possible).
For example: %2 = shufflevector <4 x i32> %0, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 0, i32 1, i32 2> is lowered to: (VBSLL_V $v0, $v0, 4)
%2 = shufflevector <4 x i32> %0, <4 x i32> zeroinitializer, <4 x i32> <i32 4, i32 0, i32 4, i32 2> is lowered to: (VSLLI_D $v0, $v0, 32)
Definition at line 1287 of file LoongArchISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorNumElements(), llvm::TargetLoweringBase::isTypeLegal(), matchShuffleAsShift(), SDValue(), and Size.
Referenced by lower128BitShuffle(), and lower256BitShuffle().
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Lower VECTOR_SHUFFLE as ZERO_EXTEND Or ANY_EXTEND (if possible).
For example: %2 = shufflevector <4 x i32> %0, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 1, i32 4> %3 = bitcast <4 x i32> %2 to <2 x i64> is lowered to: (VREPLI $v1, 0) (VILVL $v0, $v1, $v0)
Definition at line 1520 of file LoongArchISelLowering.cpp.
References DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getFreeze(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::APInt::isAllOnes(), llvm::Lower, llvm::Offset, SDValue(), llvm::LoongArchISD::VILVH, and llvm::LoongArchISD::VILVL.
Referenced by lower128BitShuffle().
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Definition at line 5991 of file LoongArchISelLowering.cpp.
References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::ISD::SHL, and truncateVecElts().
Referenced by performINTRINSIC_WO_CHAINCombine().
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Definition at line 6003 of file LoongArchISelLowering.cpp.
References llvm::ISD::AND, llvm::cast(), DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::isUInt(), and llvm::ISD::UNDEF.
Referenced by performINTRINSIC_WO_CHAINCombine().
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Definition at line 6038 of file LoongArchISelLowering.cpp.
References llvm::cast(), DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::isUInt(), llvm::ISD::UNDEF, and llvm::ISD::XOR.
Referenced by performINTRINSIC_WO_CHAINCombine().
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Definition at line 6021 of file LoongArchISelLowering.cpp.
References llvm::cast(), DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::isUInt(), llvm::ISD::OR, and llvm::ISD::UNDEF.
Referenced by performINTRINSIC_WO_CHAINCombine().
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Definition at line 6055 of file LoongArchISelLowering.cpp.
References DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementType(), llvm::isUInt(), and N.
Referenced by performINTRINSIC_WO_CHAINCombine().
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Definition at line 5964 of file LoongArchISelLowering.cpp.
References llvm::cast(), DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::isInt(), llvm::isUInt(), and llvm::ISD::UNDEF.
Referenced by performINTRINSIC_WO_CHAINCombine().
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Definition at line 767 of file LoongArchISelLowering.cpp.
References assert(), llvm::cast(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), LHS, RHS, and llvm::ISD::SETCC.
Referenced by combineSelectToBinOp(), and lowerSelectToBinOp().
Attempts to match vector shuffle as byte rotation.
Definition at line 1412 of file LoongArchISelLowering.cpp.
References assert(), llvm::Hi, isRepeatedShuffleMask(), llvm::Lo, and llvm::SmallVectorTemplateCommon< T, typename >::size().
Referenced by lowerShuffleAsByteRotate(), lowerVECTOR_SHUFFLEAsByteRotate(), and matchBinaryPermuteShuffle().
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Attempts to match a shuffle mask against the VBSLL, VBSRL, VSLLI and VSRLI instruction.
Definition at line 1212 of file LoongArchISelLowering.cpp.
References llvm::MVT::getIntegerVT(), llvm::MVT::getVectorVT(), isSequentialOrUndefInRange(), llvm::Left, llvm::Low, Size, llvm::LoongArchISD::VBSLL, llvm::LoongArchISD::VBSRL, llvm::LoongArchISD::VSLLI, and llvm::LoongArchISD::VSRLI.
Referenced by lowerShuffleAsShift(), lowerVECTOR_SHUFFLEAsShift(), and matchUnaryPermuteShuffle().
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Definition at line 5045 of file LoongArchISelLowering.cpp.
References llvm::LoongArchISD::BSTRPICK, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), N, SDValue(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::SDNode::use_size().
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Definition at line 5310 of file LoongArchISelLowering.cpp.
References checkBitcastSrcVectorSize(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::Hi, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isSimple(), llvm::Lo, N, Opc, llvm::ISD::OR, performSETCC_BITCASTCombine(), SDValue(), llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, signExtendBitcastSrcVector(), llvm::MVT::SimpleTy, llvm::SelectionDAG::SplitVector(), T, llvm::LoongArchISD::VMSKLTZ, and llvm::LoongArchISD::XVMSKLTZ.
Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().
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Definition at line 5793 of file LoongArchISelLowering.cpp.
References llvm::LoongArchISD::BITREV_4B, llvm::SelectionDAG::getNode(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, llvm::LoongArchISD::REVB_2W, and SDValue().
Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().
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Definition at line 5880 of file LoongArchISelLowering.cpp.
References llvm::LoongArchISD::BR_CC, combine_CC(), DL, llvm::SelectionDAG::getNode(), LHS, N, RHS, and SDValue().
Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().
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Definition at line 6699 of file LoongArchISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::is256BitVector(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), N, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().
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Definition at line 6071 of file LoongArchISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::CTLZ, llvm::ISD::CTPOP, DL, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMA, llvm::ISD::FMUL, llvm::ISD::FSUB, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDNode::getValueType(), llvm::ISD::INSERT_VECTOR_ELT, llvm::LoongArchSubtarget::is64Bit(), legalizeIntrinsicImmArg(), lowerVectorBitClear(), lowerVectorBitClearImm(), lowerVectorBitRevImm(), lowerVectorBitSetImm(), lowerVectorPickVE2GR(), lowerVectorSplatImm(), llvm::ISD::MUL, N, llvm::ISD::OR, llvm::ISD::SDIV, SDValue(), llvm::ISD::SHL, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SUB, truncateVecElts(), llvm::ISD::UDIV, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UREM, llvm::LoongArchISD::VALL_NONZERO, llvm::LoongArchISD::VALL_ZERO, llvm::LoongArchISD::VANY_NONZERO, llvm::LoongArchISD::VANY_ZERO, llvm::LoongArchISD::VPICK_SEXT_ELT, llvm::LoongArchISD::VPICK_ZEXT_ELT, llvm::LoongArchISD::VREPLGR2VR, llvm::LoongArchISD::VREPLVE, and llvm::ISD::XOR.
Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().
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Definition at line 6637 of file LoongArchISelLowering.cpp.
References assert(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::LoongArchISD::MOVGR2FR_W_LA64, N, and SDValue().
Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().
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Definition at line 6625 of file LoongArchISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::LoongArchISD::MOVFR2GR_S_LA64, N, and SDValue().
Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().
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Definition at line 5405 of file LoongArchISelLowering.cpp.
References llvm::ISD::AND, llvm::LoongArchISD::BSTRINS, llvm::SelectionDAG::computeKnownBits(), llvm::dbgs(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::SelectionDAG::getSignedConstant(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), llvm::APInt::isSubsetOf(), LLVM_DEBUG, N, SDValue(), llvm::ISD::SHL, llvm::ISD::SRL, std::swap(), and llvm::KnownBits::Zero.
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Definition at line 5895 of file LoongArchISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::cast(), combine_CC(), DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLen(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSignedConstant(), llvm::isa(), llvm::isInt(), llvm::isNullConstant(), LHS, N, RHS, SDValue(), llvm::LoongArchISD::SELECT_CC, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SRA, and std::swap().
Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().
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Definition at line 5237 of file LoongArchISelLowering.cpp.
References llvm::cast(), llvm::ISD::DELETED_NODE, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::EVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), N, Opc, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, T, llvm::LoongArchISD::VMSKEQZ, llvm::LoongArchISD::VMSKGEZ, llvm::LoongArchISD::VMSKLTZ, llvm::LoongArchISD::VMSKNEZ, llvm::LoongArchISD::XVMSKEQZ, llvm::LoongArchISD::XVMSKGEZ, llvm::LoongArchISD::XVMSKLTZ, and llvm::LoongArchISD::XVMSKNEZ.
Referenced by performBITCASTCombine().
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Definition at line 5724 of file LoongArchISelLowering.cpp.
References llvm::ISD::AND, llvm::cast(), checkValueWidth(), llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ConstantSDNode::getSExtValue(), llvm::SDNode::getValueType(), N, llvm::SelectionDAG::ReplaceAllUsesWith(), SDValue(), llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::SEXTLOAD, llvm::ISD::TRUNCATE, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.
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Definition at line 6668 of file LoongArchISelLowering.cpp.
References llvm::LoongArchISD::BUILD_PAIR_F64, llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::Hi, llvm::SDNode::isUndef(), llvm::Lo, N, and SDValue().
Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().
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Definition at line 5135 of file LoongArchISelLowering.cpp.
References llvm::ISD::AND, llvm::LoongArchISD::BSTRPICK, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), N, and SDValue().
Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine(), and llvm::MipsSETargetLowering::PerformDAGCombine().
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Definition at line 6652 of file LoongArchISelLowering.cpp.
References llvm::APInt::getAllOnes(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), N, SDValue(), and llvm::TargetLowering::SimplifyDemandedBits().
Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().
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Definition at line 4643 of file LoongArchISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::Acquire, llvm::AcquireRelease, assert(), llvm::ISD::BUILD_PAIR, llvm::cast(), DL, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), llvm_unreachable, llvm::Monotonic, N, llvm::Release, Results, SDValue(), llvm::SequentiallyConsistent, llvm::SelectionDAG::setNodeMemRefs(), and llvm::SelectionDAG::SplitScalar().
Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().
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Definition at line 4576 of file LoongArchISelLowering.cpp.
References llvm_unreachable, N, replaceVecCondBranchResults(), replaceVPICKVE2GRResults(), Results, llvm::LoongArchISD::VALL_NONZERO, llvm::LoongArchISD::VALL_ZERO, llvm::LoongArchISD::VANY_NONZERO, llvm::LoongArchISD::VANY_ZERO, llvm::LoongArchISD::VPICK_SEXT_ELT, and llvm::LoongArchISD::VPICK_ZEXT_ELT.
Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().
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Definition at line 4562 of file LoongArchISelLowering.cpp.
References DL, llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), N, Results, and llvm::ISD::TRUNCATE.
Referenced by replaceINTRINSIC_WO_CHAINResults().
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Definition at line 4541 of file LoongArchISelLowering.cpp.
References DL, emitErrorAndReplaceIntrinsicResults(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementType(), llvm::isUInt(), Results, and llvm::ISD::TRUNCATE.
Referenced by replaceINTRINSIC_WO_CHAINResults().
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Definition at line 5211 of file LoongArchISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::BUILD_VECTOR, DL, llvm::ISD::FREEZE, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm_unreachable, llvm::ISD::OR, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, signExtendBitcastSrcVector(), llvm::ISD::TRUNCATE, llvm::ISD::VSELECT, and llvm::ISD::XOR.
Referenced by combineBitcastvxi1(), performBITCASTCombine(), signExtendBitcastSrcVector(), and signExtendBitcastSrcVector().
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| "Number of tail calls" | ) | 
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Definition at line 923 of file LoongArchISelLowering.cpp.
References llvm::ISD::AND, llvm::bit_width(), llvm::CallingConv::C, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::getSetCCSwappedOperands(), llvm::isa(), llvm::isInt(), llvm::isMask_64(), llvm::isNullConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), RHS, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SHL, and std::swap().
Referenced by combine_CC(), and combine_CC().
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Definition at line 5983 of file LoongArchISelLowering.cpp.
References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), and llvm::SDValue::getScalarValueSizeInBits().
Referenced by lowerMSABitClear(), lowerVectorBitClear(), and performINTRINSIC_WO_CHAINCombine().
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Definition at line 7954 of file LoongArchISelLowering.cpp.
References assert(), llvm::LoongArchISD::BUILD_PAIR_F64, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::SelectionDAG::getCopyFromReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getRegInfo(), llvm::CCValAssign::getValVT(), llvm::Hi, llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), and llvm::Lo.
Referenced by llvm::LoongArchTargetLowering::LowerFormalArguments().
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Definition at line 7929 of file LoongArchISelLowering.cpp.
References llvm::CCValAssign::BCvt, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::CCValAssign::Full, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getStoreSize(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm_unreachable, and llvm::ISD::NON_EXTLOAD.
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Definition at line 7896 of file LoongArchISelLowering.cpp.
References llvm::LoongArchMachineFunctionInfo::addSExt32Register(), llvm::BitWidth, convertLocVTToValVT(), DL, llvm::Function::getArg(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::Type::getIntegerBitWidth(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::EVT::getSimpleVT(), llvm::Value::getType(), and llvm::Type::isIntegerTy().
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Definition at line 1182 of file LoongArchISelLowering.cpp.
References DL, llvm::SelectionDAG::getBitcast(), llvm::MVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::MVT::isFloatingPoint(), llvm::TargetLoweringBase::isTypeLegal(), SDValue(), and llvm::widenShuffleMaskElts().
Referenced by lower128BitShuffle(), and lower256BitShuffle().
Definition at line 7599 of file LoongArchISelLowering.cpp.
Referenced by CC_LoongArch(), and llvm::CC_RISCV().
Definition at line 7603 of file LoongArchISelLowering.cpp.
Referenced by CC_LoongArch(), and llvm::CC_RISCV().
Definition at line 7594 of file LoongArchISelLowering.cpp.
Referenced by llvm::CC_CSKY_ABIV2_SOFT_64(), CC_LoongArch(), CC_LoongArchAssign2GRLen(), llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), CC_RISCVAssign2XLen(), llvm::LoongArchTargetLowering::LowerFormalArguments(), and llvm::Ret_CSKY_ABIV2_SOFT_64().
Definition at line 7607 of file LoongArchISelLowering.cpp.
Referenced by allocateRVVReg(), and CC_LoongArch().
Definition at line 7611 of file LoongArchISelLowering.cpp.
Referenced by CC_LoongArch().
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