LLVM 19.0.0git
PPCISelLowering.cpp
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1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCISelLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCISelLowering.h"
16#include "PPC.h"
17#include "PPCCCState.h"
18#include "PPCCallingConv.h"
19#include "PPCFrameLowering.h"
20#include "PPCInstrInfo.h"
22#include "PPCPerfectShuffle.h"
23#include "PPCRegisterInfo.h"
24#include "PPCSubtarget.h"
25#include "PPCTargetMachine.h"
26#include "llvm/ADT/APFloat.h"
27#include "llvm/ADT/APInt.h"
28#include "llvm/ADT/APSInt.h"
29#include "llvm/ADT/ArrayRef.h"
30#include "llvm/ADT/DenseMap.h"
31#include "llvm/ADT/STLExtras.h"
33#include "llvm/ADT/SmallSet.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/ADT/StringRef.h"
60#include "llvm/IR/CallingConv.h"
61#include "llvm/IR/Constant.h"
62#include "llvm/IR/Constants.h"
63#include "llvm/IR/DataLayout.h"
64#include "llvm/IR/DebugLoc.h"
66#include "llvm/IR/Function.h"
67#include "llvm/IR/GlobalValue.h"
68#include "llvm/IR/IRBuilder.h"
70#include "llvm/IR/Intrinsics.h"
71#include "llvm/IR/IntrinsicsPowerPC.h"
72#include "llvm/IR/Module.h"
73#include "llvm/IR/Type.h"
74#include "llvm/IR/Use.h"
75#include "llvm/IR/Value.h"
76#include "llvm/MC/MCContext.h"
77#include "llvm/MC/MCExpr.h"
87#include "llvm/Support/Debug.h"
89#include "llvm/Support/Format.h"
95#include <algorithm>
96#include <cassert>
97#include <cstdint>
98#include <iterator>
99#include <list>
100#include <optional>
101#include <utility>
102#include <vector>
103
104using namespace llvm;
105
106#define DEBUG_TYPE "ppc-lowering"
107
108static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
109cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
110
111static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
112cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
113
114static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
115cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
116
117static cl::opt<bool> DisableSCO("disable-ppc-sco",
118cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
119
120static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
121cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
122
123static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
124cl::desc("use absolute jump tables on ppc"), cl::Hidden);
125
126static cl::opt<bool>
127 DisablePerfectShuffle("ppc-disable-perfect-shuffle",
128 cl::desc("disable vector permute decomposition"),
129 cl::init(true), cl::Hidden);
130
132 "disable-auto-paired-vec-st",
133 cl::desc("disable automatically generated 32byte paired vector stores"),
134 cl::init(true), cl::Hidden);
135
137 "ppc-min-jump-table-entries", cl::init(64), cl::Hidden,
138 cl::desc("Set minimum number of entries to use a jump table on PPC"));
139
141 "ppc-gather-alias-max-depth", cl::init(18), cl::Hidden,
142 cl::desc("max depth when checking alias info in GatherAllAliases()"));
143
144STATISTIC(NumTailCalls, "Number of tail calls");
145STATISTIC(NumSiblingCalls, "Number of sibling calls");
146STATISTIC(ShufflesHandledWithVPERM,
147 "Number of shuffles lowered to a VPERM or XXPERM");
148STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed");
149
150static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
151
152static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
153
154static const char AIXSSPCanaryWordName[] = "__ssp_canary_word";
155
156// A faster local-[exec|dynamic] TLS access sequence (enabled with the
157// -maix-small-local-[exec|dynamic]-tls option) can be produced for TLS
158// variables; consistent with the IBM XL compiler, we apply a max size of
159// slightly under 32KB.
161
162// FIXME: Remove this once the bug has been fixed!
164
166 const PPCSubtarget &STI)
167 : TargetLowering(TM), Subtarget(STI) {
168 // Initialize map that relates the PPC addressing modes to the computed flags
169 // of a load/store instruction. The map is used to determine the optimal
170 // addressing mode when selecting load and stores.
171 initializeAddrModeMap();
172 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
173 // arguments are at least 4/8 bytes aligned.
174 bool isPPC64 = Subtarget.isPPC64();
175 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
176
177 // Set up the register classes.
178 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
179 if (!useSoftFloat()) {
180 if (hasSPE()) {
181 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
182 // EFPU2 APU only supports f32
183 if (!Subtarget.hasEFPU2())
184 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
185 } else {
186 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
187 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
188 }
189 }
190
191 // Match BITREVERSE to customized fast code sequence in the td file.
194
195 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
197
198 // Custom lower inline assembly to check for special registers.
201
202 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
203 for (MVT VT : MVT::integer_valuetypes()) {
206 }
207
208 if (Subtarget.isISA3_0()) {
209 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
210 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
211 setTruncStoreAction(MVT::f64, MVT::f16, Legal);
212 setTruncStoreAction(MVT::f32, MVT::f16, Legal);
213 } else {
214 // No extending loads from f16 or HW conversions back and forth.
215 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
218 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
221 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
222 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
223 }
224
225 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
226
227 // PowerPC has pre-inc load and store's.
238 if (!Subtarget.hasSPE()) {
243 }
244
245 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
246 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
247 for (MVT VT : ScalarIntVTs) {
252 }
253
254 if (Subtarget.useCRBits()) {
256
257 if (isPPC64 || Subtarget.hasFPCVT()) {
260 isPPC64 ? MVT::i64 : MVT::i32);
263 isPPC64 ? MVT::i64 : MVT::i32);
264
267 isPPC64 ? MVT::i64 : MVT::i32);
270 isPPC64 ? MVT::i64 : MVT::i32);
271
274 isPPC64 ? MVT::i64 : MVT::i32);
277 isPPC64 ? MVT::i64 : MVT::i32);
278
281 isPPC64 ? MVT::i64 : MVT::i32);
284 isPPC64 ? MVT::i64 : MVT::i32);
285 } else {
290 }
291
292 // PowerPC does not support direct load/store of condition registers.
295
296 // FIXME: Remove this once the ANDI glue bug is fixed:
297 if (ANDIGlueBug)
299
300 for (MVT VT : MVT::integer_valuetypes()) {
303 setTruncStoreAction(VT, MVT::i1, Expand);
304 }
305
306 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
307 }
308
309 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
310 // PPC (the libcall is not available).
315
316 // We do not currently implement these libm ops for PowerPC.
317 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
318 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
319 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
320 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
322 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
323
324 // PowerPC has no SREM/UREM instructions unless we are on P9
325 // On P9 we may use a hardware instruction to compute the remainder.
326 // When the result of both the remainder and the division is required it is
327 // more efficient to compute the remainder from the result of the division
328 // rather than use the remainder instruction. The instructions are legalized
329 // directly because the DivRemPairsPass performs the transformation at the IR
330 // level.
331 if (Subtarget.isISA3_0()) {
336 } else {
341 }
342
343 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
352
353 // Handle constrained floating-point operations of scalar.
354 // TODO: Handle SPE specific operation.
360
365
366 if (!Subtarget.hasSPE()) {
369 }
370
371 if (Subtarget.hasVSX()) {
374 }
375
376 if (Subtarget.hasFSQRT()) {
379 }
380
381 if (Subtarget.hasFPRND()) {
386
391 }
392
393 // We don't support sin/cos/sqrt/fmod/pow
404
405 // MASS transformation for LLVM intrinsics with replicating fast-math flag
406 // to be consistent to PPCGenScalarMASSEntries pass
407 if (TM.getOptLevel() == CodeGenOptLevel::Aggressive) {
420 }
421
422 if (Subtarget.hasSPE()) {
425 } else {
426 setOperationAction(ISD::FMA , MVT::f64, Legal);
427 setOperationAction(ISD::FMA , MVT::f32, Legal);
428 }
429
430 if (Subtarget.hasSPE())
431 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
432
434
435 // If we're enabling GP optimizations, use hardware square root
436 if (!Subtarget.hasFSQRT() &&
437 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
438 Subtarget.hasFRE()))
440
441 if (!Subtarget.hasFSQRT() &&
442 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
443 Subtarget.hasFRES()))
445
446 if (Subtarget.hasFCPSGN()) {
449 } else {
452 }
453
454 if (Subtarget.hasFPRND()) {
459
464 }
465
466 // Prior to P10, PowerPC does not have BSWAP, but we can use vector BSWAP
467 // instruction xxbrd to speed up scalar BSWAP64.
468 if (Subtarget.isISA3_1()) {
471 } else {
474 ISD::BSWAP, MVT::i64,
475 (Subtarget.hasP9Vector() && Subtarget.isPPC64()) ? Custom : Expand);
476 }
477
478 // CTPOP or CTTZ were introduced in P8/P9 respectively
479 if (Subtarget.isISA3_0()) {
480 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
481 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
482 } else {
483 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
484 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
485 }
486
487 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
490 } else {
493 }
494
495 // PowerPC does not have ROTR
498
499 if (!Subtarget.useCRBits()) {
500 // PowerPC does not have Select
505 }
506
507 // PowerPC wants to turn select_cc of FP into fsel when possible.
510
511 // PowerPC wants to optimize integer setcc a bit
512 if (!Subtarget.useCRBits())
514
515 if (Subtarget.hasFPU()) {
519
523 }
524
525 // PowerPC does not have BRCOND which requires SetCC
526 if (!Subtarget.useCRBits())
528
530
531 if (Subtarget.hasSPE()) {
532 // SPE has built-in conversions
539
540 // SPE supports signaling compare of f32/f64.
543 } else {
544 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
547
548 // PowerPC does not have [U|S]INT_TO_FP
553 }
554
555 if (Subtarget.hasDirectMove() && isPPC64) {
560 if (TM.Options.UnsafeFPMath) {
569 }
570 } else {
575 }
576
577 // We cannot sextinreg(i1). Expand to shifts.
579
580 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
581 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
582 // support continuation, user-level threading, and etc.. As a result, no
583 // other SjLj exception interfaces are implemented and please don't build
584 // your own exception handling based on them.
585 // LLVM/Clang supports zero-cost DWARF exception handling.
588
589 // We want to legalize GlobalAddress and ConstantPool nodes into the
590 // appropriate instructions to materialize the address.
601
602 // TRAP is legal.
603 setOperationAction(ISD::TRAP, MVT::Other, Legal);
604
605 // TRAMPOLINE is custom lowered.
608
609 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
611
612 if (Subtarget.is64BitELFABI()) {
613 // VAARG always uses double-word chunks, so promote anything smaller.
615 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64);
617 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64);
619 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64);
621 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
623 } else if (Subtarget.is32BitELFABI()) {
624 // VAARG is custom lowered with the 32-bit SVR4 ABI.
627 } else
629
630 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
631 if (Subtarget.is32BitELFABI())
633 else
635
636 // Use the default implementation.
637 setOperationAction(ISD::VAEND , MVT::Other, Expand);
646
647 // We want to custom lower some of our intrinsics.
653
654 // To handle counter-based loop conditions.
656
661
662 // Comparisons that require checking two conditions.
663 if (Subtarget.hasSPE()) {
668 }
681
684
685 if (Subtarget.has64BitSupport()) {
686 // They also have instructions for converting between i64 and fp.
695 // This is just the low 32 bits of a (signed) fp->i64 conversion.
696 // We cannot do this with Promote because i64 is not a legal type.
699
700 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
703 }
704 } else {
705 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
706 if (Subtarget.hasSPE()) {
709 } else {
712 }
713 }
714
715 // With the instructions enabled under FPCVT, we can do everything.
716 if (Subtarget.hasFPCVT()) {
717 if (Subtarget.has64BitSupport()) {
726 }
727
736 }
737
738 if (Subtarget.use64BitRegs()) {
739 // 64-bit PowerPC implementations can support i64 types directly
740 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
741 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
743 // 64-bit PowerPC wants to expand i128 shifts itself.
747 } else {
748 // 32-bit PowerPC wants to expand i64 shifts itself.
752 }
753
754 // PowerPC has better expansions for funnel shifts than the generic
755 // TargetLowering::expandFunnelShift.
756 if (Subtarget.has64BitSupport()) {
759 }
762
763 if (Subtarget.hasVSX()) {
768 }
769
770 if (Subtarget.hasAltivec()) {
771 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
776 }
777 // First set operation action for all vector types to expand. Then we
778 // will selectively turn on ones that can be effectively codegen'd.
780 // add/sub are legal for all supported vector VT's.
783
784 // For v2i64, these are only valid with P8Vector. This is corrected after
785 // the loop.
786 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
791 }
792 else {
797 }
798
799 if (Subtarget.hasVSX()) {
802 }
803
804 // Vector instructions introduced in P8
805 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
808 }
809 else {
812 }
813
814 // Vector instructions introduced in P9
815 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
817 else
819
820 // We promote all shuffles to v16i8.
822 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
823
824 // We promote all non-typed operations to v4i32.
826 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
828 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
830 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
832 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
834 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
837 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
839 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
840
841 // No other operations are legal.
880
881 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
882 setTruncStoreAction(VT, InnerVT, Expand);
885 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
886 }
887 }
889 if (!Subtarget.hasP8Vector()) {
890 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
891 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
892 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
893 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
894 }
895
896 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
897 // with merges, splats, etc.
899
900 // Vector truncates to sub-word integer that fit in an Altivec/VSX register
901 // are cheap, so handle them before they get expanded to scalar.
907
908 setOperationAction(ISD::AND , MVT::v4i32, Legal);
909 setOperationAction(ISD::OR , MVT::v4i32, Legal);
910 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
911 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
913 Subtarget.useCRBits() ? Legal : Expand);
914 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
924 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
927
928 // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
929 setOperationAction(ISD::ROTL, MVT::v1i128, Custom);
930 // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w).
931 if (Subtarget.hasAltivec())
932 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
934 // With hasP8Altivec set, we can lower ISD::ROTL to vrld.
935 if (Subtarget.hasP8Altivec())
936 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
937
938 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
939 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
940 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
941 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
942
943 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
944 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
945
946 if (Subtarget.hasVSX()) {
947 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
948 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 }
951
952 if (Subtarget.hasP8Altivec())
953 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
954 else
955 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
956
957 if (Subtarget.isISA3_1()) {
958 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
959 setOperationAction(ISD::MULHS, MVT::v2i64, Legal);
960 setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
961 setOperationAction(ISD::MULHS, MVT::v4i32, Legal);
962 setOperationAction(ISD::MULHU, MVT::v4i32, Legal);
963 setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
964 setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
965 setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
966 setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
967 setOperationAction(ISD::UREM, MVT::v2i64, Legal);
968 setOperationAction(ISD::SREM, MVT::v2i64, Legal);
969 setOperationAction(ISD::UREM, MVT::v4i32, Legal);
970 setOperationAction(ISD::SREM, MVT::v4i32, Legal);
971 setOperationAction(ISD::UREM, MVT::v1i128, Legal);
972 setOperationAction(ISD::SREM, MVT::v1i128, Legal);
973 setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
974 setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
975 setOperationAction(ISD::ROTL, MVT::v1i128, Legal);
976 }
977
978 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
979 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
980
983
988
989 // Altivec does not contain unordered floating-point compare instructions
990 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
992 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
994
995 if (Subtarget.hasVSX()) {
998 if (Subtarget.hasP8Vector()) {
1001 }
1002 if (Subtarget.hasDirectMove() && isPPC64) {
1011 }
1013
1014 // The nearbyint variants are not allowed to raise the inexact exception
1015 // so we can only code-gen them with unsafe math.
1016 if (TM.Options.UnsafeFPMath) {
1019 }
1020
1021 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1022 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1023 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1025 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1026 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
1029
1031 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1032 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
1035
1036 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
1037 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1038
1039 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
1040 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
1041
1042 // Share the Altivec comparison restrictions.
1043 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
1044 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
1045 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
1046 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
1047
1048 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1049 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
1050
1052
1053 if (Subtarget.hasP8Vector())
1054 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
1055
1056 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
1057
1058 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
1059 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
1060 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
1061
1062 if (Subtarget.hasP8Altivec()) {
1063 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1064 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
1065 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1066
1067 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1068 // SRL, but not for SRA because of the instructions available:
1069 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
1070 // doing
1071 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
1072 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
1073 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1074
1075 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
1076 }
1077 else {
1078 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
1079 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
1080 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
1081
1082 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1083
1084 // VSX v2i64 only supports non-arithmetic operations.
1085 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
1086 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
1087 }
1088
1089 if (Subtarget.isISA3_1())
1090 setOperationAction(ISD::SETCC, MVT::v1i128, Legal);
1091 else
1092 setOperationAction(ISD::SETCC, MVT::v1i128, Expand);
1093
1094 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
1095 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
1097 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
1098
1100
1109
1110 // Custom handling for partial vectors of integers converted to
1111 // floating point. We already have optimal handling for v2i32 through
1112 // the DAG combine, so those aren't necessary.
1129
1130 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
1131 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
1132 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
1133 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
1136
1139
1140 // Handle constrained floating-point operations of vector.
1141 // The predictor is `hasVSX` because altivec instruction has
1142 // no exception but VSX vector instruction has.
1156
1170
1171 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
1172 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
1173
1174 for (MVT FPT : MVT::fp_valuetypes())
1175 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
1176
1177 // Expand the SELECT to SELECT_CC
1179
1180 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1181 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1182
1183 // No implementation for these ops for PowerPC.
1185 setOperationAction(ISD::FSIN, MVT::f128, Expand);
1186 setOperationAction(ISD::FCOS, MVT::f128, Expand);
1187 setOperationAction(ISD::FPOW, MVT::f128, Expand);
1189 setOperationAction(ISD::FREM, MVT::f128, Expand);
1190 }
1191
1192 if (Subtarget.hasP8Altivec()) {
1193 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
1194 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
1195 }
1196
1197 if (Subtarget.hasP9Vector()) {
1200
1201 // Test data class instructions store results in CR bits.
1202 if (Subtarget.useCRBits()) {
1206 }
1207
1208 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1209 // SRL, but not for SRA because of the instructions available:
1210 // VS{RL} and VS{RL}O.
1211 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
1212 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
1213 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1214
1215 setOperationAction(ISD::FADD, MVT::f128, Legal);
1216 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1217 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1218 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1220
1221 setOperationAction(ISD::FMA, MVT::f128, Legal);
1228
1230 setOperationAction(ISD::FRINT, MVT::f128, Legal);
1232 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
1235
1239
1240 // Handle constrained floating-point operations of fp128
1257 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
1258 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
1259 setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
1260 setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
1261 } else if (Subtarget.hasVSX()) {
1264
1265 AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32);
1266 AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32);
1267
1268 // Set FADD/FSUB as libcall to avoid the legalizer to expand the
1269 // fp_to_uint and int_to_fp.
1272
1273 setOperationAction(ISD::FMUL, MVT::f128, Expand);
1274 setOperationAction(ISD::FDIV, MVT::f128, Expand);
1275 setOperationAction(ISD::FNEG, MVT::f128, Expand);
1276 setOperationAction(ISD::FABS, MVT::f128, Expand);
1278 setOperationAction(ISD::FMA, MVT::f128, Expand);
1280
1281 // Expand the fp_extend if the target type is fp128.
1284
1285 // Expand the fp_round if the source type is fp128.
1286 for (MVT VT : {MVT::f32, MVT::f64}) {
1289 }
1290
1295
1296 // Lower following f128 select_cc pattern:
1297 // select_cc x, y, tv, fv, cc -> select_cc (setcc x, y, cc), 0, tv, fv, NE
1299
1300 // We need to handle f128 SELECT_CC with integer result type.
1302 setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand);
1303 }
1304
1305 if (Subtarget.hasP9Altivec()) {
1306 if (Subtarget.isISA3_1()) {
1311 } else {
1314 }
1322
1323 setOperationAction(ISD::ABDU, MVT::v16i8, Legal);
1324 setOperationAction(ISD::ABDU, MVT::v8i16, Legal);
1325 setOperationAction(ISD::ABDU, MVT::v4i32, Legal);
1326 setOperationAction(ISD::ABDS, MVT::v4i32, Legal);
1327 }
1328
1329 if (Subtarget.hasP10Vector()) {
1331 }
1332 }
1333
1334 if (Subtarget.pairedVectorMemops()) {
1335 addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass);
1336 setOperationAction(ISD::LOAD, MVT::v256i1, Custom);
1337 setOperationAction(ISD::STORE, MVT::v256i1, Custom);
1338 }
1339 if (Subtarget.hasMMA()) {
1340 if (Subtarget.isISAFuture())
1341 addRegisterClass(MVT::v512i1, &PPC::WACCRCRegClass);
1342 else
1343 addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass);
1344 setOperationAction(ISD::LOAD, MVT::v512i1, Custom);
1345 setOperationAction(ISD::STORE, MVT::v512i1, Custom);
1347 }
1348
1349 if (Subtarget.has64BitSupport())
1351
1352 if (Subtarget.isISA3_1())
1353 setOperationAction(ISD::SRA, MVT::v1i128, Legal);
1354
1355 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1356
1357 if (!isPPC64) {
1360 }
1361
1366 }
1367
1369
1370 if (Subtarget.hasAltivec()) {
1371 // Altivec instructions set fields to all zeros or all ones.
1373 }
1374
1375 setLibcallName(RTLIB::MULO_I128, nullptr);
1376 if (!isPPC64) {
1377 // These libcalls are not available in 32-bit.
1378 setLibcallName(RTLIB::SHL_I128, nullptr);
1379 setLibcallName(RTLIB::SRL_I128, nullptr);
1380 setLibcallName(RTLIB::SRA_I128, nullptr);
1381 setLibcallName(RTLIB::MUL_I128, nullptr);
1382 setLibcallName(RTLIB::MULO_I64, nullptr);
1383 }
1384
1387 else if (isPPC64)
1389 else
1391
1392 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1393
1394 // We have target-specific dag combine patterns for the following nodes:
1397 if (Subtarget.hasFPCVT())
1400 if (Subtarget.useCRBits())
1404
1406
1408
1409 if (Subtarget.useCRBits()) {
1411 }
1412
1413 setLibcallName(RTLIB::LOG_F128, "logf128");
1414 setLibcallName(RTLIB::LOG2_F128, "log2f128");
1415 setLibcallName(RTLIB::LOG10_F128, "log10f128");
1416 setLibcallName(RTLIB::EXP_F128, "expf128");
1417 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1418 setLibcallName(RTLIB::SIN_F128, "sinf128");
1419 setLibcallName(RTLIB::COS_F128, "cosf128");
1420 setLibcallName(RTLIB::SINCOS_F128, "sincosf128");
1421 setLibcallName(RTLIB::POW_F128, "powf128");
1422 setLibcallName(RTLIB::FMIN_F128, "fminf128");
1423 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1424 setLibcallName(RTLIB::REM_F128, "fmodf128");
1425 setLibcallName(RTLIB::SQRT_F128, "sqrtf128");
1426 setLibcallName(RTLIB::CEIL_F128, "ceilf128");
1427 setLibcallName(RTLIB::FLOOR_F128, "floorf128");
1428 setLibcallName(RTLIB::TRUNC_F128, "truncf128");
1429 setLibcallName(RTLIB::ROUND_F128, "roundf128");
1430 setLibcallName(RTLIB::LROUND_F128, "lroundf128");
1431 setLibcallName(RTLIB::LLROUND_F128, "llroundf128");
1432 setLibcallName(RTLIB::RINT_F128, "rintf128");
1433 setLibcallName(RTLIB::LRINT_F128, "lrintf128");
1434 setLibcallName(RTLIB::LLRINT_F128, "llrintf128");
1435 setLibcallName(RTLIB::NEARBYINT_F128, "nearbyintf128");
1436 setLibcallName(RTLIB::FMA_F128, "fmaf128");
1437 setLibcallName(RTLIB::FREXP_F128, "frexpf128");
1438
1439 if (Subtarget.isAIXABI()) {
1440 setLibcallName(RTLIB::MEMCPY, isPPC64 ? "___memmove64" : "___memmove");
1441 setLibcallName(RTLIB::MEMMOVE, isPPC64 ? "___memmove64" : "___memmove");
1442 setLibcallName(RTLIB::MEMSET, isPPC64 ? "___memset64" : "___memset");
1443 setLibcallName(RTLIB::BZERO, isPPC64 ? "___bzero64" : "___bzero");
1444 }
1445
1446 // With 32 condition bits, we don't need to sink (and duplicate) compares
1447 // aggressively in CodeGenPrep.
1448 if (Subtarget.useCRBits()) {
1451 }
1452
1453 // TODO: The default entry number is set to 64. This stops most jump table
1454 // generation on PPC. But it is good for current PPC HWs because the indirect
1455 // branch instruction mtctr to the jump table may lead to bad branch predict.
1456 // Re-evaluate this value on future HWs that can do better with mtctr.
1458
1460
1461 switch (Subtarget.getCPUDirective()) {
1462 default: break;
1463 case PPC::DIR_970:
1464 case PPC::DIR_A2:
1465 case PPC::DIR_E500:
1466 case PPC::DIR_E500mc:
1467 case PPC::DIR_E5500:
1468 case PPC::DIR_PWR4:
1469 case PPC::DIR_PWR5:
1470 case PPC::DIR_PWR5X:
1471 case PPC::DIR_PWR6:
1472 case PPC::DIR_PWR6X:
1473 case PPC::DIR_PWR7:
1474 case PPC::DIR_PWR8:
1475 case PPC::DIR_PWR9:
1476 case PPC::DIR_PWR10:
1480 break;
1481 }
1482
1483 if (Subtarget.enableMachineScheduler())
1485 else
1487
1489
1490 // The Freescale cores do better with aggressive inlining of memcpy and
1491 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1492 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc ||
1493 Subtarget.getCPUDirective() == PPC::DIR_E5500) {
1494 MaxStoresPerMemset = 32;
1496 MaxStoresPerMemcpy = 32;
1500 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) {
1501 // The A2 also benefits from (very) aggressive inlining of memcpy and
1502 // friends. The overhead of a the function call, even when warm, can be
1503 // over one hundred cycles.
1504 MaxStoresPerMemset = 128;
1505 MaxStoresPerMemcpy = 128;
1506 MaxStoresPerMemmove = 128;
1507 MaxLoadsPerMemcmp = 128;
1508 } else {
1511 }
1512
1513 IsStrictFPEnabled = true;
1514
1515 // Let the subtarget (CPU) decide if a predictable select is more expensive
1516 // than the corresponding branch. This information is used in CGP to decide
1517 // when to convert selects into branches.
1519
1521}
1522
1523// *********************************** NOTE ************************************
1524// For selecting load and store instructions, the addressing modes are defined
1525// as ComplexPatterns in PPCInstrInfo.td, which are then utilized in the TD
1526// patterns to match the load the store instructions.
1527//
1528// The TD definitions for the addressing modes correspond to their respective
1529// Select<AddrMode>Form() function in PPCISelDAGToDAG.cpp. These functions rely
1530// on SelectOptimalAddrMode(), which calls computeMOFlags() to compute the
1531// address mode flags of a particular node. Afterwards, the computed address
1532// flags are passed into getAddrModeForFlags() in order to retrieve the optimal
1533// addressing mode. SelectOptimalAddrMode() then sets the Base and Displacement
1534// accordingly, based on the preferred addressing mode.
1535//
1536// Within PPCISelLowering.h, there are two enums: MemOpFlags and AddrMode.
1537// MemOpFlags contains all the possible flags that can be used to compute the
1538// optimal addressing mode for load and store instructions.
1539// AddrMode contains all the possible load and store addressing modes available
1540// on Power (such as DForm, DSForm, DQForm, XForm, etc.)
1541//
1542// When adding new load and store instructions, it is possible that new address
1543// flags may need to be added into MemOpFlags, and a new addressing mode will
1544// need to be added to AddrMode. An entry of the new addressing mode (consisting
1545// of the minimal and main distinguishing address flags for the new load/store
1546// instructions) will need to be added into initializeAddrModeMap() below.
1547// Finally, when adding new addressing modes, the getAddrModeForFlags() will
1548// need to be updated to account for selecting the optimal addressing mode.
1549// *****************************************************************************
1550/// Initialize the map that relates the different addressing modes of the load
1551/// and store instructions to a set of flags. This ensures the load/store
1552/// instruction is correctly matched during instruction selection.
1553void PPCTargetLowering::initializeAddrModeMap() {
1554 AddrModesMap[PPC::AM_DForm] = {
1555 // LWZ, STW
1560 // LBZ, LHZ, STB, STH
1565 // LHA
1570 // LFS, LFD, STFS, STFD
1575 };
1576 AddrModesMap[PPC::AM_DSForm] = {
1577 // LWA
1581 // LD, STD
1585 // DFLOADf32, DFLOADf64, DSTOREf32, DSTOREf64
1589 };
1590 AddrModesMap[PPC::AM_DQForm] = {
1591 // LXV, STXV
1595 };
1596 AddrModesMap[PPC::AM_PrefixDForm] = {PPC::MOF_RPlusSImm34 |
1598 // TODO: Add mapping for quadword load/store.
1599}
1600
1601/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1602/// the desired ByVal argument alignment.
1603static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign) {
1604 if (MaxAlign == MaxMaxAlign)
1605 return;
1606 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1607 if (MaxMaxAlign >= 32 &&
1608 VTy->getPrimitiveSizeInBits().getFixedValue() >= 256)
1609 MaxAlign = Align(32);
1610 else if (VTy->getPrimitiveSizeInBits().getFixedValue() >= 128 &&
1611 MaxAlign < 16)
1612 MaxAlign = Align(16);
1613 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1614 Align EltAlign;
1615 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1616 if (EltAlign > MaxAlign)
1617 MaxAlign = EltAlign;
1618 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1619 for (auto *EltTy : STy->elements()) {
1620 Align EltAlign;
1621 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1622 if (EltAlign > MaxAlign)
1623 MaxAlign = EltAlign;
1624 if (MaxAlign == MaxMaxAlign)
1625 break;
1626 }
1627 }
1628}
1629
1630/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1631/// function arguments in the caller parameter area.
1633 const DataLayout &DL) const {
1634 // 16byte and wider vectors are passed on 16byte boundary.
1635 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1636 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
1637 if (Subtarget.hasAltivec())
1638 getMaxByValAlign(Ty, Alignment, Align(16));
1639 return Alignment.value();
1640}
1641
1643 return Subtarget.useSoftFloat();
1644}
1645
1647 return Subtarget.hasSPE();
1648}
1649
1651 return VT.isScalarInteger();
1652}
1653
1655 Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const {
1656 if (!Subtarget.isPPC64() || !Subtarget.hasVSX())
1657 return false;
1658
1659 if (auto *VTy = dyn_cast<VectorType>(VectorTy)) {
1660 if (VTy->getScalarType()->isIntegerTy()) {
1661 // ElemSizeInBits 8/16 can fit in immediate field, not needed here.
1662 if (ElemSizeInBits == 32) {
1663 Index = Subtarget.isLittleEndian() ? 2 : 1;
1664 return true;
1665 }
1666 if (ElemSizeInBits == 64) {
1667 Index = Subtarget.isLittleEndian() ? 1 : 0;
1668 return true;
1669 }
1670 }
1671 }
1672 return false;
1673}
1674
1675const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1676 switch ((PPCISD::NodeType)Opcode) {
1677 case PPCISD::FIRST_NUMBER: break;
1678 case PPCISD::FSEL: return "PPCISD::FSEL";
1679 case PPCISD::XSMAXC: return "PPCISD::XSMAXC";
1680 case PPCISD::XSMINC: return "PPCISD::XSMINC";
1681 case PPCISD::FCFID: return "PPCISD::FCFID";
1682 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1683 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1684 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1685 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1686 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1687 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1688 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1689 case PPCISD::FRE: return "PPCISD::FRE";
1690 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1691 case PPCISD::FTSQRT:
1692 return "PPCISD::FTSQRT";
1693 case PPCISD::FSQRT:
1694 return "PPCISD::FSQRT";
1695 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1696 case PPCISD::VPERM: return "PPCISD::VPERM";
1697 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1699 return "PPCISD::XXSPLTI_SP_TO_DP";
1701 return "PPCISD::XXSPLTI32DX";
1702 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1703 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1704 case PPCISD::XXPERM:
1705 return "PPCISD::XXPERM";
1706 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1707 case PPCISD::CMPB: return "PPCISD::CMPB";
1708 case PPCISD::Hi: return "PPCISD::Hi";
1709 case PPCISD::Lo: return "PPCISD::Lo";
1710 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1711 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1712 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1713 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1714 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1715 case PPCISD::PROBED_ALLOCA: return "PPCISD::PROBED_ALLOCA";
1716 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1717 case PPCISD::SRL: return "PPCISD::SRL";
1718 case PPCISD::SRA: return "PPCISD::SRA";
1719 case PPCISD::SHL: return "PPCISD::SHL";
1720 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1721 case PPCISD::CALL: return "PPCISD::CALL";
1722 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1723 case PPCISD::CALL_NOTOC: return "PPCISD::CALL_NOTOC";
1724 case PPCISD::CALL_RM:
1725 return "PPCISD::CALL_RM";
1727 return "PPCISD::CALL_NOP_RM";
1729 return "PPCISD::CALL_NOTOC_RM";
1730 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1731 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1732 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1733 case PPCISD::BCTRL_RM:
1734 return "PPCISD::BCTRL_RM";
1736 return "PPCISD::BCTRL_LOAD_TOC_RM";
1737 case PPCISD::RET_GLUE: return "PPCISD::RET_GLUE";
1738 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1739 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1740 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1741 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1742 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1743 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1744 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1745 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1746 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1748 return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
1750 return "PPCISD::ANDI_rec_1_EQ_BIT";
1752 return "PPCISD::ANDI_rec_1_GT_BIT";
1753 case PPCISD::VCMP: return "PPCISD::VCMP";
1754 case PPCISD::VCMP_rec: return "PPCISD::VCMP_rec";
1755 case PPCISD::LBRX: return "PPCISD::LBRX";
1756 case PPCISD::STBRX: return "PPCISD::STBRX";
1757 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1758 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1759 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1760 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1761 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1762 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1763 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1764 case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
1765 case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
1767 return "PPCISD::ST_VSR_SCAL_INT";
1768 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1769 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1770 case PPCISD::BDZ: return "PPCISD::BDZ";
1771 case PPCISD::MFFS: return "PPCISD::MFFS";
1772 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1773 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1774 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1775 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1776 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1777 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1778 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1779 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1780 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1781 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1782 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1783 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1784 case PPCISD::GET_TLS_MOD_AIX: return "PPCISD::GET_TLS_MOD_AIX";
1785 case PPCISD::GET_TPOINTER: return "PPCISD::GET_TPOINTER";
1786 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1787 case PPCISD::TLSGD_AIX: return "PPCISD::TLSGD_AIX";
1788 case PPCISD::TLSLD_AIX: return "PPCISD::TLSLD_AIX";
1789 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1790 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1791 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1792 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1793 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1794 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1796 return "PPCISD::PADDI_DTPREL";
1797 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1798 case PPCISD::SC: return "PPCISD::SC";
1799 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1800 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1801 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1802 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1803 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1804 case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1805 case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
1806 case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
1807 case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1808 case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
1809 case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF";
1810 case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR";
1812 return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
1814 return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR";
1815 case PPCISD::ACC_BUILD: return "PPCISD::ACC_BUILD";
1816 case PPCISD::PAIR_BUILD: return "PPCISD::PAIR_BUILD";
1817 case PPCISD::EXTRACT_VSX_REG: return "PPCISD::EXTRACT_VSX_REG";
1818 case PPCISD::XXMFACC: return "PPCISD::XXMFACC";
1819 case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
1820 case PPCISD::ZEXT_LD_SPLAT: return "PPCISD::ZEXT_LD_SPLAT";
1821 case PPCISD::SEXT_LD_SPLAT: return "PPCISD::SEXT_LD_SPLAT";
1822 case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
1824 return "PPCISD::STRICT_FADDRTZ";
1826 return "PPCISD::STRICT_FCTIDZ";
1828 return "PPCISD::STRICT_FCTIWZ";
1830 return "PPCISD::STRICT_FCTIDUZ";
1832 return "PPCISD::STRICT_FCTIWUZ";
1834 return "PPCISD::STRICT_FCFID";
1836 return "PPCISD::STRICT_FCFIDU";
1838 return "PPCISD::STRICT_FCFIDS";
1840 return "PPCISD::STRICT_FCFIDUS";
1841 case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
1842 case PPCISD::STORE_COND:
1843 return "PPCISD::STORE_COND";
1844 }
1845 return nullptr;
1846}
1847
1849 EVT VT) const {
1850 if (!VT.isVector())
1851 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1852
1854}
1855
1857 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1858 return true;
1859}
1860
1861//===----------------------------------------------------------------------===//
1862// Node matching predicates, for use by the tblgen matching code.
1863//===----------------------------------------------------------------------===//
1864
1865/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1867 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1868 return CFP->getValueAPF().isZero();
1869 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1870 // Maybe this has already been legalized into the constant pool?
1871 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1872 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1873 return CFP->getValueAPF().isZero();
1874 }
1875 return false;
1876}
1877
1878/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1879/// true if Op is undef or if it matches the specified value.
1880static bool isConstantOrUndef(int Op, int Val) {
1881 return Op < 0 || Op == Val;
1882}
1883
1884/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1885/// VPKUHUM instruction.
1886/// The ShuffleKind distinguishes between big-endian operations with
1887/// two different inputs (0), either-endian operations with two identical
1888/// inputs (1), and little-endian operations with two different inputs (2).
1889/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1891 SelectionDAG &DAG) {
1892 bool IsLE = DAG.getDataLayout().isLittleEndian();
1893 if (ShuffleKind == 0) {
1894 if (IsLE)
1895 return false;
1896 for (unsigned i = 0; i != 16; ++i)
1897 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1898 return false;
1899 } else if (ShuffleKind == 2) {
1900 if (!IsLE)
1901 return false;
1902 for (unsigned i = 0; i != 16; ++i)
1903 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1904 return false;
1905 } else if (ShuffleKind == 1) {
1906 unsigned j = IsLE ? 0 : 1;
1907 for (unsigned i = 0; i != 8; ++i)
1908 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1909 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1910 return false;
1911 }
1912 return true;
1913}
1914
1915/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1916/// VPKUWUM instruction.
1917/// The ShuffleKind distinguishes between big-endian operations with
1918/// two different inputs (0), either-endian operations with two identical
1919/// inputs (1), and little-endian operations with two different inputs (2).
1920/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1922 SelectionDAG &DAG) {
1923 bool IsLE = DAG.getDataLayout().isLittleEndian();
1924 if (ShuffleKind == 0) {
1925 if (IsLE)
1926 return false;
1927 for (unsigned i = 0; i != 16; i += 2)
1928 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1929 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1930 return false;
1931 } else if (ShuffleKind == 2) {
1932 if (!IsLE)
1933 return false;
1934 for (unsigned i = 0; i != 16; i += 2)
1935 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1936 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1937 return false;
1938 } else if (ShuffleKind == 1) {
1939 unsigned j = IsLE ? 0 : 2;
1940 for (unsigned i = 0; i != 8; i += 2)
1941 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1942 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1943 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1944 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1945 return false;
1946 }
1947 return true;
1948}
1949
1950/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1951/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1952/// current subtarget.
1953///
1954/// The ShuffleKind distinguishes between big-endian operations with
1955/// two different inputs (0), either-endian operations with two identical
1956/// inputs (1), and little-endian operations with two different inputs (2).
1957/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1959 SelectionDAG &DAG) {
1960 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>();
1961 if (!Subtarget.hasP8Vector())
1962 return false;
1963
1964 bool IsLE = DAG.getDataLayout().isLittleEndian();
1965 if (ShuffleKind == 0) {
1966 if (IsLE)
1967 return false;
1968 for (unsigned i = 0; i != 16; i += 4)
1969 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1970 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1971 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1972 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1973 return false;
1974 } else if (ShuffleKind == 2) {
1975 if (!IsLE)
1976 return false;
1977 for (unsigned i = 0; i != 16; i += 4)
1978 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1979 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1980 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1981 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1982 return false;
1983 } else if (ShuffleKind == 1) {
1984 unsigned j = IsLE ? 0 : 4;
1985 for (unsigned i = 0; i != 8; i += 4)
1986 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1987 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1988 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1989 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1990 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1991 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1992 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1993 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1994 return false;
1995 }
1996 return true;
1997}
1998
1999/// isVMerge - Common function, used to match vmrg* shuffles.
2000///
2001static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
2002 unsigned LHSStart, unsigned RHSStart) {
2003 if (N->getValueType(0) != MVT::v16i8)
2004 return false;
2005 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
2006 "Unsupported merge size!");
2007
2008 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
2009 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
2010 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
2011 LHSStart+j+i*UnitSize) ||
2012 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
2013 RHSStart+j+i*UnitSize))
2014 return false;
2015 }
2016 return true;
2017}
2018
2019/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
2020/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
2021/// The ShuffleKind distinguishes between big-endian merges with two
2022/// different inputs (0), either-endian merges with two identical inputs (1),
2023/// and little-endian merges with two different inputs (2). For the latter,
2024/// the input operands are swapped (see PPCInstrAltivec.td).
2026 unsigned ShuffleKind, SelectionDAG &DAG) {
2027 if (DAG.getDataLayout().isLittleEndian()) {
2028 if (ShuffleKind == 1) // unary
2029 return isVMerge(N, UnitSize, 0, 0);
2030 else if (ShuffleKind == 2) // swapped
2031 return isVMerge(N, UnitSize, 0, 16);
2032 else
2033 return false;
2034 } else {
2035 if (ShuffleKind == 1) // unary
2036 return isVMerge(N, UnitSize, 8, 8);
2037 else if (ShuffleKind == 0) // normal
2038 return isVMerge(N, UnitSize, 8, 24);
2039 else
2040 return false;
2041 }
2042}
2043
2044/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
2045/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
2046/// The ShuffleKind distinguishes between big-endian merges with two
2047/// different inputs (0), either-endian merges with two identical inputs (1),
2048/// and little-endian merges with two different inputs (2). For the latter,
2049/// the input operands are swapped (see PPCInstrAltivec.td).
2051 unsigned ShuffleKind, SelectionDAG &DAG) {
2052 if (DAG.getDataLayout().isLittleEndian()) {
2053 if (ShuffleKind == 1) // unary
2054 return isVMerge(N, UnitSize, 8, 8);
2055 else if (ShuffleKind == 2) // swapped
2056 return isVMerge(N, UnitSize, 8, 24);
2057 else
2058 return false;
2059 } else {
2060 if (ShuffleKind == 1) // unary
2061 return isVMerge(N, UnitSize, 0, 0);
2062 else if (ShuffleKind == 0) // normal
2063 return isVMerge(N, UnitSize, 0, 16);
2064 else
2065 return false;
2066 }
2067}
2068
2069/**
2070 * Common function used to match vmrgew and vmrgow shuffles
2071 *
2072 * The indexOffset determines whether to look for even or odd words in
2073 * the shuffle mask. This is based on the of the endianness of the target
2074 * machine.
2075 * - Little Endian:
2076 * - Use offset of 0 to check for odd elements
2077 * - Use offset of 4 to check for even elements
2078 * - Big Endian:
2079 * - Use offset of 0 to check for even elements
2080 * - Use offset of 4 to check for odd elements
2081 * A detailed description of the vector element ordering for little endian and
2082 * big endian can be found at
2083 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
2084 * Targeting your applications - what little endian and big endian IBM XL C/C++
2085 * compiler differences mean to you
2086 *
2087 * The mask to the shuffle vector instruction specifies the indices of the
2088 * elements from the two input vectors to place in the result. The elements are
2089 * numbered in array-access order, starting with the first vector. These vectors
2090 * are always of type v16i8, thus each vector will contain 16 elements of size
2091 * 8. More info on the shuffle vector can be found in the
2092 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
2093 * Language Reference.
2094 *
2095 * The RHSStartValue indicates whether the same input vectors are used (unary)
2096 * or two different input vectors are used, based on the following:
2097 * - If the instruction uses the same vector for both inputs, the range of the
2098 * indices will be 0 to 15. In this case, the RHSStart value passed should
2099 * be 0.
2100 * - If the instruction has two different vectors then the range of the
2101 * indices will be 0 to 31. In this case, the RHSStart value passed should
2102 * be 16 (indices 0-15 specify elements in the first vector while indices 16
2103 * to 31 specify elements in the second vector).
2104 *
2105 * \param[in] N The shuffle vector SD Node to analyze
2106 * \param[in] IndexOffset Specifies whether to look for even or odd elements
2107 * \param[in] RHSStartValue Specifies the starting index for the righthand input
2108 * vector to the shuffle_vector instruction
2109 * \return true iff this shuffle vector represents an even or odd word merge
2110 */
2111static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
2112 unsigned RHSStartValue) {
2113 if (N->getValueType(0) != MVT::v16i8)
2114 return false;
2115
2116 for (unsigned i = 0; i < 2; ++i)
2117 for (unsigned j = 0; j < 4; ++j)
2118 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
2119 i*RHSStartValue+j+IndexOffset) ||
2120 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
2121 i*RHSStartValue+j+IndexOffset+8))
2122 return false;
2123 return true;
2124}
2125
2126/**
2127 * Determine if the specified shuffle mask is suitable for the vmrgew or
2128 * vmrgow instructions.
2129 *
2130 * \param[in] N The shuffle vector SD Node to analyze
2131 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
2132 * \param[in] ShuffleKind Identify the type of merge:
2133 * - 0 = big-endian merge with two different inputs;
2134 * - 1 = either-endian merge with two identical inputs;
2135 * - 2 = little-endian merge with two different inputs (inputs are swapped for
2136 * little-endian merges).
2137 * \param[in] DAG The current SelectionDAG
2138 * \return true iff this shuffle mask
2139 */
2141 unsigned ShuffleKind, SelectionDAG &DAG) {
2142 if (DAG.getDataLayout().isLittleEndian()) {
2143 unsigned indexOffset = CheckEven ? 4 : 0;
2144 if (ShuffleKind == 1) // Unary
2145 return isVMerge(N, indexOffset, 0);
2146 else if (ShuffleKind == 2) // swapped
2147 return isVMerge(N, indexOffset, 16);
2148 else
2149 return false;
2150 }
2151 else {
2152 unsigned indexOffset = CheckEven ? 0 : 4;
2153 if (ShuffleKind == 1) // Unary
2154 return isVMerge(N, indexOffset, 0);
2155 else if (ShuffleKind == 0) // Normal
2156 return isVMerge(N, indexOffset, 16);
2157 else
2158 return false;
2159 }
2160 return false;
2161}
2162
2163/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
2164/// amount, otherwise return -1.
2165/// The ShuffleKind distinguishes between big-endian operations with two
2166/// different inputs (0), either-endian operations with two identical inputs
2167/// (1), and little-endian operations with two different inputs (2). For the
2168/// latter, the input operands are swapped (see PPCInstrAltivec.td).
2169int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
2170 SelectionDAG &DAG) {
2171 if (N->getValueType(0) != MVT::v16i8)
2172 return -1;
2173
2174 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2175
2176 // Find the first non-undef value in the shuffle mask.
2177 unsigned i;
2178 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
2179 /*search*/;
2180
2181 if (i == 16) return -1; // all undef.
2182
2183 // Otherwise, check to see if the rest of the elements are consecutively
2184 // numbered from this value.
2185 unsigned ShiftAmt = SVOp->getMaskElt(i);
2186 if (ShiftAmt < i) return -1;
2187
2188 ShiftAmt -= i;
2189 bool isLE = DAG.getDataLayout().isLittleEndian();
2190
2191 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
2192 // Check the rest of the elements to see if they are consecutive.
2193 for (++i; i != 16; ++i)
2194 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2195 return -1;
2196 } else if (ShuffleKind == 1) {
2197 // Check the rest of the elements to see if they are consecutive.
2198 for (++i; i != 16; ++i)
2199 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
2200 return -1;
2201 } else
2202 return -1;
2203
2204 if (isLE)
2205 ShiftAmt = 16 - ShiftAmt;
2206
2207 return ShiftAmt;
2208}
2209
2210/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
2211/// specifies a splat of a single element that is suitable for input to
2212/// one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).
2214 EVT VT = N->getValueType(0);
2215 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2216 return EltSize == 8 && N->getMaskElt(0) == N->getMaskElt(1);
2217
2218 assert(VT == MVT::v16i8 && isPowerOf2_32(EltSize) &&
2219 EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes");
2220
2221 // The consecutive indices need to specify an element, not part of two
2222 // different elements. So abandon ship early if this isn't the case.
2223 if (N->getMaskElt(0) % EltSize != 0)
2224 return false;
2225
2226 // This is a splat operation if each element of the permute is the same, and
2227 // if the value doesn't reference the second vector.
2228 unsigned ElementBase = N->getMaskElt(0);
2229
2230 // FIXME: Handle UNDEF elements too!
2231 if (ElementBase >= 16)
2232 return false;
2233
2234 // Check that the indices are consecutive, in the case of a multi-byte element
2235 // splatted with a v16i8 mask.
2236 for (unsigned i = 1; i != EltSize; ++i)
2237 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
2238 return false;
2239
2240 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
2241 if (N->getMaskElt(i) < 0) continue;
2242 for (unsigned j = 0; j != EltSize; ++j)
2243 if (N->getMaskElt(i+j) != N->getMaskElt(j))
2244 return false;
2245 }
2246 return true;
2247}
2248
2249/// Check that the mask is shuffling N byte elements. Within each N byte
2250/// element of the mask, the indices could be either in increasing or
2251/// decreasing order as long as they are consecutive.
2252/// \param[in] N the shuffle vector SD Node to analyze
2253/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
2254/// Word/DoubleWord/QuadWord).
2255/// \param[in] StepLen the delta indices number among the N byte element, if
2256/// the mask is in increasing/decreasing order then it is 1/-1.
2257/// \return true iff the mask is shuffling N byte elements.
2258static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
2259 int StepLen) {
2260 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
2261 "Unexpected element width.");
2262 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.");
2263
2264 unsigned NumOfElem = 16 / Width;
2265 unsigned MaskVal[16]; // Width is never greater than 16
2266 for (unsigned i = 0; i < NumOfElem; ++i) {
2267 MaskVal[0] = N->getMaskElt(i * Width);
2268 if ((StepLen == 1) && (MaskVal[0] % Width)) {
2269 return false;
2270 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
2271 return false;
2272 }
2273
2274 for (unsigned int j = 1; j < Width; ++j) {
2275 MaskVal[j] = N->getMaskElt(i * Width + j);
2276 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
2277 return false;
2278 }
2279 }
2280 }
2281
2282 return true;
2283}
2284
2285bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2286 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
2287 if (!isNByteElemShuffleMask(N, 4, 1))
2288 return false;
2289
2290 // Now we look at mask elements 0,4,8,12
2291 unsigned M0 = N->getMaskElt(0) / 4;
2292 unsigned M1 = N->getMaskElt(4) / 4;
2293 unsigned M2 = N->getMaskElt(8) / 4;
2294 unsigned M3 = N->getMaskElt(12) / 4;
2295 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
2296 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
2297
2298 // Below, let H and L be arbitrary elements of the shuffle mask
2299 // where H is in the range [4,7] and L is in the range [0,3].
2300 // H, 1, 2, 3 or L, 5, 6, 7
2301 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
2302 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
2303 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
2304 InsertAtByte = IsLE ? 12 : 0;
2305 Swap = M0 < 4;
2306 return true;
2307 }
2308 // 0, H, 2, 3 or 4, L, 6, 7
2309 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
2310 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
2311 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
2312 InsertAtByte = IsLE ? 8 : 4;
2313 Swap = M1 < 4;
2314 return true;
2315 }
2316 // 0, 1, H, 3 or 4, 5, L, 7
2317 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
2318 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
2319 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
2320 InsertAtByte = IsLE ? 4 : 8;
2321 Swap = M2 < 4;
2322 return true;
2323 }
2324 // 0, 1, 2, H or 4, 5, 6, L
2325 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
2326 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
2327 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
2328 InsertAtByte = IsLE ? 0 : 12;
2329 Swap = M3 < 4;
2330 return true;
2331 }
2332
2333 // If both vector operands for the shuffle are the same vector, the mask will
2334 // contain only elements from the first one and the second one will be undef.
2335 if (N->getOperand(1).isUndef()) {
2336 ShiftElts = 0;
2337 Swap = true;
2338 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
2339 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
2340 InsertAtByte = IsLE ? 12 : 0;
2341 return true;
2342 }
2343 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
2344 InsertAtByte = IsLE ? 8 : 4;
2345 return true;
2346 }
2347 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
2348 InsertAtByte = IsLE ? 4 : 8;
2349 return true;
2350 }
2351 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
2352 InsertAtByte = IsLE ? 0 : 12;
2353 return true;
2354 }
2355 }
2356
2357 return false;
2358}
2359
2361 bool &Swap, bool IsLE) {
2362 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
2363 // Ensure each byte index of the word is consecutive.
2364 if (!isNByteElemShuffleMask(N, 4, 1))
2365 return false;
2366
2367 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
2368 unsigned M0 = N->getMaskElt(0) / 4;
2369 unsigned M1 = N->getMaskElt(4) / 4;
2370 unsigned M2 = N->getMaskElt(8) / 4;
2371 unsigned M3 = N->getMaskElt(12) / 4;
2372
2373 // If both vector operands for the shuffle are the same vector, the mask will
2374 // contain only elements from the first one and the second one will be undef.
2375 if (N->getOperand(1).isUndef()) {
2376 assert(M0 < 4 && "Indexing into an undef vector?");
2377 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
2378 return false;
2379
2380 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
2381 Swap = false;
2382 return true;
2383 }
2384
2385 // Ensure each word index of the ShuffleVector Mask is consecutive.
2386 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
2387 return false;
2388
2389 if (IsLE) {
2390 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
2391 // Input vectors don't need to be swapped if the leading element
2392 // of the result is one of the 3 left elements of the second vector
2393 // (or if there is no shift to be done at all).
2394 Swap = false;
2395 ShiftElts = (8 - M0) % 8;
2396 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
2397 // Input vectors need to be swapped if the leading element
2398 // of the result is one of the 3 left elements of the first vector
2399 // (or if we're shifting by 4 - thereby simply swapping the vectors).
2400 Swap = true;
2401 ShiftElts = (4 - M0) % 4;
2402 }
2403
2404 return true;
2405 } else { // BE
2406 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
2407 // Input vectors don't need to be swapped if the leading element
2408 // of the result is one of the 4 elements of the first vector.
2409 Swap = false;
2410 ShiftElts = M0;
2411 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
2412 // Input vectors need to be swapped if the leading element
2413 // of the result is one of the 4 elements of the right vector.
2414 Swap = true;
2415 ShiftElts = M0 - 4;
2416 }
2417
2418 return true;
2419 }
2420}
2421
2423 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
2424
2425 if (!isNByteElemShuffleMask(N, Width, -1))
2426 return false;
2427
2428 for (int i = 0; i < 16; i += Width)
2429 if (N->getMaskElt(i) != i + Width - 1)
2430 return false;
2431
2432 return true;
2433}
2434
2436 return isXXBRShuffleMaskHelper(N, 2);
2437}
2438
2440 return isXXBRShuffleMaskHelper(N, 4);
2441}
2442
2444 return isXXBRShuffleMaskHelper(N, 8);
2445}
2446
2448 return isXXBRShuffleMaskHelper(N, 16);
2449}
2450
2451/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
2452/// if the inputs to the instruction should be swapped and set \p DM to the
2453/// value for the immediate.
2454/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
2455/// AND element 0 of the result comes from the first input (LE) or second input
2456/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
2457/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
2458/// mask.
2460 bool &Swap, bool IsLE) {
2461 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8");
2462
2463 // Ensure each byte index of the double word is consecutive.
2464 if (!isNByteElemShuffleMask(N, 8, 1))
2465 return false;
2466
2467 unsigned M0 = N->getMaskElt(0) / 8;
2468 unsigned M1 = N->getMaskElt(8) / 8;
2469 assert(((M0 | M1) < 4) && "A mask element out of bounds?");
2470
2471 // If both vector operands for the shuffle are the same vector, the mask will
2472 // contain only elements from the first one and the second one will be undef.
2473 if (N->getOperand(1).isUndef()) {
2474 if ((M0 | M1) < 2) {
2475 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
2476 Swap = false;
2477 return true;
2478 } else
2479 return false;
2480 }
2481
2482 if (IsLE) {
2483 if (M0 > 1 && M1 < 2) {
2484 Swap = false;
2485 } else if (M0 < 2 && M1 > 1) {
2486 M0 = (M0 + 2) % 4;
2487 M1 = (M1 + 2) % 4;
2488 Swap = true;
2489 } else
2490 return false;
2491
2492 // Note: if control flow comes here that means Swap is already set above
2493 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2494 return true;
2495 } else { // BE
2496 if (M0 < 2 && M1 > 1) {
2497 Swap = false;
2498 } else if (M0 > 1 && M1 < 2) {
2499 M0 = (M0 + 2) % 4;
2500 M1 = (M1 + 2) % 4;
2501 Swap = true;
2502 } else
2503 return false;
2504
2505 // Note: if control flow comes here that means Swap is already set above
2506 DM = (M0 << 1) + (M1 & 1);
2507 return true;
2508 }
2509}
2510
2511
2512/// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
2513/// appropriate for PPC mnemonics (which have a big endian bias - namely
2514/// elements are counted from the left of the vector register).
2515unsigned PPC::getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
2516 SelectionDAG &DAG) {
2517 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2518 assert(isSplatShuffleMask(SVOp, EltSize));
2519 EVT VT = SVOp->getValueType(0);
2520
2521 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2522 return DAG.getDataLayout().isLittleEndian() ? 1 - SVOp->getMaskElt(0)
2523 : SVOp->getMaskElt(0);
2524
2525 if (DAG.getDataLayout().isLittleEndian())
2526 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2527 else
2528 return SVOp->getMaskElt(0) / EltSize;
2529}
2530
2531/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2532/// by using a vspltis[bhw] instruction of the specified element size, return
2533/// the constant being splatted. The ByteSize field indicates the number of
2534/// bytes of each element [124] -> [bhw].
2536 SDValue OpVal;
2537
2538 // If ByteSize of the splat is bigger than the element size of the
2539 // build_vector, then we have a case where we are checking for a splat where
2540 // multiple elements of the buildvector are folded together into a single
2541 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2542 unsigned EltSize = 16/N->getNumOperands();
2543 if (EltSize < ByteSize) {
2544 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2545 SDValue UniquedVals[4];
2546 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
2547
2548 // See if all of the elements in the buildvector agree across.
2549 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2550 if (N->getOperand(i).isUndef()) continue;
2551 // If the element isn't a constant, bail fully out.
2552 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2553
2554 if (!UniquedVals[i&(Multiple-1)].getNode())
2555 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2556 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2557 return SDValue(); // no match.
2558 }
2559
2560 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2561 // either constant or undef values that are identical for each chunk. See
2562 // if these chunks can form into a larger vspltis*.
2563
2564 // Check to see if all of the leading entries are either 0 or -1. If
2565 // neither, then this won't fit into the immediate field.
2566 bool LeadingZero = true;
2567 bool LeadingOnes = true;
2568 for (unsigned i = 0; i != Multiple-1; ++i) {
2569 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2570
2571 LeadingZero &= isNullConstant(UniquedVals[i]);
2572 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2573 }
2574 // Finally, check the least significant entry.
2575 if (LeadingZero) {
2576 if (!UniquedVals[Multiple-1].getNode())
2577 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2578 int Val = UniquedVals[Multiple - 1]->getAsZExtVal();
2579 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2580 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2581 }
2582 if (LeadingOnes) {
2583 if (!UniquedVals[Multiple-1].getNode())
2584 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2585 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2586 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2587 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2588 }
2589
2590 return SDValue();
2591 }
2592
2593 // Check to see if this buildvec has a single non-undef value in its elements.
2594 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2595 if (N->getOperand(i).isUndef()) continue;
2596 if (!OpVal.getNode())
2597 OpVal = N->getOperand(i);
2598 else if (OpVal != N->getOperand(i))
2599 return SDValue();
2600 }
2601
2602 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2603
2604 unsigned ValSizeInBytes = EltSize;
2605 uint64_t Value = 0;
2606 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2607 Value = CN->getZExtValue();
2608 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2609 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
2610 Value = llvm::bit_cast<uint32_t>(CN->getValueAPF().convertToFloat());
2611 }
2612
2613 // If the splat value is larger than the element value, then we can never do
2614 // this splat. The only case that we could fit the replicated bits into our
2615 // immediate field for would be zero, and we prefer to use vxor for it.
2616 if (ValSizeInBytes < ByteSize) return SDValue();
2617
2618 // If the element value is larger than the splat value, check if it consists
2619 // of a repeated bit pattern of size ByteSize.
2620 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2621 return SDValue();
2622
2623 // Properly sign extend the value.
2624 int MaskVal = SignExtend32(Value, ByteSize * 8);
2625
2626 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2627 if (MaskVal == 0) return SDValue();
2628
2629 // Finally, if this value fits in a 5 bit sext field, return it
2630 if (SignExtend32<5>(MaskVal) == MaskVal)
2631 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2632 return SDValue();
2633}
2634
2635//===----------------------------------------------------------------------===//
2636// Addressing Mode Selection
2637//===----------------------------------------------------------------------===//
2638
2639/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2640/// or 64-bit immediate, and if the value can be accurately represented as a
2641/// sign extension from a 16-bit value. If so, this returns true and the
2642/// immediate.
2643bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2644 if (!isa<ConstantSDNode>(N))
2645 return false;
2646
2647 Imm = (int16_t)N->getAsZExtVal();
2648 if (N->getValueType(0) == MVT::i32)
2649 return Imm == (int32_t)N->getAsZExtVal();
2650 else
2651 return Imm == (int64_t)N->getAsZExtVal();
2652}
2654 return isIntS16Immediate(Op.getNode(), Imm);
2655}
2656
2657/// Used when computing address flags for selecting loads and stores.
2658/// If we have an OR, check if the LHS and RHS are provably disjoint.
2659/// An OR of two provably disjoint values is equivalent to an ADD.
2660/// Most PPC load/store instructions compute the effective address as a sum,
2661/// so doing this conversion is useful.
2662static bool provablyDisjointOr(SelectionDAG &DAG, const SDValue &N) {
2663 if (N.getOpcode() != ISD::OR)
2664 return false;
2665 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2666 if (!LHSKnown.Zero.getBoolValue())
2667 return false;
2668 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2669 return (~(LHSKnown.Zero | RHSKnown.Zero) == 0);
2670}
2671
2672/// SelectAddressEVXRegReg - Given the specified address, check to see if it can
2673/// be represented as an indexed [r+r] operation.
2675 SDValue &Index,
2676 SelectionDAG &DAG) const {
2677 for (SDNode *U : N->uses()) {
2678 if (MemSDNode *Memop = dyn_cast<MemSDNode>(U)) {
2679 if (Memop->getMemoryVT() == MVT::f64) {
2680 Base = N.getOperand(0);
2681 Index = N.getOperand(1);
2682 return true;
2683 }
2684 }
2685 }
2686 return false;
2687}
2688
2689/// isIntS34Immediate - This method tests if value of node given can be
2690/// accurately represented as a sign extension from a 34-bit value. If so,
2691/// this returns true and the immediate.
2692bool llvm::isIntS34Immediate(SDNode *N, int64_t &Imm) {
2693 if (!isa<ConstantSDNode>(N))
2694 return false;
2695
2696 Imm = (int64_t)N->getAsZExtVal();
2697 return isInt<34>(Imm);
2698}
2700 return isIntS34Immediate(Op.getNode(), Imm);
2701}
2702
2703/// SelectAddressRegReg - Given the specified addressed, check to see if it
2704/// can be represented as an indexed [r+r] operation. Returns false if it
2705/// can be more efficiently represented as [r+imm]. If \p EncodingAlignment is
2706/// non-zero and N can be represented by a base register plus a signed 16-bit
2707/// displacement, make a more precise judgement by checking (displacement % \p
2708/// EncodingAlignment).
2711 MaybeAlign EncodingAlignment) const {
2712 // If we have a PC Relative target flag don't select as [reg+reg]. It will be
2713 // a [pc+imm].
2715 return false;
2716
2717 int16_t Imm = 0;
2718 if (N.getOpcode() == ISD::ADD) {
2719 // Is there any SPE load/store (f64), which can't handle 16bit offset?
2720 // SPE load/store can only handle 8-bit offsets.
2721 if (hasSPE() && SelectAddressEVXRegReg(N, Base, Index, DAG))
2722 return true;
2723 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2724 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2725 return false; // r+i
2726 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2727 return false; // r+i
2728
2729 Base = N.getOperand(0);
2730 Index = N.getOperand(1);
2731 return true;
2732 } else if (N.getOpcode() == ISD::OR) {
2733 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2734 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2735 return false; // r+i can fold it if we can.
2736
2737 // If this is an or of disjoint bitfields, we can codegen this as an add
2738 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2739 // disjoint.
2740 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2741
2742 if (LHSKnown.Zero.getBoolValue()) {
2743 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2744 // If all of the bits are known zero on the LHS or RHS, the add won't
2745 // carry.
2746 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2747 Base = N.getOperand(0);
2748 Index = N.getOperand(1);
2749 return true;
2750 }
2751 }
2752 }
2753
2754 return false;
2755}
2756
2757// If we happen to be doing an i64 load or store into a stack slot that has
2758// less than a 4-byte alignment, then the frame-index elimination may need to
2759// use an indexed load or store instruction (because the offset may not be a
2760// multiple of 4). The extra register needed to hold the offset comes from the
2761// register scavenger, and it is possible that the scavenger will need to use
2762// an emergency spill slot. As a result, we need to make sure that a spill slot
2763// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2764// stack slot.
2765static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2766 // FIXME: This does not handle the LWA case.
2767 if (VT != MVT::i64)
2768 return;
2769
2770 // NOTE: We'll exclude negative FIs here, which come from argument
2771 // lowering, because there are no known test cases triggering this problem
2772 // using packed structures (or similar). We can remove this exclusion if
2773 // we find such a test case. The reason why this is so test-case driven is
2774 // because this entire 'fixup' is only to prevent crashes (from the
2775 // register scavenger) on not-really-valid inputs. For example, if we have:
2776 // %a = alloca i1
2777 // %b = bitcast i1* %a to i64*
2778 // store i64* a, i64 b
2779 // then the store should really be marked as 'align 1', but is not. If it
2780 // were marked as 'align 1' then the indexed form would have been
2781 // instruction-selected initially, and the problem this 'fixup' is preventing
2782 // won't happen regardless.
2783 if (FrameIdx < 0)
2784 return;
2785
2787 MachineFrameInfo &MFI = MF.getFrameInfo();
2788
2789 if (MFI.getObjectAlign(FrameIdx) >= Align(4))
2790 return;
2791
2792 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2793 FuncInfo->setHasNonRISpills();
2794}
2795
2796/// Returns true if the address N can be represented by a base register plus
2797/// a signed 16-bit displacement [r+imm], and if it is not better
2798/// represented as reg+reg. If \p EncodingAlignment is non-zero, only accept
2799/// displacements that are multiples of that value.
2801 SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG,
2802 MaybeAlign EncodingAlignment) const {
2803 // FIXME dl should come from parent load or store, not from address
2804 SDLoc dl(N);
2805
2806 // If we have a PC Relative target flag don't select as [reg+imm]. It will be
2807 // a [pc+imm].
2809 return false;
2810
2811 // If this can be more profitably realized as r+r, fail.
2812 if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
2813 return false;
2814
2815 if (N.getOpcode() == ISD::ADD) {
2816 int16_t imm = 0;
2817 if (isIntS16Immediate(N.getOperand(1), imm) &&
2818 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2819 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2820 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2821 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2822 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2823 } else {
2824 Base = N.getOperand(0);
2825 }
2826 return true; // [r+i]
2827 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2828 // Match LOAD (ADD (X, Lo(G))).
2829 assert(!N.getOperand(1).getConstantOperandVal(1) &&
2830 "Cannot handle constant offsets yet!");
2831 Disp = N.getOperand(1).getOperand(0); // The global address.
2836 Base = N.getOperand(0);
2837 return true; // [&g+r]
2838 }
2839 } else if (N.getOpcode() == ISD::OR) {
2840 int16_t imm = 0;
2841 if (isIntS16Immediate(N.getOperand(1), imm) &&
2842 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2843 // If this is an or of disjoint bitfields, we can codegen this as an add
2844 // (for better address arithmetic) if the LHS and RHS of the OR are
2845 // provably disjoint.
2846 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2847
2848 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2849 // If all of the bits are known zero on the LHS or RHS, the add won't
2850 // carry.
2851 if (FrameIndexSDNode *FI =
2852 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2853 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2854 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2855 } else {
2856 Base = N.getOperand(0);
2857 }
2858 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2859 return true;
2860 }
2861 }
2862 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2863 // Loading from a constant address.
2864
2865 // If this address fits entirely in a 16-bit sext immediate field, codegen
2866 // this as "d, 0"
2867 int16_t Imm;
2868 if (isIntS16Immediate(CN, Imm) &&
2869 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm))) {
2870 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2871 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2872 CN->getValueType(0));
2873 return true;
2874 }
2875
2876 // Handle 32-bit sext immediates with LIS + addr mode.
2877 if ((CN->getValueType(0) == MVT::i32 ||
2878 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2879 (!EncodingAlignment ||
2880 isAligned(*EncodingAlignment, CN->getZExtValue()))) {
2881 int Addr = (int)CN->getZExtValue();
2882
2883 // Otherwise, break this down into an LIS + disp.
2884 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2885
2886 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2887 MVT::i32);
2888 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2889 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2890 return true;
2891 }
2892 }
2893
2894 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2895 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2896 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2897 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2898 } else
2899 Base = N;
2900 return true; // [r+0]
2901}
2902
2903/// Similar to the 16-bit case but for instructions that take a 34-bit
2904/// displacement field (prefixed loads/stores).
2906 SDValue &Base,
2907 SelectionDAG &DAG) const {
2908 // Only on 64-bit targets.
2909 if (N.getValueType() != MVT::i64)
2910 return false;
2911
2912 SDLoc dl(N);
2913 int64_t Imm = 0;
2914
2915 if (N.getOpcode() == ISD::ADD) {
2916 if (!isIntS34Immediate(N.getOperand(1), Imm))
2917 return false;
2918 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2919 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2920 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2921 else
2922 Base = N.getOperand(0);
2923 return true;
2924 }
2925
2926 if (N.getOpcode() == ISD::OR) {
2927 if (!isIntS34Immediate(N.getOperand(1), Imm))
2928 return false;
2929 // If this is an or of disjoint bitfields, we can codegen this as an add
2930 // (for better address arithmetic) if the LHS and RHS of the OR are
2931 // provably disjoint.
2932 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2933 if ((LHSKnown.Zero.getZExtValue() | ~(uint64_t)Imm) != ~0ULL)
2934 return false;
2935 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2936 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2937 else
2938 Base = N.getOperand(0);
2939 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2940 return true;
2941 }
2942
2943 if (isIntS34Immediate(N, Imm)) { // If the address is a 34-bit const.
2944 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2945 Base = DAG.getRegister(PPC::ZERO8, N.getValueType());
2946 return true;
2947 }
2948
2949 return false;
2950}
2951
2952/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2953/// represented as an indexed [r+r] operation.
2955 SDValue &Index,
2956 SelectionDAG &DAG) const {
2957 // Check to see if we can easily represent this as an [r+r] address. This
2958 // will fail if it thinks that the address is more profitably represented as
2959 // reg+imm, e.g. where imm = 0.
2960 if (SelectAddressRegReg(N, Base, Index, DAG))
2961 return true;
2962
2963 // If the address is the result of an add, we will utilize the fact that the
2964 // address calculation includes an implicit add. However, we can reduce
2965 // register pressure if we do not materialize a constant just for use as the
2966 // index register. We only get rid of the add if it is not an add of a
2967 // value and a 16-bit signed constant and both have a single use.
2968 int16_t imm = 0;
2969 if (N.getOpcode() == ISD::ADD &&
2970 (!isIntS16Immediate(N.getOperand(1), imm) ||
2971 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2972 Base = N.getOperand(0);
2973 Index = N.getOperand(1);
2974 return true;
2975 }
2976
2977 // Otherwise, do it the hard way, using R0 as the base register.
2978 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2979 N.getValueType());
2980 Index = N;
2981 return true;
2982}
2983
2984template <typename Ty> static bool isValidPCRelNode(SDValue N) {
2985 Ty *PCRelCand = dyn_cast<Ty>(N);
2986 return PCRelCand && (PPCInstrInfo::hasPCRelFlag(PCRelCand->getTargetFlags()));
2987}
2988
2989/// Returns true if this address is a PC Relative address.
2990/// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG
2991/// or if the node opcode is PPCISD::MAT_PCREL_ADDR.
2993 // This is a materialize PC Relative node. Always select this as PC Relative.
2994 Base = N;
2995 if (N.getOpcode() == PPCISD::MAT_PCREL_ADDR)
2996 return true;
2997 if (isValidPCRelNode<ConstantPoolSDNode>(N) ||
2998 isValidPCRelNode<GlobalAddressSDNode>(N) ||
2999 isValidPCRelNode<JumpTableSDNode>(N) ||
3000 isValidPCRelNode<BlockAddressSDNode>(N))
3001 return true;
3002 return false;
3003}
3004
3005/// Returns true if we should use a direct load into vector instruction
3006/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
3007static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
3008
3009 // If there are any other uses other than scalar to vector, then we should
3010 // keep it as a scalar load -> direct move pattern to prevent multiple
3011 // loads.
3012 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
3013 if (!LD)
3014 return false;
3015
3016 EVT MemVT = LD->getMemoryVT();
3017 if (!MemVT.isSimple())
3018 return false;
3019 switch(MemVT.getSimpleVT().SimpleTy) {
3020 case MVT::i64:
3021 break;
3022 case MVT::i32:
3023 if (!ST.hasP8Vector())
3024 return false;
3025 break;
3026 case MVT::i16:
3027 case MVT::i8:
3028 if (!ST.hasP9Vector())
3029 return false;
3030 break;
3031 default:
3032 return false;
3033 }
3034
3035 SDValue LoadedVal(N, 0);
3036 if (!LoadedVal.hasOneUse())
3037 return false;
3038
3039 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end();
3040 UI != UE; ++UI)
3041 if (UI.getUse().get().getResNo() == 0 &&
3042 UI->getOpcode() != ISD::SCALAR_TO_VECTOR &&
3043 UI->getOpcode() != PPCISD::SCALAR_TO_VECTOR_PERMUTED)
3044 return false;
3045
3046 return true;
3047}
3048
3049/// getPreIndexedAddressParts - returns true by value, base pointer and
3050/// offset pointer and addressing mode by reference if the node's address
3051/// can be legally represented as pre-indexed load / store address.
3053 SDValue &Offset,
3055 SelectionDAG &DAG) const {
3056 if (DisablePPCPreinc) return false;
3057
3058 bool isLoad = true;
3059 SDValue Ptr;
3060 EVT VT;
3061 Align Alignment;
3062 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3063 Ptr = LD->getBasePtr();
3064 VT = LD->getMemoryVT();
3065 Alignment = LD->getAlign();
3066 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3067 Ptr = ST->getBasePtr();
3068 VT = ST->getMemoryVT();
3069 Alignment = ST->getAlign();
3070 isLoad = false;
3071 } else
3072 return false;
3073
3074 // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
3075 // instructions because we can fold these into a more efficient instruction
3076 // instead, (such as LXSD).
3077 if (isLoad && usePartialVectorLoads(N, Subtarget)) {
3078 return false;
3079 }
3080
3081 // PowerPC doesn't have preinc load/store instructions for vectors
3082 if (VT.isVector())
3083 return false;
3084
3085 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
3086 // Common code will reject creating a pre-inc form if the base pointer
3087 // is a frame index, or if N is a store and the base pointer is either
3088 // the same as or a predecessor of the value being stored. Check for
3089 // those situations here, and try with swapped Base/Offset instead.
3090 bool Swap = false;
3091
3092 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
3093 Swap = true;
3094 else if (!isLoad) {
3095 SDValue Val = cast<StoreSDNode>(N)->getValue();
3096 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
3097 Swap = true;
3098 }
3099
3100 if (Swap)
3102
3103 AM = ISD::PRE_INC;
3104 return true;
3105 }
3106
3107 // LDU/STU can only handle immediates that are a multiple of 4.
3108 if (VT != MVT::i64) {
3109 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, std::nullopt))
3110 return false;
3111 } else {
3112 // LDU/STU need an address with at least 4-byte alignment.
3113 if (Alignment < Align(4))
3114 return false;
3115
3116 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, Align(4)))
3117 return false;
3118 }
3119
3120 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3121 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
3122 // sext i32 to i64 when addr mode is r+i.
3123 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
3124 LD->getExtensionType() == ISD::SEXTLOAD &&
3125 isa<ConstantSDNode>(Offset))
3126 return false;
3127 }
3128
3129 AM = ISD::PRE_INC;
3130 return true;
3131}
3132
3133//===----------------------------------------------------------------------===//
3134// LowerOperation implementation
3135//===----------------------------------------------------------------------===//
3136
3137/// Return true if we should reference labels using a PICBase, set the HiOpFlags
3138/// and LoOpFlags to the target MO flags.
3139static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
3140 unsigned &HiOpFlags, unsigned &LoOpFlags,
3141 const GlobalValue *GV = nullptr) {
3142 HiOpFlags = PPCII::MO_HA;
3143 LoOpFlags = PPCII::MO_LO;
3144
3145 // Don't use the pic base if not in PIC relocation model.
3146 if (IsPIC) {
3147 HiOpFlags = PPCII::MO_PIC_HA_FLAG;
3148 LoOpFlags = PPCII::MO_PIC_LO_FLAG;
3149 }
3150}
3151
3152static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
3153 SelectionDAG &DAG) {
3154 SDLoc DL(HiPart);
3155 EVT PtrVT = HiPart.getValueType();
3156 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
3157
3158 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
3159 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
3160
3161 // With PIC, the first instruction is actually "GR+hi(&G)".
3162 if (isPIC)
3163 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
3164 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
3165
3166 // Generate non-pic code that has direct accesses to the constant pool.
3167 // The address of the global is just (hi(&g)+lo(&g)).
3168 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
3169}
3170
3172 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3173 FuncInfo->setUsesTOCBasePtr();
3174}
3175
3178}
3179
3180SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
3181 SDValue GA) const {
3182 const bool Is64Bit = Subtarget.isPPC64();
3183 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
3184 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
3185 : Subtarget.isAIXABI()
3186 ? DAG.getRegister(PPC::R2, VT)
3187 : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
3188 SDValue Ops[] = { GA, Reg };
3189 return DAG.getMemIntrinsicNode(
3190 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
3193}
3194
3195SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
3196 SelectionDAG &DAG) const {
3197 EVT PtrVT = Op.getValueType();
3198 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3199 const Constant *C = CP->getConstVal();
3200
3201 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3202 // The actual address of the GlobalValue is stored in the TOC.
3203 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3204 if (Subtarget.isUsingPCRelativeCalls()) {
3205 SDLoc DL(CP);
3206 EVT Ty = getPointerTy(DAG.getDataLayout());
3207 SDValue ConstPool = DAG.getTargetConstantPool(
3208 C, Ty, CP->getAlign(), CP->getOffset(), PPCII::MO_PCREL_FLAG);
3209 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, ConstPool);
3210 }
3211 setUsesTOCBasePtr(DAG);
3212 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0);
3213 return getTOCEntry(DAG, SDLoc(CP), GA);
3214 }
3215
3216 unsigned MOHiFlag, MOLoFlag;
3217 bool IsPIC = isPositionIndependent();
3218 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3219
3220 if (IsPIC && Subtarget.isSVR4ABI()) {
3221 SDValue GA =
3222 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), PPCII::MO_PIC_FLAG);
3223 return getTOCEntry(DAG, SDLoc(CP), GA);
3224 }
3225
3226 SDValue CPIHi =
3227 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOHiFlag);
3228 SDValue CPILo =
3229 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOLoFlag);
3230 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
3231}
3232
3233// For 64-bit PowerPC, prefer the more compact relative encodings.
3234// This trades 32 bits per jump table entry for one or two instructions
3235// on the jump site.
3237 if (isJumpTableRelative())
3239
3241}
3242
3245 return false;
3246 if (Subtarget.isPPC64() || Subtarget.isAIXABI())
3247 return true;
3249}
3250
3252 SelectionDAG &DAG) const {
3253 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3255
3256 switch (getTargetMachine().getCodeModel()) {
3257 case CodeModel::Small:
3258 case CodeModel::Medium:
3260 default:
3261 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
3263 }
3264}
3265
3266const MCExpr *
3268 unsigned JTI,
3269 MCContext &Ctx) const {
3270 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3272
3273 switch (getTargetMachine().getCodeModel()) {
3274 case CodeModel::Small:
3275 case CodeModel::Medium:
3277 default:
3278 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
3279 }
3280}
3281
3282SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
3283 EVT PtrVT = Op.getValueType();
3284 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3285
3286 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3287 if (Subtarget.isUsingPCRelativeCalls()) {
3288 SDLoc DL(JT);
3289 EVT Ty = getPointerTy(DAG.getDataLayout());
3290 SDValue GA =
3291 DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG);
3292 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3293 return MatAddr;
3294 }
3295
3296 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3297 // The actual address of the GlobalValue is stored in the TOC.
3298 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3299 setUsesTOCBasePtr(DAG);
3300 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
3301 return getTOCEntry(DAG, SDLoc(JT), GA);
3302 }
3303
3304 unsigned MOHiFlag, MOLoFlag;
3305 bool IsPIC = isPositionIndependent();
3306 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3307
3308 if (IsPIC && Subtarget.isSVR4ABI()) {
3309 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3311 return getTOCEntry(DAG, SDLoc(GA), GA);
3312 }
3313
3314 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
3315 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
3316 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
3317}
3318
3319SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
3320 SelectionDAG &DAG) const {
3321 EVT PtrVT = Op.getValueType();
3322 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
3323 const BlockAddress *BA = BASDN->getBlockAddress();
3324
3325 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3326 if (Subtarget.isUsingPCRelativeCalls()) {
3327 SDLoc DL(BASDN);
3328 EVT Ty = getPointerTy(DAG.getDataLayout());
3329 SDValue GA = DAG.getTargetBlockAddress(BA, Ty, BASDN->getOffset(),
3331 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3332 return MatAddr;
3333 }
3334
3335 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3336 // The actual BlockAddress is stored in the TOC.
3337 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3338 setUsesTOCBasePtr(DAG);
3339 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
3340 return getTOCEntry(DAG, SDLoc(BASDN), GA);
3341 }
3342
3343 // 32-bit position-independent ELF stores the BlockAddress in the .got.
3344 if (Subtarget.is32BitELFABI() && isPositionIndependent())
3345 return getTOCEntry(
3346 DAG, SDLoc(BASDN),
3347 DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset()));
3348
3349 unsigned MOHiFlag, MOLoFlag;
3350 bool IsPIC = isPositionIndependent();
3351 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3352 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
3353 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
3354 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
3355}
3356
3357SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
3358 SelectionDAG &DAG) const {
3359 if (Subtarget.isAIXABI())
3360 return LowerGlobalTLSAddressAIX(Op, DAG);
3361
3362 return LowerGlobalTLSAddressLinux(Op, DAG);
3363}
3364
3365SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
3366 SelectionDAG &DAG) const {
3367 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3368
3369 if (DAG.getTarget().useEmulatedTLS())
3370 report_fatal_error("Emulated TLS is not yet supported on AIX");
3371
3372 SDLoc dl(GA);
3373 const GlobalValue *GV = GA->getGlobal();
3374 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3375 bool Is64Bit = Subtarget.isPPC64();
3377 bool IsTLSLocalExecModel = Model == TLSModel::LocalExec;
3378
3379 if (IsTLSLocalExecModel || Model == TLSModel::InitialExec) {
3380 bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
3381 bool HasAIXSmallTLSGlobalAttr = false;
3382 SDValue VariableOffsetTGA =
3383 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TPREL_FLAG);
3384 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3385 SDValue TLSReg;
3386
3387 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
3388 if (GVar->hasAttribute("aix-small-tls"))
3389 HasAIXSmallTLSGlobalAttr = true;
3390
3391 if (Is64Bit) {
3392 // For local-exec and initial-exec on AIX (64-bit), the sequence generated
3393 // involves a load of the variable offset (from the TOC), followed by an
3394 // add of the loaded variable offset to R13 (the thread pointer).
3395 // This code sequence looks like:
3396 // ld reg1,var[TC](2)
3397 // add reg2, reg1, r13 // r13 contains the thread pointer
3398 TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3399
3400 // With the -maix-small-local-exec-tls option, or with the "aix-small-tls"
3401 // global variable attribute, produce a faster access sequence for
3402 // local-exec TLS variables where the offset from the TLS base is encoded
3403 // as an immediate operand.
3404 //
3405 // We only utilize the faster local-exec access sequence when the TLS
3406 // variable has a size within the policy limit. We treat types that are
3407 // not sized or are empty as being over the policy size limit.
3408 if ((HasAIXSmallLocalExecTLS || HasAIXSmallTLSGlobalAttr) &&
3409 IsTLSLocalExecModel) {
3410 Type *GVType = GV->getValueType();
3411 if (GVType->isSized() && !GVType->isEmptyTy() &&
3412 GV->getParent()->getDataLayout().getTypeAllocSize(GVType) <=
3414 return DAG.getNode(PPCISD::Lo, dl, PtrVT, VariableOffsetTGA, TLSReg);
3415 }
3416 } else {
3417 // For local-exec and initial-exec on AIX (32-bit), the sequence generated
3418 // involves loading the variable offset from the TOC, generating a call to
3419 // .__get_tpointer to get the thread pointer (which will be in R3), and
3420 // adding the two together:
3421 // lwz reg1,var[TC](2)
3422 // bla .__get_tpointer
3423 // add reg2, reg1, r3
3424 TLSReg = DAG.getNode(PPCISD::GET_TPOINTER, dl, PtrVT);
3425
3426 // We do not implement the 32-bit version of the faster access sequence
3427 // for local-exec that is controlled by the -maix-small-local-exec-tls
3428 // option, or the "aix-small-tls" global variable attribute.
3429 if (HasAIXSmallLocalExecTLS || HasAIXSmallTLSGlobalAttr)
3430 report_fatal_error("The small-local-exec TLS access sequence is "
3431 "currently only supported on AIX (64-bit mode).");
3432 }
3433 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset);
3434 }
3435
3436 if (Model == TLSModel::LocalDynamic) {
3437 bool HasAIXSmallLocalDynamicTLS = Subtarget.hasAIXSmallLocalDynamicTLS();
3438
3439 // We do not implement the 32-bit version of the faster access sequence
3440 // for local-dynamic that is controlled by -maix-small-local-dynamic-tls.
3441 if (!Is64Bit && HasAIXSmallLocalDynamicTLS)
3442 report_fatal_error("The small-local-dynamic TLS access sequence is "
3443 "currently only supported on AIX (64-bit mode).");
3444
3445 // For local-dynamic on AIX, we need to generate one TOC entry for each
3446 // variable offset, and a single module-handle TOC entry for the entire
3447 // file.
3448
3449 SDValue VariableOffsetTGA =
3450 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSLD_FLAG);
3451 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3452
3454 GlobalVariable *TLSGV =
3455 dyn_cast_or_null<GlobalVariable>(M->getOrInsertGlobal(
3456 StringRef("_$TLSML"), PointerType::getUnqual(*DAG.getContext())));
3458 assert(TLSGV && "Not able to create GV for _$TLSML.");
3459 SDValue ModuleHandleTGA =
3460 DAG.getTargetGlobalAddress(TLSGV, dl, PtrVT, 0, PPCII::MO_TLSLDM_FLAG);
3461 SDValue ModuleHandleTOC = getTOCEntry(DAG, dl, ModuleHandleTGA);
3462 SDValue ModuleHandle =
3463 DAG.getNode(PPCISD::TLSLD_AIX, dl, PtrVT, ModuleHandleTOC);
3464
3465 // With the -maix-small-local-dynamic-tls option, produce a faster access
3466 // sequence for local-dynamic TLS variables where the offset from the
3467 // module-handle is encoded as an immediate operand.
3468 //
3469 // We only utilize the faster local-dynamic access sequence when the TLS
3470 // variable has a size within the policy limit. We treat types that are
3471 // not sized or are empty as being over the policy size limit.
3472 if (HasAIXSmallLocalDynamicTLS) {
3473 Type *GVType = GV->getValueType();
3474 if (GVType->isSized() && !GVType->isEmptyTy() &&
3475 GV->getParent()->getDataLayout().getTypeAllocSize(GVType) <=
3477 return DAG.getNode(PPCISD::Lo, dl, PtrVT, VariableOffsetTGA,
3478 ModuleHandle);
3479 }
3480
3481 return DAG.getNode(ISD::ADD, dl, PtrVT, ModuleHandle, VariableOffset);
3482 }
3483
3484 // If Local- or Initial-exec or Local-dynamic is not possible or specified,
3485 // all GlobalTLSAddress nodes are lowered using the general-dynamic model. We
3486 // need to generate two TOC entries, one for the variable offset, one for the
3487 // region handle. The global address for the TOC entry of the region handle is
3488 // created with the MO_TLSGDM_FLAG flag and the global address for the TOC
3489 // entry of the variable offset is created with MO_TLSGD_FLAG.
3490 SDValue VariableOffsetTGA =
3491 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGD_FLAG);
3492 SDValue RegionHandleTGA =
3493 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGDM_FLAG);
3494 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3495 SDValue RegionHandle = getTOCEntry(DAG, dl, RegionHandleTGA);
3496 return DAG.getNode(PPCISD::TLSGD_AIX, dl, PtrVT, VariableOffset,
3497 RegionHandle);
3498}
3499
3500SDValue PPCTargetLowering::LowerGlobalTLSAddressLinux(SDValue Op,
3501 SelectionDAG &DAG) const {
3502 // FIXME: TLS addresses currently use medium model code sequences,
3503 // which is the most useful form. Eventually support for small and
3504 // large models could be added if users need it, at the cost of
3505 // additional complexity.
3506 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3507 if (DAG.getTarget().useEmulatedTLS())
3508 return LowerToTLSEmulatedModel(GA, DAG);
3509
3510 SDLoc dl(GA);
3511 const GlobalValue *GV = GA->getGlobal();
3512 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3513 bool is64bit = Subtarget.isPPC64();
3514 const Module *M = DAG.getMachineFunction().getFunction().getParent();
3515 PICLevel::Level picLevel = M->getPICLevel();
3516
3518 TLSModel::Model Model = TM.getTLSModel(GV);
3519
3520 if (Model == TLSModel::LocalExec) {
3521 if (Subtarget.isUsingPCRelativeCalls()) {
3522 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3523 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3525 SDValue MatAddr =
3526 DAG.getNode(PPCISD::TLS_LOCAL_EXEC_MAT_ADDR, dl, PtrVT, TGA);
3527 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, MatAddr);
3528 }
3529
3530 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3532 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3534 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
3535 : DAG.getRegister(PPC::R2, MVT::i32);
3536
3537 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
3538 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
3539 }
3540
3541 if (Model == TLSModel::InitialExec) {
3542 bool IsPCRel = Subtarget.isUsingPCRelativeCalls();
3544 GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_GOT_TPREL_PCREL_FLAG : 0);
3545 SDValue TGATLS = DAG.getTargetGlobalAddress(
3546 GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_TLS_PCREL_FLAG : PPCII::MO_TLS);
3547 SDValue TPOffset;
3548 if (IsPCRel) {
3549 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, dl, PtrVT, TGA);
3550 TPOffset = DAG.getLoad(MVT::i64, dl, DAG.getEntryNode(), MatPCRel,
3552 } else {
3553 SDValue GOTPtr;
3554 if (is64bit) {
3555 setUsesTOCBasePtr(DAG);
3556 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3557 GOTPtr =
3558 DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, PtrVT, GOTReg, TGA);
3559 } else {
3560 if (!TM.isPositionIndependent())
3561 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
3562 else if (picLevel == PICLevel::SmallPIC)
3563 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3564 else
3565 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3566 }
3567 TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, PtrVT, TGA, GOTPtr);
3568 }
3569 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
3570 }
3571
3572 if (Model == TLSModel::GeneralDynamic) {
3573 if (Subtarget.isUsingPCRelativeCalls()) {
3574 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3576 return DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3577 }
3578
3579 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3580 SDValue GOTPtr;
3581 if (is64bit) {
3582 setUsesTOCBasePtr(DAG);
3583 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3584 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
3585 GOTReg, TGA);
3586 } else {
3587 if (picLevel == PICLevel::SmallPIC)
3588 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3589 else
3590 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3591 }
3592 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
3593 GOTPtr, TGA, TGA);
3594 }
3595
3596 if (Model == TLSModel::LocalDynamic) {
3597 if (Subtarget.isUsingPCRelativeCalls()) {
3598 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3600 SDValue MatPCRel =
3601 DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3602 return DAG.getNode(PPCISD::PADDI_DTPREL, dl, PtrVT, MatPCRel, TGA);
3603 }
3604
3605 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3606 SDValue GOTPtr;
3607 if (is64bit) {
3608 setUsesTOCBasePtr(DAG);
3609 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3610 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
3611 GOTReg, TGA);
3612 } else {
3613 if (picLevel == PICLevel::SmallPIC)
3614 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3615 else
3616 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3617 }
3618 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
3619 PtrVT, GOTPtr, TGA, TGA);
3620 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
3621 PtrVT, TLSAddr, TGA);
3622 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
3623 }
3624
3625 llvm_unreachable("Unknown TLS model!");
3626}
3627
3628SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
3629 SelectionDAG &DAG) const {
3630 EVT PtrVT = Op.getValueType();
3631 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
3632 SDLoc DL(GSDN);
3633 const GlobalValue *GV = GSDN->getGlobal();
3634
3635 // 64-bit SVR4 ABI & AIX ABI code is always position-independent.
3636 // The actual address of the GlobalValue is stored in the TOC.
3637 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3638 if (Subtarget.isUsingPCRelativeCalls()) {
3639 EVT Ty = getPointerTy(DAG.getDataLayout());
3641 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3643 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3644 SDValue Load = DAG.getLoad(MVT::i64, DL, DAG.getEntryNode(), MatPCRel,
3646 return Load;
3647 } else {
3648 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3650 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3651 }
3652 }
3653 setUsesTOCBasePtr(DAG);
3654 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
3655 return getTOCEntry(DAG, DL, GA);
3656 }
3657
3658 unsigned MOHiFlag, MOLoFlag;
3659 bool IsPIC = isPositionIndependent();
3660 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
3661
3662 if (IsPIC && Subtarget.isSVR4ABI()) {
3663 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
3664 GSDN->getOffset(),
3666 return getTOCEntry(DAG, DL, GA);
3667 }
3668
3669 SDValue GAHi =
3670 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
3671 SDValue GALo =
3672 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
3673
3674 return LowerLabelRef(GAHi, GALo, IsPIC, DAG);
3675}
3676
3677SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3678 bool IsStrict = Op->isStrictFPOpcode();
3680 cast<CondCodeSDNode>(Op.getOperand(IsStrict ? 3 : 2))->get();
3681 SDValue LHS = Op.getOperand(IsStrict ? 1 : 0);
3682 SDValue RHS = Op.getOperand(IsStrict ? 2 : 1);
3683 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
3684 EVT LHSVT =