LLVM 19.0.0git
PPCSubtarget.cpp
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1//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPC specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCSubtarget.h"
17#include "PPC.h"
18#include "PPCRegisterInfo.h"
19#include "PPCTargetMachine.h"
24#include "llvm/IR/Attributes.h"
25#include "llvm/IR/Function.h"
26#include "llvm/IR/GlobalAlias.h"
27#include "llvm/IR/GlobalValue.h"
32#include <cstdlib>
33
34using namespace llvm;
35
36#define DEBUG_TYPE "ppc-subtarget"
37
38#define GET_SUBTARGETINFO_TARGET_DESC
39#define GET_SUBTARGETINFO_CTOR
40#include "PPCGenSubtargetInfo.inc"
41
42static cl::opt<bool>
43 EnableMachinePipeliner("ppc-enable-pipeliner",
44 cl::desc("Enable Machine Pipeliner for PPC"),
45 cl::init(false), cl::Hidden);
46
48 StringRef TuneCPU,
49 StringRef FS) {
50 initializeEnvironment();
51 initSubtargetFeatures(CPU, TuneCPU, FS);
52 return *this;
53}
54
55PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
56 const std::string &TuneCPU, const std::string &FS,
57 const PPCTargetMachine &TM)
58 : PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS), TargetTriple(TT),
59 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
60 TargetTriple.getArch() == Triple::ppc64le),
61 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
62 InstrInfo(*this), TLInfo(TM, *this) {
64 Legalizer.reset(new PPCLegalizerInfo(*this));
65 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
66 RegBankInfo.reset(RBI);
67
68 InstSelector.reset(createPPCInstructionSelector(TM, *this, *RBI));
69}
70
71void PPCSubtarget::initializeEnvironment() {
75}
76
77void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
78 StringRef FS) {
79 // Determine default and user specified characteristics
80 std::string CPUName = std::string(CPU);
81 if (CPUName.empty() || CPU == "generic") {
82 // If cross-compiling with -march=ppc64le without -mcpu
84 CPUName = "ppc64le";
86 CPUName = "e500";
87 else
88 CPUName = "generic";
89 }
90
91 // Determine the CPU to schedule for.
92 if (TuneCPU.empty()) TuneCPU = CPUName;
93
94 // Initialize scheduling itinerary for the specified CPU.
95 InstrItins = getInstrItineraryForCPU(CPUName);
96
97 // Parse features string.
98 ParseSubtargetFeatures(CPUName, TuneCPU, FS);
99
100 // If the user requested use of 64-bit regs, but the cpu selected doesn't
101 // support it, ignore.
102 if (IsPPC64 && has64BitSupport())
103 Use64BitRegs = true;
104
106 IsSecurePlt = true;
107
108 if (HasSPE && IsPPC64)
109 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
110 if (HasSPE && (HasAltivec || HasVSX || HasFPU))
112 "SPE and traditional floating point cannot both be enabled.\n", false);
113
114 // If not SPE, set standard FPU
115 if (!HasSPE)
116 HasFPU = true;
117
119
120 // Determine endianness.
122
123 if (HasAIXSmallLocalExecTLS || HasAIXSmallLocalDynamicTLS) {
124 if (!TargetTriple.isOSAIX() || !IsPPC64)
125 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute is "
126 "only supported on AIX in "
127 "64-bit mode.\n",
128 false);
129 // The aix-small-local-[exec|dynamic]-tls attribute should only be used with
130 // -data-sections, as having data sections turned off with this option
131 // is not ideal for performance. Moreover, the
132 // small-local-[exec|dynamic]-tls region is a limited resource, and should
133 // not be used for variables that may be replaced.
134 if (!TM.getDataSections())
135 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute can "
136 "only be specified with "
137 "-data-sections.\n",
138 false);
139 }
140
141 if (HasAIXShLibTLSModelOpt && (!TargetTriple.isOSAIX() || !IsPPC64))
142 report_fatal_error("The aix-shared-lib-tls-model-opt attribute "
143 "is only supported on AIX in 64-bit mode.\n",
144 false);
145}
146
147bool PPCSubtarget::enableMachineScheduler() const { return true; }
148
150 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner;
151}
152
153bool PPCSubtarget::useDFAforSMS() const { return false; }
154
155// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
156bool PPCSubtarget::enablePostRAScheduler() const { return true; }
157
158PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
159 return TargetSubtargetInfo::ANTIDEP_ALL;
160}
161
162void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
163 CriticalPathRCs.clear();
164 CriticalPathRCs.push_back(isPPC64() ?
165 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
166}
167
169 unsigned NumRegionInstrs) const {
170 // The GenericScheduler that we use defaults to scheduling bottom up only.
171 // We want to schedule from both the top and the bottom and so we set
172 // OnlyBottomUp to false.
173 // We want to do bi-directional scheduling since it provides a more balanced
174 // schedule leading to better performance.
175 Policy.OnlyBottomUp = false;
176 // Spilling is generally expensive on all PPC cores, so always enable
177 // register-pressure tracking.
178 Policy.ShouldTrackPressure = true;
179}
180
182 return true;
183}
184
185bool PPCSubtarget::enableSubRegLiveness() const { return true; }
186
188 if (isAIXABI()) {
189 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
190 // On AIX the only symbols that aren't indirect are toc-data.
191 return !GVar->hasAttribute("toc-data");
192
193 return true;
194 }
195
196 // Large code model always uses the TOC even for local symbols.
198 return true;
199
200 if (TM.shouldAssumeDSOLocal(GV))
201 return false;
202 return true;
203}
204
206 const GlobalValue *GV) const {
207 // If there isn't an attribute to override the module code model
208 // this will be the effective code model.
209 CodeModel::Model ModuleModel = TM.getCodeModel();
210
211 // Initially support per global code model for AIX only.
212 if (!isAIXABI())
213 return ModuleModel;
214
215 // Only GlobalVariables carry an attribute which can override the module code
216 // model.
217 assert(GV && "Unexpected NULL GlobalValue");
218 const GlobalVariable *GlobalVar =
219 [](const GlobalValue *GV) -> const GlobalVariable * {
220 const GlobalVariable *Var = dyn_cast<GlobalVariable>(GV);
221 if (Var)
222 return Var;
223
224 const GlobalAlias *Alias = dyn_cast<GlobalAlias>(GV);
225 if (Alias)
226 return dyn_cast<GlobalVariable>(Alias->getAliaseeObject());
227
228 return nullptr;
229 }(GV);
230
231 if (!GlobalVar)
232 return ModuleModel;
233
234 std::optional<CodeModel::Model> MaybeCodeModel = GlobalVar->getCodeModel();
235 if (MaybeCodeModel) {
236 CodeModel::Model CM = *MaybeCodeModel;
237 assert((CM == CodeModel::Small || CM == CodeModel::Large) &&
238 "invalid code model for AIX");
239 return CM;
240 }
241
242 return ModuleModel;
243}
244
245bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
246bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
247
249 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
251}
252
253// GlobalISEL
255 return CallLoweringInfo.get();
256}
257
259 return RegBankInfo.get();
260}
261
263 return Legalizer.get();
264}
265
267 return InstSelector.get();
268}
static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)
This file contains the simple types necessary to represent the attributes associated with functions a...
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for PowerPC.
This file declares the targeting of the RegisterBankInfo class for PowerPC.
static cl::opt< bool > EnableMachinePipeliner("ppc-enable-pipeliner", cl::desc("Enable Machine Pipeliner for PPC"), cl::init(false), cl::Hidden)
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const GlobalObject * getAliaseeObject() const
Definition: Globals.cpp:582
This class provides the information for the PowerPC target legalizer for GlobalISel.
std::unique_ptr< InstructionSelector > InstSelector
Definition: PPCSubtarget.h:113
bool enableMachinePipeliner() const override
Pipeliner customization.
bool useDFAforSMS() const override
Machine Pipeliner customization.
bool isAIXABI() const
Definition: PPCSubtarget.h:214
const CallLowering * getCallLowering() const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: PPCSubtarget.h:81
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: PPCSubtarget.h:112
POPCNTDKind HasPOPCNTD
Definition: PPCSubtarget.h:101
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: PPCSubtarget.h:88
Align StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: PPCSubtarget.h:85
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isUsingPCRelativeCalls() const
bool enableSubRegLiveness() const override
const PPCTargetLowering * getTargetLowering() const override
Definition: PPCSubtarget.h:146
InstructionSelector * getInstructionSelector() const override
unsigned CPUDirective
Which cpu directive was used.
Definition: PPCSubtarget.h:96
AntiDepBreakMode getAntiDepBreakMode() const override
bool useAA() const override
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef TuneCPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and feature string so that we c...
CodeModel::Model getCodeModel(const TargetMachine &TM, const GlobalValue *GV) const
Calculates the effective code model for argument GV.
bool isELFv2ABI() const
Align getPlatformStackAlignment() const
Definition: PPCSubtarget.h:188
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:155
PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &TuneCPU, const std::string &FS, const PPCTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
const PPCTargetMachine & TM
Definition: PPCSubtarget.h:103
bool enableMachineScheduler() const override
Scheduling customization.
const RegisterBankInfo * getRegBankInfo() const override
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:152
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: PPCSubtarget.h:110
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Common code between 32-bit and 64-bit PowerPC targets.
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
bool shouldAssumeDSOLocal(const GlobalValue *GV) const
bool getDataSections() const
Return true if data objects should be emitted into their own section, corresponds to -fdata-sections.
CodeModel::Model getCodeModel() const
Returns the code model.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
SubArchType getSubArch() const
get the parsed subarchitecture type for this triple.
Definition: Triple.h:376
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:373
bool isOSAIX() const
Tests whether the OS is AIX.
Definition: Triple.h:710
@ PPCSubArch_spe
Definition: Triple.h:158
bool isPPC32SecurePlt() const
Tests whether the target 32-bit PowerPC uses Secure PLT.
Definition: Triple.h:977
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.