LLVM 20.0.0git
PPCSubtarget.cpp
Go to the documentation of this file.
1//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPC specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCSubtarget.h"
17#include "PPC.h"
18#include "PPCRegisterInfo.h"
19#include "PPCSelectionDAGInfo.h"
20#include "PPCTargetMachine.h"
25#include "llvm/IR/GlobalAlias.h"
26#include "llvm/IR/GlobalValue.h"
32#include <cstdlib>
33
34using namespace llvm;
35
36#define DEBUG_TYPE "ppc-subtarget"
37
38#define GET_SUBTARGETINFO_TARGET_DESC
39#define GET_SUBTARGETINFO_CTOR
40#include "PPCGenSubtargetInfo.inc"
41
42static cl::opt<bool>
43 EnableMachinePipeliner("ppc-enable-pipeliner",
44 cl::desc("Enable Machine Pipeliner for PPC"),
45 cl::init(false), cl::Hidden);
46
48 StringRef TuneCPU,
49 StringRef FS) {
50 initializeEnvironment();
51 initSubtargetFeatures(CPU, TuneCPU, FS);
52 return *this;
53}
54
55PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
56 const std::string &TuneCPU, const std::string &FS,
57 const PPCTargetMachine &TM)
58 : PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS), TargetTriple(TT),
59 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
60 TargetTriple.getArch() == Triple::ppc64le),
61 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
62 InstrInfo(*this), TLInfo(TM, *this) {
63 TSInfo = std::make_unique<PPCSelectionDAGInfo>();
64
66 Legalizer.reset(new PPCLegalizerInfo(*this));
67 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
68 RegBankInfo.reset(RBI);
69
70 InstSelector.reset(createPPCInstructionSelector(TM, *this, *RBI));
71}
72
74
76 return TSInfo.get();
77}
78
79void PPCSubtarget::initializeEnvironment() {
83}
84
85void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
86 StringRef FS) {
87 // Determine default and user specified characteristics
88 std::string CPUName = std::string(CPU);
89 if (CPUName.empty() || CPU == "generic") {
91 CPUName = "e500";
92 else
93 CPUName = std::string(PPC::getNormalizedPPCTargetCPU(TargetTriple));
94 }
95
96 // Determine the CPU to schedule for.
97 if (TuneCPU.empty()) TuneCPU = CPUName;
98
99 // Initialize scheduling itinerary for the specified CPU.
100 InstrItins = getInstrItineraryForCPU(CPUName);
101
102 // Parse features string.
103 ParseSubtargetFeatures(CPUName, TuneCPU, FS);
104
105 // If the user requested use of 64-bit regs, but the cpu selected doesn't
106 // support it, ignore.
107 if (IsPPC64 && has64BitSupport())
108 Use64BitRegs = true;
109
111 IsSecurePlt = true;
112
113 if (HasSPE && IsPPC64)
114 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
115 if (HasSPE && (HasAltivec || HasVSX || HasFPU))
117 "SPE and traditional floating point cannot both be enabled.\n", false);
118
119 // If not SPE, set standard FPU
120 if (!HasSPE)
121 HasFPU = true;
122
124
125 // Determine endianness.
127
128 if (HasAIXSmallLocalExecTLS || HasAIXSmallLocalDynamicTLS) {
129 if (!TargetTriple.isOSAIX() || !IsPPC64)
130 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute is "
131 "only supported on AIX in "
132 "64-bit mode.\n",
133 false);
134 // The aix-small-local-[exec|dynamic]-tls attribute should only be used with
135 // -data-sections, as having data sections turned off with this option
136 // is not ideal for performance. Moreover, the
137 // small-local-[exec|dynamic]-tls region is a limited resource, and should
138 // not be used for variables that may be replaced.
139 if (!TM.getDataSections())
140 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute can "
141 "only be specified with "
142 "-data-sections.\n",
143 false);
144 }
145
146 if (HasAIXShLibTLSModelOpt && (!TargetTriple.isOSAIX() || !IsPPC64))
147 report_fatal_error("The aix-shared-lib-tls-model-opt attribute "
148 "is only supported on AIX in 64-bit mode.\n",
149 false);
150}
151
152bool PPCSubtarget::enableMachineScheduler() const { return true; }
153
155 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner;
156}
157
158bool PPCSubtarget::useDFAforSMS() const { return false; }
159
160// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
161bool PPCSubtarget::enablePostRAScheduler() const { return true; }
162
163PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
164 return TargetSubtargetInfo::ANTIDEP_ALL;
165}
166
167void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
168 CriticalPathRCs.clear();
169 CriticalPathRCs.push_back(isPPC64() ?
170 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
171}
172
174 unsigned NumRegionInstrs) const {
175 // The GenericScheduler that we use defaults to scheduling bottom up only.
176 // We want to schedule from both the top and the bottom and so we set
177 // OnlyBottomUp to false.
178 // We want to do bi-directional scheduling since it provides a more balanced
179 // schedule leading to better performance.
180 Policy.OnlyBottomUp = false;
181 // Spilling is generally expensive on all PPC cores, so always enable
182 // register-pressure tracking.
183 Policy.ShouldTrackPressure = true;
184}
185
187 return true;
188}
189
190bool PPCSubtarget::enableSubRegLiveness() const { return true; }
191
193 if (isAIXABI()) {
194 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
195 // On AIX the only symbols that aren't indirect are toc-data.
196 return !GVar->hasAttribute("toc-data");
197
198 return true;
199 }
200
201 // Large code model always uses the TOC even for local symbols.
203 return true;
204
205 if (TM.shouldAssumeDSOLocal(GV))
206 return false;
207 return true;
208}
209
211 const GlobalValue *GV) const {
212 // If there isn't an attribute to override the module code model
213 // this will be the effective code model.
214 CodeModel::Model ModuleModel = TM.getCodeModel();
215
216 // Initially support per global code model for AIX only.
217 if (!isAIXABI())
218 return ModuleModel;
219
220 // Only GlobalVariables carry an attribute which can override the module code
221 // model.
222 assert(GV && "Unexpected NULL GlobalValue");
223 const GlobalVariable *GlobalVar =
224 [](const GlobalValue *GV) -> const GlobalVariable * {
225 const GlobalVariable *Var = dyn_cast<GlobalVariable>(GV);
226 if (Var)
227 return Var;
228
229 const GlobalAlias *Alias = dyn_cast<GlobalAlias>(GV);
230 if (Alias)
231 return dyn_cast<GlobalVariable>(Alias->getAliaseeObject());
232
233 return nullptr;
234 }(GV);
235
236 if (!GlobalVar)
237 return ModuleModel;
238
239 std::optional<CodeModel::Model> MaybeCodeModel = GlobalVar->getCodeModel();
240 if (MaybeCodeModel) {
241 CodeModel::Model CM = *MaybeCodeModel;
242 assert((CM == CodeModel::Small || CM == CodeModel::Large) &&
243 "invalid code model for AIX");
244 return CM;
245 }
246
247 return ModuleModel;
248}
249
250bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
251bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
252
254 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
256}
257
258// GlobalISEL
260 return CallLoweringInfo.get();
261}
262
264 return RegBankInfo.get();
265}
266
268 return Legalizer.get();
269}
270
272 return InstSelector.get();
273}
static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for PowerPC.
This file declares the targeting of the RegisterBankInfo class for PowerPC.
static cl::opt< bool > EnableMachinePipeliner("ppc-enable-pipeliner", cl::desc("Enable Machine Pipeliner for PPC"), cl::init(false), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const GlobalObject * getAliaseeObject() const
Definition: Globals.cpp:595
This class provides the information for the PowerPC target legalizer for GlobalISel.
std::unique_ptr< InstructionSelector > InstSelector
Definition: PPCSubtarget.h:116
bool enableMachinePipeliner() const override
Pipeliner customization.
bool useDFAforSMS() const override
Machine Pipeliner customization.
bool isAIXABI() const
Definition: PPCSubtarget.h:219
const CallLowering * getCallLowering() const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: PPCSubtarget.h:82
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: PPCSubtarget.h:115
~PPCSubtarget() override
POPCNTDKind HasPOPCNTD
Definition: PPCSubtarget.h:102
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: PPCSubtarget.h:89
Align StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: PPCSubtarget.h:86
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isUsingPCRelativeCalls() const
bool enableSubRegLiveness() const override
const PPCTargetLowering * getTargetLowering() const override
Definition: PPCSubtarget.h:151
InstructionSelector * getInstructionSelector() const override
unsigned CPUDirective
Which cpu directive was used.
Definition: PPCSubtarget.h:97
AntiDepBreakMode getAntiDepBreakMode() const override
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool useAA() const override
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef TuneCPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and feature string so that we c...
CodeModel::Model getCodeModel(const TargetMachine &TM, const GlobalValue *GV) const
Calculates the effective code model for argument GV.
bool isELFv2ABI() const
Align getPlatformStackAlignment() const
Definition: PPCSubtarget.h:193
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:160
PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &TuneCPU, const std::string &FS, const PPCTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
const PPCTargetMachine & TM
Definition: PPCSubtarget.h:104
std::unique_ptr< const SelectionDAGTargetInfo > TSInfo
Definition: PPCSubtarget.h:110
bool enableMachineScheduler() const override
Scheduling customization.
const RegisterBankInfo * getRegBankInfo() const override
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:157
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: PPCSubtarget.h:113
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Common code between 32-bit and 64-bit PowerPC targets.
Holds all the information related to register banks.
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:147
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
bool shouldAssumeDSOLocal(const GlobalValue *GV) const
bool getDataSections() const
Return true if data objects should be emitted into their own section, corresponds to -fdata-sections.
CodeModel::Model getCodeModel() const
Returns the code model.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
SubArchType getSubArch() const
get the parsed subarchitecture type for this triple.
Definition: Triple.h:386
bool isOSAIX() const
Tests whether the OS is AIX.
Definition: Triple.h:721
@ PPCSubArch_spe
Definition: Triple.h:157
bool isPPC32SecurePlt() const
Tests whether the target 32-bit PowerPC uses Secure PLT.
Definition: Triple.h:994
StringRef getNormalizedPPCTargetCPU(const Triple &T, StringRef CPUName="")
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.