LLVM  14.0.0git
PPCSubtarget.cpp
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1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the PPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "PPCSubtarget.h"
14 #include "GISel/PPCCallLowering.h"
15 #include "GISel/PPCLegalizerInfo.h"
17 #include "PPC.h"
18 #include "PPCRegisterInfo.h"
19 #include "PPCTargetMachine.h"
23 #include "llvm/IR/Attributes.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/IR/GlobalValue.h"
26 #include "llvm/MC/TargetRegistry.h"
29 #include <cstdlib>
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "ppc-subtarget"
34 
35 #define GET_SUBTARGETINFO_TARGET_DESC
36 #define GET_SUBTARGETINFO_CTOR
37 #include "PPCGenSubtargetInfo.inc"
38 
39 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
40 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
41 
42 static cl::opt<bool>
43  EnableMachinePipeliner("ppc-enable-pipeliner",
44  cl::desc("Enable Machine Pipeliner for PPC"),
45  cl::init(false), cl::Hidden);
46 
48  StringRef FS) {
49  initializeEnvironment();
50  initSubtargetFeatures(CPU, FS);
51  return *this;
52 }
53 
54 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
55  const std::string &FS, const PPCTargetMachine &TM)
56  : PPCGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT),
57  IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
58  TargetTriple.getArch() == Triple::ppc64le),
59  TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
60  InstrInfo(*this), TLInfo(TM, *this) {
62  Legalizer.reset(new PPCLegalizerInfo(*this));
63  auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
64  RegBankInfo.reset(RBI);
65 
67  *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI));
68 }
69 
70 void PPCSubtarget::initializeEnvironment() {
71  StackAlignment = Align(16);
73  HasMFOCRF = false;
74  Has64BitSupport = false;
75  Use64BitRegs = false;
76  UseCRBits = false;
77  HasHardFloat = false;
78  HasAltivec = false;
79  HasSPE = false;
80  HasEFPU2 = false;
81  HasFPU = false;
82  HasVSX = false;
83  NeedsTwoConstNR = false;
84  HasP8Vector = false;
85  HasP8Altivec = false;
86  HasP8Crypto = false;
87  HasP9Vector = false;
88  HasP9Altivec = false;
89  HasMMA = false;
90  HasROPProtect = false;
91  HasPrivileged = false;
92  HasP10Vector = false;
93  HasPrefixInstrs = false;
94  HasPCRelativeMemops = false;
95  HasFCPSGN = false;
96  HasFSQRT = false;
97  HasFRE = false;
98  HasFRES = false;
99  HasFRSQRTE = false;
100  HasFRSQRTES = false;
101  HasRecipPrec = false;
102  HasSTFIWX = false;
103  HasLFIWAX = false;
104  HasFPRND = false;
105  HasFPCVT = false;
106  HasISEL = false;
107  HasBPERMD = false;
108  HasExtDiv = false;
109  HasCMPB = false;
110  HasLDBRX = false;
111  IsBookE = false;
112  HasOnlyMSYNC = false;
113  IsPPC4xx = false;
114  IsPPC6xx = false;
115  IsE500 = false;
116  FeatureMFTB = false;
117  AllowsUnalignedFPAccess = false;
118  DeprecatedDST = false;
119  HasICBT = false;
121  HasPartwordAtomics = false;
122  HasQuadwordAtomics = false;
123  HasDirectMove = false;
124  HasHTM = false;
125  HasFloat128 = false;
126  HasFusion = false;
127  HasStoreFusion = false;
128  HasAddiLoadFusion = false;
129  HasAddisLoadFusion = false;
130  HasArithAddFusion = false;
131  HasAddLogicalFusion = false;
132  HasLogicalAddFusion = false;
133  HasLogicalFusion = false;
134  HasSha3Fusion = false;
135  HasCompareFusion = false;
136  HasWideImmFusion = false;
137  HasZeroMoveFusion = false;
138  HasBack2BackFusion = false;
139  IsISA2_06 = false;
140  IsISA2_07 = false;
141  IsISA3_0 = false;
142  IsISA3_1 = false;
143  UseLongCalls = false;
144  SecurePlt = false;
145  VectorsUseTwoUnits = false;
146  UsePPCPreRASchedStrategy = false;
148  PairedVectorMemops = false;
150  HasModernAIXAs = false;
151  IsAIX = false;
152 
154 }
155 
156 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
157  // Determine default and user specified characteristics
158  std::string CPUName = std::string(CPU);
159  if (CPUName.empty() || CPU == "generic") {
160  // If cross-compiling with -march=ppc64le without -mcpu
162  CPUName = "ppc64le";
164  CPUName = "e500";
165  else
166  CPUName = "generic";
167  }
168 
169  // Initialize scheduling itinerary for the specified CPU.
170  InstrItins = getInstrItineraryForCPU(CPUName);
171 
172  // Parse features string.
173  ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
174 
175  // If the user requested use of 64-bit regs, but the cpu selected doesn't
176  // support it, ignore.
177  if (IsPPC64 && has64BitSupport())
178  Use64BitRegs = true;
179 
183  SecurePlt = true;
184 
185  if (HasSPE && IsPPC64)
186  report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
187  if (HasSPE && (HasAltivec || HasVSX || HasFPU))
189  "SPE and traditional floating point cannot both be enabled.\n", false);
190 
191  // If not SPE, set standard FPU
192  if (!HasSPE)
193  HasFPU = true;
194 
196 
197  // Determine endianness.
199 }
200 
201 bool PPCSubtarget::enableMachineScheduler() const { return true; }
202 
204  return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner;
205 }
206 
207 bool PPCSubtarget::useDFAforSMS() const { return false; }
208 
209 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
210 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
211 
212 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
213  return TargetSubtargetInfo::ANTIDEP_ALL;
214 }
215 
216 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
217  CriticalPathRCs.clear();
218  CriticalPathRCs.push_back(isPPC64() ?
219  &PPC::G8RCRegClass : &PPC::GPRCRegClass);
220 }
221 
223  unsigned NumRegionInstrs) const {
224  // The GenericScheduler that we use defaults to scheduling bottom up only.
225  // We want to schedule from both the top and the bottom and so we set
226  // OnlyBottomUp to false.
227  // We want to do bi-directional scheduling since it provides a more balanced
228  // schedule leading to better performance.
229  Policy.OnlyBottomUp = false;
230  // Spilling is generally expensive on all PPC cores, so always enable
231  // register-pressure tracking.
232  Policy.ShouldTrackPressure = true;
233 }
234 
235 bool PPCSubtarget::useAA() const {
236  return true;
237 }
238 
240  return UseSubRegLiveness;
241 }
242 
244  // Large code model always uses the TOC even for local symbols.
246  return true;
247  if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
248  return false;
249  return true;
250 }
251 
252 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
253 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
254 
256  return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
258 }
259 
260 // GlobalISEL
262  return CallLoweringInfo.get();
263 }
264 
266  return RegBankInfo.get();
267 }
268 
270  return Legalizer.get();
271 }
272 
274  return InstSelector.get();
275 }
llvm::PPCSubtarget::AllowsUnalignedFPAccess
bool AllowsUnalignedFPAccess
Definition: PPCSubtarget.h:136
llvm::PPCSubtarget::PPCSubtarget
PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const PPCTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
Definition: PPCSubtarget.cpp:54
llvm::MachineSchedPolicy::OnlyBottomUp
bool OnlyBottomUp
Definition: MachineScheduler.h:189
llvm::PPCSubtarget::HasZeroMoveFusion
bool HasZeroMoveFusion
Definition: PPCSubtarget.h:157
llvm::PPCSubtarget::IsISA2_06
bool IsISA2_06
Definition: PPCSubtarget.h:159
llvm::PPCSubtarget::IsISA2_07
bool IsISA2_07
Definition: PPCSubtarget.h:160
llvm::PPCSubtarget::getRegisterInfo
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:223
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::PPCSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: PPCSubtarget.cpp:265
PPCRegisterInfo.h
llvm::PPCSubtarget::HasExtDiv
bool HasExtDiv
Definition: PPCSubtarget.h:127
llvm::X86AS::FS
@ FS
Definition: X86.h:188
PPCCallLowering.h
EnableMachinePipeliner
static cl::opt< bool > EnableMachinePipeliner("ppc-enable-pipeliner", cl::desc("Enable Machine Pipeliner for PPC"), cl::init(false), cl::Hidden)
llvm::PPCSubtarget::InstrItins
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: PPCSubtarget.h:88
llvm::PPCSubtarget::getPlatformStackAlignment
Align getPlatformStackAlignment() const
Definition: PPCSubtarget.h:319
llvm::PPCSubtarget::HasISEL
bool HasISEL
Definition: PPCSubtarget.h:125
llvm::PPCSubtarget::PredictableSelectIsExpensive
bool PredictableSelectIsExpensive
Definition: PPCSubtarget.h:169
llvm::PPCSubtarget::HasLFIWAX
bool HasLFIWAX
Definition: PPCSubtarget.h:122
llvm::PPCSubtarget::HasDirectMove
bool HasDirectMove
Definition: PPCSubtarget.h:143
llvm::PPCSubtarget::HasInvariantFunctionDescriptors
bool HasInvariantFunctionDescriptors
Definition: PPCSubtarget.h:140
llvm::PPCSubtarget::HasROPProtect
bool HasROPProtect
Definition: PPCSubtarget.h:115
llvm::CodeModel::Medium
@ Medium
Definition: CodeGen.h:28
llvm::Triple::getOSMajorVersion
unsigned getOSMajorVersion() const
Return just the major version number, this is specialized because it is a common query.
Definition: Triple.h:347
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::PPCTargetMachine::isLittleEndian
bool isLittleEndian() const
Definition: PPCTargetMachine.cpp:556
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::PPCSubtarget::HasAltivec
bool HasAltivec
Definition: PPCSubtarget.h:100
llvm::PPCSubtarget::DeprecatedDST
bool DeprecatedDST
Definition: PPCSubtarget.h:137
llvm::PPCSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: PPCSubtarget.cpp:261
llvm::PPCSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Scheduling customization.
Definition: PPCSubtarget.cpp:201
InstructionSelect.h
llvm::PPCSubtarget::getTargetMachine
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:226
llvm::PPCSubtarget::HasLogicalAddFusion
bool HasLogicalAddFusion
Definition: PPCSubtarget.h:152
llvm::PPCSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: PPCSubtarget.cpp:269
llvm::PPCSubtarget::VectorsUseTwoUnits
bool VectorsUseTwoUnits
Definition: PPCSubtarget.h:165
llvm::PPCSubtarget::HasPrefixInstrs
bool HasPrefixInstrs
Definition: PPCSubtarget.h:112
llvm::PPCSubtarget::HasLDBRX
bool HasLDBRX
Definition: PPCSubtarget.h:129
llvm::PPCSubtarget::useAA
bool useAA() const override
Definition: PPCSubtarget.cpp:235
llvm::PPCSubtarget::HasFCPSGN
bool HasFCPSGN
Definition: PPCSubtarget.h:117
llvm::PPCSubtarget::hasPCRelativeMemops
bool hasPCRelativeMemops() const
Definition: PPCSubtarget.h:288
PPCRegisterBankInfo.h
llvm::PPCSubtarget::HasVSX
bool HasVSX
Definition: PPCSubtarget.h:104
llvm::PPCSubtarget::HasPCRelativeMemops
bool HasPCRelativeMemops
Definition: PPCSubtarget.h:113
llvm::PPCSubtarget::IsBookE
bool IsBookE
Definition: PPCSubtarget.h:130
PPCSubtarget.h
CommandLine.h
llvm::PPCSubtarget::TM
const PPCTargetMachine & TM
Definition: PPCSubtarget.h:175
llvm::PPCSubtarget::HasFSQRT
bool HasFSQRT
Definition: PPCSubtarget.h:118
llvm::PPCSubtarget::HasSTFIWX
bool HasSTFIWX
Definition: PPCSubtarget.h:121
GlobalValue.h
llvm::PPCSubtarget::FeatureMFTB
bool FeatureMFTB
Definition: PPCSubtarget.h:135
llvm::PPCSubtarget::CPUDirective
unsigned CPUDirective
Which cpu directive was used.
Definition: PPCSubtarget.h:91
TargetMachine.h
llvm::PPCSubtarget::TargetTriple
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: PPCSubtarget.h:81
llvm::PPCSubtarget::HasFRE
bool HasFRE
Definition: PPCSubtarget.h:119
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
llvm::PPCSubtarget::IsE500
bool IsE500
Definition: PPCSubtarget.h:132
llvm::Legalizer
Definition: Legalizer.h:31
llvm::PPCSubtarget::HasBPERMD
bool HasBPERMD
Definition: PPCSubtarget.h:126
llvm::createPPCInstructionSelector
InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)
Definition: PPCInstructionSelector.cpp:87
llvm::PPCSubtarget::overrideSchedPolicy
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
Definition: PPCSubtarget.cpp:222
llvm::PPCSubtarget::HasAddisLoadFusion
bool HasAddisLoadFusion
Definition: PPCSubtarget.h:149
llvm::PPCSubtarget::HasCompareFusion
bool HasCompareFusion
Definition: PPCSubtarget.h:155
llvm::PPCSubtarget::HasFPU
bool HasFPU
Definition: PPCSubtarget.h:101
llvm::PPCSubtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
Definition: PPCSubtarget.cpp:210
llvm::PPCSubtarget::isPPC64
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
Definition: PPCSubtarget.cpp:253
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
PPC.h
llvm::PPCSubtarget::HasFPRND
bool HasFPRND
Definition: PPCSubtarget.h:123
llvm::PPCSubtarget::HasBack2BackFusion
bool HasBack2BackFusion
Definition: PPCSubtarget.h:158
llvm::PPCSubtarget::HasP8Crypto
bool HasP8Crypto
Definition: PPCSubtarget.h:108
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::PPCSubtarget::UseLongCalls
bool UseLongCalls
Definition: PPCSubtarget.h:163
llvm::PPCSubtarget::IsLittleEndian
bool IsLittleEndian
Definition: PPCSubtarget.h:138
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:311
llvm::PPCSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::PPCSubtarget::isGVIndirectSymbol
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
Definition: PPCSubtarget.cpp:243
llvm::PPCSubtarget::HasWideImmFusion
bool HasWideImmFusion
Definition: PPCSubtarget.h:156
PPCGenSubtargetInfo
llvm::Triple::ppc64le
@ ppc64le
Definition: Triple.h:69
llvm::cl::opt< bool >
llvm::PPCSubtarget::UsePPCPreRASchedStrategy
bool UsePPCPreRASchedStrategy
Definition: PPCSubtarget.h:166
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::PPCSubtarget::HasMFOCRF
bool HasMFOCRF
Used by the ISel to turn in optimizations for POWER4-derived architectures.
Definition: PPCSubtarget.h:94
llvm::PPCSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Definition: PPCSubtarget.cpp:239
llvm::PPCSubtarget::IsPPC6xx
bool IsPPC6xx
Definition: PPCSubtarget.h:134
llvm::PPCSubtarget::POPCNTD_Unavailable
@ POPCNTD_Unavailable
Definition: PPCSubtarget.h:74
llvm::PPCSubtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: PPCSubtarget.h:184
llvm::PPCSubtarget::useDFAforSMS
bool useDFAforSMS() const override
Machine Pipeliner customization.
Definition: PPCSubtarget.cpp:207
llvm::PPCSubtarget::HasFRES
bool HasFRES
Definition: PPCSubtarget.h:119
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:578
llvm::Triple::isOSFreeBSD
bool isOSFreeBSD() const
Definition: Triple.h:494
llvm::PPCSubtarget::HasQuadwordAtomics
bool HasQuadwordAtomics
Definition: PPCSubtarget.h:142
llvm::PPCSubtarget::IsPPC4xx
bool IsPPC4xx
Definition: PPCSubtarget.h:133
llvm::PPCSubtarget::HasFRSQRTES
bool HasFRSQRTES
Definition: PPCSubtarget.h:119
llvm::Triple::isOSOpenBSD
bool isOSOpenBSD() const
Definition: Triple.h:490
llvm::PPCSubtarget::StackAlignment
Align StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: PPCSubtarget.h:85
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::PPCSubtarget::HasMMA
bool HasMMA
Definition: PPCSubtarget.h:114
llvm::PPCSubtarget::HasOnlyMSYNC
bool HasOnlyMSYNC
Definition: PPCSubtarget.h:131
llvm::PPCSubtarget::HasP8Vector
bool HasP8Vector
Definition: PPCSubtarget.h:106
llvm::PPCSubtarget::IsPPC64
bool IsPPC64
Definition: PPCSubtarget.h:99
llvm::PPC::DIR_NONE
@ DIR_NONE
Definition: PPCSubtarget.h:41
llvm::PPCSubtarget::HasRecipPrec
bool HasRecipPrec
Definition: PPCSubtarget.h:120
llvm::PPCSubtarget::HasP9Altivec
bool HasP9Altivec
Definition: PPCSubtarget.h:110
llvm::PPCSubtarget::HasSha3Fusion
bool HasSha3Fusion
Definition: PPCSubtarget.h:154
llvm::PPCSubtarget::HasAddiLoadFusion
bool HasAddiLoadFusion
Definition: PPCSubtarget.h:148
llvm::Triple::isMusl
bool isMusl() const
Tests whether the environment is musl-libc.
Definition: Triple.h:672
llvm::PPCSubtarget::HasAddLogicalFusion
bool HasAddLogicalFusion
Definition: PPCSubtarget.h:151
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::PPCSubtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: PPCSubtarget.h:185
llvm::PPCSubtarget::HasFPCVT
bool HasFPCVT
Definition: PPCSubtarget.h:124
llvm::PPCTargetMachine::isPPC64
bool isPPC64() const
Definition: PPCTargetMachine.h:60
llvm::PPCSubtarget::has64BitSupport
bool has64BitSupport() const
has64BitSupport - Return true if the selected CPU supports 64-bit instructions, regardless of whether...
Definition: PPCSubtarget.h:243
llvm::PPCSubtarget::IsISA3_1
bool IsISA3_1
Definition: PPCSubtarget.h:162
llvm::PPCSubtarget::HasICBT
bool HasICBT
Definition: PPCSubtarget.h:139
llvm::PPCSubtarget::Use64BitRegs
bool Use64BitRegs
Definition: PPCSubtarget.h:96
llvm::PPCSubtarget::PairedVectorMemops
bool PairedVectorMemops
Definition: PPCSubtarget.h:168
llvm::TargetMachine::shouldAssumeDSOLocal
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
Definition: TargetMachine.cpp:94
llvm::PPCSubtarget::getAntiDepBreakMode
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: PPCSubtarget.cpp:212
llvm::PPCSubtarget::HasPOPCNTD
POPCNTDKind HasPOPCNTD
Definition: PPCSubtarget.h:173
llvm::PPCSubtarget::HasPartwordAtomics
bool HasPartwordAtomics
Definition: PPCSubtarget.h:141
llvm::PPCSubtarget::Has64BitSupport
bool Has64BitSupport
Definition: PPCSubtarget.h:95
llvm::MachineSchedPolicy::ShouldTrackPressure
bool ShouldTrackPressure
Definition: MachineScheduler.h:181
llvm::PPCSubtarget::HasP9Vector
bool HasP9Vector
Definition: PPCSubtarget.h:109
llvm::PPCSubtarget::HasLogicalFusion
bool HasLogicalFusion
Definition: PPCSubtarget.h:153
llvm::PPCSubtarget::getTargetLowering
const PPCTargetLowering * getTargetLowering() const override
Definition: PPCSubtarget.h:217
Attributes.h
llvm::PPCLegalizerInfo
This class provides the information for the PowerPC target legalizer for GlobalISel.
Definition: PPCLegalizerInfo.h:23
llvm::PPCSubtarget::enableMachinePipeliner
bool enableMachinePipeliner() const override
Pipeliner customization.
Definition: PPCSubtarget.cpp:203
llvm::Triple::getSubArch
SubArchType getSubArch() const
get the parsed subarchitecture type for this triple.
Definition: Triple.h:314
PPCLegalizerInfo.h
llvm::PPCSubtarget::initializeSubtargetDependencies
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
Definition: PPCSubtarget.cpp:47
llvm::PPCSubtarget::IsISA3_0
bool IsISA3_0
Definition: PPCSubtarget.h:161
Function.h
llvm::PPCSubtarget::IsAIX
bool IsAIX
Definition: PPCSubtarget.h:171
llvm::PPCSubtarget::HasSPE
bool HasSPE
Definition: PPCSubtarget.h:102
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.cpp:74
llvm::PPCTargetMachine
Common code between 32-bit and 64-bit PowerPC targets.
Definition: PPCTargetMachine.h:25
llvm::PPCSubtarget::HasModernAIXAs
bool HasModernAIXAs
Definition: PPCSubtarget.h:170
llvm::PPCSubtarget::HasArithAddFusion
bool HasArithAddFusion
Definition: PPCSubtarget.h:150
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
llvm::PPCSubtarget::HasHardFloat
bool HasHardFloat
Definition: PPCSubtarget.h:98
llvm::PPCSubtarget::UsePPCPostRASchedStrategy
bool UsePPCPostRASchedStrategy
Definition: PPCSubtarget.h:167
llvm::PPCSubtarget::NeedsTwoConstNR
bool NeedsTwoConstNR
Definition: PPCSubtarget.h:105
llvm::PPCSubtarget::HasStoreFusion
bool HasStoreFusion
Definition: PPCSubtarget.h:147
MachineScheduler.h
llvm::PPCSubtarget::isUsingPCRelativeCalls
bool isUsingPCRelativeCalls() const
Definition: PPCSubtarget.cpp:255
llvm::PPCSubtarget::HasFloat128
bool HasFloat128
Definition: PPCSubtarget.h:145
llvm::PPCSubtarget::HasFRSQRTE
bool HasFRSQRTE
Definition: PPCSubtarget.h:119
llvm::PPCSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: PPCSubtarget.cpp:273
llvm::PPCSubtarget::HasP10Vector
bool HasP10Vector
Definition: PPCSubtarget.h:111
llvm::Triple::isOSNetBSD
bool isOSNetBSD() const
Definition: Triple.h:486
llvm::PPCTargetMachine::isELFv2ABI
bool isELFv2ABI() const
Definition: PPCTargetMachine.h:59
llvm::PPCSubtarget::HasEFPU2
bool HasEFPU2
Definition: PPCSubtarget.h:103
llvm::PPCSubtarget::HasPrivileged
bool HasPrivileged
Definition: PPCSubtarget.h:116
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Definition: PPCSubtarget.h:164
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Definition: PPCSubtarget.cpp:216
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Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
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GlobalISel related APIs.
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Definition: PPCSubtarget.h:144
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Definition: PPCRegisterBankInfo.h:33
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Definition: PPCSubtarget.h:97
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Definition: CallLowering.h:43
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