LLVM 19.0.0git
PPCSubtarget.cpp
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1//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPC specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCSubtarget.h"
17#include "PPC.h"
18#include "PPCRegisterInfo.h"
19#include "PPCTargetMachine.h"
24#include "llvm/IR/Attributes.h"
25#include "llvm/IR/Function.h"
26#include "llvm/IR/GlobalValue.h"
30#include <cstdlib>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "ppc-subtarget"
35
36#define GET_SUBTARGETINFO_TARGET_DESC
37#define GET_SUBTARGETINFO_CTOR
38#include "PPCGenSubtargetInfo.inc"
39
40static cl::opt<bool>
41 EnableMachinePipeliner("ppc-enable-pipeliner",
42 cl::desc("Enable Machine Pipeliner for PPC"),
43 cl::init(false), cl::Hidden);
44
46 StringRef TuneCPU,
47 StringRef FS) {
48 initializeEnvironment();
49 initSubtargetFeatures(CPU, TuneCPU, FS);
50 return *this;
51}
52
53PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
54 const std::string &TuneCPU, const std::string &FS,
55 const PPCTargetMachine &TM)
56 : PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS), TargetTriple(TT),
57 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
58 TargetTriple.getArch() == Triple::ppc64le),
59 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
60 InstrInfo(*this), TLInfo(TM, *this) {
62 Legalizer.reset(new PPCLegalizerInfo(*this));
63 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
64 RegBankInfo.reset(RBI);
65
67 *static_cast<const PPCTargetMachine *>(&TM), *this, *RBI));
68}
69
70void PPCSubtarget::initializeEnvironment() {
74}
75
76void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
77 StringRef FS) {
78 // Determine default and user specified characteristics
79 std::string CPUName = std::string(CPU);
80 if (CPUName.empty() || CPU == "generic") {
81 // If cross-compiling with -march=ppc64le without -mcpu
83 CPUName = "ppc64le";
85 CPUName = "e500";
86 else
87 CPUName = "generic";
88 }
89
90 // Determine the CPU to schedule for.
91 if (TuneCPU.empty()) TuneCPU = CPUName;
92
93 // Initialize scheduling itinerary for the specified CPU.
94 InstrItins = getInstrItineraryForCPU(CPUName);
95
96 // Parse features string.
97 ParseSubtargetFeatures(CPUName, TuneCPU, FS);
98
99 // If the user requested use of 64-bit regs, but the cpu selected doesn't
100 // support it, ignore.
101 if (IsPPC64 && has64BitSupport())
102 Use64BitRegs = true;
103
105 IsSecurePlt = true;
106
107 if (HasSPE && IsPPC64)
108 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
109 if (HasSPE && (HasAltivec || HasVSX || HasFPU))
111 "SPE and traditional floating point cannot both be enabled.\n", false);
112
113 // If not SPE, set standard FPU
114 if (!HasSPE)
115 HasFPU = true;
116
118
119 // Determine endianness.
121
122 if (HasAIXSmallLocalExecTLS || HasAIXSmallLocalDynamicTLS) {
123 if (!TargetTriple.isOSAIX() || !IsPPC64)
124 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute is "
125 "only supported on AIX in "
126 "64-bit mode.\n",
127 false);
128 // The aix-small-local-[exec|dynamic]-tls attribute should only be used with
129 // -data-sections, as having data sections turned off with this option
130 // is not ideal for performance. Moreover, the
131 // small-local-[exec|dynamic]-tls region is a limited resource, and should
132 // not be used for variables that may be replaced.
133 if (!TM.getDataSections())
134 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute can "
135 "only be specified with "
136 "-data-sections.\n",
137 false);
138 }
139
140 if (HasAIXShLibTLSModelOpt && (!TargetTriple.isOSAIX() || !IsPPC64))
141 report_fatal_error("The aix-shared-lib-tls-model-opt attribute "
142 "is only supported on AIX in 64-bit mode.\n",
143 false);
144}
145
146bool PPCSubtarget::enableMachineScheduler() const { return true; }
147
149 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner;
150}
151
152bool PPCSubtarget::useDFAforSMS() const { return false; }
153
154// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
155bool PPCSubtarget::enablePostRAScheduler() const { return true; }
156
157PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
158 return TargetSubtargetInfo::ANTIDEP_ALL;
159}
160
161void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
162 CriticalPathRCs.clear();
163 CriticalPathRCs.push_back(isPPC64() ?
164 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
165}
166
168 unsigned NumRegionInstrs) const {
169 // The GenericScheduler that we use defaults to scheduling bottom up only.
170 // We want to schedule from both the top and the bottom and so we set
171 // OnlyBottomUp to false.
172 // We want to do bi-directional scheduling since it provides a more balanced
173 // schedule leading to better performance.
174 Policy.OnlyBottomUp = false;
175 // Spilling is generally expensive on all PPC cores, so always enable
176 // register-pressure tracking.
177 Policy.ShouldTrackPressure = true;
178}
179
181 return true;
182}
183
184bool PPCSubtarget::enableSubRegLiveness() const { return true; }
185
187 if (isAIXABI()) {
188 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
189 // On AIX the only symbols that aren't indirect are toc-data.
190 return !GVar->hasAttribute("toc-data");
191
192 return true;
193 }
194
195 // Large code model always uses the TOC even for local symbols.
197 return true;
198
199 if (TM.shouldAssumeDSOLocal(GV))
200 return false;
201 return true;
202}
203
205 const GlobalValue *GV) const {
206 // If there isn't an attribute to override the module code model
207 // this will be the effective code model.
208 CodeModel::Model ModuleModel = TM.getCodeModel();
209
210 // Initially support per global code model for AIX only.
211 if (!isAIXABI())
212 return ModuleModel;
213
214 // Only GlobalVariables carry an attribute which can override the module code
215 // model.
216 assert(GV && "Unexpected NULL GlobalValue");
217 const GlobalVariable *GlobalVar =
218 [](const GlobalValue *GV) -> const GlobalVariable * {
219 const GlobalVariable *Var = dyn_cast<GlobalVariable>(GV);
220 if (Var)
221 return Var;
222
223 const GlobalAlias *Alias = dyn_cast<GlobalAlias>(GV);
224 if (Alias)
225 return dyn_cast<GlobalVariable>(Alias->getAliaseeObject());
226
227 return nullptr;
228 }(GV);
229
230 if (!GlobalVar)
231 return ModuleModel;
232
233 std::optional<CodeModel::Model> MaybeCodeModel = GlobalVar->getCodeModel();
234 if (MaybeCodeModel) {
235 CodeModel::Model CM = *MaybeCodeModel;
236 assert((CM == CodeModel::Small || CM == CodeModel::Large) &&
237 "invalid code model for AIX");
238 return CM;
239 }
240
241 return ModuleModel;
242}
243
244bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
245bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }
246
248 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
250}
251
252// GlobalISEL
254 return CallLoweringInfo.get();
255}
256
258 return RegBankInfo.get();
259}
260
262 return Legalizer.get();
263}
264
266 return InstSelector.get();
267}
static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)
This file contains the simple types necessary to represent the attributes associated with functions a...
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for PowerPC.
This file declares the targeting of the RegisterBankInfo class for PowerPC.
static cl::opt< bool > EnableMachinePipeliner("ppc-enable-pipeliner", cl::desc("Enable Machine Pipeliner for PPC"), cl::init(false), cl::Hidden)
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const GlobalObject * getAliaseeObject() const
Definition: Globals.cpp:578
This class provides the information for the PowerPC target legalizer for GlobalISel.
std::unique_ptr< InstructionSelector > InstSelector
Definition: PPCSubtarget.h:113
bool enableMachinePipeliner() const override
Pipeliner customization.
bool useDFAforSMS() const override
Machine Pipeliner customization.
bool isAIXABI() const
Definition: PPCSubtarget.h:214
const CallLowering * getCallLowering() const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: PPCSubtarget.h:81
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: PPCSubtarget.h:112
POPCNTDKind HasPOPCNTD
Definition: PPCSubtarget.h:101
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: PPCSubtarget.h:88
Align StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: PPCSubtarget.h:85
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isUsingPCRelativeCalls() const
bool enableSubRegLiveness() const override
const PPCTargetLowering * getTargetLowering() const override
Definition: PPCSubtarget.h:146
InstructionSelector * getInstructionSelector() const override
unsigned CPUDirective
Which cpu directive was used.
Definition: PPCSubtarget.h:96
AntiDepBreakMode getAntiDepBreakMode() const override
bool useAA() const override
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef TuneCPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and feature string so that we c...
CodeModel::Model getCodeModel(const TargetMachine &TM, const GlobalValue *GV) const
Calculates the effective code model for argument GV.
bool isELFv2ABI() const
Align getPlatformStackAlignment() const
Definition: PPCSubtarget.h:188
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:155
PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &TuneCPU, const std::string &FS, const PPCTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
const PPCTargetMachine & TM
Definition: PPCSubtarget.h:103
bool enableMachineScheduler() const override
Scheduling customization.
const RegisterBankInfo * getRegBankInfo() const override
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:152
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: PPCSubtarget.h:110
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Common code between 32-bit and 64-bit PowerPC targets.
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
bool shouldAssumeDSOLocal(const GlobalValue *GV) const
bool getDataSections() const
Return true if data objects should be emitted into their own section, corresponds to -fdata-sections.
CodeModel::Model getCodeModel() const
Returns the code model.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
SubArchType getSubArch() const
get the parsed subarchitecture type for this triple.
Definition: Triple.h:376
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:373
bool isOSAIX() const
Tests whether the OS is AIX.
Definition: Triple.h:710
@ PPCSubArch_spe
Definition: Triple.h:158
bool isPPC32SecurePlt() const
Tests whether the target 32-bit PowerPC uses Secure PLT.
Definition: Triple.h:977
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.