LLVM 20.0.0git
PPCSubtarget.h
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1//===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14#define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15
16#include "PPCFrameLowering.h"
17#include "PPCISelLowering.h"
18#include "PPCInstrInfo.h"
24#include "llvm/IR/DataLayout.h"
27#include <string>
28
29#define GET_SUBTARGETINFO_HEADER
30#include "PPCGenSubtargetInfo.inc"
31
32// GCC #defines PPC on Linux but we use it as our namespace name
33#undef PPC
34
35namespace llvm {
36class StringRef;
37
38namespace PPC {
39 // -m directive values.
40enum {
66 DIR_64
67};
68}
69
70class GlobalValue;
71
73public:
78 };
79
80protected:
81 /// TargetTriple - What processor and OS we're targeting.
83
84 /// stackAlignment - The minimum alignment known to hold of the stack frame on
85 /// entry to the function and which must be maintained by every function.
87
88 /// Selected instruction itineraries (one entry per itinerary class.)
90
91// Bool members corresponding to the SubtargetFeatures defined in tablegen.
92#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
93 bool ATTRIBUTE = DEFAULT;
94#include "PPCGenSubtargetInfo.inc"
95
96 /// Which cpu directive was used.
97 unsigned CPUDirective;
98
99 bool IsPPC64;
101
103
109
110 /// GlobalISel related APIs.
111 std::unique_ptr<CallLowering> CallLoweringInfo;
112 std::unique_ptr<LegalizerInfo> Legalizer;
113 std::unique_ptr<RegisterBankInfo> RegBankInfo;
114 std::unique_ptr<InstructionSelector> InstSelector;
115
116public:
117 /// This constructor initializes the data members to match that
118 /// of the specified triple.
119 ///
120 PPCSubtarget(const Triple &TT, const std::string &CPU,
121 const std::string &TuneCPU, const std::string &FS,
122 const PPCTargetMachine &TM);
123
124 /// ParseSubtargetFeatures - Parses features string setting specified
125 /// subtarget options. Definition of function is auto generated by tblgen.
127
128 /// getStackAlignment - Returns the minimum alignment known to hold of the
129 /// stack frame on entry to the function and which must be maintained by every
130 /// function for this subtarget.
132
133 /// getCPUDirective - Returns the -m directive specified for the cpu.
134 ///
135 unsigned getCPUDirective() const { return CPUDirective; }
136
137 /// getInstrItins - Return the instruction itineraries based on subtarget
138 /// selection.
140 return &InstrItins;
141 }
142
143 const PPCFrameLowering *getFrameLowering() const override {
144 return &FrameLowering;
145 }
146 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
147 const PPCTargetLowering *getTargetLowering() const override {
148 return &TLInfo;
149 }
151 return &TSInfo;
152 }
153 const PPCRegisterInfo *getRegisterInfo() const override {
154 return &getInstrInfo()->getRegisterInfo();
155 }
156 const PPCTargetMachine &getTargetMachine() const { return TM; }
157
158 /// initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and
159 /// feature string so that we can use initializer lists for subtarget
160 /// initialization.
162 StringRef TuneCPU,
163 StringRef FS);
164
165private:
166 void initializeEnvironment();
167 void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
168
169public:
170 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
171 ///
172 bool isPPC64() const;
173
174 // useSoftFloat - Return true if soft-float option is turned on.
175 bool useSoftFloat() const {
176 if (isAIXABI() && !HasHardFloat)
177 report_fatal_error("soft-float is not yet supported on AIX.");
178 return !HasHardFloat;
179 }
180
181 // isLittleEndian - True if generating little-endian code
182 bool isLittleEndian() const { return IsLittleEndian; }
183
184// Getters for SubtargetFeatures defined in tablegen.
185#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
186 bool GETTER() const { return ATTRIBUTE; }
187#include "PPCGenSubtargetInfo.inc"
188
190 return Align(16);
191 }
192
193 unsigned getRedZoneSize() const {
194 if (isPPC64())
195 // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
196 return 288;
197
198 // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
199 // PPC32 SVR4ABI has no redzone.
200 return isAIXABI() ? 220 : 0;
201 }
202
204 return hasVSX() && isLittleEndian() && !hasP9Vector();
205 }
206
208
209 const Triple &getTargetTriple() const { return TargetTriple; }
210
211 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
213 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
214
215 bool isAIXABI() const { return TargetTriple.isOSAIX(); }
216 bool isSVR4ABI() const { return !isAIXABI(); }
217 bool isELFv2ABI() const;
218
219 bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); }
220 bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); }
221 bool isUsingPCRelativeCalls() const;
222
223 /// Originally, this function return hasISEL(). Now we always enable it,
224 /// but may expand the ISEL instruction later.
225 bool enableEarlyIfConversion() const override { return true; }
226
227 /// Scheduling customization.
228 bool enableMachineScheduler() const override;
229 /// Pipeliner customization.
230 bool enableMachinePipeliner() const override;
231 /// Machine Pipeliner customization
232 bool useDFAforSMS() const override;
233 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
234 bool enablePostRAScheduler() const override;
235 AntiDepBreakMode getAntiDepBreakMode() const override;
236 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
237
239 unsigned NumRegionInstrs) const override;
240 bool useAA() const override;
241
242 bool enableSubRegLiveness() const override;
243
244 bool enableSpillageCopyElimination() const override { return true; }
245
246 /// True if the GV will be accessed via an indirect symbol.
247 bool isGVIndirectSymbol(const GlobalValue *GV) const;
248
249 /// Calculates the effective code model for argument GV.
251 const GlobalValue *GV) const;
252
253 /// True if the ABI is descriptor based.
255 // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
256 // v1 ABI uses descriptors.
257 return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
258 }
259
260 unsigned descriptorTOCAnchorOffset() const {
262 "Should only be called when the target uses descriptors.");
263 return IsPPC64 ? 8 : 4;
264 }
265
268 "Should only be called when the target uses descriptors.");
269 return IsPPC64 ? 16 : 8;
270 }
271
274 "Should only be called when the target uses descriptors.");
275 return IsPPC64 ? PPC::X11 : PPC::R11;
276 }
277
279 assert((is64BitELFABI() || isAIXABI()) &&
280 "Should only be called when the target is a TOC based ABI.");
281 return IsPPC64 ? PPC::X2 : PPC::R2;
282 }
283
285 assert((is64BitELFABI() || isAIXABI()) &&
286 "Should only be called for targets with a thread pointer register.");
287 return IsPPC64 ? PPC::X13 : PPC::R13;
288 }
289
291 return IsPPC64 ? PPC::X1 : PPC::R1;
292 }
293
294 bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
295
297 return PredictableSelectIsExpensive;
298 }
299
300 // Select allocation orders of GPRC and G8RC. It should be strictly consistent
301 // with corresponding AltOrders in PPCRegisterInfo.td.
302 unsigned getGPRAllocationOrderIdx() const {
303 if (is64BitELFABI())
304 return 1;
305 if (isAIXABI())
306 return 2;
307 return 0;
308 }
309
310 // GlobalISEL
311 const CallLowering *getCallLowering() const override;
312 const RegisterBankInfo *getRegBankInfo() const override;
313 const LegalizerInfo *getLegalizerInfo() const override;
315};
316} // End llvm namespace
317
318#endif
This file describes how to lower LLVM calls to machine code calls.
Interface for Targets to specify which operations they can successfully select and how the others sho...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Itinerary data supplied by a subtarget to be used by a target.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:274
std::unique_ptr< InstructionSelector > InstSelector
Definition: PPCSubtarget.h:114
bool enableMachinePipeliner() const override
Pipeliner customization.
bool useDFAforSMS() const override
Machine Pipeliner customization.
bool is32BitELFABI() const
Definition: PPCSubtarget.h:220
std::unique_ptr< LegalizerInfo > Legalizer
Definition: PPCSubtarget.h:112
PPCTargetLowering TLInfo
Definition: PPCSubtarget.h:107
unsigned descriptorTOCAnchorOffset() const
Definition: PPCSubtarget.h:260
bool isTargetMachO() const
Definition: PPCSubtarget.h:212
PPCFrameLowering FrameLowering
Definition: PPCSubtarget.h:105
bool isAIXABI() const
Definition: PPCSubtarget.h:215
const CallLowering * getCallLowering() const override
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: PPCSubtarget.h:82
const LegalizerInfo * getLegalizerInfo() const override
unsigned getGPRAllocationOrderIdx() const
Definition: PPCSubtarget.h:302
bool useSoftFloat() const
Definition: PPCSubtarget.h:175
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: PPCSubtarget.h:113
bool isXRaySupported() const override
Definition: PPCSubtarget.h:294
POPCNTDKind HasPOPCNTD
Definition: PPCSubtarget.h:102
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: PPCSubtarget.h:89
Align StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: PPCSubtarget.h:86
const PPCFrameLowering * getFrameLowering() const override
Definition: PPCSubtarget.h:143
bool needsSwapsForVSXMemOps() const
Definition: PPCSubtarget.h:203
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
PPCInstrInfo InstrInfo
Definition: PPCSubtarget.h:106
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isUsingPCRelativeCalls() const
bool enableSubRegLiveness() const override
bool usesFunctionDescriptors() const
True if the ABI is descriptor based.
Definition: PPCSubtarget.h:254
const PPCTargetLowering * getTargetLowering() const override
Definition: PPCSubtarget.h:147
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: PPCSubtarget.h:139
SelectionDAGTargetInfo TSInfo
Definition: PPCSubtarget.h:108
InstructionSelector * getInstructionSelector() const override
bool enableEarlyIfConversion() const override
Originally, this function return hasISEL().
Definition: PPCSubtarget.h:225
MCRegister getEnvironmentPointerRegister() const
Definition: PPCSubtarget.h:272
unsigned CPUDirective
Which cpu directive was used.
Definition: PPCSubtarget.h:97
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:146
unsigned getRedZoneSize() const
Definition: PPCSubtarget.h:193
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
Definition: PPCSubtarget.h:150
AntiDepBreakMode getAntiDepBreakMode() const override
MCRegister getThreadPointerRegister() const
Definition: PPCSubtarget.h:284
bool isSVR4ABI() const
Definition: PPCSubtarget.h:216
unsigned getCPUDirective() const
getCPUDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:135
bool enableSpillageCopyElimination() const override
Definition: PPCSubtarget.h:244
POPCNTDKind hasPOPCNTD() const
Definition: PPCSubtarget.h:207
bool isLittleEndian() const
Definition: PPCSubtarget.h:182
bool isTargetLinux() const
Definition: PPCSubtarget.h:213
MCRegister getTOCPointerRegister() const
Definition: PPCSubtarget.h:278
bool isTargetELF() const
Definition: PPCSubtarget.h:211
MCRegister getStackPointerRegister() const
Definition: PPCSubtarget.h:290
bool useAA() const override
Align getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: PPCSubtarget.h:131
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef TuneCPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and feature string so that we c...
bool is64BitELFABI() const
Definition: PPCSubtarget.h:219
CodeModel::Model getCodeModel(const TargetMachine &TM, const GlobalValue *GV) const
Calculates the effective code model for argument GV.
bool isELFv2ABI() const
Align getPlatformStackAlignment() const
Definition: PPCSubtarget.h:189
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:156
const PPCTargetMachine & TM
Definition: PPCSubtarget.h:104
bool isPredictableSelectIsExpensive() const
Definition: PPCSubtarget.h:296
bool enableMachineScheduler() const override
Scheduling customization.
const RegisterBankInfo * getRegBankInfo() const override
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:153
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
const Triple & getTargetTriple() const
Definition: PPCSubtarget.h:209
unsigned descriptorEnvironmentPointerOffset() const
Definition: PPCSubtarget.h:266
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: PPCSubtarget.h:111
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Common code between 32-bit and 64-bit PowerPC targets.
Holds all the information related to register banks.
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:732
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:678
bool isOSAIX() const
Tests whether the OS is AIX.
Definition: Triple.h:710
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:719
@ DIR_PWR_FUTURE
Definition: PPCSubtarget.h:65
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.