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13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
29 #define GET_SUBTARGETINFO_HEADER
30 #include "PPCGenSubtargetInfo.inc"
234 void initializeEnvironment();
391 unsigned NumRegionInstrs)
const override;
392 bool useAA()
const override;
408 "Should only be called when the target uses descriptors.");
414 "Should only be called when the target uses descriptors.");
420 "Should only be called when the target uses descriptors.");
421 return IsPPC64 ? PPC::X11 : PPC::R11;
426 "Should only be called when the target is a TOC based ABI.");
431 return IsPPC64 ? PPC::X1 : PPC::R1;
bool AllowsUnalignedFPAccess
PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const PPCTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
bool useCRBits() const
useCRBits - Return true if we should store and manipulate i1 values in the individual condition regis...
bool hasRecipPrec() const
POPCNTDKind hasPOPCNTD() const
const PPCRegisterInfo * getRegisterInfo() const override
This is an optimization pass for GlobalISel generic memory operations.
SelectionDAGTargetInfo TSInfo
bool usesFunctionDescriptors() const
True if the ABI is descriptor based.
const RegisterBankInfo * getRegBankInfo() const override
bool hasPrefixInstrs() const
bool hasAddisLoadFusion() const
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Align getPlatformStackAlignment() const
bool PredictableSelectIsExpensive
bool HasInvariantFunctionDescriptors
bool hasSha3Fusion() const
bool isLittleEndian() const
bool hasROPProtect() const
const PPCFrameLowering * getFrameLowering() const override
const Triple & getTargetTriple() const
Triple - Helper class for working with autoconf configuration names.
const CallLowering * getCallLowering() const override
bool enableMachineScheduler() const override
Scheduling customization.
bool hasArithAddFusion() const
bool isOSLinux() const
Tests whether the OS is Linux.
const PPCTargetMachine & getTargetMachine() const
bool needsTwoConstNR() const
const LegalizerInfo * getLegalizerInfo() const override
bool vectorsUseTwoUnits() const
bool useAA() const override
MCRegister getStackPointerRegister() const
bool usePPCPostRASchedStrategy() const
bool is64BitELFABI() const
bool hasPCRelativeMemops() const
bool hasP8Altivec() const
const PPCTargetMachine & TM
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
unsigned CPUDirective
Which cpu directive was used.
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
bool hasLogicalAddFusion() const
MCRegister getTOCPointerRegister() const
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
std::unique_ptr< LegalizerInfo > Legalizer
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
unsigned descriptorTOCAnchorOffset() const
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool hasPartwordAtomics() const
unsigned getRedZoneSize() const
const PPCInstrInfo * getInstrInfo() const override
bool usePPCPreRASchedStrategy() const
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool isOSAIX() const
Tests whether the OS is AIX.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
bool hasOnlyMSYNC() const
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool UsePPCPreRASchedStrategy
Holds all the information related to register banks.
bool isTargetLinux() const
Provides the logic to select generic machine instructions.
bool HasMFOCRF
Used by the ISel to turn in optimizations for POWER4-derived architectures.
bool enableSubRegLiveness() const override
std::unique_ptr< RegisterBankInfo > RegBankInfo
bool useDFAforSMS() const override
Machine Pipeliner customization.
bool hasP9Altivec() const
bool is32BitELFABI() const
bool needsSwapsForVSXMemOps() const
bool hasWideImmFusion() const
Align StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
bool hasBack2BackFusion() const
bool hasLogicalFusion() const
bool isPredictableSelectIsExpensive() const
PPCFrameLowering FrameLowering
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
bool hasDirectMove() const
bool hasStoreFusion() const
StringRef - Represent a constant reference to a string, i.e.
std::unique_ptr< InstructionSelector > InstSelector
Align getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
bool has64BitSupport() const
has64BitSupport - Return true if the selected CPU supports 64-bit instructions, regardless of whether...
bool hasAddLogicalFusion() const
AntiDepBreakMode getAntiDepBreakMode() const override
bool hasZeroMoveFusion() const
bool hasInvariantFunctionDescriptors() const
const PPCTargetLowering * getTargetLowering() const override
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool enableMachinePipeliner() const override
Pipeliner customization.
bool hasPrivileged() const
bool useSoftFloat() const
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool hasAddiLoadFusion() const
Common code between 32-bit and 64-bit PowerPC targets.
unsigned getGPRAllocationOrderIdx() const
bool hasCompareFusion() const
bool UsePPCPostRASchedStrategy
bool isUsingPCRelativeCalls() const
InstructionSelector * getInstructionSelector() const override
MCRegister getEnvironmentPointerRegister() const
unsigned descriptorEnvironmentPointerOffset() const
should just be implemented with a CLZ instruction Since there are other e PPC
bool isXRaySupported() const override
bool isDeprecatedDST() const
bool useLongCalls() const
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
unsigned getCPUDirective() const
getCPUDirective - Returns the -m directive specified for the cpu.
bool hasQuadwordAtomics() const
bool allowsUnalignedFPAccess() const
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isFeatureMFTB() const
Itinerary data supplied by a subtarget to be used by a target.
bool isTargetMachO() const
bool enableEarlyIfConversion() const override
Originally, this function return hasISEL().
bool pairedVectorMemops() const
bool use64BitRegs() const
use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit registers in 32-bit mode when...
Wrapper class representing physical registers. Should be passed by value.
bool hasP10Vector() const