LLVM  12.0.0git
PPCSubtarget.h
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1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the PowerPC specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15 
16 #include "PPCFrameLowering.h"
17 #include "PPCISelLowering.h"
18 #include "PPCInstrInfo.h"
19 #include "llvm/ADT/Triple.h"
25 #include "llvm/IR/DataLayout.h"
27 #include <string>
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "PPCGenSubtargetInfo.inc"
31 
32 // GCC #defines PPC on Linux but we use it as our namespace name
33 #undef PPC
34 
35 namespace llvm {
36 class StringRef;
37 
38 namespace PPC {
39  // -m directive values.
40 enum {
66 };
67 }
68 
69 class GlobalValue;
70 
72 public:
73  enum POPCNTDKind {
77  };
78 
79 protected:
80  /// TargetTriple - What processor and OS we're targeting.
82 
83  /// stackAlignment - The minimum alignment known to hold of the stack frame on
84  /// entry to the function and which must be maintained by every function.
86 
87  /// Selected instruction itineraries (one entry per itinerary class.)
89 
90  /// Which cpu directive was used.
91  unsigned CPUDirective;
92 
93  /// Used by the ISel to turn in optimizations for POWER4-derived architectures
94  bool HasMFOCRF;
97  bool UseCRBits;
99  bool IsPPC64;
101  bool HasFPU;
102  bool HasSPE;
103  bool HasEFPU2;
104  bool HasVSX;
114  bool HasMMA;
115  bool HasFCPSGN;
116  bool HasFSQRT;
119  bool HasSTFIWX;
120  bool HasLFIWAX;
121  bool HasFPRND;
122  bool HasFPCVT;
123  bool HasISEL;
124  bool HasBPERMD;
125  bool HasExtDiv;
126  bool HasCMPB;
127  bool HasLDBRX;
128  bool IsBookE;
130  bool IsE500;
131  bool IsPPC4xx;
132  bool IsPPC6xx;
137  bool HasICBT;
141  bool HasHTM;
143  bool HasFusion;
147  bool IsISA3_0;
148  bool IsISA3_1;
150  bool SecurePlt;
157  bool IsAIX;
158 
160 
166 
167  /// GlobalISel related APIs.
168  std::unique_ptr<CallLowering> CallLoweringInfo;
169  std::unique_ptr<LegalizerInfo> Legalizer;
170  std::unique_ptr<RegisterBankInfo> RegBankInfo;
171  std::unique_ptr<InstructionSelector> InstSelector;
172 
173 public:
174  /// This constructor initializes the data members to match that
175  /// of the specified triple.
176  ///
177  PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
178  const PPCTargetMachine &TM);
179 
180  /// ParseSubtargetFeatures - Parses features string setting specified
181  /// subtarget options. Definition of function is auto generated by tblgen.
183 
184  /// getStackAlignment - Returns the minimum alignment known to hold of the
185  /// stack frame on entry to the function and which must be maintained by every
186  /// function for this subtarget.
188 
189  /// getCPUDirective - Returns the -m directive specified for the cpu.
190  ///
191  unsigned getCPUDirective() const { return CPUDirective; }
192 
193  /// getInstrItins - Return the instruction itineraries based on subtarget
194  /// selection.
195  const InstrItineraryData *getInstrItineraryData() const override {
196  return &InstrItins;
197  }
198 
199  const PPCFrameLowering *getFrameLowering() const override {
200  return &FrameLowering;
201  }
202  const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
203  const PPCTargetLowering *getTargetLowering() const override {
204  return &TLInfo;
205  }
206  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
207  return &TSInfo;
208  }
209  const PPCRegisterInfo *getRegisterInfo() const override {
210  return &getInstrInfo()->getRegisterInfo();
211  }
212  const PPCTargetMachine &getTargetMachine() const { return TM; }
213 
214  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
215  /// so that we can use initializer lists for subtarget initialization.
217 
218 private:
219  void initializeEnvironment();
220  void initSubtargetFeatures(StringRef CPU, StringRef FS);
221 
222 public:
223  /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
224  ///
225  bool isPPC64() const;
226 
227  /// has64BitSupport - Return true if the selected CPU supports 64-bit
228  /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
229  bool has64BitSupport() const { return Has64BitSupport; }
230  // useSoftFloat - Return true if soft-float option is turned on.
231  bool useSoftFloat() const {
232  if (isAIXABI() && !HasHardFloat)
233  report_fatal_error("soft-float is not yet supported on AIX.");
234  return !HasHardFloat;
235  }
236 
237  /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
238  /// registers in 32-bit mode when possible. This can only true if
239  /// has64BitSupport() returns true.
240  bool use64BitRegs() const { return Use64BitRegs; }
241 
242  /// useCRBits - Return true if we should store and manipulate i1 values in
243  /// the individual condition register bits.
244  bool useCRBits() const { return UseCRBits; }
245 
246  // isLittleEndian - True if generating little-endian code
247  bool isLittleEndian() const { return IsLittleEndian; }
248 
249  // Specific obvious features.
250  bool hasFCPSGN() const { return HasFCPSGN; }
251  bool hasFSQRT() const { return HasFSQRT; }
252  bool hasFRE() const { return HasFRE; }
253  bool hasFRES() const { return HasFRES; }
254  bool hasFRSQRTE() const { return HasFRSQRTE; }
255  bool hasFRSQRTES() const { return HasFRSQRTES; }
256  bool hasRecipPrec() const { return HasRecipPrec; }
257  bool hasSTFIWX() const { return HasSTFIWX; }
258  bool hasLFIWAX() const { return HasLFIWAX; }
259  bool hasFPRND() const { return HasFPRND; }
260  bool hasFPCVT() const { return HasFPCVT; }
261  bool hasAltivec() const { return HasAltivec; }
262  bool hasSPE() const { return HasSPE; }
263  bool hasEFPU2() const { return HasEFPU2; }
264  bool hasFPU() const { return HasFPU; }
265  bool hasVSX() const { return HasVSX; }
266  bool needsTwoConstNR() const { return NeedsTwoConstNR; }
267  bool hasP8Vector() const { return HasP8Vector; }
268  bool hasP8Altivec() const { return HasP8Altivec; }
269  bool hasP8Crypto() const { return HasP8Crypto; }
270  bool hasP9Vector() const { return HasP9Vector; }
271  bool hasP9Altivec() const { return HasP9Altivec; }
272  bool hasP10Vector() const { return HasP10Vector; }
273  bool hasPrefixInstrs() const { return HasPrefixInstrs; }
274  bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
275  bool hasMMA() const { return HasMMA; }
276  bool pairedVectorMemops() const { return PairedVectorMemops; }
277  bool hasMFOCRF() const { return HasMFOCRF; }
278  bool hasISEL() const { return HasISEL; }
279  bool hasBPERMD() const { return HasBPERMD; }
280  bool hasExtDiv() const { return HasExtDiv; }
281  bool hasCMPB() const { return HasCMPB; }
282  bool hasLDBRX() const { return HasLDBRX; }
283  bool isBookE() const { return IsBookE; }
284  bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
285  bool isPPC4xx() const { return IsPPC4xx; }
286  bool isPPC6xx() const { return IsPPC6xx; }
287  bool isSecurePlt() const {return SecurePlt; }
288  bool vectorsUseTwoUnits() const {return VectorsUseTwoUnits; }
289  bool isE500() const { return IsE500; }
290  bool isFeatureMFTB() const { return FeatureMFTB; }
292  bool isDeprecatedDST() const { return DeprecatedDST; }
293  bool hasICBT() const { return HasICBT; }
296  }
299  bool hasPartwordAtomics() const { return HasPartwordAtomics; }
300  bool hasDirectMove() const { return HasDirectMove; }
301 
303  return Align(16);
304  }
305 
306  unsigned getRedZoneSize() const {
307  if (isPPC64())
308  // 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
309  return 288;
310 
311  // AIX PPC32: 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
312  // PPC32 SVR4ABI has no redzone.
313  return isAIXABI() ? 220 : 0;
314  }
315 
316  bool hasHTM() const { return HasHTM; }
317  bool hasFloat128() const { return HasFloat128; }
318  bool isISA3_0() const { return IsISA3_0; }
319  bool isISA3_1() const { return IsISA3_1; }
320  bool useLongCalls() const { return UseLongCalls; }
321  bool hasFusion() const { return HasFusion; }
322  bool hasStoreFusion() const { return HasStoreFusion; }
323  bool hasAddiLoadFusion() const { return HasAddiLoadFusion; }
324  bool hasAddisLoadFusion() const { return HasAddisLoadFusion; }
325  bool needsSwapsForVSXMemOps() const {
326  return hasVSX() && isLittleEndian() && !hasP9Vector();
327  }
328 
329  POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
330 
331  const Triple &getTargetTriple() const { return TargetTriple; }
332 
333  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
334  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
335  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
336 
337  bool isAIXABI() const { return TargetTriple.isOSAIX(); }
338  bool isSVR4ABI() const { return !isAIXABI(); }
339  bool isELFv2ABI() const;
340 
341  bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); }
342  bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); }
343  bool isUsingPCRelativeCalls() const;
344 
345  /// Originally, this function return hasISEL(). Now we always enable it,
346  /// but may expand the ISEL instruction later.
347  bool enableEarlyIfConversion() const override { return true; }
348 
349  /// Scheduling customization.
350  bool enableMachineScheduler() const override;
351  /// Pipeliner customization.
352  bool enableMachinePipeliner() const override;
353  /// Machine Pipeliner customization
354  bool useDFAforSMS() const override;
355  /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
356  bool enablePostRAScheduler() const override;
357  AntiDepBreakMode getAntiDepBreakMode() const override;
358  void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
359 
361  unsigned NumRegionInstrs) const override;
362  bool useAA() const override;
363 
364  bool enableSubRegLiveness() const override;
365 
366  /// True if the GV will be accessed via an indirect symbol.
367  bool isGVIndirectSymbol(const GlobalValue *GV) const;
368 
369  /// True if the ABI is descriptor based.
370  bool usesFunctionDescriptors() const {
371  // Both 32-bit and 64-bit AIX are descriptor based. For ELF only the 64-bit
372  // v1 ABI uses descriptors.
373  return isAIXABI() || (is64BitELFABI() && !isELFv2ABI());
374  }
375 
376  unsigned descriptorTOCAnchorOffset() const {
378  "Should only be called when the target uses descriptors.");
379  return IsPPC64 ? 8 : 4;
380  }
381 
384  "Should only be called when the target uses descriptors.");
385  return IsPPC64 ? 16 : 8;
386  }
387 
390  "Should only be called when the target uses descriptors.");
391  return IsPPC64 ? PPC::X11 : PPC::R11;
392  }
393 
395  assert((is64BitELFABI() || isAIXABI()) &&
396  "Should only be called when the target is a TOC based ABI.");
397  return IsPPC64 ? PPC::X2 : PPC::R2;
398  }
399 
401  return IsPPC64 ? PPC::X1 : PPC::R1;
402  }
403 
404  bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; }
405 
408  }
409 
410  // GlobalISEL
411  const CallLowering *getCallLowering() const override;
412  const RegisterBankInfo *getRegBankInfo() const override;
413  const LegalizerInfo *getLegalizerInfo() const override;
415 };
416 } // End llvm namespace
417 
418 #endif
unsigned descriptorEnvironmentPointerOffset() const
Definition: PPCSubtarget.h:382
bool isAIXABI() const
Definition: PPCSubtarget.h:337
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const PPCTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
const RegisterBankInfo * getRegBankInfo() const override
bool hasFPCVT() const
Definition: PPCSubtarget.h:260
bool enableEarlyIfConversion() const override
Originally, this function return hasISEL().
Definition: PPCSubtarget.h:347
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
bool hasBPERMD() const
Definition: PPCSubtarget.h:279
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Align getPlatformStackAlignment() const
Definition: PPCSubtarget.h:302
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
Definition: PPCSubtarget.h:206
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
bool hasPCRelativeMemops() const
Definition: PPCSubtarget.h:274
Align getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: PPCSubtarget.h:187
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:629
MCRegister getStackPointerRegister() const
Definition: PPCSubtarget.h:400
bool hasMMA() const
Definition: PPCSubtarget.h:275
Align StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: PPCSubtarget.h:85
bool useAA() const override
bool hasVSX() const
Definition: PPCSubtarget.h:265
bool hasFSQRT() const
Definition: PPCSubtarget.h:251
bool useDFAforSMS() const override
Machine Pipeliner customization.
bool hasStoreFusion() const
Definition: PPCSubtarget.h:322
#define R2(n)
std::unique_ptr< LegalizerInfo > Legalizer
Definition: PPCSubtarget.h:169
bool hasSPE() const
Definition: PPCSubtarget.h:262
bool isTargetLinux() const
Definition: PPCSubtarget.h:335
bool needsTwoConstNR() const
Definition: PPCSubtarget.h:266
bool isISA3_1() const
Definition: PPCSubtarget.h:319
bool hasAddisLoadFusion() const
Definition: PPCSubtarget.h:324
Holds all the information related to register banks.
bool hasFusion() const
Definition: PPCSubtarget.h:321
bool hasP10Vector() const
Definition: PPCSubtarget.h:272
bool isISA3_0() const
Definition: PPCSubtarget.h:318
SelectionDAGTargetInfo TSInfo
Definition: PPCSubtarget.h:165
bool hasDirectMove() const
Definition: PPCSubtarget.h:300
POPCNTDKind HasPOPCNTD
Definition: PPCSubtarget.h:159
bool hasLDBRX() const
Definition: PPCSubtarget.h:282
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool hasMFOCRF() const
Definition: PPCSubtarget.h:277
bool hasP8Crypto() const
Definition: PPCSubtarget.h:269
std::unique_ptr< InstructionSelector > InstSelector
Definition: PPCSubtarget.h:171
bool is64BitELFABI() const
Definition: PPCSubtarget.h:341
bool isTargetELF() const
Definition: PPCSubtarget.h:333
bool useSoftFloat() const
Definition: PPCSubtarget.h:231
bool hasExtDiv() const
Definition: PPCSubtarget.h:280
InstructionSelector * getInstructionSelector() const override
bool isELFv2ABI() const
bool has64BitSupport() const
has64BitSupport - Return true if the selected CPU supports 64-bit instructions, regardless of whether...
Definition: PPCSubtarget.h:229
bool hasP9Vector() const
Definition: PPCSubtarget.h:270
unsigned descriptorTOCAnchorOffset() const
Definition: PPCSubtarget.h:376
Itinerary data supplied by a subtarget to be used by a target.
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:212
const LegalizerInfo * getLegalizerInfo() const override
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: PPCSubtarget.h:88
bool hasSTFIWX() const
Definition: PPCSubtarget.h:257
bool hasInvariantFunctionDescriptors() const
Definition: PPCSubtarget.h:294
bool allowsUnalignedFPAccess() const
Definition: PPCSubtarget.h:291
bool usesFunctionDescriptors() const
True if the ABI is descriptor based.
Definition: PPCSubtarget.h:370
bool vectorsUseTwoUnits() const
Definition: PPCSubtarget.h:288
bool isPredictableSelectIsExpensive() const
Definition: PPCSubtarget.h:406
bool isSecurePlt() const
Definition: PPCSubtarget.h:287
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Definition: PPCSubtarget.h:168
bool hasFRES() const
Definition: PPCSubtarget.h:253
bool enableSubRegLiveness() const override
bool hasFRSQRTES() const
Definition: PPCSubtarget.h:255
AntiDepBreakMode getAntiDepBreakMode() const override
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool hasEFPU2() const
Definition: PPCSubtarget.h:263
bool HasInvariantFunctionDescriptors
Definition: PPCSubtarget.h:138
PPCFrameLowering FrameLowering
Definition: PPCSubtarget.h:162
PPCInstrInfo InstrInfo
Definition: PPCSubtarget.h:163
const PPCFrameLowering * getFrameLowering() const override
Definition: PPCSubtarget.h:199
bool hasPartwordAtomics() const
Definition: PPCSubtarget.h:299
const PPCTargetLowering * getTargetLowering() const override
Definition: PPCSubtarget.h:203
bool hasFPRND() const
Definition: PPCSubtarget.h:259
unsigned getCPUDirective() const
getCPUDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:191
Common code between 32-bit and 64-bit PowerPC targets.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:642
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
uint64_t Align
bool PredictableSelectIsExpensive
Definition: PPCSubtarget.h:155
bool isLittleEndian() const
Definition: PPCSubtarget.h:247
const PPCTargetMachine & TM
Definition: PPCSubtarget.h:161
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
bool hasP8Vector() const
Definition: PPCSubtarget.h:267
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: PPCSubtarget.h:170
bool isOSAIX() const
Tests whether the OS is AIX.
Definition: Triple.h:624
bool isE500() const
Definition: PPCSubtarget.h:289
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:209
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isBookE() const
Definition: PPCSubtarget.h:283
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:202
bool hasCMPB() const
Definition: PPCSubtarget.h:281
bool is32BitELFABI() const
Definition: PPCSubtarget.h:342
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:592
bool isFeatureMFTB() const
Definition: PPCSubtarget.h:290
bool hasP8Altivec() const
Definition: PPCSubtarget.h:268
bool UsePPCPostRASchedStrategy
Definition: PPCSubtarget.h:153
bool hasP9Altivec() const
Definition: PPCSubtarget.h:271
bool hasFPU() const
Definition: PPCSubtarget.h:264
const CallLowering * getCallLowering() const override
unsigned getRedZoneSize() const
Definition: PPCSubtarget.h:306
bool hasRecipPrec() const
Definition: PPCSubtarget.h:256
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: PPCSubtarget.h:81
bool isPPC4xx() const
Definition: PPCSubtarget.h:285
bool hasHTM() const
Definition: PPCSubtarget.h:316
bool useLongCalls() const
Definition: PPCSubtarget.h:320
bool use64BitRegs() const
use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit registers in 32-bit mode when...
Definition: PPCSubtarget.h:240
bool enableMachineScheduler() const override
Scheduling customization.
bool hasICBT() const
Definition: PPCSubtarget.h:293
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: PPCSubtarget.h:195
bool pairedVectorMemops() const
Definition: PPCSubtarget.h:276
MCRegister getTOCPointerRegister() const
Definition: PPCSubtarget.h:394
bool hasFloat128() const
Definition: PPCSubtarget.h:317
bool hasFRSQRTE() const
Definition: PPCSubtarget.h:254
bool hasLFIWAX() const
Definition: PPCSubtarget.h:258
bool hasFCPSGN() const
Definition: PPCSubtarget.h:250
PPCTargetLowering TLInfo
Definition: PPCSubtarget.h:164
bool hasAltivec() const
Definition: PPCSubtarget.h:261
bool enableMachinePipeliner() const override
Pipeliner customization.
bool hasISEL() const
Definition: PPCSubtarget.h:278
bool useCRBits() const
useCRBits - Return true if we should store and manipulate i1 values in the individual condition regis...
Definition: PPCSubtarget.h:244
MCRegister getEnvironmentPointerRegister() const
Definition: PPCSubtarget.h:388
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool usePPCPostRASchedStrategy() const
Definition: PPCSubtarget.h:298
bool hasFRE() const
Definition: PPCSubtarget.h:252
POPCNTDKind hasPOPCNTD() const
Definition: PPCSubtarget.h:329
bool needsSwapsForVSXMemOps() const
Definition: PPCSubtarget.h:325
bool isTargetMachO() const
Definition: PPCSubtarget.h:334
This file describes how to lower LLVM calls to machine code calls.
bool isUsingPCRelativeCalls() const
bool hasAddiLoadFusion() const
Definition: PPCSubtarget.h:323
bool usePPCPreRASchedStrategy() const
Definition: PPCSubtarget.h:297
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
bool isSVR4ABI() const
Definition: PPCSubtarget.h:338
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
bool hasPrefixInstrs() const
Definition: PPCSubtarget.h:273
bool isXRaySupported() const override
Definition: PPCSubtarget.h:404
bool HasMFOCRF
Used by the ISel to turn in optimizations for POWER4-derived architectures.
Definition: PPCSubtarget.h:94
unsigned CPUDirective
Which cpu directive was used.
Definition: PPCSubtarget.h:91
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:279
const Triple & getTargetTriple() const
Definition: PPCSubtarget.h:331
bool hasOnlyMSYNC() const
Definition: PPCSubtarget.h:284
bool isPPC6xx() const
Definition: PPCSubtarget.h:286
bool isDeprecatedDST() const
Definition: PPCSubtarget.h:292
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.