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13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
19 #define GET_INSTRINFO_HEADER
20 #include "PPCGenInstrInfo.inc"
135 #define NoInstr PPC::INSTRUCTION_LIST_END
136 #define Pwr8LoadOpcodes \
138 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
139 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \
140 PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, PPC::EVLDD, \
141 PPC::RESTORE_QUADWORD \
144 #define Pwr9LoadOpcodes \
146 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
147 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
148 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \
149 NoInstr, PPC::RESTORE_QUADWORD \
152 #define Pwr10LoadOpcodes \
154 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
155 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
156 PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
157 PPC::RESTORE_UACC, NoInstr, PPC::RESTORE_QUADWORD \
160 #define Pwr8StoreOpcodes \
162 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
163 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \
164 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, PPC::EVSTDD, \
165 PPC::SPILL_QUADWORD \
168 #define Pwr9StoreOpcodes \
170 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
171 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
172 PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, \
173 PPC::SPILL_QUADWORD \
176 #define Pwr10StoreOpcodes \
178 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
179 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
180 PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
181 NoInstr, PPC::SPILL_QUADWORD \
185 #define StoreOpcodesForSpill \
186 { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes }
187 #define LoadOpcodesForSpill \
188 { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes }
199 void StoreRegToStackSlot(
MachineFunction &MF,
unsigned SrcReg,
bool isKill,
203 unsigned DestReg,
int FrameIdx,
210 unsigned OpNoForForwarding,
MachineInstr **KilledDef)
const;
214 unsigned OpNoForForwarding)
const;
218 unsigned ConstantOpNo,
224 bool KillDefMI)
const;
231 unsigned &OpNoForForwarding,
232 bool &SeenIntermediateUse)
const;
237 unsigned OpNoForForwarding)
const;
246 int64_t BaseImm = 0)
const;
250 bool &IsFwdFeederRegKilled)
const;
251 unsigned getSpillTarget()
const;
252 const unsigned *getStoreOpcodesForSpillArray()
const;
253 const unsigned *getLoadOpcodesForSpillArray()
const;
255 int16_t getFMAOpIdxInfo(
unsigned Opcode)
const;
265 virtual void anchor();
280 unsigned OpIdx2)
const override;
301 if (!
get(Opcode).isCall())
311 case PPC::BL8_NOTOC_TLS:
312 case PPC::BL8_NOTOC_RM:
327 case PPC::BL8_NOP_TLS:
339 case PPC::BL8_NOP_RM:
340 case PPC::BLA8_NOP_RM:
342 case PPC::BCTRL8_LDinto_toc:
343 case PPC::BCTRL8_LDinto_toc_RM:
345 case PPC::TCRETURNdi8:
346 case PPC::TCRETURNai8:
347 case PPC::TCRETURNri8:
378 case PPC::TCRETURNdi:
379 case PPC::TCRETURNai:
380 case PPC::TCRETURNri:
381 case PPC::BCTRL_LWZinto_toc:
382 case PPC::BCTRL_LWZinto_toc_RM:
392 unsigned CopyOpcodes[] = {
PPC::OR, PPC::OR8, PPC::FMR,
393 PPC::VOR, PPC::XXLOR, PPC::XXLORf,
394 PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR,
396 for (
int i = 0; CopyOpcodes[
i] != -1U;
i++)
397 if (Opcode == CopyOpcodes[
i])
411 unsigned *PredCost =
nullptr)
const override;
416 unsigned UseIdx)
const override;
418 SDNode *DefNode,
unsigned DefIdx,
419 SDNode *UseNode,
unsigned UseIdx)
const override {
420 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
426 unsigned DefIdx)
const override {
450 bool DoRegPressureReduce)
const;
457 bool DoRegPressureReduce)
const override;
495 unsigned &SubIdx)
const override;
504 unsigned &SrcOpIdx2)
const override;
514 bool AllowModify)
const override;
516 int *BytesRemoved =
nullptr)
const override;
520 int *BytesAdded =
nullptr)
const override;
525 int &)
const override;
533 bool KillSrc)
const override;
582 unsigned NumCycles,
unsigned ExtraPredCycles,
588 unsigned NumT,
unsigned ExtraT,
590 unsigned NumF,
unsigned ExtraF,
617 bool SkipDead)
const override;
623 int64_t &
Value)
const override;
635 int64_t &Offset,
unsigned &
Width,
643 bool &OffsetIsScalable,
unsigned &
Width,
650 unsigned NumLoads,
unsigned NumBytes)
const override;
665 std::pair<unsigned, unsigned>
681 return Reg >= PPC::VF0 &&
Reg <= PPC::VF31;
684 return Reg >= PPC::V0 &&
Reg <= PPC::V31;
692 const unsigned PhiDepth)
const;
713 unsigned &XFormOpcode,
714 int64_t &OffsetOfImmInstr,
718 int64_t OffsetImm)
const;
736 unsigned RegNo)
const;
747 bool &SeenIntermediateUse)
const;
769 case PPC::VSSRCRegClassID:
770 case PPC::VSFRCRegClassID:
772 return PPC::VSX32 + (
Reg - PPC::VF0);
776 case PPC::VSRCRegClassID:
778 return PPC::VSX32 + (
Reg - PPC::V0);
788 bool isBDNZ(
unsigned Opcode)
const;
800 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
@ XFormMemOp
This instruction is an X-Form memory operation.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
This is an optimization pass for GlobalISel generic memory operations.
void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI, unsigned RegNo) const
Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].
MachineInstrBuilder & UseMI
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool isPrefixed(unsigned Opcode) const
uint64_t OpNoForForwarding
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
static bool isVFRegister(unsigned Reg)
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
MachineInstr * getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
Reg
All possible values of the reg field in the ModR/M byte.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
Represents one node in the SelectionDAG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const
The instances of the Type class are immutable: once they are created, they are never changed.
unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const
uint64_t ZeroIsSpecialNew
int getExtendResourceLenLimit() const override
On PowerPC, we try to reassociate FMA chain which will increase instruction size.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
bool isBDNZ(unsigned Opcode) const
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Instances of this class represent a single low-level machine instruction.
bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Returns true if the two given memory operations should be scheduled adjacent.
uint64_t IsSummingOperands
unsigned const TargetRegisterInfo * TRI
void materializeImmPostRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isNoTOCCallInstr(unsigned Opcode) const
Check if Opcode corresponds to a call instruction that should be marked with the NOTOC relocation.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
bool isXFormMemOp(unsigned Opcode) const
bool shouldReduceRegisterPressure(MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const override
On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure ...
@ PPC970_Cracked
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
@ PPC970_Shift
PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that an instruction is issued to...
MCInst getNop() const override
Return the noop instruction to use for a noop.
#define LoadOpcodesForSpill
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
@ PPC970_First
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
static bool isSameClassPhysRegCopy(unsigned Opcode)
This is an important base class in LLVM.
Provide an instruction scheduling machine model to CodeGen passes.
Representation of each machine instruction.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
@ NewDef_Shift
Shift count to bypass PPC970 flags.
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
bool useMachineCombiner() const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MCOperandInfo * OpInfo
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for a fma chain ending in Root.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
uint64_t ZeroIsSpecialOrig
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
SmallVector< MachineOperand, 4 > Cond
bool isPredicated(const MachineInstr &MI) const override
MachineBasicBlock MachineBasicBlock::iterator MBBI
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
bool isTOCSaveMI(const MachineInstr &MI) const
uint64_t ImmMustBeMultipleOf
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase=nullptr) const
Should compile to something r4 addze r3 instead we get
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Return true if two MIs access different memory addresses and false otherwise.
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const
#define StoreOpcodesForSpill
static int getRecordFormOpcode(unsigned Opcode)
@ Prefixed
This instruction is prefixed.
bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Return true if get the base operand, byte offset of an instruction and the memory width.
MachineInstrBuilder MachineInstrBuilder & DefMI
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Get the base operand and byte offset of an instruction that reads/writes memory.
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
@ BCTRL
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
bool expandVSXMemPseudo(MachineInstr &MI) const
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
bool foldFrameOffset(MachineInstr &MI) const
void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
@ PPC970_Single
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
PPCInstrInfo(PPCSubtarget &STI)
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
LLVM Value Representation.
Itinerary data supplied by a subtarget to be used by a target.
void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.
Wrapper class representing physical registers. Should be passed by value.
@ PPC970_Pseudo
These are the various PPC970 execution unit pipelines.
static bool isVRRegister(unsigned Reg)
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.