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PPCInstrInfo.h
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1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 
16 #include "PPCRegisterInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "PPCGenInstrInfo.inc"
21 
22 namespace llvm {
23 
24 /// PPCII - This namespace holds all of the PowerPC target-specific
25 /// per-instruction flags. These must match the corresponding definitions in
26 /// PPC.td and PPCInstrFormats.td.
27 namespace PPCII {
28 enum {
29  // PPC970 Instruction Flags. These flags describe the characteristics of the
30  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
31  // raw machine instructions.
32 
33  /// PPC970_First - This instruction starts a new dispatch group, so it will
34  /// always be the first one in the group.
35  PPC970_First = 0x1,
36 
37  /// PPC970_Single - This instruction starts a new dispatch group and
38  /// terminates it, so it will be the sole instruction in the group.
40 
41  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
42  /// two dispatch pipes to be available to issue.
44 
45  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
46  /// an instruction is issued to.
49 };
51  /// These are the various PPC970 execution unit pipelines. Each instruction
52  /// is one of these.
53  PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
54  PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
55  PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
56  PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
57  PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
58  PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
59  PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
60  PPC970_BRU = 7 << PPC970_Shift // Branch Unit
61 };
62 
63 enum {
64  /// Shift count to bypass PPC970 flags
66 
67  /// This instruction is an X-Form memory operation.
69  /// This instruction is prefixed.
70  Prefixed = 0x1 << (NewDef_Shift+1)
71 };
72 } // end namespace PPCII
73 
74 // Instructions that have an immediate form might be convertible to that
75 // form if the correct input is a result of a load immediate. In order to
76 // know whether the transformation is special, we might need to know some
77 // of the details of the two forms.
78 struct ImmInstrInfo {
79  // Is the immediate field in the immediate form signed or unsigned?
81  // Does the immediate need to be a multiple of some value?
83  // Is R0/X0 treated specially by the original r+r instruction?
84  // If so, in which operand?
86  // Is R0/X0 treated specially by the new r+i instruction?
87  // If so, in which operand?
89  // Is the operation commutative?
91  // The operand number to check for add-immediate def.
93  // The operand number for the immediate.
95  // The opcode of the new instruction.
97  // The size of the immediate.
99  // The immediate should be truncated to N bits.
101  // Is the instruction summing the operand
103 };
104 
105 // Information required to convert an instruction to just a materialized
106 // immediate.
108  unsigned Imm : 16;
109  unsigned Is64Bit : 1;
110  unsigned SetCR : 1;
111 };
112 
113 // Index into the OpcodesForSpill array.
131  SOK_LastOpcodeSpill // This must be last on the enum.
132 };
133 
134 // Define list of load and store spill opcodes.
135 #define NoInstr PPC::INSTRUCTION_LIST_END
136 #define Pwr8LoadOpcodes \
137  { \
138  PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
139  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \
140  PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, PPC::EVLDD, \
141  PPC::RESTORE_QUADWORD \
142  }
143 
144 #define Pwr9LoadOpcodes \
145  { \
146  PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
147  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
148  PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \
149  NoInstr, PPC::RESTORE_QUADWORD \
150  }
151 
152 #define Pwr10LoadOpcodes \
153  { \
154  PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
155  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
156  PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
157  PPC::RESTORE_UACC, NoInstr, PPC::RESTORE_QUADWORD \
158  }
159 
160 #define Pwr8StoreOpcodes \
161  { \
162  PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
163  PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \
164  PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, PPC::EVSTDD, \
165  PPC::SPILL_QUADWORD \
166  }
167 
168 #define Pwr9StoreOpcodes \
169  { \
170  PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
171  PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
172  PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, \
173  PPC::SPILL_QUADWORD \
174  }
175 
176 #define Pwr10StoreOpcodes \
177  { \
178  PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
179  PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
180  PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
181  NoInstr, PPC::SPILL_QUADWORD \
182  }
183 
184 // Initialize arrays for load and store spill opcodes on supported subtargets.
185 #define StoreOpcodesForSpill \
186  { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes }
187 #define LoadOpcodesForSpill \
188  { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes }
189 
190 class PPCSubtarget;
192  PPCSubtarget &Subtarget;
193  const PPCRegisterInfo RI;
194  const unsigned StoreSpillOpcodesArray[3][SOK_LastOpcodeSpill] =
196  const unsigned LoadSpillOpcodesArray[3][SOK_LastOpcodeSpill] =
198 
199  void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
200  int FrameIdx, const TargetRegisterClass *RC,
201  SmallVectorImpl<MachineInstr *> &NewMIs) const;
202  void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
203  unsigned DestReg, int FrameIdx,
204  const TargetRegisterClass *RC,
205  SmallVectorImpl<MachineInstr *> &NewMIs) const;
206 
207  // Replace the instruction with single LI if possible. \p DefMI must be LI or
208  // LI8.
209  bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
210  unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
211  // If the inst is imm-form and its register operand is produced by a ADDI, put
212  // the imm into the inst directly and remove the ADDI if possible.
213  bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
214  unsigned OpNoForForwarding) const;
215  // If the inst is x-form and has imm-form and one of its operand is produced
216  // by a LI, put the imm into the inst directly and remove the LI if possible.
217  bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
218  unsigned ConstantOpNo,
219  MachineInstr &DefMI) const;
220  // If the inst is x-form and has imm-form and one of its operand is produced
221  // by an add-immediate, try to transform it when possible.
222  bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
223  unsigned ConstantOpNo, MachineInstr &DefMI,
224  bool KillDefMI) const;
225  // Try to find that, if the instruction 'MI' contains any operand that
226  // could be forwarded from some inst that feeds it. If yes, return the
227  // Def of that operand. And OpNoForForwarding is the operand index in
228  // the 'MI' for that 'Def'. If we see another use of this Def between
229  // the Def and the MI, SeenIntermediateUse becomes 'true'.
230  MachineInstr *getForwardingDefMI(MachineInstr &MI,
231  unsigned &OpNoForForwarding,
232  bool &SeenIntermediateUse) const;
233 
234  // Can the user MI have it's source at index \p OpNoForForwarding
235  // forwarded from an add-immediate that feeds it?
236  bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
237  unsigned OpNoForForwarding) const;
238  bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
239  const ImmInstrInfo &III,
240  MachineOperand *&ImmMO,
241  MachineOperand *&RegMO) const;
242  bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
243  const MachineInstr &DefMI,
244  const ImmInstrInfo &III,
245  int64_t &Imm,
246  int64_t BaseImm = 0) const;
247  bool isRegElgibleForForwarding(const MachineOperand &RegMO,
248  const MachineInstr &DefMI,
249  const MachineInstr &MI, bool KillDefMI,
250  bool &IsFwdFeederRegKilled) const;
251  unsigned getSpillTarget() const;
252  const unsigned *getStoreOpcodesForSpillArray() const;
253  const unsigned *getLoadOpcodesForSpillArray() const;
254  unsigned getSpillIndex(const TargetRegisterClass *RC) const;
255  int16_t getFMAOpIdxInfo(unsigned Opcode) const;
256  void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern,
259  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
260  bool isLoadFromConstantPool(MachineInstr *I) const;
261  Register
262  generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty,
263  SmallVectorImpl<MachineInstr *> &InsInstrs) const;
264  const Constant *getConstantFromConstantPool(MachineInstr *I) const;
265  virtual void anchor();
266 
267 protected:
268  /// Commutes the operands in the given instruction.
269  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
270  ///
271  /// Do not call this method for a non-commutable instruction or for
272  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
273  /// Even though the instruction is commutable, the method may still
274  /// fail to commute the operands, null pointer is returned in such cases.
275  ///
276  /// For example, we can commute rlwimi instructions, but only if the
277  /// rotate amt is zero. We also have to munge the immediates a bit.
279  unsigned OpIdx1,
280  unsigned OpIdx2) const override;
281 
282 public:
283  explicit PPCInstrInfo(PPCSubtarget &STI);
284 
285  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
286  /// such, whenever a client has an instance of instruction info, it should
287  /// always be able to get register info as well (through this method).
288  ///
289  const PPCRegisterInfo &getRegisterInfo() const { return RI; }
290 
291  bool isXFormMemOp(unsigned Opcode) const {
292  return get(Opcode).TSFlags & PPCII::XFormMemOp;
293  }
294  bool isPrefixed(unsigned Opcode) const {
295  return get(Opcode).TSFlags & PPCII::Prefixed;
296  }
297 
298  static bool isSameClassPhysRegCopy(unsigned Opcode) {
299  unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR,
300  PPC::VOR, PPC::XXLOR, PPC::XXLORf,
301  PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR,
302  PPC::EVOR, -1U};
303  for (int i = 0; CopyOpcodes[i] != -1U; i++)
304  if (Opcode == CopyOpcodes[i])
305  return true;
306  return false;
307  }
308 
311  const ScheduleDAG *DAG) const override;
314  const ScheduleDAG *DAG) const override;
315 
316  unsigned getInstrLatency(const InstrItineraryData *ItinData,
317  const MachineInstr &MI,
318  unsigned *PredCost = nullptr) const override;
319 
320  int getOperandLatency(const InstrItineraryData *ItinData,
321  const MachineInstr &DefMI, unsigned DefIdx,
322  const MachineInstr &UseMI,
323  unsigned UseIdx) const override;
325  SDNode *DefNode, unsigned DefIdx,
326  SDNode *UseNode, unsigned UseIdx) const override {
327  return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
328  UseNode, UseIdx);
329  }
330 
331  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
332  const MachineInstr &DefMI,
333  unsigned DefIdx) const override {
334  // Machine LICM should hoist all instructions in low-register-pressure
335  // situations; none are sufficiently free to justify leaving in a loop
336  // body.
337  return false;
338  }
339 
340  bool useMachineCombiner() const override {
341  return true;
342  }
343 
344  /// When getMachineCombinerPatterns() finds patterns, this function generates
345  /// the instructions that could replace the original code sequence
350  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
351 
352  /// Return true when there is potentially a faster code sequence for a fma
353  /// chain ending in \p Root. All potential patterns are output in the \p
354  /// P array.
355  bool getFMAPatterns(MachineInstr &Root,
357  bool DoRegPressureReduce) const;
358 
359  /// Return true when there is potentially a faster code sequence
360  /// for an instruction chain ending in <Root>. All potential patterns are
361  /// output in the <Pattern> array.
364  bool DoRegPressureReduce) const override;
365 
366  /// On PowerPC, we leverage machine combiner pass to reduce register pressure
367  /// when the register pressure is high for one BB.
368  /// Return true if register pressure for \p MBB is high and ABI is supported
369  /// to reduce register pressure. Otherwise return false.
370  bool
372  RegisterClassInfo *RegClassInfo) const override;
373 
374  /// Fixup the placeholders we put in genAlternativeCodeSequence() for
375  /// MachineCombiner.
376  void
378  SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
379 
380  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
381 
382  /// On PowerPC, we try to reassociate FMA chain which will increase
383  /// instruction size. Set extension resource length limit to 1 for edge case.
384  /// Resource Length is calculated by scaled resource usage in getCycles().
385  /// Because of the division in getCycles(), it returns different cycles due to
386  /// legacy scaled resource usage. So new resource length may be same with
387  /// legacy or 1 bigger than legacy.
388  /// We need to execlude the 1 bigger case even the resource length is not
389  /// perserved for more FMA chain reassociations on PowerPC.
390  int getExtendResourceLenLimit() const override { return 1; }
391 
392  void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
393  MachineInstr &NewMI1,
394  MachineInstr &NewMI2) const override;
395 
396  void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const override;
397 
399  Register &SrcReg, Register &DstReg,
400  unsigned &SubIdx) const override;
401  unsigned isLoadFromStackSlot(const MachineInstr &MI,
402  int &FrameIndex) const override;
404  AAResults *AA) const override;
405  unsigned isStoreToStackSlot(const MachineInstr &MI,
406  int &FrameIndex) const override;
407 
408  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
409  unsigned &SrcOpIdx2) const override;
410 
412  MachineBasicBlock::iterator MI) const override;
413 
414 
415  // Branch analysis.
417  MachineBasicBlock *&FBB,
419  bool AllowModify) const override;
421  int *BytesRemoved = nullptr) const override;
424  const DebugLoc &DL,
425  int *BytesAdded = nullptr) const override;
426 
427  // Select analysis.
429  Register, Register, Register, int &, int &,
430  int &) const override;
432  const DebugLoc &DL, Register DstReg,
434  Register FalseReg) const override;
435 
437  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
438  bool KillSrc) const override;
439 
442  Register SrcReg, bool isKill, int FrameIndex,
443  const TargetRegisterClass *RC,
444  const TargetRegisterInfo *TRI) const override;
445 
446  // Emits a register spill without updating the register class for vector
447  // registers. This ensures that when we spill a vector register the
448  // element order in the register is the same as it was in memory.
451  unsigned SrcReg, bool isKill, int FrameIndex,
452  const TargetRegisterClass *RC,
453  const TargetRegisterInfo *TRI) const;
454 
457  Register DestReg, int FrameIndex,
458  const TargetRegisterClass *RC,
459  const TargetRegisterInfo *TRI) const override;
460 
461  // Emits a register reload without updating the register class for vector
462  // registers. This ensures that when we reload a vector register the
463  // element order in the register is the same as it was in memory.
466  unsigned DestReg, int FrameIndex,
467  const TargetRegisterClass *RC,
468  const TargetRegisterInfo *TRI) const;
469 
470  unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const;
471 
472  unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const;
473 
474  bool
476 
478  MachineRegisterInfo *MRI) const override;
479 
481  Register Reg) const;
482 
483  // If conversion by predication (only supported by some branch instructions).
484  // All of the profitability checks always return true; it is always
485  // profitable to use the predicated branches.
487  unsigned NumCycles, unsigned ExtraPredCycles,
488  BranchProbability Probability) const override {
489  return true;
490  }
491 
493  unsigned NumT, unsigned ExtraT,
494  MachineBasicBlock &FMBB,
495  unsigned NumF, unsigned ExtraF,
496  BranchProbability Probability) const override;
497 
499  BranchProbability Probability) const override {
500  return true;
501  }
502 
504  MachineBasicBlock &FMBB) const override {
505  return false;
506  }
507 
508  // Predication support.
509  bool isPredicated(const MachineInstr &MI) const override;
510 
512  const MachineBasicBlock *MBB,
513  const MachineFunction &MF) const override;
514 
516  ArrayRef<MachineOperand> Pred) const override;
517 
519  ArrayRef<MachineOperand> Pred2) const override;
520 
521  bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
522  bool SkipDead) const override;
523 
524  // Comparison optimization.
525 
526  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
527  Register &SrcReg2, int64_t &Mask,
528  int64_t &Value) const override;
529 
530  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
531  Register SrcReg2, int64_t Mask, int64_t Value,
532  const MachineRegisterInfo *MRI) const override;
533 
534 
535  /// Return true if get the base operand, byte offset of an instruction and
536  /// the memory width. Width is the size of memory that is being
537  /// loaded/stored (e.g. 1, 2, 4, 8).
539  const MachineOperand *&BaseOp,
540  int64_t &Offset, unsigned &Width,
541  const TargetRegisterInfo *TRI) const;
542 
543  /// Get the base operand and byte offset of an instruction that reads/writes
544  /// memory.
546  const MachineInstr &LdSt,
548  bool &OffsetIsScalable, unsigned &Width,
549  const TargetRegisterInfo *TRI) const override;
550 
551  /// Returns true if the two given memory operations should be scheduled
552  /// adjacent.
555  unsigned NumLoads, unsigned NumBytes) const override;
556 
557  /// Return true if two MIs access different memory addresses and false
558  /// otherwise
559  bool
561  const MachineInstr &MIb) const override;
562 
563  /// GetInstSize - Return the number of bytes of code the specified
564  /// instruction may be. This returns the maximum number of bytes.
565  ///
566  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
567 
568  MCInst getNop() const override;
569 
570  std::pair<unsigned, unsigned>
571  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
572 
575 
578 
579  // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
580  bool expandVSXMemPseudo(MachineInstr &MI) const;
581 
582  // Lower pseudo instructions after register allocation.
583  bool expandPostRAPseudo(MachineInstr &MI) const override;
584 
585  static bool isVFRegister(unsigned Reg) {
586  return Reg >= PPC::VF0 && Reg <= PPC::VF31;
587  }
588  static bool isVRRegister(unsigned Reg) {
589  return Reg >= PPC::V0 && Reg <= PPC::V31;
590  }
591  const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
592  static int getRecordFormOpcode(unsigned Opcode);
593 
594  bool isTOCSaveMI(const MachineInstr &MI) const;
595 
596  bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
597  const unsigned PhiDepth) const;
598 
599  /// Return true if the output of the instruction is always a sign-extended,
600  /// i.e. 0 to 31-th bits are same as 32-th bit.
601  bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
602  return isSignOrZeroExtended(MI, true, depth);
603  }
604 
605  /// Return true if the output of the instruction is always zero-extended,
606  /// i.e. 0 to 31-th bits are all zeros
607  bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
608  return isSignOrZeroExtended(MI, false, depth);
609  }
610 
612  MachineInstr **KilledDef = nullptr) const;
613  bool foldFrameOffset(MachineInstr &MI) const;
614  bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
615  bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
616  bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const;
617  bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
618  unsigned &XFormOpcode,
619  int64_t &OffsetOfImmInstr,
620  ImmInstrInfo &III) const;
621  bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
622  MachineInstr *&ADDIMI, int64_t &OffsetAddi,
623  int64_t OffsetImm) const;
624 
625  /// Fixup killed/dead flag for register \p RegNo between instructions [\p
626  /// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate
627  /// register killed/dead flags semantics, this function can be called to fix
628  /// up. Before calling this function,
629  /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
630  /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
631  /// and possible definition for \p RegNo is \p StartMI or \p EndMI. For
632  /// pre-RA cases, definition may be \p StartMI through COPY, \p StartMI
633  /// will be adjust to true definition.
634  /// 3. We can do accurate fixup for the case when all instructions between
635  /// [\p StartMI, \p EndMI] are in same basic block.
636  /// 4. For the case when \p StartMI and \p EndMI are not in same basic block,
637  /// we conservatively clear kill flag for all uses of \p RegNo for pre-RA
638  /// and for post-RA, we give an assertion as without reaching definition
639  /// analysis post-RA, \p StartMI and \p EndMI are hard to keep right.
640  void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
641  unsigned RegNo) const;
642  void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
643  void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
644  int64_t Imm) const;
645 
646  bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
647  bool PostRA) const;
648 
649  // In PostRA phase, try to find instruction defines \p Reg before \p MI.
650  // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
652  bool &SeenIntermediateUse) const;
653 
654  /// getRegNumForOperand - some operands use different numbering schemes
655  /// for the same registers. For example, a VSX instruction may have any of
656  /// vs0-vs63 allocated whereas an Altivec instruction could only have
657  /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
658  /// register number needed for the opcode/operand number combination.
659  /// The operand number argument will be useful when we need to extend this
660  /// to instructions that use both Altivec and VSX numbering (for different
661  /// operands).
662  static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
663  unsigned OpNo) {
664  int16_t regClass = Desc.OpInfo[OpNo].RegClass;
665  switch (regClass) {
666  // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
667  // VSX32-VSX63 during encoding/disassembling
668  case PPC::VSSRCRegClassID:
669  case PPC::VSFRCRegClassID:
670  if (isVFRegister(Reg))
671  return PPC::VSX32 + (Reg - PPC::VF0);
672  break;
673  // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
674  // VSX32-VSX63 during encoding/disassembling
675  case PPC::VSRCRegClassID:
676  if (isVRRegister(Reg))
677  return PPC::VSX32 + (Reg - PPC::V0);
678  break;
679  // Other RegClass doesn't need mapping
680  default:
681  break;
682  }
683  return Reg;
684  }
685 
686  /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
687  bool isBDNZ(unsigned Opcode) const;
688 
689  /// Find the hardware loop instruction used to set-up the specified loop.
690  /// On PPC, we have two instructions used to set-up the hardware loop
691  /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
692  /// instructions to indicate the end of a loop.
693  MachineInstr *
694  findLoopInstr(MachineBasicBlock &PreHeader,
695  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
696 
697  /// Analyze loop L, which must be a single-basic-block loop, and if the
698  /// conditions can be understood enough produce a PipelinerLoopInfo object.
699  std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
700  analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
701 };
702 
703 }
704 
705 #endif
llvm::PPCII::PPC970_Unit
PPC970_Unit
Definition: PPCInstrInfo.h:50
llvm::PPCInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: PPCInstrInfo.cpp:1126
i
i
Definition: README.txt:29
llvm::PPCRegisterInfo
Definition: PPCRegisterInfo.h:57
llvm::PPCInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: PPCInstrInfo.cpp:1972
llvm::PPCInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: PPCInstrInfo.cpp:2888
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::PPCInstrInfo::fixupIsDeadOrKill
void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI, unsigned RegNo) const
Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].
Definition: PPCInstrInfo.cpp:3335
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::PPCInstrInfo::replaceInstrOperandWithImm
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
Definition: PPCInstrInfo.cpp:3162
llvm::PPCII::PPC970_Mask
@ PPC970_Mask
Definition: PPCInstrInfo.h:48
PPCRegisterInfo.h
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:633
llvm::PPCInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: PPCInstrInfo.cpp:2999
llvm::PPCInstrInfo::isProfitableToUnpredicate
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: PPCInstrInfo.h:503
llvm::PPCII::PPC970_Shift
@ PPC970_Shift
PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that an instruction is issued to...
Definition: PPCInstrInfo.h:47
llvm::PPCII::PPC970_Cracked
@ PPC970_Cracked
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
Definition: PPCInstrInfo.h:43
llvm::SOK_SpillToVSR
@ SOK_SpillToVSR
Definition: PPCInstrInfo.h:125
llvm::SOK_PairedVecSpill
@ SOK_PairedVecSpill
Definition: PPCInstrInfo.h:126
llvm::PPCInstrInfo::isPrefixed
bool isPrefixed(unsigned Opcode) const
Definition: PPCInstrInfo.h:294
llvm::ImmInstrInfo::OpNoForForwarding
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:92
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::LoadImmediateInfo::SetCR
unsigned SetCR
Definition: PPCInstrInfo.h:110
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::PPCII::PPC970_VALU
@ PPC970_VALU
Definition: PPCInstrInfo.h:58
llvm::PPCII::NewDef_Shift
@ NewDef_Shift
Shift count to bypass PPC970 flags.
Definition: PPCInstrInfo.h:65
llvm::PPCInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
Definition: PPCInstrInfo.h:324
llvm::PPCInstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override
Definition: PPCInstrInfo.cpp:2380
llvm::PPCInstrInfo::isSignExtended
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:601
llvm::PPCInstrInfo::isVFRegister
static bool isVFRegister(unsigned Reg)
Definition: PPCInstrInfo.h:585
llvm::PPCInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: PPCInstrInfo.cpp:1686
llvm::PPCInstrInfo::isAssociativeAndCommutative
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Definition: PPCInstrInfo.cpp:252
llvm::PPCInstrInfo::getDefMIPostRA
MachineInstr * getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
Definition: PPCInstrInfo.cpp:3216
llvm::SOK_VRVectorSpill
@ SOK_VRVectorSpill
Definition: PPCInstrInfo.h:121
llvm::PPCInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: PPCInstrInfo.cpp:2050
llvm::PPCInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
Definition: PPCInstrInfo.cpp:2350
llvm::PPCInstrInfo
Definition: PPCInstrInfo.h:191
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::PPCInstrInfo::isADDInstrEligibleForFolding
bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const
Definition: PPCInstrInfo.cpp:3568
llvm::PPCII::PPC970_FPU
@ PPC970_FPU
Definition: PPCInstrInfo.h:56
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
TargetInstrInfo.h
llvm::PPCInstrInfo::getStoreOpcodeForSpill
unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const
Definition: PPCInstrInfo.cpp:1919
llvm::ImmInstrInfo::ZeroIsSpecialNew
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:88
llvm::SOK_PairedG8Spill
@ SOK_PairedG8Spill
Definition: PPCInstrInfo.h:130
llvm::PPCII::PPC970_First
@ PPC970_First
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
Definition: PPCInstrInfo.h:35
llvm::PPCInstrInfo::getExtendResourceLenLimit
int getExtendResourceLenLimit() const override
On PowerPC, we try to reassociate FMA chain which will increase instruction size.
Definition: PPCInstrInfo.h:390
llvm::LoadImmediateInfo::Is64Bit
unsigned Is64Bit
Definition: PPCInstrInfo.h:109
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:449
llvm::PPCInstrInfo::isBDNZ
bool isBDNZ(unsigned Opcode) const
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
Definition: PPCInstrInfo.cpp:5362
llvm::PPCInstrInfo::setSpecialOperandAttr
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
Definition: PPCInstrInfo.cpp:221
llvm::PPCInstrInfo::getInstrLatency
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Definition: PPCInstrInfo.cpp:136
llvm::PPCInstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: PPCInstrInfo.cpp:1574
llvm::SOK_LastOpcodeSpill
@ SOK_LastOpcodeSpill
Definition: PPCInstrInfo.h:131
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::PPCInstrInfo::onlyFoldImmediate
bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const
Definition: PPCInstrInfo.cpp:2063
llvm::PPCInstrInfo::CreateTargetPostRAHazardRecognizer
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
Definition: PPCInstrInfo.cpp:116
llvm::PPCInstrInfo::shouldClusterMemOps
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Returns true if the two given memory operations should be scheduled adjacent.
Definition: PPCInstrInfo.cpp:2811
llvm::ImmInstrInfo::IsSummingOperands
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:102
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::PPCInstrInfo::replaceInstrWithLI
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
Definition: PPCInstrInfo.cpp:3193
llvm::LoadImmediateInfo
Definition: PPCInstrInfo.h:107
llvm::SOK_Float8Spill
@ SOK_Float8Spill
Definition: PPCInstrInfo.h:117
llvm::PPCInstrInfo::isCoalescableExtInstr
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
Definition: PPCInstrInfo.cpp:1054
llvm::PPCInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: PPCInstrInfo.cpp:2032
llvm::PPCII::Prefixed
@ Prefixed
This instruction is prefixed.
Definition: PPCInstrInfo.h:70
llvm::PPCII::PPC970_VPERM
@ PPC970_VPERM
Definition: PPCInstrInfo.h:59
llvm::PPCInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
Definition: PPCInstrInfo.cpp:2869
llvm::SOK_SPESpill
@ SOK_SPESpill
Definition: PPCInstrInfo.h:129
llvm::PPCInstrInfo::insertNoop
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Definition: PPCInstrInfo.cpp:1242
llvm::ImmInstrInfo::SignedImm
uint64_t SignedImm
Definition: PPCInstrInfo.h:80
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
llvm::AAResults
Definition: AliasAnalysis.h:456
llvm::PPCInstrInfo::isXFormMemOp
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:291
llvm::PPCInstrInfo::shouldReduceRegisterPressure
bool shouldReduceRegisterPressure(MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const override
On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure ...
Definition: PPCInstrInfo.cpp:613
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::PPCInstrInfo::getNop
MCInst getNop() const override
Return the noop instruction to use for a noop.
Definition: PPCInstrInfo.cpp:1262
LoadOpcodesForSpill
#define LoadOpcodesForSpill
Definition: PPCInstrInfo.h:187
llvm::PPCInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
Definition: PPCInstrInfo.cpp:2130
llvm::PPCInstrInfo::isImmInstrEligibleForFolding
bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const
Definition: PPCInstrInfo.cpp:3575
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SOK_UAccumulatorSpill
@ SOK_UAccumulatorSpill
Definition: PPCInstrInfo.h:128
llvm::SOK_Int4Spill
@ SOK_Int4Spill
Definition: PPCInstrInfo.h:115
llvm::PPCInstrInfo::updatedRC
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
Definition: PPCInstrInfo.cpp:5076
llvm::PPCInstrInfo::findLoopInstr
MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
Definition: PPCInstrInfo.cpp:5456
llvm::LoadImmediateInfo::Imm
unsigned Imm
Definition: PPCInstrInfo.h:108
llvm::PPCInstrInfo::PredicateInstruction
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Definition: PPCInstrInfo.cpp:2183
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:89
llvm::PPCInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: PPCInstrInfo.cpp:1226
llvm::PPCII::XFormMemOp
@ XFormMemOp
This instruction is an X-Form memory operation.
Definition: PPCInstrInfo.h:68
llvm::PPCInstrInfo::analyzeLoopForPipelining
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
Definition: PPCInstrInfo.cpp:5436
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::PPCInstrInfo::isADDIInstrEligibleForFolding
bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const
Definition: PPCInstrInfo.cpp:3551
llvm::PPCInstrInfo::genAlternativeCodeSequence
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: PPCInstrInfo.cpp:774
llvm::SOK_CRSpill
@ SOK_CRSpill
Definition: PPCInstrInfo.h:119
llvm::PPCInstrInfo::ClobbersPredicate
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
Definition: PPCInstrInfo.cpp:2313
llvm::PPCInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: PPCInstrInfo.cpp:2172
llvm::PPCInstrInfo::isSameClassPhysRegCopy
static bool isSameClassPhysRegCopy(unsigned Opcode)
Definition: PPCInstrInfo.h:298
llvm::SOK_VectorFloat8Spill
@ SOK_VectorFloat8Spill
Definition: PPCInstrInfo.h:123
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::PPCII::PPC970_CRU
@ PPC970_CRU
Definition: PPCInstrInfo.h:57
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:31
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::PPCInstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: PPCInstrInfo.cpp:1531
uint64_t
llvm::PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Definition: PPCInstrInfo.cpp:2909
llvm::ImmInstrInfo
Definition: PPCInstrInfo.h:78
llvm::ImmInstrInfo::IsCommutative
uint64_t IsCommutative
Definition: PPCInstrInfo.h:90
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::ImmInstrInfo::TruncateImmTo
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:100
llvm::PPCInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
Definition: PPCInstrInfo.cpp:166
llvm::SpillOpcodeKey
SpillOpcodeKey
Definition: PPCInstrInfo.h:114
llvm::PPCInstrInfo::isSignOrZeroExtended
bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, const unsigned PhiDepth) const
Definition: PPCInstrInfo.cpp:5203
llvm::SOK_Int8Spill
@ SOK_Int8Spill
Definition: PPCInstrInfo.h:116
llvm::PPCInstrInfo::hasLowDefLatency
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
Definition: PPCInstrInfo.h:331
llvm::PPCInstrInfo::useMachineCombiner
bool useMachineCombiner() const override
Definition: PPCInstrInfo.h:340
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:30
llvm::PPCInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: PPCInstrInfo.cpp:1069
llvm::SOK_VectorFloat4Spill
@ SOK_VectorFloat4Spill
Definition: PPCInstrInfo.h:124
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::PPCInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: PPCInstrInfo.cpp:1271
llvm::PPCInstrInfo::getFMAPatterns
bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for a fma chain ending in Root.
Definition: PPCInstrInfo.cpp:367
llvm::SOK_AccumulatorSpill
@ SOK_AccumulatorSpill
Definition: PPCInstrInfo.h:127
llvm::PPCInstrInfo::SubsumesPredicate
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Definition: PPCInstrInfo.cpp:2282
llvm::PPCInstrInfo::loadRegFromStackSlotNoUpd
void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Definition: PPCInstrInfo.cpp:2007
llvm::ImmInstrInfo::ZeroIsSpecialOrig
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:85
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::PPCInstrInfo::convertToImmediateForm
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
Definition: PPCInstrInfo.cpp:3663
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::PPCInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Definition: PPCInstrInfo.cpp:2161
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::PPCInstrInfo::isZeroExtended
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:607
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::PPCInstrInfo::instrHasImmForm
bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
Definition: PPCInstrInfo.cpp:3852
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::PPCInstrInfo::isTOCSaveMI
bool isTOCSaveMI(const MachineInstr &MI) const
Definition: PPCInstrInfo.cpp:5185
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::ImmInstrInfo::ImmMustBeMultipleOf
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:82
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
PPCGenInstrInfo
llvm::PPCInstrInfo::getRegisterInfo
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:289
llvm::PPCInstrInfo::getRegNumForOperand
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
Definition: PPCInstrInfo.h:662
uint16_t
llvm::PPCInstrInfo::combineRLWINM
bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase=nullptr) const
Definition: PPCInstrInfo.cpp:3715
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::PPCInstrInfo::getMachineCombinerPatterns
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
Definition: PPCInstrInfo.cpp:759
llvm::PPCInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Return true if two MIs access different memory addresses and false otherwise.
Definition: PPCInstrInfo.cpp:5494
llvm::PPCII::PPC970_FXU
@ PPC970_FXU
Definition: PPCInstrInfo.h:54
llvm::PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: PPCInstrInfo.cpp:2894
llvm::PPCInstrInfo::getLoadOpcodeForSpill
unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const
Definition: PPCInstrInfo.cpp:1925
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:410
StoreOpcodesForSpill
#define StoreOpcodesForSpill
Definition: PPCInstrInfo.h:185
llvm::PPCInstrInfo::getRecordFormOpcode
static int getRecordFormOpcode(unsigned Opcode)
Definition: PPCInstrInfo.cpp:5082
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::PPCInstrInfo::isValidToBeChangedReg
bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const
Definition: PPCInstrInfo.cpp:3618
llvm::SOK_Float4Spill
@ SOK_Float4Spill
Definition: PPCInstrInfo.h:118
llvm::PPCInstrInfo::getMemOperandWithOffsetWidth
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Return true if get the base operand, byte offset of an instruction and the memory width.
Definition: PPCInstrInfo.cpp:5471
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::PPCInstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Get the base operand and byte offset of an instruction that reads/writes memory.
Definition: PPCInstrInfo.cpp:2760
llvm::PPCInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
Definition: PPCInstrInfo.cpp:1142
llvm::PPCInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: PPCInstrInfo.cpp:1478
llvm::PPCII::PPC970_Single
@ PPC970_Single
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
Definition: PPCInstrInfo.h:39
llvm::SOK_VSXVectorSpill
@ SOK_VSXVectorSpill
Definition: PPCInstrInfo.h:122
llvm::SmallVectorImpl< MachineInstr * >
llvm::PPCInstrInfo::expandVSXMemPseudo
bool expandVSXMemPseudo(MachineInstr &MI) const
Definition: PPCInstrInfo.cpp:2933
llvm::PPCII::PPC970_LSU
@ PPC970_LSU
Definition: PPCInstrInfo.h:55
llvm::PPCII::PPC970_BRU
@ PPC970_BRU
Definition: PPCInstrInfo.h:60
llvm::PPCInstrInfo::CreateTargetHazardRecognizer
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
Definition: PPCInstrInfo.cpp:99
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SOK_CRBitSpill
@ SOK_CRBitSpill
Definition: PPCInstrInfo.h:120
llvm::PPCInstrInfo::foldFrameOffset
bool foldFrameOffset(MachineInstr &MI) const
Definition: PPCInstrInfo.cpp:3454
llvm::PPCInstrInfo::storeRegToStackSlotNoUpd
void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Definition: PPCInstrInfo.cpp:1952
llvm::PPCInstrInfo::isProfitableToDupForIfCvt
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:498
llvm::PPCInstrInfo::isProfitableToIfCvt
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:486
llvm::PPCInstrInfo::PPCInstrInfo
PPCInstrInfo(PPCSubtarget &STI)
Definition: PPCInstrInfo.cpp:90
llvm::PPCInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: PPCInstrInfo.cpp:1446
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::PPCInstrInfo::isReallyTriviallyReMaterializable
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
Definition: PPCInstrInfo.cpp:1089
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::ImmInstrInfo::ImmOpcode
uint64_t ImmOpcode
Definition: PPCInstrInfo.h:96
llvm::ImmInstrInfo::ImmOpNo
uint64_t ImmOpNo
Definition: PPCInstrInfo.h:94
llvm::PPCInstrInfo::finalizeInsInstrs
void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.
Definition: PPCInstrInfo.cpp:543
llvm::ImmInstrInfo::ImmWidth
uint64_t ImmWidth
Definition: PPCInstrInfo.h:98
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::PPCII::PPC970_Pseudo
@ PPC970_Pseudo
These are the various PPC970 execution unit pipelines.
Definition: PPCInstrInfo.h:53
llvm::PPCInstrInfo::isVRRegister
static bool isVRRegister(unsigned Reg)
Definition: PPCInstrInfo.h:588
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20