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PPCInstrInfo.h
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1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 
16 #include "PPC.h"
17 #include "PPCRegisterInfo.h"
19 
20 #define GET_INSTRINFO_HEADER
21 #include "PPCGenInstrInfo.inc"
22 
23 namespace llvm {
24 
25 /// PPCII - This namespace holds all of the PowerPC target-specific
26 /// per-instruction flags. These must match the corresponding definitions in
27 /// PPC.td and PPCInstrFormats.td.
28 namespace PPCII {
29 enum {
30  // PPC970 Instruction Flags. These flags describe the characteristics of the
31  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
32  // raw machine instructions.
33 
34  /// PPC970_First - This instruction starts a new dispatch group, so it will
35  /// always be the first one in the group.
36  PPC970_First = 0x1,
37 
38  /// PPC970_Single - This instruction starts a new dispatch group and
39  /// terminates it, so it will be the sole instruction in the group.
41 
42  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
43  /// two dispatch pipes to be available to issue.
45 
46  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
47  /// an instruction is issued to.
50 };
52  /// These are the various PPC970 execution unit pipelines. Each instruction
53  /// is one of these.
54  PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
55  PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
56  PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
57  PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
58  PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
59  PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
60  PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
61  PPC970_BRU = 7 << PPC970_Shift // Branch Unit
62 };
63 
64 enum {
65  /// Shift count to bypass PPC970 flags
67 
68  /// This instruction is an X-Form memory operation.
69  XFormMemOp = 0x1 << (NewDef_Shift+1)
70 };
71 } // end namespace PPCII
72 
73 // Instructions that have an immediate form might be convertible to that
74 // form if the correct input is a result of a load immediate. In order to
75 // know whether the transformation is special, we might need to know some
76 // of the details of the two forms.
77 struct ImmInstrInfo {
78  // Is the immediate field in the immediate form signed or unsigned?
79  uint64_t SignedImm : 1;
80  // Does the immediate need to be a multiple of some value?
81  uint64_t ImmMustBeMultipleOf : 5;
82  // Is R0/X0 treated specially by the original r+r instruction?
83  // If so, in which operand?
84  uint64_t ZeroIsSpecialOrig : 3;
85  // Is R0/X0 treated specially by the new r+i instruction?
86  // If so, in which operand?
87  uint64_t ZeroIsSpecialNew : 3;
88  // Is the operation commutative?
89  uint64_t IsCommutative : 1;
90  // The operand number to check for add-immediate def.
91  uint64_t OpNoForForwarding : 3;
92  // The operand number for the immediate.
93  uint64_t ImmOpNo : 3;
94  // The opcode of the new instruction.
95  uint64_t ImmOpcode : 16;
96  // The size of the immediate.
97  uint64_t ImmWidth : 5;
98  // The immediate should be truncated to N bits.
99  uint64_t TruncateImmTo : 5;
100  // Is the instruction summing the operand
101  uint64_t IsSummingOperands : 1;
102 };
103 
104 // Information required to convert an instruction to just a materialized
105 // immediate.
107  unsigned Imm : 16;
108  unsigned Is64Bit : 1;
109  unsigned SetCR : 1;
110 };
111 
112 class PPCSubtarget;
114  PPCSubtarget &Subtarget;
115  const PPCRegisterInfo RI;
116 
117  void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
118  int FrameIdx, const TargetRegisterClass *RC,
119  SmallVectorImpl<MachineInstr *> &NewMIs) const;
120  void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
121  unsigned DestReg, int FrameIdx,
122  const TargetRegisterClass *RC,
123  SmallVectorImpl<MachineInstr *> &NewMIs) const;
124 
125  // If the inst has imm-form and one of its operand is produced by a LI,
126  // put the imm into the inst directly and remove the LI if possible.
127  bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
128  unsigned ConstantOpNo, MachineInstr &DefMI,
129  int64_t Imm) const;
130  // If the inst has imm-form and one of its operand is produced by an
131  // add-immediate, try to transform it when possible.
132  bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
133  unsigned ConstantOpNo, MachineInstr &DefMI,
134  bool KillDefMI) const;
135  // Try to find that, if the instruction 'MI' contains any operand that
136  // could be forwarded from some inst that feeds it. If yes, return the
137  // Def of that operand. And OpNoForForwarding is the operand index in
138  // the 'MI' for that 'Def'. If we see another use of this Def between
139  // the Def and the MI, SeenIntermediateUse becomes 'true'.
140  MachineInstr *getForwardingDefMI(MachineInstr &MI,
141  unsigned &OpNoForForwarding,
142  bool &SeenIntermediateUse) const;
143 
144  // Can the user MI have it's source at index \p OpNoForForwarding
145  // forwarded from an add-immediate that feeds it?
146  bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
147  unsigned OpNoForForwarding) const;
148  bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
149  const ImmInstrInfo &III,
150  MachineOperand *&ImmMO,
151  MachineOperand *&RegMO) const;
152  bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
153  const MachineInstr &DefMI,
154  const ImmInstrInfo &III,
155  int64_t &Imm) const;
156  bool isRegElgibleForForwarding(const MachineOperand &RegMO,
157  const MachineInstr &DefMI,
158  const MachineInstr &MI, bool KillDefMI,
159  bool &IsFwdFeederRegKilled) const;
160  const unsigned *getStoreOpcodesForSpillArray() const;
161  const unsigned *getLoadOpcodesForSpillArray() const;
162  virtual void anchor();
163 
164 protected:
165  /// Commutes the operands in the given instruction.
166  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
167  ///
168  /// Do not call this method for a non-commutable instruction or for
169  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
170  /// Even though the instruction is commutable, the method may still
171  /// fail to commute the operands, null pointer is returned in such cases.
172  ///
173  /// For example, we can commute rlwimi instructions, but only if the
174  /// rotate amt is zero. We also have to munge the immediates a bit.
175  MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
176  unsigned OpIdx1,
177  unsigned OpIdx2) const override;
178 
179 public:
180  explicit PPCInstrInfo(PPCSubtarget &STI);
181 
182  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
183  /// such, whenever a client has an instance of instruction info, it should
184  /// always be able to get register info as well (through this method).
185  ///
186  const PPCRegisterInfo &getRegisterInfo() const { return RI; }
187 
188  bool isXFormMemOp(unsigned Opcode) const {
189  return get(Opcode).TSFlags & PPCII::XFormMemOp;
190  }
191  static bool isSameClassPhysRegCopy(unsigned Opcode) {
192  unsigned CopyOpcodes[] =
193  { PPC::OR, PPC::OR8, PPC::FMR, PPC::VOR, PPC::XXLOR, PPC::XXLORf,
194  PPC::XSCPSGNDP, PPC::MCRF, PPC::QVFMR, PPC::QVFMRs, PPC::QVFMRb,
195  PPC::CROR, PPC::EVOR, -1U };
196  for (int i = 0; CopyOpcodes[i] != -1U; i++)
197  if (Opcode == CopyOpcodes[i])
198  return true;
199  return false;
200  }
201 
203  CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
204  const ScheduleDAG *DAG) const override;
206  CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
207  const ScheduleDAG *DAG) const override;
208 
209  unsigned getInstrLatency(const InstrItineraryData *ItinData,
210  const MachineInstr &MI,
211  unsigned *PredCost = nullptr) const override;
212 
213  int getOperandLatency(const InstrItineraryData *ItinData,
214  const MachineInstr &DefMI, unsigned DefIdx,
215  const MachineInstr &UseMI,
216  unsigned UseIdx) const override;
218  SDNode *DefNode, unsigned DefIdx,
219  SDNode *UseNode, unsigned UseIdx) const override {
220  return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
221  UseNode, UseIdx);
222  }
223 
224  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
225  const MachineInstr &DefMI,
226  unsigned DefIdx) const override {
227  // Machine LICM should hoist all instructions in low-register-pressure
228  // situations; none are sufficiently free to justify leaving in a loop
229  // body.
230  return false;
231  }
232 
233  bool useMachineCombiner() const override {
234  return true;
235  }
236 
237  /// Return true when there is potentially a faster code sequence
238  /// for an instruction chain ending in <Root>. All potential patterns are
239  /// output in the <Pattern> array.
240  bool getMachineCombinerPatterns(
241  MachineInstr &Root,
243 
244  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
245 
246  bool isCoalescableExtInstr(const MachineInstr &MI,
247  unsigned &SrcReg, unsigned &DstReg,
248  unsigned &SubIdx) const override;
249  unsigned isLoadFromStackSlot(const MachineInstr &MI,
250  int &FrameIndex) const override;
251  bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
252  AliasAnalysis *AA) const override;
253  unsigned isStoreToStackSlot(const MachineInstr &MI,
254  int &FrameIndex) const override;
255 
256  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
257  unsigned &SrcOpIdx2) const override;
258 
259  void insertNoop(MachineBasicBlock &MBB,
260  MachineBasicBlock::iterator MI) const override;
261 
262 
263  // Branch analysis.
264  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
265  MachineBasicBlock *&FBB,
267  bool AllowModify) const override;
268  unsigned removeBranch(MachineBasicBlock &MBB,
269  int *BytesRemoved = nullptr) const override;
270  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
272  const DebugLoc &DL,
273  int *BytesAdded = nullptr) const override;
274 
275  // Select analysis.
276  bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
277  unsigned, unsigned, int &, int &, int &) const override;
278  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
279  const DebugLoc &DL, unsigned DstReg,
280  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
281  unsigned FalseReg) const override;
282 
283  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
284  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
285  bool KillSrc) const override;
286 
287  void storeRegToStackSlot(MachineBasicBlock &MBB,
289  unsigned SrcReg, bool isKill, int FrameIndex,
290  const TargetRegisterClass *RC,
291  const TargetRegisterInfo *TRI) const override;
292 
293  void loadRegFromStackSlot(MachineBasicBlock &MBB,
295  unsigned DestReg, int FrameIndex,
296  const TargetRegisterClass *RC,
297  const TargetRegisterInfo *TRI) const override;
298 
299  unsigned getStoreOpcodeForSpill(unsigned Reg,
300  const TargetRegisterClass *RC = nullptr) const;
301 
302  unsigned getLoadOpcodeForSpill(unsigned Reg,
303  const TargetRegisterClass *RC = nullptr) const;
304 
305  bool
306  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
307 
308  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
309  MachineRegisterInfo *MRI) const override;
310 
311  // If conversion by predication (only supported by some branch instructions).
312  // All of the profitability checks always return true; it is always
313  // profitable to use the predicated branches.
315  unsigned NumCycles, unsigned ExtraPredCycles,
316  BranchProbability Probability) const override {
317  return true;
318  }
319 
320  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
321  unsigned NumT, unsigned ExtraT,
322  MachineBasicBlock &FMBB,
323  unsigned NumF, unsigned ExtraF,
324  BranchProbability Probability) const override;
325 
326  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
327  BranchProbability Probability) const override {
328  return true;
329  }
330 
332  MachineBasicBlock &FMBB) const override {
333  return false;
334  }
335 
336  // Predication support.
337  bool isPredicated(const MachineInstr &MI) const override;
338 
339  bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
340 
341  bool PredicateInstruction(MachineInstr &MI,
342  ArrayRef<MachineOperand> Pred) const override;
343 
344  bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
345  ArrayRef<MachineOperand> Pred2) const override;
346 
347  bool DefinesPredicate(MachineInstr &MI,
348  std::vector<MachineOperand> &Pred) const override;
349 
350  bool isPredicable(const MachineInstr &MI) const override;
351 
352  // Comparison optimization.
353 
354  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
355  unsigned &SrcReg2, int &Mask, int &Value) const override;
356 
357  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
358  unsigned SrcReg2, int Mask, int Value,
359  const MachineRegisterInfo *MRI) const override;
360 
361  /// GetInstSize - Return the number of bytes of code the specified
362  /// instruction may be. This returns the maximum number of bytes.
363  ///
364  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
365 
366  void getNoop(MCInst &NopInst) const override;
367 
368  std::pair<unsigned, unsigned>
369  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
370 
372  getSerializableDirectMachineOperandTargetFlags() const override;
373 
375  getSerializableBitmaskMachineOperandTargetFlags() const override;
376 
377  // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
378  bool expandVSXMemPseudo(MachineInstr &MI) const;
379 
380  // Lower pseudo instructions after register allocation.
381  bool expandPostRAPseudo(MachineInstr &MI) const override;
382 
383  static bool isVFRegister(unsigned Reg) {
384  return Reg >= PPC::VF0 && Reg <= PPC::VF31;
385  }
386  static bool isVRRegister(unsigned Reg) {
387  return Reg >= PPC::V0 && Reg <= PPC::V31;
388  }
389  const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
390  static int getRecordFormOpcode(unsigned Opcode);
391 
392  bool isTOCSaveMI(const MachineInstr &MI) const;
393 
394  bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
395  const unsigned PhiDepth) const;
396 
397  /// Return true if the output of the instruction is always a sign-extended,
398  /// i.e. 0 to 31-th bits are same as 32-th bit.
399  bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const {
400  return isSignOrZeroExtended(MI, true, depth);
401  }
402 
403  /// Return true if the output of the instruction is always zero-extended,
404  /// i.e. 0 to 31-th bits are all zeros
405  bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
406  return isSignOrZeroExtended(MI, false, depth);
407  }
408 
409  bool convertToImmediateForm(MachineInstr &MI,
410  MachineInstr **KilledDef = nullptr) const;
411 
412  /// Fixup killed/dead flag for register \p RegNo between instructions [\p
413  /// StartMI, \p EndMI]. Some PostRA transformations may violate register
414  /// killed/dead flags semantics, this function can be called to fix up. Before
415  /// calling this function,
416  /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
417  /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
418  /// and possible definition for \p RegNo is \p StartMI or \p EndMI.
419  /// 3. Ensure that all instructions between [\p StartMI, \p EndMI] are in same
420  /// basic block.
421  void fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI,
422  unsigned RegNo) const;
423  void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
424  void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
425  int64_t Imm) const;
426 
427  bool instrHasImmForm(const MachineInstr &MI, ImmInstrInfo &III,
428  bool PostRA) const;
429 
430  /// getRegNumForOperand - some operands use different numbering schemes
431  /// for the same registers. For example, a VSX instruction may have any of
432  /// vs0-vs63 allocated whereas an Altivec instruction could only have
433  /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
434  /// register number needed for the opcode/operand number combination.
435  /// The operand number argument will be useful when we need to extend this
436  /// to instructions that use both Altivec and VSX numbering (for different
437  /// operands).
438  static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
439  unsigned OpNo) {
440  int16_t regClass = Desc.OpInfo[OpNo].RegClass;
441  switch (regClass) {
442  // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
443  // VSX32-VSX63 during encoding/disassembling
444  case PPC::VSSRCRegClassID:
445  case PPC::VSFRCRegClassID:
446  if (isVFRegister(Reg))
447  return PPC::VSX32 + (Reg - PPC::VF0);
448  break;
449  // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
450  // VSX32-VSX63 during encoding/disassembling
451  case PPC::VSRCRegClassID:
452  if (isVRRegister(Reg))
453  return PPC::VSX32 + (Reg - PPC::V0);
454  break;
455  // Other RegClass doesn't need mapping
456  default:
457  break;
458  }
459  return Reg;
460  }
461 };
462 
463 }
464 
465 #endif
This class represents lattice values for constants.
Definition: AllocatorList.h:23
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:87
bool useMachineCombiner() const override
Definition: PPCInstrInfo.h:233
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned Reg
This instruction is an X-Form memory operation.
Definition: PPCInstrInfo.h:69
uint64_t IsCommutative
Definition: PPCInstrInfo.h:89
These are the various PPC970 execution unit pipelines.
Definition: PPCInstrInfo.h:54
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:99
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:91
Shift count to bypass PPC970 flags.
Definition: PPCInstrInfo.h:66
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:101
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
Definition: PPCInstrInfo.h:40
bool isSignExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always a sign-extended, i.e.
Definition: PPCInstrInfo.h:399
PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that an instruction is issued to...
Definition: PPCInstrInfo.h:48
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:188
static bool isVRRegister(unsigned Reg)
Definition: PPCInstrInfo.h:386
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: PPCInstrInfo.h:331
Provide an instruction scheduling machine model to CodeGen passes.
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:84
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
Definition: PPCInstrInfo.h:44
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
#define P(N)
unsigned const MachineRegisterInfo * MRI
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
MachineInstrBuilder & UseMI
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:30
static bool isSameClassPhysRegCopy(unsigned Opcode)
Definition: PPCInstrInfo.h:191
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:326
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
Definition: PPCInstrInfo.h:438
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder MachineInstrBuilder & DefMI
Represents one node in the SelectionDAG.
static bool isVFRegister(unsigned Reg)
Definition: PPCInstrInfo.h:383
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
Definition: PPCInstrInfo.h:224
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
Definition: MachineInstr.h:63
int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
Definition: PPCInstrInfo.h:217
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:72
#define I(x, y, z)
Definition: MD5.cpp:58
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:81
LLVM Value Representation.
Definition: Value.h:72
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
Definition: PPCInstrInfo.h:36
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:186
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:314
bool isZeroExtended(const MachineInstr &MI, const unsigned depth=0) const
Return true if the output of the instruction is always zero-extended, i.e.
Definition: PPCInstrInfo.h:405