LLVM  16.0.0git
PPCInstrInfo.h
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1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the PowerPC implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 
16 #include "PPCRegisterInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "PPCGenInstrInfo.inc"
21 
22 namespace llvm {
23 
24 /// PPCII - This namespace holds all of the PowerPC target-specific
25 /// per-instruction flags. These must match the corresponding definitions in
26 /// PPC.td and PPCInstrFormats.td.
27 namespace PPCII {
28 enum {
29  // PPC970 Instruction Flags. These flags describe the characteristics of the
30  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
31  // raw machine instructions.
32 
33  /// PPC970_First - This instruction starts a new dispatch group, so it will
34  /// always be the first one in the group.
35  PPC970_First = 0x1,
36 
37  /// PPC970_Single - This instruction starts a new dispatch group and
38  /// terminates it, so it will be the sole instruction in the group.
40 
41  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
42  /// two dispatch pipes to be available to issue.
44 
45  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
46  /// an instruction is issued to.
49 };
51  /// These are the various PPC970 execution unit pipelines. Each instruction
52  /// is one of these.
53  PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
54  PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
55  PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
56  PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
57  PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
58  PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
59  PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
60  PPC970_BRU = 7 << PPC970_Shift // Branch Unit
61 };
62 
63 enum {
64  /// Shift count to bypass PPC970 flags
66 
67  /// This instruction is an X-Form memory operation.
69  /// This instruction is prefixed.
70  Prefixed = 0x1 << (NewDef_Shift + 1),
71  /// This instruction produced a sign extended result.
72  SExt32To64 = 0x1 << (NewDef_Shift + 2),
73  /// This instruction produced a zero extended result.
74  ZExt32To64 = 0x1 << (NewDef_Shift + 3)
75 };
76 } // end namespace PPCII
77 
78 // Instructions that have an immediate form might be convertible to that
79 // form if the correct input is a result of a load immediate. In order to
80 // know whether the transformation is special, we might need to know some
81 // of the details of the two forms.
82 struct ImmInstrInfo {
83  // Is the immediate field in the immediate form signed or unsigned?
85  // Does the immediate need to be a multiple of some value?
87  // Is R0/X0 treated specially by the original r+r instruction?
88  // If so, in which operand?
90  // Is R0/X0 treated specially by the new r+i instruction?
91  // If so, in which operand?
93  // Is the operation commutative?
95  // The operand number to check for add-immediate def.
97  // The operand number for the immediate.
99  // The opcode of the new instruction.
101  // The size of the immediate.
103  // The immediate should be truncated to N bits.
105  // Is the instruction summing the operand
107 };
108 
109 // Information required to convert an instruction to just a materialized
110 // immediate.
112  unsigned Imm : 16;
113  unsigned Is64Bit : 1;
114  unsigned SetCR : 1;
115 };
116 
117 // Index into the OpcodesForSpill array.
135  SOK_LastOpcodeSpill // This must be last on the enum.
136 };
137 
138 // Define list of load and store spill opcodes.
139 #define NoInstr PPC::INSTRUCTION_LIST_END
140 #define Pwr8LoadOpcodes \
141  { \
142  PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
143  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \
144  PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, PPC::EVLDD, \
145  PPC::RESTORE_QUADWORD \
146  }
147 
148 #define Pwr9LoadOpcodes \
149  { \
150  PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
151  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
152  PPC::DFLOADf32, PPC::SPILLTOVSR_LD, NoInstr, NoInstr, NoInstr, \
153  NoInstr, PPC::RESTORE_QUADWORD \
154  }
155 
156 #define Pwr10LoadOpcodes \
157  { \
158  PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
159  PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \
160  PPC::DFLOADf32, PPC::SPILLTOVSR_LD, PPC::LXVP, PPC::RESTORE_ACC, \
161  PPC::RESTORE_UACC, NoInstr, PPC::RESTORE_QUADWORD \
162  }
163 
164 #define Pwr8StoreOpcodes \
165  { \
166  PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
167  PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \
168  PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, PPC::EVSTDD, \
169  PPC::SPILL_QUADWORD \
170  }
171 
172 #define Pwr9StoreOpcodes \
173  { \
174  PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
175  PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
176  PPC::SPILLTOVSR_ST, NoInstr, NoInstr, NoInstr, NoInstr, \
177  PPC::SPILL_QUADWORD \
178  }
179 
180 #define Pwr10StoreOpcodes \
181  { \
182  PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \
183  PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \
184  PPC::SPILLTOVSR_ST, PPC::STXVP, PPC::SPILL_ACC, PPC::SPILL_UACC, \
185  NoInstr, PPC::SPILL_QUADWORD \
186  }
187 
188 // Initialize arrays for load and store spill opcodes on supported subtargets.
189 #define StoreOpcodesForSpill \
190  { Pwr8StoreOpcodes, Pwr9StoreOpcodes, Pwr10StoreOpcodes }
191 #define LoadOpcodesForSpill \
192  { Pwr8LoadOpcodes, Pwr9LoadOpcodes, Pwr10LoadOpcodes }
193 
194 class PPCSubtarget;
196  PPCSubtarget &Subtarget;
197  const PPCRegisterInfo RI;
198  const unsigned StoreSpillOpcodesArray[3][SOK_LastOpcodeSpill] =
200  const unsigned LoadSpillOpcodesArray[3][SOK_LastOpcodeSpill] =
202 
203  void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
204  int FrameIdx, const TargetRegisterClass *RC,
205  SmallVectorImpl<MachineInstr *> &NewMIs) const;
206  void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
207  unsigned DestReg, int FrameIdx,
208  const TargetRegisterClass *RC,
209  SmallVectorImpl<MachineInstr *> &NewMIs) const;
210 
211  // Replace the instruction with single LI if possible. \p DefMI must be LI or
212  // LI8.
213  bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
214  unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
215  // If the inst is imm-form and its register operand is produced by a ADDI, put
216  // the imm into the inst directly and remove the ADDI if possible.
217  bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
218  unsigned OpNoForForwarding) const;
219  // If the inst is x-form and has imm-form and one of its operand is produced
220  // by a LI, put the imm into the inst directly and remove the LI if possible.
221  bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
222  unsigned ConstantOpNo,
223  MachineInstr &DefMI) const;
224  // If the inst is x-form and has imm-form and one of its operand is produced
225  // by an add-immediate, try to transform it when possible.
226  bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
227  unsigned ConstantOpNo, MachineInstr &DefMI,
228  bool KillDefMI) const;
229  // Try to find that, if the instruction 'MI' contains any operand that
230  // could be forwarded from some inst that feeds it. If yes, return the
231  // Def of that operand. And OpNoForForwarding is the operand index in
232  // the 'MI' for that 'Def'. If we see another use of this Def between
233  // the Def and the MI, SeenIntermediateUse becomes 'true'.
234  MachineInstr *getForwardingDefMI(MachineInstr &MI,
235  unsigned &OpNoForForwarding,
236  bool &SeenIntermediateUse) const;
237 
238  // Can the user MI have it's source at index \p OpNoForForwarding
239  // forwarded from an add-immediate that feeds it?
240  bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
241  unsigned OpNoForForwarding) const;
242  bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
243  const ImmInstrInfo &III,
244  MachineOperand *&ImmMO,
245  MachineOperand *&RegMO) const;
246  bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
247  const MachineInstr &DefMI,
248  const ImmInstrInfo &III,
249  int64_t &Imm,
250  int64_t BaseImm = 0) const;
251  bool isRegElgibleForForwarding(const MachineOperand &RegMO,
252  const MachineInstr &DefMI,
253  const MachineInstr &MI, bool KillDefMI,
254  bool &IsFwdFeederRegKilled) const;
255  unsigned getSpillTarget() const;
256  const unsigned *getStoreOpcodesForSpillArray() const;
257  const unsigned *getLoadOpcodesForSpillArray() const;
258  unsigned getSpillIndex(const TargetRegisterClass *RC) const;
259  int16_t getFMAOpIdxInfo(unsigned Opcode) const;
260  void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern,
263  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
264  bool isLoadFromConstantPool(MachineInstr *I) const;
265  Register
266  generateLoadForNewConst(unsigned Idx, MachineInstr *MI, Type *Ty,
267  SmallVectorImpl<MachineInstr *> &InsInstrs) const;
268  const Constant *getConstantFromConstantPool(MachineInstr *I) const;
269  virtual void anchor();
270 
271 protected:
272  /// Commutes the operands in the given instruction.
273  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
274  ///
275  /// Do not call this method for a non-commutable instruction or for
276  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
277  /// Even though the instruction is commutable, the method may still
278  /// fail to commute the operands, null pointer is returned in such cases.
279  ///
280  /// For example, we can commute rlwimi instructions, but only if the
281  /// rotate amt is zero. We also have to munge the immediates a bit.
283  unsigned OpIdx1,
284  unsigned OpIdx2) const override;
285 
286 public:
287  explicit PPCInstrInfo(PPCSubtarget &STI);
288 
289  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
290  /// such, whenever a client has an instance of instruction info, it should
291  /// always be able to get register info as well (through this method).
292  ///
293  const PPCRegisterInfo &getRegisterInfo() const { return RI; }
294 
295  bool isXFormMemOp(unsigned Opcode) const {
296  return get(Opcode).TSFlags & PPCII::XFormMemOp;
297  }
298  bool isPrefixed(unsigned Opcode) const {
299  return get(Opcode).TSFlags & PPCII::Prefixed;
300  }
301  bool isSExt32To64(unsigned Opcode) const {
302  return get(Opcode).TSFlags & PPCII::SExt32To64;
303  }
304  bool isZExt32To64(unsigned Opcode) const {
305  return get(Opcode).TSFlags & PPCII::ZExt32To64;
306  }
307 
308  /// Check if Opcode corresponds to a call instruction that should be marked
309  /// with the NOTOC relocation.
310  bool isNoTOCCallInstr(unsigned Opcode) const {
311  if (!get(Opcode).isCall())
312  return false;
313 
314  switch (Opcode) {
315  default:
316 #ifndef NDEBUG
317  llvm_unreachable("Unknown call opcode");
318 #endif
319  return false;
320  case PPC::BL8_NOTOC:
321  case PPC::BL8_NOTOC_TLS:
322  case PPC::BL8_NOTOC_RM:
323  return true;
324 #ifndef NDEBUG
325  case PPC::BL8:
326  case PPC::BL:
327  case PPC::BL8_TLS:
328  case PPC::BL_TLS:
329  case PPC::BLA8:
330  case PPC::BLA:
331  case PPC::BCCL:
332  case PPC::BCCLA:
333  case PPC::BCL:
334  case PPC::BCLn:
335  case PPC::BL8_NOP:
336  case PPC::BL_NOP:
337  case PPC::BL8_NOP_TLS:
338  case PPC::BLA8_NOP:
339  case PPC::BCTRL8:
340  case PPC::BCTRL:
341  case PPC::BCCCTRL8:
342  case PPC::BCCCTRL:
343  case PPC::BCCTRL8:
344  case PPC::BCCTRL:
345  case PPC::BCCTRL8n:
346  case PPC::BCCTRLn:
347  case PPC::BL8_RM:
348  case PPC::BLA8_RM:
349  case PPC::BL8_NOP_RM:
350  case PPC::BLA8_NOP_RM:
351  case PPC::BCTRL8_RM:
352  case PPC::BCTRL8_LDinto_toc:
353  case PPC::BCTRL8_LDinto_toc_RM:
354  case PPC::BL8_TLS_:
355  case PPC::TCRETURNdi8:
356  case PPC::TCRETURNai8:
357  case PPC::TCRETURNri8:
358  case PPC::TAILBCTR8:
359  case PPC::TAILB8:
360  case PPC::TAILBA8:
361  case PPC::BCLalways:
362  case PPC::BLRL:
363  case PPC::BCCLRL:
364  case PPC::BCLRL:
365  case PPC::BCLRLn:
366  case PPC::BDZL:
367  case PPC::BDNZL:
368  case PPC::BDZLA:
369  case PPC::BDNZLA:
370  case PPC::BDZLp:
371  case PPC::BDNZLp:
372  case PPC::BDZLAp:
373  case PPC::BDNZLAp:
374  case PPC::BDZLm:
375  case PPC::BDNZLm:
376  case PPC::BDZLAm:
377  case PPC::BDNZLAm:
378  case PPC::BDZLRL:
379  case PPC::BDNZLRL:
380  case PPC::BDZLRLp:
381  case PPC::BDNZLRLp:
382  case PPC::BDZLRLm:
383  case PPC::BDNZLRLm:
384  case PPC::BL_RM:
385  case PPC::BLA_RM:
386  case PPC::BL_NOP_RM:
387  case PPC::BCTRL_RM:
388  case PPC::TCRETURNdi:
389  case PPC::TCRETURNai:
390  case PPC::TCRETURNri:
391  case PPC::BCTRL_LWZinto_toc:
392  case PPC::BCTRL_LWZinto_toc_RM:
393  case PPC::TAILBCTR:
394  case PPC::TAILB:
395  case PPC::TAILBA:
396  return false;
397 #endif
398  }
399  }
400 
401  static bool isSameClassPhysRegCopy(unsigned Opcode) {
402  unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR,
403  PPC::VOR, PPC::XXLOR, PPC::XXLORf,
404  PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR,
405  PPC::EVOR, -1U};
406  for (int i = 0; CopyOpcodes[i] != -1U; i++)
407  if (Opcode == CopyOpcodes[i])
408  return true;
409  return false;
410  }
411 
414  const ScheduleDAG *DAG) const override;
417  const ScheduleDAG *DAG) const override;
418 
419  unsigned getInstrLatency(const InstrItineraryData *ItinData,
420  const MachineInstr &MI,
421  unsigned *PredCost = nullptr) const override;
422 
423  int getOperandLatency(const InstrItineraryData *ItinData,
424  const MachineInstr &DefMI, unsigned DefIdx,
425  const MachineInstr &UseMI,
426  unsigned UseIdx) const override;
428  SDNode *DefNode, unsigned DefIdx,
429  SDNode *UseNode, unsigned UseIdx) const override {
430  return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
431  UseNode, UseIdx);
432  }
433 
434  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
435  const MachineInstr &DefMI,
436  unsigned DefIdx) const override {
437  // Machine LICM should hoist all instructions in low-register-pressure
438  // situations; none are sufficiently free to justify leaving in a loop
439  // body.
440  return false;
441  }
442 
443  bool useMachineCombiner() const override {
444  return true;
445  }
446 
447  /// When getMachineCombinerPatterns() finds patterns, this function generates
448  /// the instructions that could replace the original code sequence
453  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
454 
455  /// Return true when there is potentially a faster code sequence for a fma
456  /// chain ending in \p Root. All potential patterns are output in the \p
457  /// P array.
458  bool getFMAPatterns(MachineInstr &Root,
460  bool DoRegPressureReduce) const;
461 
462  /// Return true when there is potentially a faster code sequence
463  /// for an instruction chain ending in <Root>. All potential patterns are
464  /// output in the <Pattern> array.
467  bool DoRegPressureReduce) const override;
468 
469  /// On PowerPC, we leverage machine combiner pass to reduce register pressure
470  /// when the register pressure is high for one BB.
471  /// Return true if register pressure for \p MBB is high and ABI is supported
472  /// to reduce register pressure. Otherwise return false.
473  bool
475  RegisterClassInfo *RegClassInfo) const override;
476 
477  /// Fixup the placeholders we put in genAlternativeCodeSequence() for
478  /// MachineCombiner.
479  void
481  SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
482 
483  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
484 
485  /// On PowerPC, we try to reassociate FMA chain which will increase
486  /// instruction size. Set extension resource length limit to 1 for edge case.
487  /// Resource Length is calculated by scaled resource usage in getCycles().
488  /// Because of the division in getCycles(), it returns different cycles due to
489  /// legacy scaled resource usage. So new resource length may be same with
490  /// legacy or 1 bigger than legacy.
491  /// We need to execlude the 1 bigger case even the resource length is not
492  /// perserved for more FMA chain reassociations on PowerPC.
493  int getExtendResourceLenLimit() const override { return 1; }
494 
495  void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
496  MachineInstr &NewMI1,
497  MachineInstr &NewMI2) const override;
498 
499  // PowerPC specific version of setSpecialOperandAttr that copies Flags to MI
500  // and clears nuw, nsw, and exact flags.
501  void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const;
502 
504  Register &SrcReg, Register &DstReg,
505  unsigned &SubIdx) const override;
506  unsigned isLoadFromStackSlot(const MachineInstr &MI,
507  int &FrameIndex) const override;
508  bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
509  unsigned isStoreToStackSlot(const MachineInstr &MI,
510  int &FrameIndex) const override;
511 
512  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
513  unsigned &SrcOpIdx2) const override;
514 
516  MachineBasicBlock::iterator MI) const override;
517 
518 
519  // Branch analysis.
521  MachineBasicBlock *&FBB,
523  bool AllowModify) const override;
525  int *BytesRemoved = nullptr) const override;
528  const DebugLoc &DL,
529  int *BytesAdded = nullptr) const override;
530 
531  // Select analysis.
533  Register, Register, Register, int &, int &,
534  int &) const override;
536  const DebugLoc &DL, Register DstReg,
538  Register FalseReg) const override;
539 
541  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
542  bool KillSrc) const override;
543 
546  Register SrcReg, bool isKill, int FrameIndex,
547  const TargetRegisterClass *RC,
548  const TargetRegisterInfo *TRI) const override;
549 
550  // Emits a register spill without updating the register class for vector
551  // registers. This ensures that when we spill a vector register the
552  // element order in the register is the same as it was in memory.
555  unsigned SrcReg, bool isKill, int FrameIndex,
556  const TargetRegisterClass *RC,
557  const TargetRegisterInfo *TRI) const;
558 
561  Register DestReg, int FrameIndex,
562  const TargetRegisterClass *RC,
563  const TargetRegisterInfo *TRI) const override;
564 
565  // Emits a register reload without updating the register class for vector
566  // registers. This ensures that when we reload a vector register the
567  // element order in the register is the same as it was in memory.
570  unsigned DestReg, int FrameIndex,
571  const TargetRegisterClass *RC,
572  const TargetRegisterInfo *TRI) const;
573 
574  unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const;
575 
576  unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const;
577 
578  bool
580 
582  MachineRegisterInfo *MRI) const override;
583 
585  Register Reg) const;
586 
587  // If conversion by predication (only supported by some branch instructions).
588  // All of the profitability checks always return true; it is always
589  // profitable to use the predicated branches.
591  unsigned NumCycles, unsigned ExtraPredCycles,
592  BranchProbability Probability) const override {
593  return true;
594  }
595 
597  unsigned NumT, unsigned ExtraT,
598  MachineBasicBlock &FMBB,
599  unsigned NumF, unsigned ExtraF,
600  BranchProbability Probability) const override;
601 
603  BranchProbability Probability) const override {
604  return true;
605  }
606 
608  MachineBasicBlock &FMBB) const override {
609  return false;
610  }
611 
612  // Predication support.
613  bool isPredicated(const MachineInstr &MI) const override;
614 
616  const MachineBasicBlock *MBB,
617  const MachineFunction &MF) const override;
618 
620  ArrayRef<MachineOperand> Pred) const override;
621 
623  ArrayRef<MachineOperand> Pred2) const override;
624 
625  bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
626  bool SkipDead) const override;
627 
628  // Comparison optimization.
629 
630  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
631  Register &SrcReg2, int64_t &Mask,
632  int64_t &Value) const override;
633 
634  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
635  Register SrcReg2, int64_t Mask, int64_t Value,
636  const MachineRegisterInfo *MRI) const override;
637 
638 
639  /// Return true if get the base operand, byte offset of an instruction and
640  /// the memory width. Width is the size of memory that is being
641  /// loaded/stored (e.g. 1, 2, 4, 8).
643  const MachineOperand *&BaseOp,
644  int64_t &Offset, unsigned &Width,
645  const TargetRegisterInfo *TRI) const;
646 
647  /// Get the base operand and byte offset of an instruction that reads/writes
648  /// memory.
650  const MachineInstr &LdSt,
651  SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
652  bool &OffsetIsScalable, unsigned &Width,
653  const TargetRegisterInfo *TRI) const override;
654 
655  /// Returns true if the two given memory operations should be scheduled
656  /// adjacent.
659  unsigned NumLoads, unsigned NumBytes) const override;
660 
661  /// Return true if two MIs access different memory addresses and false
662  /// otherwise
663  bool
665  const MachineInstr &MIb) const override;
666 
667  /// GetInstSize - Return the number of bytes of code the specified
668  /// instruction may be. This returns the maximum number of bytes.
669  ///
670  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
671 
672  MCInst getNop() const override;
673 
674  std::pair<unsigned, unsigned>
675  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
676 
679 
682 
683  // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
684  bool expandVSXMemPseudo(MachineInstr &MI) const;
685 
686  // Lower pseudo instructions after register allocation.
687  bool expandPostRAPseudo(MachineInstr &MI) const override;
688 
689  static bool isVFRegister(unsigned Reg) {
690  return Reg >= PPC::VF0 && Reg <= PPC::VF31;
691  }
692  static bool isVRRegister(unsigned Reg) {
693  return Reg >= PPC::V0 && Reg <= PPC::V31;
694  }
695  const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
696  static int getRecordFormOpcode(unsigned Opcode);
697 
698  bool isTOCSaveMI(const MachineInstr &MI) const;
699 
700  std::pair<bool, bool>
701  isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth,
702  const MachineRegisterInfo *MRI) const;
703 
704  // Return true if the register is sign-extended from 32 to 64 bits.
705  bool isSignExtended(const unsigned Reg,
706  const MachineRegisterInfo *MRI) const {
707  return isSignOrZeroExtended(Reg, 0, MRI).first;
708  }
709 
710  // Return true if the register is zero-extended from 32 to 64 bits.
711  bool isZeroExtended(const unsigned Reg,
712  const MachineRegisterInfo *MRI) const {
713  return isSignOrZeroExtended(Reg, 0, MRI).second;
714  }
715 
717  MachineInstr **KilledDef = nullptr) const;
718  bool foldFrameOffset(MachineInstr &MI) const;
719  bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
720  bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
721  bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const;
722  bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
723  unsigned &XFormOpcode,
724  int64_t &OffsetOfImmInstr,
725  ImmInstrInfo &III) const;
726  bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
727  MachineInstr *&ADDIMI, int64_t &OffsetAddi,
728  int64_t OffsetImm) const;
729 
730  /// Fixup killed/dead flag for register \p RegNo between instructions [\p
731  /// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate
732  /// register killed/dead flags semantics, this function can be called to fix
733  /// up. Before calling this function,
734  /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
735  /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
736  /// and possible definition for \p RegNo is \p StartMI or \p EndMI. For
737  /// pre-RA cases, definition may be \p StartMI through COPY, \p StartMI
738  /// will be adjust to true definition.
739  /// 3. We can do accurate fixup for the case when all instructions between
740  /// [\p StartMI, \p EndMI] are in same basic block.
741  /// 4. For the case when \p StartMI and \p EndMI are not in same basic block,
742  /// we conservatively clear kill flag for all uses of \p RegNo for pre-RA
743  /// and for post-RA, we give an assertion as without reaching definition
744  /// analysis post-RA, \p StartMI and \p EndMI are hard to keep right.
745  void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
746  unsigned RegNo) const;
747  void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
748  void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
749  int64_t Imm) const;
750 
751  bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
752  bool PostRA) const;
753 
754  // In PostRA phase, try to find instruction defines \p Reg before \p MI.
755  // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
757  bool &SeenIntermediateUse) const;
758 
759  // Materialize immediate after RA.
762  const DebugLoc &DL, Register Reg,
763  int64_t Imm) const;
764 
765  /// getRegNumForOperand - some operands use different numbering schemes
766  /// for the same registers. For example, a VSX instruction may have any of
767  /// vs0-vs63 allocated whereas an Altivec instruction could only have
768  /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
769  /// register number needed for the opcode/operand number combination.
770  /// The operand number argument will be useful when we need to extend this
771  /// to instructions that use both Altivec and VSX numbering (for different
772  /// operands).
773  static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
774  unsigned OpNo) {
775  int16_t regClass = Desc.OpInfo[OpNo].RegClass;
776  switch (regClass) {
777  // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
778  // VSX32-VSX63 during encoding/disassembling
779  case PPC::VSSRCRegClassID:
780  case PPC::VSFRCRegClassID:
781  if (isVFRegister(Reg))
782  return PPC::VSX32 + (Reg - PPC::VF0);
783  break;
784  // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
785  // VSX32-VSX63 during encoding/disassembling
786  case PPC::VSRCRegClassID:
787  if (isVRRegister(Reg))
788  return PPC::VSX32 + (Reg - PPC::V0);
789  break;
790  // Other RegClass doesn't need mapping
791  default:
792  break;
793  }
794  return Reg;
795  }
796 
797  /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
798  bool isBDNZ(unsigned Opcode) const;
799 
800  /// Find the hardware loop instruction used to set-up the specified loop.
801  /// On PPC, we have two instructions used to set-up the hardware loop
802  /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8)
803  /// instructions to indicate the end of a loop.
804  MachineInstr *
805  findLoopInstr(MachineBasicBlock &PreHeader,
806  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const;
807 
808  /// Analyze loop L, which must be a single-basic-block loop, and if the
809  /// conditions can be understood enough produce a PipelinerLoopInfo object.
810  std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
811  analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
812 };
813 
814 }
815 
816 #endif
llvm::PPCII::PPC970_Unit
PPC970_Unit
Definition: PPCInstrInfo.h:50
llvm::PPCInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: PPCInstrInfo.cpp:1129
i
i
Definition: README.txt:29
llvm::PPCRegisterInfo
Definition: PPCRegisterInfo.h:57
llvm::PPCII::PPC970_Shift
@ PPC970_Shift
PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that an instruction is issued to...
Definition: PPCInstrInfo.h:47
llvm::PPCInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: PPCInstrInfo.cpp:1975
llvm::PPCInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: PPCInstrInfo.cpp:2898
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::PPCInstrInfo::fixupIsDeadOrKill
void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI, unsigned RegNo) const
Fixup killed/dead flag for register RegNo between instructions [StartMI, EndMI].
Definition: PPCInstrInfo.cpp:3386
llvm::PPCInstrInfo::isZExt32To64
bool isZExt32To64(unsigned Opcode) const
Definition: PPCInstrInfo.h:304
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:105
llvm::PPCInstrInfo::replaceInstrOperandWithImm
void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, int64_t Imm) const
Definition: PPCInstrInfo.cpp:3172
PPCRegisterInfo.h
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::PPCInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: PPCInstrInfo.cpp:3009
llvm::PPCInstrInfo::isProfitableToUnpredicate
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: PPCInstrInfo.h:607
llvm::SOK_SpillToVSR
@ SOK_SpillToVSR
Definition: PPCInstrInfo.h:129
llvm::SOK_PairedVecSpill
@ SOK_PairedVecSpill
Definition: PPCInstrInfo.h:130
llvm::PPCInstrInfo::isPrefixed
bool isPrefixed(unsigned Opcode) const
Definition: PPCInstrInfo.h:298
llvm::ImmInstrInfo::OpNoForForwarding
uint64_t OpNoForForwarding
Definition: PPCInstrInfo.h:96
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::LoadImmediateInfo::SetCR
unsigned SetCR
Definition: PPCInstrInfo.h:114
llvm::PPCII::ZExt32To64
@ ZExt32To64
This instruction produced a zero extended result.
Definition: PPCInstrInfo.h:74
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::PPCII::PPC970_VALU
@ PPC970_VALU
Definition: PPCInstrInfo.h:58
llvm::PPCInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
Definition: PPCInstrInfo.h:427
llvm::PPCInstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const override
Definition: PPCInstrInfo.cpp:2385
llvm::PPCInstrInfo::isVFRegister
static bool isVFRegister(unsigned Reg)
Definition: PPCInstrInfo.h:689
llvm::PPCInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: PPCInstrInfo.cpp:1689
llvm::PPCInstrInfo::isAssociativeAndCommutative
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Definition: PPCInstrInfo.cpp:253
llvm::PPCInstrInfo::getDefMIPostRA
MachineInstr * getDefMIPostRA(unsigned Reg, MachineInstr &MI, bool &SeenIntermediateUse) const
Definition: PPCInstrInfo.cpp:3226
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SOK_VRVectorSpill
@ SOK_VRVectorSpill
Definition: PPCInstrInfo.h:125
llvm::PPCInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: PPCInstrInfo.cpp:2053
llvm::PPCInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
Definition: PPCInstrInfo.cpp:2355
llvm::PPCInstrInfo
Definition: PPCInstrInfo.h:195
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:462
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::PPCInstrInfo::isADDInstrEligibleForFolding
bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const
Definition: PPCInstrInfo.cpp:3619
llvm::PPCII::PPC970_FPU
@ PPC970_FPU
Definition: PPCInstrInfo.h:56
llvm::PPCII::NewDef_Shift
@ NewDef_Shift
Shift count to bypass PPC970 flags.
Definition: PPCInstrInfo.h:65
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
TargetInstrInfo.h
llvm::PPCInstrInfo::getStoreOpcodeForSpill
unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const
Definition: PPCInstrInfo.cpp:1922
llvm::ImmInstrInfo::ZeroIsSpecialNew
uint64_t ZeroIsSpecialNew
Definition: PPCInstrInfo.h:92
llvm::SOK_PairedG8Spill
@ SOK_PairedG8Spill
Definition: PPCInstrInfo.h:134
llvm::PPCInstrInfo::getExtendResourceLenLimit
int getExtendResourceLenLimit() const override
On PowerPC, we try to reassociate FMA chain which will increase instruction size.
Definition: PPCInstrInfo.h:493
llvm::LoadImmediateInfo::Is64Bit
unsigned Is64Bit
Definition: PPCInstrInfo.h:113
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::PPCInstrInfo::isBDNZ
bool isBDNZ(unsigned Opcode) const
Check Opcode is BDNZ (Decrement CTR and branch if it is still nonzero).
Definition: PPCInstrInfo.cpp:5436
llvm::PPCInstrInfo::setSpecialOperandAttr
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
Definition: PPCInstrInfo.cpp:222
llvm::PPCInstrInfo::getInstrLatency
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Definition: PPCInstrInfo.cpp:137
llvm::PPCInstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: PPCInstrInfo.cpp:1577
llvm::SOK_LastOpcodeSpill
@ SOK_LastOpcodeSpill
Definition: PPCInstrInfo.h:135
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::PPCInstrInfo::onlyFoldImmediate
bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg) const
Definition: PPCInstrInfo.cpp:2066
llvm::PPCInstrInfo::CreateTargetPostRAHazardRecognizer
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
Definition: PPCInstrInfo.cpp:117
llvm::PPCInstrInfo::shouldClusterMemOps
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
Returns true if the two given memory operations should be scheduled adjacent.
Definition: PPCInstrInfo.cpp:2821
llvm::ImmInstrInfo::IsSummingOperands
uint64_t IsSummingOperands
Definition: PPCInstrInfo.h:106
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::PPCInstrInfo::materializeImmPostRA
void materializeImmPostRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, int64_t Imm) const
Definition: PPCInstrInfo.cpp:3243
llvm::PPCInstrInfo::replaceInstrWithLI
void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const
Definition: PPCInstrInfo.cpp:3203
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::LoadImmediateInfo
Definition: PPCInstrInfo.h:111
llvm::SOK_Float8Spill
@ SOK_Float8Spill
Definition: PPCInstrInfo.h:121
llvm::PPCInstrInfo::isCoalescableExtInstr
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
Definition: PPCInstrInfo.cpp:1055
llvm::PPCInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: PPCInstrInfo.cpp:2035
llvm::PPCInstrInfo::isNoTOCCallInstr
bool isNoTOCCallInstr(unsigned Opcode) const
Check if Opcode corresponds to a call instruction that should be marked with the NOTOC relocation.
Definition: PPCInstrInfo.h:310
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::PPCII::PPC970_VPERM
@ PPC970_VPERM
Definition: PPCInstrInfo.h:59
llvm::PPCInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
Definition: PPCInstrInfo.cpp:2879
llvm::PPCII::PPC970_Mask
@ PPC970_Mask
Definition: PPCInstrInfo.h:48
llvm::SOK_SPESpill
@ SOK_SPESpill
Definition: PPCInstrInfo.h:133
llvm::PPCInstrInfo::insertNoop
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Definition: PPCInstrInfo.cpp:1245
llvm::ImmInstrInfo::SignedImm
uint64_t SignedImm
Definition: PPCInstrInfo.h:84
llvm::PPCII::PPC970_First
@ PPC970_First
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
Definition: PPCInstrInfo.h:35
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
llvm::PPCInstrInfo::isXFormMemOp
bool isXFormMemOp(unsigned Opcode) const
Definition: PPCInstrInfo.h:295
llvm::PPCInstrInfo::shouldReduceRegisterPressure
bool shouldReduceRegisterPressure(MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const override
On PowerPC, we leverage machine combiner pass to reduce register pressure when the register pressure ...
Definition: PPCInstrInfo.cpp:614
llvm::PPCII::XFormMemOp
@ XFormMemOp
This instruction is an X-Form memory operation.
Definition: PPCInstrInfo.h:68
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::PPCInstrInfo::getNop
MCInst getNop() const override
Return the noop instruction to use for a noop.
Definition: PPCInstrInfo.cpp:1265
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
LoadOpcodesForSpill
#define LoadOpcodesForSpill
Definition: PPCInstrInfo.h:191
llvm::PPCInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
Definition: PPCInstrInfo.cpp:2133
llvm::PPCInstrInfo::isImmInstrEligibleForFolding
bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, unsigned &XFormOpcode, int64_t &OffsetOfImmInstr, ImmInstrInfo &III) const
Definition: PPCInstrInfo.cpp:3626
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::SOK_UAccumulatorSpill
@ SOK_UAccumulatorSpill
Definition: PPCInstrInfo.h:132
llvm::SOK_Int4Spill
@ SOK_Int4Spill
Definition: PPCInstrInfo.h:119
llvm::PPCInstrInfo::updatedRC
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
Definition: PPCInstrInfo.cpp:5127
llvm::PPCInstrInfo::findLoopInstr
MachineInstr * findLoopInstr(MachineBasicBlock &PreHeader, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
Definition: PPCInstrInfo.cpp:5530
llvm::LoadImmediateInfo::Imm
unsigned Imm
Definition: PPCInstrInfo.h:112
llvm::PPCInstrInfo::PredicateInstruction
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Definition: PPCInstrInfo.cpp:2185
llvm::PPCII::SExt32To64
@ SExt32To64
This instruction produced a sign extended result.
Definition: PPCInstrInfo.h:72
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::PPCInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: PPCInstrInfo.cpp:1229
llvm::PPCInstrInfo::analyzeLoopForPipelining
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
Definition: PPCInstrInfo.cpp:5510
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::PPCInstrInfo::isADDIInstrEligibleForFolding
bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const
Definition: PPCInstrInfo.cpp:3602
llvm::PPCInstrInfo::genAlternativeCodeSequence
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: PPCInstrInfo.cpp:775
llvm::SOK_CRSpill
@ SOK_CRSpill
Definition: PPCInstrInfo.h:123
llvm::PPCInstrInfo::ClobbersPredicate
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
Definition: PPCInstrInfo.cpp:2320
llvm::PPCInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: PPCInstrInfo.cpp:2174
llvm::PPCInstrInfo::isSameClassPhysRegCopy
static bool isSameClassPhysRegCopy(unsigned Opcode)
Definition: PPCInstrInfo.h:401
llvm::SOK_VectorFloat8Spill
@ SOK_VectorFloat8Spill
Definition: PPCInstrInfo.h:127
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::PPCII::PPC970_CRU
@ PPC970_CRU
Definition: PPCInstrInfo.h:57
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::PPCInstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: PPCInstrInfo.cpp:1534
uint64_t
llvm::PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Definition: PPCInstrInfo.cpp:2919
llvm::PPCInstrInfo::isReallyTriviallyReMaterializable
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
Definition: PPCInstrInfo.cpp:1090
llvm::ImmInstrInfo
Definition: PPCInstrInfo.h:82
llvm::ImmInstrInfo::IsCommutative
uint64_t IsCommutative
Definition: PPCInstrInfo.h:94
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ImmInstrInfo::TruncateImmTo
uint64_t TruncateImmTo
Definition: PPCInstrInfo.h:104
llvm::PPCInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
Definition: PPCInstrInfo.cpp:167
llvm::SpillOpcodeKey
SpillOpcodeKey
Definition: PPCInstrInfo.h:118
llvm::SOK_Int8Spill
@ SOK_Int8Spill
Definition: PPCInstrInfo.h:120
llvm::PPCInstrInfo::hasLowDefLatency
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
Definition: PPCInstrInfo.h:434
llvm::PPCInstrInfo::useMachineCombiner
bool useMachineCombiner() const override
Definition: PPCInstrInfo.h:443
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:29
llvm::PPCInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: PPCInstrInfo.cpp:1070
llvm::SOK_VectorFloat4Spill
@ SOK_VectorFloat4Spill
Definition: PPCInstrInfo.h:128
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::PPCInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: PPCInstrInfo.cpp:1274
llvm::PPCInstrInfo::getFMAPatterns
bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for a fma chain ending in Root.
Definition: PPCInstrInfo.cpp:368
llvm::SOK_AccumulatorSpill
@ SOK_AccumulatorSpill
Definition: PPCInstrInfo.h:131
llvm::PPCInstrInfo::SubsumesPredicate
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Definition: PPCInstrInfo.cpp:2289
llvm::PPCInstrInfo::loadRegFromStackSlotNoUpd
void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Definition: PPCInstrInfo.cpp:2010
llvm::ImmInstrInfo::ZeroIsSpecialOrig
uint64_t ZeroIsSpecialOrig
Definition: PPCInstrInfo.h:89
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ScheduleDAG
Definition: ScheduleDAG.h:554
llvm::PPCII::Prefixed
@ Prefixed
This instruction is prefixed.
Definition: PPCInstrInfo.h:70
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::PPCInstrInfo::convertToImmediateForm
bool convertToImmediateForm(MachineInstr &MI, MachineInstr **KilledDef=nullptr) const
Definition: PPCInstrInfo.cpp:3714
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::PPCInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Definition: PPCInstrInfo.cpp:2163
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::PPCInstrInfo::instrHasImmForm
bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, bool PostRA) const
Definition: PPCInstrInfo.cpp:3903
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::PPCInstrInfo::isSExt32To64
bool isSExt32To64(unsigned Opcode) const
Definition: PPCInstrInfo.h:301
llvm::PPCInstrInfo::isTOCSaveMI
bool isTOCSaveMI(const MachineInstr &MI) const
Definition: PPCInstrInfo.cpp:5246
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::ImmInstrInfo::ImmMustBeMultipleOf
uint64_t ImmMustBeMultipleOf
Definition: PPCInstrInfo.h:86
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::PPCII::PPC970_Cracked
@ PPC970_Cracked
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
Definition: PPCInstrInfo.h:43
PPCGenInstrInfo
llvm::PPCInstrInfo::getRegisterInfo
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:293
llvm::PPCInstrInfo::getRegNumForOperand
static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, unsigned OpNo)
getRegNumForOperand - some operands use different numbering schemes for the same registers.
Definition: PPCInstrInfo.h:773
uint16_t
llvm::PPCInstrInfo::combineRLWINM
bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase=nullptr) const
Definition: PPCInstrInfo.cpp:3766
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::PPCInstrInfo::isSignOrZeroExtended
std::pair< bool, bool > isSignOrZeroExtended(const unsigned Reg, const unsigned BinOpDepth, const MachineRegisterInfo *MRI) const
Definition: PPCInstrInfo.cpp:5268
llvm::PPCInstrInfo::getMachineCombinerPatterns
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
Definition: PPCInstrInfo.cpp:760
llvm::PPCInstrInfo::areMemAccessesTriviallyDisjoint
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
Return true if two MIs access different memory addresses and false otherwise.
Definition: PPCInstrInfo.cpp:5568
llvm::PPCII::PPC970_FXU
@ PPC970_FXU
Definition: PPCInstrInfo.h:54
llvm::PPCISD::BCTRL_RM
@ BCTRL_RM
Definition: PPCISelLowering.h:208
llvm::PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: PPCInstrInfo.cpp:2904
llvm::PPCInstrInfo::getLoadOpcodeForSpill
unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const
Definition: PPCInstrInfo.cpp:1928
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
StoreOpcodesForSpill
#define StoreOpcodesForSpill
Definition: PPCInstrInfo.h:189
llvm::PPCInstrInfo::getRecordFormOpcode
static int getRecordFormOpcode(unsigned Opcode)
Definition: PPCInstrInfo.cpp:5133
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::PPCII::PPC970_Single
@ PPC970_Single
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
Definition: PPCInstrInfo.h:39
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::PPCInstrInfo::isValidToBeChangedReg
bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, MachineInstr *&ADDIMI, int64_t &OffsetAddi, int64_t OffsetImm) const
Definition: PPCInstrInfo.cpp:3669
llvm::SOK_Float4Spill
@ SOK_Float4Spill
Definition: PPCInstrInfo.h:122
llvm::PPCInstrInfo::getMemOperandWithOffsetWidth
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
Return true if get the base operand, byte offset of an instruction and the memory width.
Definition: PPCInstrInfo.cpp:5545
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:106
llvm::PPCInstrInfo::isZeroExtended
bool isZeroExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const
Definition: PPCInstrInfo.h:711
llvm::PPCInstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Get the base operand and byte offset of an instruction that reads/writes memory.
Definition: PPCInstrInfo.cpp:2770
llvm::PPCInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
Definition: PPCInstrInfo.cpp:1145
llvm::PPCInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: PPCInstrInfo.cpp:1481
llvm::SOK_VSXVectorSpill
@ SOK_VSXVectorSpill
Definition: PPCInstrInfo.h:126
llvm::SmallVectorImpl< MachineInstr * >
llvm::PPCISD::BCTRL
@ BCTRL
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
Definition: PPCISelLowering.h:196
llvm::PPCInstrInfo::expandVSXMemPseudo
bool expandVSXMemPseudo(MachineInstr &MI) const
Definition: PPCInstrInfo.cpp:2943
llvm::PPCII::PPC970_LSU
@ PPC970_LSU
Definition: PPCInstrInfo.h:55
llvm::PPCII::PPC970_BRU
@ PPC970_BRU
Definition: PPCInstrInfo.h:60
llvm::PPCInstrInfo::CreateTargetHazardRecognizer
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
Definition: PPCInstrInfo.cpp:100
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SOK_CRBitSpill
@ SOK_CRBitSpill
Definition: PPCInstrInfo.h:124
llvm::PPCInstrInfo::foldFrameOffset
bool foldFrameOffset(MachineInstr &MI) const
Definition: PPCInstrInfo.cpp:3505
llvm::PPCInstrInfo::storeRegToStackSlotNoUpd
void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Definition: PPCInstrInfo.cpp:1955
llvm::PPCInstrInfo::isProfitableToDupForIfCvt
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:602
llvm::PPCInstrInfo::isProfitableToIfCvt
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:590
llvm::PPCInstrInfo::PPCInstrInfo
PPCInstrInfo(PPCSubtarget &STI)
Definition: PPCInstrInfo.cpp:91
llvm::PPCInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: PPCInstrInfo.cpp:1449
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::PPCInstrInfo::isSignExtended
bool isSignExtended(const unsigned Reg, const MachineRegisterInfo *MRI) const
Definition: PPCInstrInfo.h:705
llvm::ImmInstrInfo::ImmOpcode
uint64_t ImmOpcode
Definition: PPCInstrInfo.h:100
llvm::ImmInstrInfo::ImmOpNo
uint64_t ImmOpNo
Definition: PPCInstrInfo.h:98
llvm::PPCInstrInfo::finalizeInsInstrs
void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
Fixup the placeholders we put in genAlternativeCodeSequence() for MachineCombiner.
Definition: PPCInstrInfo.cpp:544
llvm::ImmInstrInfo::ImmWidth
uint64_t ImmWidth
Definition: PPCInstrInfo.h:102
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::PPCII::PPC970_Pseudo
@ PPC970_Pseudo
These are the various PPC970 execution unit pipelines.
Definition: PPCInstrInfo.h:53
llvm::PPCInstrInfo::isVRRegister
static bool isVRRegister(unsigned Reg)
Definition: PPCInstrInfo.h:692
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20