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TargetSubtargetInfo.h
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1 //===- llvm/CodeGen/TargetSubtargetInfo.h - Target Information --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the subtarget options of a Target machine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H
14 #define LLVM_CODEGEN_TARGETSUBTARGETINFO_H
15 
16 #include "llvm/ADT/APInt.h"
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
24 #include "llvm/Support/CodeGen.h"
25 #include <memory>
26 #include <vector>
27 
28 
29 namespace llvm {
30 
31 class CallLowering;
32 class InstrItineraryData;
33 struct InstrStage;
34 class InstructionSelector;
35 class LegalizerInfo;
36 class MachineInstr;
37 struct MachineSchedPolicy;
38 struct MCReadAdvanceEntry;
39 struct MCWriteLatencyEntry;
40 struct MCWriteProcResEntry;
41 class RegisterBankInfo;
42 class SDep;
43 class SelectionDAGTargetInfo;
44 struct SubtargetFeatureKV;
45 struct SubtargetSubTypeKV;
46 struct SubtargetInfoKV;
47 class SUnit;
48 class TargetFrameLowering;
49 class TargetInstrInfo;
50 class TargetLowering;
51 class TargetRegisterClass;
52 class TargetRegisterInfo;
53 class TargetSchedModel;
54 class Triple;
55 
56 //===----------------------------------------------------------------------===//
57 ///
58 /// TargetSubtargetInfo - Generic base class for all target subtargets. All
59 /// Target-specific options that control code generation and printing should
60 /// be exposed through a TargetSubtargetInfo-derived class.
61 ///
63 protected: // Can only create subclasses...
67  const MCWriteProcResEntry *WPR,
68  const MCWriteLatencyEntry *WL,
69  const MCReadAdvanceEntry *RA, const InstrStage *IS,
70  const unsigned *OC, const unsigned *FP);
71 
72 public:
73  // AntiDepBreakMode - Type of anti-dependence breaking that should
74  // be performed before post-RA scheduling.
75  using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };
77 
78  TargetSubtargetInfo() = delete;
79  TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
81  ~TargetSubtargetInfo() override;
82 
83  virtual bool isXRaySupported() const { return false; }
84 
85  // Interfaces to the major aspects of target machine information:
86  //
87  // -- Instruction opcode and operand information
88  // -- Pipelines and scheduling information
89  // -- Stack frame information
90  // -- Selection DAG lowering information
91  // -- Call lowering information
92  //
93  // N.B. These objects may change during compilation. It's not safe to cache
94  // them between functions.
95  virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
96  virtual const TargetFrameLowering *getFrameLowering() const {
97  return nullptr;
98  }
99  virtual const TargetLowering *getTargetLowering() const { return nullptr; }
101  return nullptr;
102  }
103  virtual const CallLowering *getCallLowering() const { return nullptr; }
104 
105  // FIXME: This lets targets specialize the selector by subtarget (which lets
106  // us do things like a dedicated avx512 selector). However, we might want
107  // to also specialize selectors by MachineFunction, which would let us be
108  // aware of optsize/optnone and such.
110  return nullptr;
111  }
112 
113  /// Target can subclass this hook to select a different DAG scheduler.
116  return nullptr;
117  }
118 
119  virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; }
120 
121  /// getRegisterInfo - If register information is available, return it. If
122  /// not, return null.
123  virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
124 
125  /// If the information for the register banks is available, return it.
126  /// Otherwise return nullptr.
127  virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; }
128 
129  /// getInstrItineraryData - Returns instruction itinerary data for the target
130  /// or specific subtarget.
131  virtual const InstrItineraryData *getInstrItineraryData() const {
132  return nullptr;
133  }
134 
135  /// Resolve a SchedClass at runtime, where SchedClass identifies an
136  /// MCSchedClassDesc with the isVariant property. This may return the ID of
137  /// another variant SchedClass, but repeated invocation must quickly terminate
138  /// in a nonvariant SchedClass.
139  virtual unsigned resolveSchedClass(unsigned SchedClass,
140  const MachineInstr *MI,
141  const TargetSchedModel *SchedModel) const {
142  return 0;
143  }
144 
145  /// Returns true if MI is a dependency breaking zero-idiom instruction for the
146  /// subtarget.
147  ///
148  /// This function also sets bits in Mask related to input operands that
149  /// are not in a data dependency relationship. There is one bit for each
150  /// machine operand; implicit operands follow explicit operands in the bit
151  /// representation used for Mask. An empty (i.e. a mask with all bits
152  /// cleared) means: data dependencies are "broken" for all the explicit input
153  /// machine operands of MI.
154  virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
155  return false;
156  }
157 
158  /// Returns true if MI is a dependency breaking instruction for the subtarget.
159  ///
160  /// Similar in behavior to `isZeroIdiom`. However, it knows how to identify
161  /// all dependency breaking instructions (i.e. not just zero-idioms).
162  ///
163  /// As for `isZeroIdiom`, this method returns a mask of "broken" dependencies.
164  /// (See method `isZeroIdiom` for a detailed description of Mask).
165  virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
166  return isZeroIdiom(MI, Mask);
167  }
168 
169  /// Returns true if MI is a candidate for move elimination.
170  ///
171  /// A candidate for move elimination may be optimized out at register renaming
172  /// stage. Subtargets can specify the set of optimizable moves by
173  /// instantiating tablegen class `IsOptimizableRegisterMove` (see
174  /// llvm/Target/TargetInstrPredicate.td).
175  ///
176  /// SubtargetEmitter is responsible for processing all the definitions of class
177  /// IsOptimizableRegisterMove, and auto-generate an override for this method.
178  virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const {
179  return false;
180  }
181 
182  /// True if the subtarget should run MachineScheduler after aggressive
183  /// coalescing.
184  ///
185  /// This currently replaces the SelectionDAG scheduler with the "source" order
186  /// scheduler (though see below for an option to turn this off and use the
187  /// TargetLowering preference). It does not yet disable the postRA scheduler.
188  virtual bool enableMachineScheduler() const;
189 
190  /// True if the machine scheduler should disable the TLI preference
191  /// for preRA scheduling with the source level scheduler.
192  virtual bool enableMachineSchedDefaultSched() const { return true; }
193 
194  /// True if the subtarget should run MachinePipeliner
195  virtual bool enableMachinePipeliner() const { return true; };
196 
197  /// True if the subtarget should enable joining global copies.
198  ///
199  /// By default this is enabled if the machine scheduler is enabled, but
200  /// can be overridden.
201  virtual bool enableJoinGlobalCopies() const;
202 
203  /// True if the subtarget should run a scheduler after register allocation.
204  ///
205  /// By default this queries the PostRAScheduling bit in the scheduling model
206  /// which is the preferred way to influence this.
207  virtual bool enablePostRAScheduler() const;
208 
209  /// True if the subtarget should run the atomic expansion pass.
210  virtual bool enableAtomicExpand() const;
211 
212  /// True if the subtarget should run the indirectbr expansion pass.
213  virtual bool enableIndirectBrExpand() const;
214 
215  /// Override generic scheduling policy within a region.
216  ///
217  /// This is a convenient way for targets that don't provide any custom
218  /// scheduling heuristics (no custom MachineSchedStrategy) to make
219  /// changes to the generic scheduling policy.
221  unsigned NumRegionInstrs) const {}
222 
223  // Perform target specific adjustments to the latency of a schedule
224  // dependency.
225  virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
226 
227  // For use with PostRAScheduling: get the anti-dependence breaking that should
228  // be performed before post-RA scheduling.
229  virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
230 
231  // For use with PostRAScheduling: in CriticalPathRCs, return any register
232  // classes that should only be considered for anti-dependence breaking if they
233  // are on the critical path.
234  virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
235  return CriticalPathRCs.clear();
236  }
237 
238  // Provide an ordered list of schedule DAG mutations for the post-RA
239  // scheduler.
240  virtual void getPostRAMutations(
241  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
242  }
243 
244  // Provide an ordered list of schedule DAG mutations for the machine
245  // pipeliner.
246  virtual void getSMSMutations(
247  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
248  }
249 
250  /// Default to DFA for resource management, return false when target will use
251  /// ProcResource in InstrSchedModel instead.
252  virtual bool useDFAforSMS() const { return true; }
253 
254  // For use with PostRAScheduling: get the minimum optimization level needed
255  // to enable post-RA scheduling.
257  return CodeGenOpt::Default;
258  }
259 
260  /// True if the subtarget should run the local reassignment
261  /// heuristic of the register allocator.
262  /// This heuristic may be compile time intensive, \p OptLevel provides
263  /// a finer grain to tune the register allocator.
264  virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
265 
266  /// True if the subtarget should consider the cost of local intervals
267  /// created by a split candidate when choosing the best split candidate. This
268  /// heuristic may be compile time intensive.
269  virtual bool enableAdvancedRASplitCost() const;
270 
271  /// Enable use of alias analysis during code generation (during MI
272  /// scheduling, DAGCombine, etc.).
273  virtual bool useAA() const;
274 
275  /// \brief Sink addresses into blocks using GEP instructions rather than
276  /// pointer casts and arithmetic.
277  virtual bool addrSinkUsingGEPs() const {
278  return useAA();
279  }
280 
281  /// Enable the use of the early if conversion pass.
282  virtual bool enableEarlyIfConversion() const { return false; }
283 
284  /// Return PBQPConstraint(s) for the target.
285  ///
286  /// Override to provide custom PBQP constraints.
287  virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
288  return nullptr;
289  }
290 
291  /// Enable tracking of subregister liveness in register allocator.
292  /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where
293  /// possible.
294  virtual bool enableSubRegLiveness() const { return false; }
295 
296  /// This is called after a .mir file was loaded.
297  virtual void mirFileLoaded(MachineFunction &MF) const;
298 
299  /// True if the register allocator should use the allocation orders exactly as
300  /// written in the tablegen descriptions, false if it should allocate
301  /// the specified physical register later if is it callee-saved.
303  unsigned PhysReg) const {
304  return false;
305  }
306 };
307 
308 } // end namespace llvm
309 
310 #endif // LLVM_CODEGEN_TARGETSUBTARGETINFO_H
virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const
virtual bool enableMachinePipeliner() const
True if the subtarget should run MachinePipeliner.
virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const
Returns true if MI is a candidate for move elimination.
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetLowering * getTargetLowering() const
virtual bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const
True if the register allocator should use the allocation orders exactly as written in the tablegen de...
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const
virtual bool isXRaySupported() const
virtual bool enableEarlyIfConversion() const
Enable the use of the early if conversion pass.
SI optimize exec mask operations pre RA
virtual std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const
Return PBQPConstraint(s) for the target.
virtual bool useDFAforSMS() const
Default to DFA for resource management, return false when target will use ProcResource in InstrSchedM...
Holds all the information related to register banks.
Provide an instruction scheduling machine model to CodeGen passes.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
virtual bool enableMachineSchedDefaultSched() const
True if the machine scheduler should disable the TLI preference for preRA scheduling with the source ...
ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOpt::Level) FunctionPassCtor
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual AntiDepBreakMode getAntiDepBreakMode() const
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const
Override generic scheduling policy within a region.
virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const
Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Itinerary data supplied by a subtarget to be used by a target.
virtual const TargetInstrInfo * getInstrInfo() const
virtual void mirFileLoaded(MachineFunction &MF) const
This is called after a .mir file was loaded.
virtual bool addrSinkUsingGEPs() const
Sink addresses into blocks using GEP instructions rather than pointer casts and arithmetic.
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
TargetInstrInfo - Interface to description of machine instruction set.
Scheduling dependency.
Definition: ScheduleDAG.h:49
virtual bool enableSubRegLiveness() const
Enable tracking of subregister liveness in register allocator.
virtual const LegalizerInfo * getLegalizerInfo() const
Move duplicate certain instructions close to their use
Definition: Localizer.cpp:27
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:64
virtual void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
virtual bool enableIndirectBrExpand() const
True if the subtarget should run the indirectbr expansion pass.
virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const
Returns true if MI is a dependency breaking instruction for the subtarget.
enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode
virtual InstructionSelector * getInstructionSelector() const
virtual const CallLowering * getCallLowering() const
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:78
Information about stack frame layout on the target.
Class for arbitrary precision integers.
Definition: APInt.h:69
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)
Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:95
TargetSubtargetInfo - Generic base class for all target subtargets.
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don&#39;t provide their own MachineSchedStrategy.
Representation of each machine instruction.
Definition: MachineInstr.h:64
virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator...
These values represent a non-pipelined step in the execution of an instruction.
TargetSubtargetInfo & operator=(const TargetSubtargetInfo &)=delete
virtual void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
virtual const TargetFrameLowering * getFrameLowering() const
Generic base class for all target subtargets.
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
virtual bool enableAdvancedRASplitCost() const
True if the subtarget should consider the cost of local intervals created by a split candidate when c...
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const
virtual RegisterScheduler::FunctionPassCtor getDAGScheduler(CodeGenOpt::Level) const
Target can subclass this hook to select a different DAG scheduler.
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242