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13 #ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H
14 #define LLVM_CODEGEN_TARGETSUBTARGETINFO_H
30 class MachineFunction;
31 class ScheduleDAGMutation;
34 class InlineAsmLowering;
35 class InstrItineraryData;
37 class InstructionSelector;
40 struct MachineSchedPolicy;
41 struct MCReadAdvanceEntry;
42 struct MCWriteLatencyEntry;
43 struct MCWriteProcResEntry;
44 class RegisterBankInfo;
46 class SelectionDAGTargetInfo;
48 class TargetFrameLowering;
49 class TargetInstrInfo;
51 class TargetRegisterClass;
52 class TargetRegisterInfo;
53 class TargetSchedModel;
70 const unsigned *
OC,
const unsigned *
FP);
229 unsigned NumRegionInstrs)
const {}
247 return CriticalPathRCs.
clear();
253 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
const {
259 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
const {
280 virtual bool useAA()
const;
310 unsigned PhysReg)
const {
317 virtual unsigned char
325 #endif // LLVM_CODEGEN_TARGETSUBTARGETINFO_H
This is an optimization pass for GlobalISel generic memory operations.
Information about stack frame layout on the target.
enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
virtual const TargetInstrInfo * getInstrInfo() const
virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator.
Triple - Helper class for working with autoconf configuration names.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool enableSubRegLiveness() const
Enable tracking of subregister liveness in register allocator.
virtual void mirFileLoaded(MachineFunction &MF) const
This is called after a .mir file was loaded.
virtual bool enableMachineSchedDefaultSched() const
True if the machine scheduler should disable the TLI preference for preRA scheduling with the source ...
virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
virtual bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const
True if the register allocator should use the allocation orders exactly as written in the tablegen de...
virtual InstructionSelector * getInstructionSelector() const
virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
TargetInstrInfo - Interface to description of machine instruction set.
virtual bool isXRaySupported() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const
~TargetSubtargetInfo() override
ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOpt::Level) FunctionPassCtor
Holds all the information related to register banks.
Provides the logic to select generic machine instructions.
virtual bool enableIndirectBrExpand() const
True if the subtarget should run the indirectbr expansion pass.
Provide an instruction scheduling machine model to CodeGen passes.
Representation of each machine instruction.
virtual bool enablePostRAMachineScheduler() const
True if the subtarget should run a machine scheduler after register allocation.
virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const
Returns true if MI is a candidate for move elimination.
Specify the latency in cpu cycles for a particular scheduling class and def index.
virtual bool useDFAforSMS() const
Default to DFA for resource management, return false when target will use ProcResource in InstrSchedM...
virtual bool enableEarlyIfConversion() const
Enable the use of the early if conversion pass.
virtual unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const
Classify a global function reference.
virtual RegisterScheduler::FunctionPassCtor getDAGScheduler(CodeGenOpt::Level) const
Target can subclass this hook to select a different DAG scheduler.
virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const
Override generic scheduling policy within a region.
SI optimize exec mask operations pre RA
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
Class for arbitrary precision integers.
virtual const CallLowering * getCallLowering() const
virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const
Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
StringRef - Represent a constant reference to a string, i.e.
virtual bool enableMachinePipeliner() const
True if the subtarget should run MachinePipeliner.
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const
Return PBQPConstraint(s) for the target.
These values represent a non-pipelined step in the execution of an instruction.
virtual const LegalizerInfo * getLegalizerInfo() const
virtual const TargetFrameLowering * getFrameLowering() const
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
TargetSubtargetInfo()=delete
virtual const InlineAsmLowering * getInlineAsmLowering() const
virtual void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const
Returns true if MI is a dependency breaking instruction for the subtarget.
virtual void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
virtual bool addrSinkUsingGEPs() const
Sink addresses into blocks using GEP instructions rather than pointer casts and arithmetic.
virtual const TargetLowering * getTargetLowering() const
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
virtual void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
TargetSubtargetInfo & operator=(const TargetSubtargetInfo &)=delete
Scheduling unit. This is a node in the scheduling DAG.
Level
Code generation optimization level.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Generic base class for all target subtargets.
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
Itinerary data supplied by a subtarget to be used by a target.
virtual AntiDepBreakMode getAntiDepBreakMode() const
A Use represents the edge between a Value definition and its users.
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.