14#ifndef LLVM_MC_MCSCHEDULE_H
15#define LLVM_MC_MCSCHEDULE_H
31class InstrItineraryData;
125#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
341 "No extra information available for this model");
377 const MCInst &Inst)
const;
383 const MCInstOrMachineInstr &Inst,
385 ResolveVariantSchedClass =
391 const MCSchedClassDesc &SCDesc);
398 const MCInst &Inst)
const;
403 unsigned WriteResourceIdx = 0);
417 const MCInstOrMachineInstr &Inst,
419 ResolveVariantSchedClass)
const {
420 static const int NoInformationAvailable = -1;
430 return NoInformationAvailable;
436 unsigned SCClass =
Desc.getSchedClass();
440 for (
unsigned Idx = 0, IdxEnd = Inst.getNumOperands();
Idx != IdxEnd; ++
Idx)
449 SCDesc = ResolveVariantSchedClass(SCDesc);
451 if (!SCDesc || !SCDesc->
isValid())
452 return NoInformationAvailable;
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Itinerary data supplied by a subtarget to be used by a target.
std::optional< unsigned > getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Generic base class for all target subtargets.
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
An efficient, type-erasing, non-owning reference to a callable.
This is an optimization pass for GlobalISel generic memory operations.
ArrayRef(const T &OneElt) -> ArrayRef< T >
Description of the encoding of one expression Op.
An itinerary represents the scheduling information for an instruction.
Define a kind of processor resource that will be modeled by the scheduler.
bool operator==(const MCProcResourceDesc &Other) const
const unsigned * SubUnitsIdxBegin
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
bool operator==(const MCReadAdvanceEntry &Other) const
Specify the cost of a register definition in terms of number of physical register allocated at regist...
bool AllowMoveElimination
A register file descriptor.
uint16_t NumRegisterCostEntries
bool AllowZeroMoveEliminationOnly
uint16_t RegisterCostEntryIdx
uint16_t MaxMovesEliminatedPerCycle
Summarize the scheduling resources required for an instruction of a particular scheduling class.
static const unsigned short InvalidNumMicroOps
uint16_t NumWriteLatencyEntries
uint16_t NumReadAdvanceEntries
uint16_t NumWriteProcResEntries
static const unsigned short VariantNumMicroOps
Machine model for scheduling, bundling, and heuristics.
static const MCSchedModel Default
Returns the default initialized model.
bool isOutOfOrder() const
Return true if machine supports out of order execution.
bool hasExtraProcessorInfo() const
static unsigned getForwardingDelayCycles(ArrayRef< MCReadAdvanceEntry > Entries, unsigned WriteResourceIdx=0)
Returns the maximum forwarding delay for register reads dependent on writes of scheduling class Write...
static const unsigned DefaultLoopMicroOpBufferSize
const InstrItinerary * InstrItineraries
static const unsigned DefaultHighLatency
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
unsigned getProcessorID() const
const MCExtraProcessorInfo & getExtraProcessorInfo() const
unsigned getNumProcResourceKinds() const
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
static const unsigned DefaultLoadLatency
unsigned LoopMicroOpBufferSize
static int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Returns the latency value for the scheduling class.
static const unsigned DefaultMicroOpBufferSize
friend class InstrItineraryData
const MCSchedClassDesc * SchedClassTable
const MCProcResourceDesc * ProcResourceTable
static const unsigned DefaultMispredictPenalty
unsigned MicroOpBufferSize
const MCExtraProcessorInfo * ExtraProcessorInfo
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
static double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
static const unsigned DefaultIssueWidth
unsigned NumProcResourceKinds
bool isComplete() const
Return true if this machine model data for all instructions with a scheduling class (itinerary class ...
unsigned MispredictPenalty
Specify the latency in cpu cycles for a particular scheduling class and def index.
bool operator==(const MCWriteLatencyEntry &Other) const
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
bool operator==(const MCWriteProcResEntry &Other) const
uint16_t AcquireAtCycle
Cycle at which the resource will be aquired by an instruction, relatively to the cycle in which the i...
uint16_t ReleaseAtCycle
Cycle at which the resource will be released by an instruction, relatively to the cycle in which the ...