LLVM 20.0.0git
MCSchedule.h
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1//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the classes used to describe a subtarget's machine model
10// for scheduling and other instruction cost heuristics.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_MC_MCSCHEDULE_H
15#define LLVM_MC_MCSCHEDULE_H
16
17#include "llvm/ADT/StringRef.h"
18#include "llvm/MC/MCInstrDesc.h"
20#include <cassert>
21#include <optional>
22
23namespace llvm {
24
25template <typename T> class ArrayRef;
26struct InstrItinerary;
27class MCSubtargetInfo;
28class MCInstrInfo;
29class MCInst;
30class MCInstrDesc;
31class InstrItineraryData;
32
33/// Define a kind of processor resource that will be modeled by the scheduler.
35 const char *Name;
36 unsigned NumUnits; // Number of resource of this kind
37 unsigned SuperIdx; // Index of the resources kind that contains this kind.
38
39 // Number of resources that may be buffered.
40 //
41 // Buffered resources (BufferSize != 0) may be consumed at some indeterminate
42 // cycle after dispatch. This should be used for out-of-order cpus when
43 // instructions that use this resource can be buffered in a reservaton
44 // station.
45 //
46 // Unbuffered resources (BufferSize == 0) always consume their resource some
47 // fixed number of cycles after dispatch. If a resource is unbuffered, then
48 // the scheduler will avoid scheduling instructions with conflicting resources
49 // in the same cycle. This is for in-order cpus, or the in-order portion of
50 // an out-of-order cpus.
52
53 // If the resource has sub-units, a pointer to the first element of an array
54 // of `NumUnits` elements containing the ProcResourceIdx of the sub units.
55 // nullptr if the resource does not have sub-units.
56 const unsigned *SubUnitsIdxBegin;
57
58 bool operator==(const MCProcResourceDesc &Other) const {
59 return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx
60 && BufferSize == Other.BufferSize;
61 }
62};
63
64/// Identify one of the processor resource kinds consumed by a
65/// particular scheduling class for the specified number of cycles.
68 /// Cycle at which the resource will be released by an instruction,
69 /// relatively to the cycle in which the instruction is issued
70 /// (assuming no stalls inbetween).
72 /// Cycle at which the resource will be aquired by an instruction,
73 /// relatively to the cycle in which the instruction is issued
74 /// (assuming no stalls inbetween).
76
78 return ProcResourceIdx == Other.ProcResourceIdx &&
79 ReleaseAtCycle == Other.ReleaseAtCycle &&
80 AcquireAtCycle == Other.AcquireAtCycle;
81 }
82};
83
84/// Specify the latency in cpu cycles for a particular scheduling class and def
85/// index. -1 indicates an invalid latency. Heuristics would typically consider
86/// an instruction with invalid latency to have infinite latency. Also identify
87/// the WriteResources of this def. When the operand expands to a sequence of
88/// writes, this ID is the last write in the sequence.
90 int16_t Cycles;
92
94 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
95 }
96};
97
98/// Specify the number of cycles allowed after instruction issue before a
99/// particular use operand reads its registers. This effectively reduces the
100/// write's latency. Here we allow negative cycles for corner cases where
101/// latency increases. This rule only applies when the entry's WriteResource
102/// matches the write's WriteResource.
103///
104/// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
105/// WriteResourceIdx.
107 unsigned UseIdx;
110
112 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
113 && Cycles == Other.Cycles;
114 }
115};
116
117/// Summarize the scheduling resources required for an instruction of a
118/// particular scheduling class.
119///
120/// Defined as an aggregate struct for creating tables with initializer lists.
122 static const unsigned short InvalidNumMicroOps = (1U << 13) - 1;
123 static const unsigned short VariantNumMicroOps = InvalidNumMicroOps - 1;
124
125#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
126 const char* Name;
127#endif
132 uint16_t WriteProcResIdx; // First index into WriteProcResTable.
134 uint16_t WriteLatencyIdx; // First index into WriteLatencyTable.
136 uint16_t ReadAdvanceIdx; // First index into ReadAdvanceTable.
138
139 bool isValid() const {
141 }
142 bool isVariant() const {
144 }
145};
146
147/// Specify the cost of a register definition in terms of number of physical
148/// register allocated at register renaming stage. For example, AMD Jaguar.
149/// natively supports 128-bit data types, and operations on 256-bit registers
150/// (i.e. YMM registers) are internally split into two COPs (complex operations)
151/// and each COP updates a physical register. Basically, on Jaguar, a YMM
152/// register write effectively consumes two physical registers. That means,
153/// the cost of a YMM write in the BtVer2 model is 2.
156 unsigned Cost;
158};
159
160/// A register file descriptor.
161///
162/// This struct allows to describe processor register files. In particular, it
163/// helps describing the size of the register file, as well as the cost of
164/// allocating a register file at register renaming stage.
165/// FIXME: this struct can be extended to provide information about the number
166/// of read/write ports to the register file. A value of zero for field
167/// 'NumPhysRegs' means: this register file has an unbounded number of physical
168/// registers.
170 const char *Name;
173 // Index of the first cost entry in MCExtraProcessorInfo::RegisterCostTable.
175 // A value of zero means: there is no limit in the number of moves that can be
176 // eliminated every cycle.
178 // Ture if this register file only knows how to optimize register moves from
179 // known zero registers.
181};
182
183/// Provide extra details about the machine processor.
184///
185/// This is a collection of "optional" processor information that is not
186/// normally used by the LLVM machine schedulers, but that can be consumed by
187/// external tools like llvm-mca to improve the quality of the peformance
188/// analysis.
190 // Actual size of the reorder buffer in hardware.
192 // Number of instructions retired per cycle.
198 unsigned LoadQueueID;
199 unsigned StoreQueueID;
200};
201
202/// Machine model for scheduling, bundling, and heuristics.
203///
204/// The machine model directly provides basic information about the
205/// microarchitecture to the scheduler in the form of properties. It also
206/// optionally refers to scheduler resource tables and itinerary
207/// tables. Scheduler resource tables model the latency and cost for each
208/// instruction type. Itinerary tables are an independent mechanism that
209/// provides a detailed reservation table describing each cycle of instruction
210/// execution. Subtargets may define any or all of the above categories of data
211/// depending on the type of CPU and selected scheduler.
212///
213/// The machine independent properties defined here are used by the scheduler as
214/// an abstract machine model. A real micro-architecture has a number of
215/// buffers, queues, and stages. Declaring that a given machine-independent
216/// abstract property corresponds to a specific physical property across all
217/// subtargets can't be done. Nonetheless, the abstract model is
218/// useful. Futhermore, subtargets typically extend this model with processor
219/// specific resources to model any hardware features that can be exploited by
220/// scheduling heuristics and aren't sufficiently represented in the abstract.
221///
222/// The abstract pipeline is built around the notion of an "issue point". This
223/// is merely a reference point for counting machine cycles. The physical
224/// machine will have pipeline stages that delay execution. The scheduler does
225/// not model those delays because they are irrelevant as long as they are
226/// consistent. Inaccuracies arise when instructions have different execution
227/// delays relative to each other, in addition to their intrinsic latency. Those
228/// special cases can be handled by TableGen constructs such as, ReadAdvance,
229/// which reduces latency when reading data, and ReleaseAtCycles, which consumes
230/// a processor resource when writing data for a number of abstract
231/// cycles.
232///
233/// TODO: One tool currently missing is the ability to add a delay to
234/// ReleaseAtCycles. That would be easy to add and would likely cover all cases
235/// currently handled by the legacy itinerary tables.
236///
237/// A note on out-of-order execution and, more generally, instruction
238/// buffers. Part of the CPU pipeline is always in-order. The issue point, which
239/// is the point of reference for counting cycles, only makes sense as an
240/// in-order part of the pipeline. Other parts of the pipeline are sometimes
241/// falling behind and sometimes catching up. It's only interesting to model
242/// those other, decoupled parts of the pipeline if they may be predictably
243/// resource constrained in a way that the scheduler can exploit.
244///
245/// The LLVM machine model distinguishes between in-order constraints and
246/// out-of-order constraints so that the target's scheduling strategy can apply
247/// appropriate heuristics. For a well-balanced CPU pipeline, out-of-order
248/// resources would not typically be treated as a hard scheduling
249/// constraint. For example, in the GenericScheduler, a delay caused by limited
250/// out-of-order resources is not directly reflected in the number of cycles
251/// that the scheduler sees between issuing an instruction and its dependent
252/// instructions. In other words, out-of-order resources don't directly increase
253/// the latency between pairs of instructions. However, they can still be used
254/// to detect potential bottlenecks across a sequence of instructions and bias
255/// the scheduling heuristics appropriately.
257 // IssueWidth is the maximum number of instructions that may be scheduled in
258 // the same per-cycle group. This is meant to be a hard in-order constraint
259 // (a.k.a. "hazard"). In the GenericScheduler strategy, no more than
260 // IssueWidth micro-ops can ever be scheduled in a particular cycle.
261 //
262 // In practice, IssueWidth is useful to model any bottleneck between the
263 // decoder (after micro-op expansion) and the out-of-order reservation
264 // stations or the decoder bandwidth itself. If the total number of
265 // reservation stations is also a bottleneck, or if any other pipeline stage
266 // has a bandwidth limitation, then that can be naturally modeled by adding an
267 // out-of-order processor resource.
268 unsigned IssueWidth;
269 static const unsigned DefaultIssueWidth = 1;
270
271 // MicroOpBufferSize is the number of micro-ops that the processor may buffer
272 // for out-of-order execution.
273 //
274 // "0" means operations that are not ready in this cycle are not considered
275 // for scheduling (they go in the pending queue). Latency is paramount. This
276 // may be more efficient if many instructions are pending in a schedule.
277 //
278 // "1" means all instructions are considered for scheduling regardless of
279 // whether they are ready in this cycle. Latency still causes issue stalls,
280 // but we balance those stalls against other heuristics.
281 //
282 // "> 1" means the processor is out-of-order. This is a machine independent
283 // estimate of highly machine specific characteristics such as the register
284 // renaming pool and reorder buffer.
286 static const unsigned DefaultMicroOpBufferSize = 0;
287
288 // LoopMicroOpBufferSize is the number of micro-ops that the processor may
289 // buffer for optimized loop execution. More generally, this represents the
290 // optimal number of micro-ops in a loop body. A loop may be partially
291 // unrolled to bring the count of micro-ops in the loop body closer to this
292 // number.
294 static const unsigned DefaultLoopMicroOpBufferSize = 0;
295
296 // LoadLatency is the expected latency of load instructions.
297 unsigned LoadLatency;
298 static const unsigned DefaultLoadLatency = 4;
299
300 // HighLatency is the expected latency of "very high latency" operations.
301 // See TargetInstrInfo::isHighLatencyDef().
302 // By default, this is set to an arbitrarily high number of cycles
303 // likely to have some impact on scheduling heuristics.
304 unsigned HighLatency;
305 static const unsigned DefaultHighLatency = 10;
306
307 // MispredictPenalty is the typical number of extra cycles the processor
308 // takes to recover from a branch misprediction.
310 static const unsigned DefaultMispredictPenalty = 10;
311
312 bool PostRAScheduler; // default value is false
313
315
316 // Tells the MachineScheduler whether or not to track resource usage
317 // using intervals via ResourceSegments (see
318 // llvm/include/llvm/CodeGen/MachineScheduler.h).
320
321 unsigned ProcID;
326 // Instruction itinerary tables used by InstrItineraryData.
327 friend class InstrItineraryData;
329
331
333
334 unsigned getProcessorID() const { return ProcID; }
335
336 /// Does this machine model include instruction-level scheduling.
337 bool hasInstrSchedModel() const { return SchedClassTable; }
338
341 "No extra information available for this model");
342 return *ExtraProcessorInfo;
343 }
344
345 /// Return true if this machine model data for all instructions with a
346 /// scheduling class (itinerary class or SchedRW list).
347 bool isComplete() const { return CompleteModel; }
348
349 /// Return true if machine supports out of order execution.
350 bool isOutOfOrder() const { return MicroOpBufferSize > 1; }
351
352 unsigned getNumProcResourceKinds() const {
354 }
355
356 const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
357 assert(hasInstrSchedModel() && "No scheduling machine model");
358
359 assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");
360 return &ProcResourceTable[ProcResourceIdx];
361 }
362
363 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const {
364 assert(hasInstrSchedModel() && "No scheduling machine model");
365
366 assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx");
367 return &SchedClassTable[SchedClassIdx];
368 }
369
370 /// Returns the latency value for the scheduling class.
371 static int computeInstrLatency(const MCSubtargetInfo &STI,
372 const MCSchedClassDesc &SCDesc);
373
374 int computeInstrLatency(const MCSubtargetInfo &STI, unsigned SClass) const;
375
376 int computeInstrLatency(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
377 const MCInst &Inst) const;
378
379 template <typename MCSubtargetInfo, typename MCInstrInfo,
380 typename InstrItineraryData, typename MCInstOrMachineInstr>
382 const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
383 const MCInstOrMachineInstr &Inst,
385 ResolveVariantSchedClass =
386 [](const MCSchedClassDesc *SCDesc) { return SCDesc; }) const;
387
388 // Returns the reciprocal throughput information from a MCSchedClassDesc.
389 static double
390 getReciprocalThroughput(const MCSubtargetInfo &STI,
391 const MCSchedClassDesc &SCDesc);
392
393 static double
394 getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID);
395
396 double
397 getReciprocalThroughput(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
398 const MCInst &Inst) const;
399
400 /// Returns the maximum forwarding delay for register reads dependent on
401 /// writes of scheduling class WriteResourceIdx.
402 static unsigned getForwardingDelayCycles(ArrayRef<MCReadAdvanceEntry> Entries,
403 unsigned WriteResourceIdx = 0);
404
405 /// Returns the default initialized model.
406 static const MCSchedModel Default;
407};
408
409// The first three are only template'd arguments so we can get away with leaving
410// them as incomplete types below. The third is a template over
411// MCInst/MachineInstr so as to avoid a layering violation here that would make
412// the MC layer depend on CodeGen.
413template <typename MCSubtargetInfo, typename MCInstrInfo,
414 typename InstrItineraryData, typename MCInstOrMachineInstr>
416 const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
417 const MCInstOrMachineInstr &Inst,
419 ResolveVariantSchedClass) const {
420 static const int NoInformationAvailable = -1;
421 // Check if we have a scheduling model for instructions.
422 if (!hasInstrSchedModel()) {
423 // Try to fall back to the itinerary model if the scheduling model doesn't
424 // have a scheduling table. Note the default does not have a table.
425
426 llvm::StringRef CPU = STI.getCPU();
427
428 // Check if we have a CPU to get the itinerary information.
429 if (CPU.empty())
430 return NoInformationAvailable;
431
432 // Get itinerary information.
434 // Get the scheduling class of the requested instruction.
435 const MCInstrDesc &Desc = MCII.get(Inst.getOpcode());
436 unsigned SCClass = Desc.getSchedClass();
437
438 unsigned Latency = 0;
439
440 for (unsigned Idx = 0, IdxEnd = Inst.getNumOperands(); Idx != IdxEnd; ++Idx)
441 if (std::optional<unsigned> OperCycle = IID.getOperandCycle(SCClass, Idx))
442 Latency = std::max(Latency, *OperCycle);
443
444 return int(Latency);
445 }
446
447 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
448 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
449 SCDesc = ResolveVariantSchedClass(SCDesc);
450
451 if (!SCDesc || !SCDesc->isValid())
452 return NoInformationAvailable;
453
454 return MCSchedModel::computeInstrLatency(STI, *SCDesc);
455}
456
457} // namespace llvm
458
459#endif
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Itinerary data supplied by a subtarget to be used by a target.
std::optional< unsigned > getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:185
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:600
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Generic base class for all target subtargets.
StringRef getCPU() const
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:147
An efficient, type-erasing, non-owning reference to a callable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Other
Any other memory.
ArrayRef(const T &OneElt) -> ArrayRef< T >
Description of the encoding of one expression Op.
An itinerary represents the scheduling information for an instruction.
Provide extra details about the machine processor.
Definition: MCSchedule.h:189
const MCRegisterFileDesc * RegisterFiles
Definition: MCSchedule.h:194
const MCRegisterCostEntry * RegisterCostTable
Definition: MCSchedule.h:196
Define a kind of processor resource that will be modeled by the scheduler.
Definition: MCSchedule.h:34
bool operator==(const MCProcResourceDesc &Other) const
Definition: MCSchedule.h:58
const unsigned * SubUnitsIdxBegin
Definition: MCSchedule.h:56
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:106
bool operator==(const MCReadAdvanceEntry &Other) const
Definition: MCSchedule.h:111
Specify the cost of a register definition in terms of number of physical register allocated at regist...
Definition: MCSchedule.h:154
A register file descriptor.
Definition: MCSchedule.h:169
uint16_t NumRegisterCostEntries
Definition: MCSchedule.h:172
uint16_t MaxMovesEliminatedPerCycle
Definition: MCSchedule.h:177
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Definition: MCSchedule.h:121
bool isValid() const
Definition: MCSchedule.h:139
bool isVariant() const
Definition: MCSchedule.h:142
static const unsigned short InvalidNumMicroOps
Definition: MCSchedule.h:122
uint16_t NumWriteLatencyEntries
Definition: MCSchedule.h:135
uint16_t NumReadAdvanceEntries
Definition: MCSchedule.h:137
uint16_t NumWriteProcResEntries
Definition: MCSchedule.h:133
static const unsigned short VariantNumMicroOps
Definition: MCSchedule.h:123
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:256
unsigned LoadLatency
Definition: MCSchedule.h:297
static const MCSchedModel Default
Returns the default initialized model.
Definition: MCSchedule.h:406
bool isOutOfOrder() const
Return true if machine supports out of order execution.
Definition: MCSchedule.h:350
bool hasExtraProcessorInfo() const
Definition: MCSchedule.h:332
unsigned HighLatency
Definition: MCSchedule.h:304
static unsigned getForwardingDelayCycles(ArrayRef< MCReadAdvanceEntry > Entries, unsigned WriteResourceIdx=0)
Returns the maximum forwarding delay for register reads dependent on writes of scheduling class Write...
Definition: MCSchedule.cpp:163
static const unsigned DefaultLoopMicroOpBufferSize
Definition: MCSchedule.h:294
const InstrItinerary * InstrItineraries
Definition: MCSchedule.h:328
static const unsigned DefaultHighLatency
Definition: MCSchedule.h:305
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
Definition: MCSchedule.h:363
unsigned getProcessorID() const
Definition: MCSchedule.h:334
const MCExtraProcessorInfo & getExtraProcessorInfo() const
Definition: MCSchedule.h:339
unsigned getNumProcResourceKinds() const
Definition: MCSchedule.h:352
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
Definition: MCSchedule.h:337
static const unsigned DefaultLoadLatency
Definition: MCSchedule.h:298
unsigned LoopMicroOpBufferSize
Definition: MCSchedule.h:293
static int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Returns the latency value for the scheduling class.
Definition: MCSchedule.cpp:42
static const unsigned DefaultMicroOpBufferSize
Definition: MCSchedule.h:286
friend class InstrItineraryData
Definition: MCSchedule.h:327
const MCSchedClassDesc * SchedClassTable
Definition: MCSchedule.h:323
const MCProcResourceDesc * ProcResourceTable
Definition: MCSchedule.h:322
static const unsigned DefaultMispredictPenalty
Definition: MCSchedule.h:310
unsigned MicroOpBufferSize
Definition: MCSchedule.h:285
unsigned NumSchedClasses
Definition: MCSchedule.h:325
unsigned IssueWidth
Definition: MCSchedule.h:268
const MCExtraProcessorInfo * ExtraProcessorInfo
Definition: MCSchedule.h:330
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
Definition: MCSchedule.h:356
static double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Definition: MCSchedule.cpp:97
static const unsigned DefaultIssueWidth
Definition: MCSchedule.h:269
unsigned NumProcResourceKinds
Definition: MCSchedule.h:324
bool isComplete() const
Return true if this machine model data for all instructions with a scheduling class (itinerary class ...
Definition: MCSchedule.h:347
unsigned MispredictPenalty
Definition: MCSchedule.h:309
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:89
bool operator==(const MCWriteLatencyEntry &Other) const
Definition: MCSchedule.h:93
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:66
bool operator==(const MCWriteProcResEntry &Other) const
Definition: MCSchedule.h:77
uint16_t AcquireAtCycle
Cycle at which the resource will be aquired by an instruction, relatively to the cycle in which the i...
Definition: MCSchedule.h:75
uint16_t ReleaseAtCycle
Cycle at which the resource will be released by an instruction, relatively to the cycle in which the ...
Definition: MCSchedule.h:71