LLVM 17.0.0git
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1//===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9// This file defines the classes used to describe a subtarget's machine model
10// for scheduling and other instruction cost heuristics.
17#include "llvm/Config/llvm-config.h"
19#include <cassert>
21namespace llvm {
23template <typename T> class ArrayRef;
24struct InstrItinerary;
25class MCSubtargetInfo;
26class MCInstrInfo;
27class MCInst;
28class InstrItineraryData;
30/// Define a kind of processor resource that will be modeled by the scheduler.
32 const char *Name;
33 unsigned NumUnits; // Number of resource of this kind
34 unsigned SuperIdx; // Index of the resources kind that contains this kind.
36 // Number of resources that may be buffered.
37 //
38 // Buffered resources (BufferSize != 0) may be consumed at some indeterminate
39 // cycle after dispatch. This should be used for out-of-order cpus when
40 // instructions that use this resource can be buffered in a reservaton
41 // station.
42 //
43 // Unbuffered resources (BufferSize == 0) always consume their resource some
44 // fixed number of cycles after dispatch. If a resource is unbuffered, then
45 // the scheduler will avoid scheduling instructions with conflicting resources
46 // in the same cycle. This is for in-order cpus, or the in-order portion of
47 // an out-of-order cpus.
50 // If the resource has sub-units, a pointer to the first element of an array
51 // of `NumUnits` elements containing the ProcResourceIdx of the sub units.
52 // nullptr if the resource does not have sub-units.
53 const unsigned *SubUnitsIdxBegin;
55 bool operator==(const MCProcResourceDesc &Other) const {
56 return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx
57 && BufferSize == Other.BufferSize;
58 }
61/// Identify one of the processor resource kinds consumed by a particular
62/// scheduling class for the specified number of cycles.
68 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
69 }
72/// Specify the latency in cpu cycles for a particular scheduling class and def
73/// index. -1 indicates an invalid latency. Heuristics would typically consider
74/// an instruction with invalid latency to have infinite latency. Also identify
75/// the WriteResources of this def. When the operand expands to a sequence of
76/// writes, this ID is the last write in the sequence.
78 int16_t Cycles;
82 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
83 }
86/// Specify the number of cycles allowed after instruction issue before a
87/// particular use operand reads its registers. This effectively reduces the
88/// write's latency. Here we allow negative cycles for corner cases where
89/// latency increases. This rule only applies when the entry's WriteResource
90/// matches the write's WriteResource.
92/// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
93/// WriteResourceIdx.
95 unsigned UseIdx;
97 int Cycles;
99 bool operator==(const MCReadAdvanceEntry &Other) const {
100 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
101 && Cycles == Other.Cycles;
102 }
105/// Summarize the scheduling resources required for an instruction of a
106/// particular scheduling class.
108/// Defined as an aggregate struct for creating tables with initializer lists.
110 static const unsigned short InvalidNumMicroOps = (1U << 13) - 1;
111 static const unsigned short VariantNumMicroOps = InvalidNumMicroOps - 1;
113#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
114 const char* Name;
120 uint16_t WriteProcResIdx; // First index into WriteProcResTable.
122 uint16_t WriteLatencyIdx; // First index into WriteLatencyTable.
124 uint16_t ReadAdvanceIdx; // First index into ReadAdvanceTable.
127 bool isValid() const {
129 }
130 bool isVariant() const {
132 }
135/// Specify the cost of a register definition in terms of number of physical
136/// register allocated at register renaming stage. For example, AMD Jaguar.
137/// natively supports 128-bit data types, and operations on 256-bit registers
138/// (i.e. YMM registers) are internally split into two COPs (complex operations)
139/// and each COP updates a physical register. Basically, on Jaguar, a YMM
140/// register write effectively consumes two physical registers. That means,
141/// the cost of a YMM write in the BtVer2 model is 2.
144 unsigned Cost;
148/// A register file descriptor.
150/// This struct allows to describe processor register files. In particular, it
151/// helps describing the size of the register file, as well as the cost of
152/// allocating a register file at register renaming stage.
153/// FIXME: this struct can be extended to provide information about the number
154/// of read/write ports to the register file. A value of zero for field
155/// 'NumPhysRegs' means: this register file has an unbounded number of physical
156/// registers.
158 const char *Name;
161 // Index of the first cost entry in MCExtraProcessorInfo::RegisterCostTable.
163 // A value of zero means: there is no limit in the number of moves that can be
164 // eliminated every cycle.
166 // Ture if this register file only knows how to optimize register moves from
167 // known zero registers.
171/// Provide extra details about the machine processor.
173/// This is a collection of "optional" processor information that is not
174/// normally used by the LLVM machine schedulers, but that can be consumed by
175/// external tools like llvm-mca to improve the quality of the peformance
176/// analysis.
178 // Actual size of the reorder buffer in hardware.
180 // Number of instructions retired per cycle.
186 unsigned LoadQueueID;
187 unsigned StoreQueueID;
190/// Machine model for scheduling, bundling, and heuristics.
192/// The machine model directly provides basic information about the
193/// microarchitecture to the scheduler in the form of properties. It also
194/// optionally refers to scheduler resource tables and itinerary
195/// tables. Scheduler resource tables model the latency and cost for each
196/// instruction type. Itinerary tables are an independent mechanism that
197/// provides a detailed reservation table describing each cycle of instruction
198/// execution. Subtargets may define any or all of the above categories of data
199/// depending on the type of CPU and selected scheduler.
201/// The machine independent properties defined here are used by the scheduler as
202/// an abstract machine model. A real micro-architecture has a number of
203/// buffers, queues, and stages. Declaring that a given machine-independent
204/// abstract property corresponds to a specific physical property across all
205/// subtargets can't be done. Nonetheless, the abstract model is
206/// useful. Futhermore, subtargets typically extend this model with processor
207/// specific resources to model any hardware features that can be exploited by
208/// scheduling heuristics and aren't sufficiently represented in the abstract.
210/// The abstract pipeline is built around the notion of an "issue point". This
211/// is merely a reference point for counting machine cycles. The physical
212/// machine will have pipeline stages that delay execution. The scheduler does
213/// not model those delays because they are irrelevant as long as they are
214/// consistent. Inaccuracies arise when instructions have different execution
215/// delays relative to each other, in addition to their intrinsic latency. Those
216/// special cases can be handled by TableGen constructs such as, ReadAdvance,
217/// which reduces latency when reading data, and ResourceCycles, which consumes
218/// a processor resource when writing data for a number of abstract
219/// cycles.
221/// TODO: One tool currently missing is the ability to add a delay to
222/// ResourceCycles. That would be easy to add and would likely cover all cases
223/// currently handled by the legacy itinerary tables.
225/// A note on out-of-order execution and, more generally, instruction
226/// buffers. Part of the CPU pipeline is always in-order. The issue point, which
227/// is the point of reference for counting cycles, only makes sense as an
228/// in-order part of the pipeline. Other parts of the pipeline are sometimes
229/// falling behind and sometimes catching up. It's only interesting to model
230/// those other, decoupled parts of the pipeline if they may be predictably
231/// resource constrained in a way that the scheduler can exploit.
233/// The LLVM machine model distinguishes between in-order constraints and
234/// out-of-order constraints so that the target's scheduling strategy can apply
235/// appropriate heuristics. For a well-balanced CPU pipeline, out-of-order
236/// resources would not typically be treated as a hard scheduling
237/// constraint. For example, in the GenericScheduler, a delay caused by limited
238/// out-of-order resources is not directly reflected in the number of cycles
239/// that the scheduler sees between issuing an instruction and its dependent
240/// instructions. In other words, out-of-order resources don't directly increase
241/// the latency between pairs of instructions. However, they can still be used
242/// to detect potential bottlenecks across a sequence of instructions and bias
243/// the scheduling heuristics appropriately.
245 // IssueWidth is the maximum number of instructions that may be scheduled in
246 // the same per-cycle group. This is meant to be a hard in-order constraint
247 // (a.k.a. "hazard"). In the GenericScheduler strategy, no more than
248 // IssueWidth micro-ops can ever be scheduled in a particular cycle.
249 //
250 // In practice, IssueWidth is useful to model any bottleneck between the
251 // decoder (after micro-op expansion) and the out-of-order reservation
252 // stations or the decoder bandwidth itself. If the total number of
253 // reservation stations is also a bottleneck, or if any other pipeline stage
254 // has a bandwidth limitation, then that can be naturally modeled by adding an
255 // out-of-order processor resource.
256 unsigned IssueWidth;
257 static const unsigned DefaultIssueWidth = 1;
259 // MicroOpBufferSize is the number of micro-ops that the processor may buffer
260 // for out-of-order execution.
261 //
262 // "0" means operations that are not ready in this cycle are not considered
263 // for scheduling (they go in the pending queue). Latency is paramount. This
264 // may be more efficient if many instructions are pending in a schedule.
265 //
266 // "1" means all instructions are considered for scheduling regardless of
267 // whether they are ready in this cycle. Latency still causes issue stalls,
268 // but we balance those stalls against other heuristics.
269 //
270 // "> 1" means the processor is out-of-order. This is a machine independent
271 // estimate of highly machine specific characteristics such as the register
272 // renaming pool and reorder buffer.
274 static const unsigned DefaultMicroOpBufferSize = 0;
276 // LoopMicroOpBufferSize is the number of micro-ops that the processor may
277 // buffer for optimized loop execution. More generally, this represents the
278 // optimal number of micro-ops in a loop body. A loop may be partially
279 // unrolled to bring the count of micro-ops in the loop body closer to this
280 // number.
282 static const unsigned DefaultLoopMicroOpBufferSize = 0;
284 // LoadLatency is the expected latency of load instructions.
285 unsigned LoadLatency;
286 static const unsigned DefaultLoadLatency = 4;
288 // HighLatency is the expected latency of "very high latency" operations.
289 // See TargetInstrInfo::isHighLatencyDef().
290 // By default, this is set to an arbitrarily high number of cycles
291 // likely to have some impact on scheduling heuristics.
292 unsigned HighLatency;
293 static const unsigned DefaultHighLatency = 10;
295 // MispredictPenalty is the typical number of extra cycles the processor
296 // takes to recover from a branch misprediction.
298 static const unsigned DefaultMispredictPenalty = 10;
300 bool PostRAScheduler; // default value is false
304 unsigned ProcID;
309 // Instruction itinerary tables used by InstrItineraryData.
310 friend class InstrItineraryData;
317 unsigned getProcessorID() const { return ProcID; }
319 /// Does this machine model include instruction-level scheduling.
320 bool hasInstrSchedModel() const { return SchedClassTable; }
324 "No extra information available for this model");
325 return *ExtraProcessorInfo;
326 }
328 /// Return true if this machine model data for all instructions with a
329 /// scheduling class (itinerary class or SchedRW list).
330 bool isComplete() const { return CompleteModel; }
332 /// Return true if machine supports out of order execution.
333 bool isOutOfOrder() const { return MicroOpBufferSize > 1; }
335 unsigned getNumProcResourceKinds() const {
337 }
339 const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
340 assert(hasInstrSchedModel() && "No scheduling machine model");
342 assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");
343 return &ProcResourceTable[ProcResourceIdx];
344 }
346 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const {
347 assert(hasInstrSchedModel() && "No scheduling machine model");
349 assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx");
350 return &SchedClassTable[SchedClassIdx];
351 }
353 /// Returns the latency value for the scheduling class.
354 static int computeInstrLatency(const MCSubtargetInfo &STI,
355 const MCSchedClassDesc &SCDesc);
357 int computeInstrLatency(const MCSubtargetInfo &STI, unsigned SClass) const;
358 int computeInstrLatency(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
359 const MCInst &Inst) const;
361 // Returns the reciprocal throughput information from a MCSchedClassDesc.
362 static double
364 const MCSchedClassDesc &SCDesc);
366 static double
367 getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID);
369 double
371 const MCInst &Inst) const;
373 /// Returns the maximum forwarding delay for register reads dependent on
374 /// writes of scheduling class WriteResourceIdx.
376 unsigned WriteResourceIdx = 0);
378 /// Returns the default initialized model.
379 static const MCSchedModel &GetDefaultSchedModel() { return Default; }
380 static const MCSchedModel Default;
383} // namespace llvm
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Itinerary data supplied by a subtarget to be used by a target.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Generic base class for all target subtargets.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
ArrayRef(const T &OneElt) -> ArrayRef< T >
An itinerary represents the scheduling information for an instruction.
Provide extra details about the machine processor.
Definition: MCSchedule.h:177
const MCRegisterFileDesc * RegisterFiles
Definition: MCSchedule.h:182
const MCRegisterCostEntry * RegisterCostTable
Definition: MCSchedule.h:184
Define a kind of processor resource that will be modeled by the scheduler.
Definition: MCSchedule.h:31
bool operator==(const MCProcResourceDesc &Other) const
Definition: MCSchedule.h:55
const unsigned * SubUnitsIdxBegin
Definition: MCSchedule.h:53
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:94
bool operator==(const MCReadAdvanceEntry &Other) const
Definition: MCSchedule.h:99
Specify the cost of a register definition in terms of number of physical register allocated at regist...
Definition: MCSchedule.h:142
A register file descriptor.
Definition: MCSchedule.h:157
uint16_t NumRegisterCostEntries
Definition: MCSchedule.h:160
uint16_t MaxMovesEliminatedPerCycle
Definition: MCSchedule.h:165
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Definition: MCSchedule.h:109
bool isValid() const
Definition: MCSchedule.h:127
bool isVariant() const
Definition: MCSchedule.h:130
static const unsigned short InvalidNumMicroOps
Definition: MCSchedule.h:110
uint16_t NumWriteLatencyEntries
Definition: MCSchedule.h:123
uint16_t NumReadAdvanceEntries
Definition: MCSchedule.h:125
uint16_t NumWriteProcResEntries
Definition: MCSchedule.h:121
static const unsigned short VariantNumMicroOps
Definition: MCSchedule.h:111
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
unsigned LoadLatency
Definition: MCSchedule.h:285
static const MCSchedModel Default
Definition: MCSchedule.h:380
bool isOutOfOrder() const
Return true if machine supports out of order execution.
Definition: MCSchedule.h:333
bool hasExtraProcessorInfo() const
Definition: MCSchedule.h:315
unsigned HighLatency
Definition: MCSchedule.h:292
static unsigned getForwardingDelayCycles(ArrayRef< MCReadAdvanceEntry > Entries, unsigned WriteResourceIdx=0)
Returns the maximum forwarding delay for register reads dependent on writes of scheduling class Write...
Definition: MCSchedule.cpp:155
static const unsigned DefaultLoopMicroOpBufferSize
Definition: MCSchedule.h:282
static const MCSchedModel & GetDefaultSchedModel()
Returns the default initialized model.
Definition: MCSchedule.h:379
const InstrItinerary * InstrItineraries
Definition: MCSchedule.h:311
static const unsigned DefaultHighLatency
Definition: MCSchedule.h:293
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
Definition: MCSchedule.h:346
unsigned getProcessorID() const
Definition: MCSchedule.h:317
const MCExtraProcessorInfo & getExtraProcessorInfo() const
Definition: MCSchedule.h:322
unsigned getNumProcResourceKinds() const
Definition: MCSchedule.h:335
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
Definition: MCSchedule.h:320
static const unsigned DefaultLoadLatency
Definition: MCSchedule.h:286
unsigned LoopMicroOpBufferSize
Definition: MCSchedule.h:281
static int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Returns the latency value for the scheduling class.
Definition: MCSchedule.cpp:41
static const unsigned DefaultMicroOpBufferSize
Definition: MCSchedule.h:274
const MCSchedClassDesc * SchedClassTable
Definition: MCSchedule.h:306
const MCProcResourceDesc * ProcResourceTable
Definition: MCSchedule.h:305
static const unsigned DefaultMispredictPenalty
Definition: MCSchedule.h:298
unsigned MicroOpBufferSize
Definition: MCSchedule.h:273
unsigned NumSchedClasses
Definition: MCSchedule.h:308
unsigned IssueWidth
Definition: MCSchedule.h:256
const MCExtraProcessorInfo * ExtraProcessorInfo
Definition: MCSchedule.h:313
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
Definition: MCSchedule.h:339
static double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Definition: MCSchedule.cpp:89
static const unsigned DefaultIssueWidth
Definition: MCSchedule.h:257
unsigned NumProcResourceKinds
Definition: MCSchedule.h:307
bool isComplete() const
Return true if this machine model data for all instructions with a scheduling class (itinerary class ...
Definition: MCSchedule.h:330
unsigned MispredictPenalty
Definition: MCSchedule.h:297
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:77
bool operator==(const MCWriteLatencyEntry &Other) const
Definition: MCSchedule.h:81
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:63
bool operator==(const MCWriteProcResEntry &Other) const
Definition: MCSchedule.h:67