Machine model for scheduling, bundling, and heuristics. More...

#include "llvm/MC/MCSchedule.h"

Public Member Functions
bool	hasExtraProcessorInfo () const

unsigned	getProcessorID () const

bool	hasInstrSchedModel () const
	Does this machine model include instruction-level scheduling.

const MCExtraProcessorInfo &	getExtraProcessorInfo () const

bool	isComplete () const
	Return true if this machine model data for all instructions with a scheduling class (itinerary class or SchedRW list).

bool	isOutOfOrder () const
	Return true if machine supports out of order execution.

unsigned	getNumProcResourceKinds () const

const MCProcResourceDesc *	getProcResource (unsigned ProcResourceIdx) const

const MCSchedClassDesc *	getSchedClassDesc (unsigned SchedClassIdx) const

int	computeInstrLatency (const MCSubtargetInfo &STI, unsigned SClass) const

int	computeInstrLatency (const MCSubtargetInfo &STI, const MCInstrInfo &MCII, const MCInst &Inst) const

template<typename MCSubtargetInfo , typename MCInstrInfo , typename InstrItineraryData , typename MCInstOrMachineInstr >
int	computeInstrLatency (const MCSubtargetInfo &STI, const MCInstrInfo &MCII, const MCInstOrMachineInstr &Inst, llvm::function_ref< const MCSchedClassDesc (const MCSchedClassDesc )> ResolveVariantSchedClass=[](const MCSchedClassDesc *SCDesc) { return SCDesc;}) const

double	getReciprocalThroughput (const MCSubtargetInfo &STI, const MCInstrInfo &MCII, const MCInst &Inst) const

Static Public Member Functions
static int	computeInstrLatency (const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
	Returns the latency value for the scheduling class.

static double	getReciprocalThroughput (const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)

static double	getReciprocalThroughput (unsigned SchedClass, const InstrItineraryData &IID)

static unsigned	getForwardingDelayCycles (ArrayRef< MCReadAdvanceEntry > Entries, unsigned WriteResourceIdx=0)
	Returns the maximum forwarding delay for register reads dependent on writes of scheduling class WriteResourceIdx.

Static Public Attributes
static const unsigned	DefaultIssueWidth = 1

static const unsigned	DefaultMicroOpBufferSize = 0

static const unsigned	DefaultLoopMicroOpBufferSize = 0

static const unsigned	DefaultLoadLatency = 4

static const unsigned	DefaultHighLatency = 10

static const unsigned	DefaultMispredictPenalty = 10

static const MCSchedModel	Default
	Returns the default initialized model.

Friends
class	InstrItineraryData

Detailed Description

Machine model for scheduling, bundling, and heuristics.

The machine model directly provides basic information about the microarchitecture to the scheduler in the form of properties. It also optionally refers to scheduler resource tables and itinerary tables. Scheduler resource tables model the latency and cost for each instruction type. Itinerary tables are an independent mechanism that provides a detailed reservation table describing each cycle of instruction execution. Subtargets may define any or all of the above categories of data depending on the type of CPU and selected scheduler.

The machine independent properties defined here are used by the scheduler as an abstract machine model. A real micro-architecture has a number of buffers, queues, and stages. Declaring that a given machine-independent abstract property corresponds to a specific physical property across all subtargets can't be done. Nonetheless, the abstract model is useful. Futhermore, subtargets typically extend this model with processor specific resources to model any hardware features that can be exploited by scheduling heuristics and aren't sufficiently represented in the abstract.

The abstract pipeline is built around the notion of an "issue point". This is merely a reference point for counting machine cycles. The physical machine will have pipeline stages that delay execution. The scheduler does not model those delays because they are irrelevant as long as they are consistent. Inaccuracies arise when instructions have different execution delays relative to each other, in addition to their intrinsic latency. Those special cases can be handled by TableGen constructs such as, ReadAdvance, which reduces latency when reading data, and ReleaseAtCycles, which consumes a processor resource when writing data for a number of abstract cycles.

TODO: One tool currently missing is the ability to add a delay to ReleaseAtCycles. That would be easy to add and would likely cover all cases currently handled by the legacy itinerary tables.

A note on out-of-order execution and, more generally, instruction buffers. Part of the CPU pipeline is always in-order. The issue point, which is the point of reference for counting cycles, only makes sense as an in-order part of the pipeline. Other parts of the pipeline are sometimes falling behind and sometimes catching up. It's only interesting to model those other, decoupled parts of the pipeline if they may be predictably resource constrained in a way that the scheduler can exploit.

The LLVM machine model distinguishes between in-order constraints and out-of-order constraints so that the target's scheduling strategy can apply appropriate heuristics. For a well-balanced CPU pipeline, out-of-order resources would not typically be treated as a hard scheduling constraint. For example, in the GenericScheduler, a delay caused by limited out-of-order resources is not directly reflected in the number of cycles that the scheduler sees between issuing an instruction and its dependent instructions. In other words, out-of-order resources don't directly increase the latency between pairs of instructions. However, they can still be used to detect potential bottlenecks across a sequence of instructions and bias the scheduling heuristics appropriately.

Definition at line 256 of file MCSchedule.h.

Member Function Documentation

◆ computeInstrLatency() [1/4]

int MCSchedModel::computeInstrLatency	(	const MCSubtargetInfo &	STI,
		const MCInstrInfo &	MCII,
		const MCInst &	Inst
	)		const

Definition at line 69 of file MCSchedule.cpp.

References assert(), computeInstrLatency(), getProcessorID(), getSchedClassDesc(), InstrItineraryData, and llvm::MCSubtargetInfo::resolveVariantSchedClass().

◆ computeInstrLatency() [2/4]

template<typename MCSubtargetInfo , typename MCInstrInfo , typename InstrItineraryData , typename MCInstOrMachineInstr >

int llvm::MCSchedModel::computeInstrLatency	(	const MCSubtargetInfo &	STI,
		const MCInstrInfo &	MCII,
		const MCInstOrMachineInstr &	Inst,
		llvm::function_ref< const MCSchedClassDesc (const MCSchedClassDesc )>	ResolveVariantSchedClass = `[](const MCSchedClassDesc *SCDesc) { return SCDesc; }`
	)		const

Definition at line 415 of file MCSchedule.h.

References computeInstrLatency(), llvm::StringRef::empty(), llvm::MCInstrInfo::get(), llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getInstrItineraryForCPU(), llvm::InstrItineraryData::getOperandCycle(), llvm::MCInstrDesc::getSchedClass(), getSchedClassDesc(), hasInstrSchedModel(), Idx, llvm::MCSchedClassDesc::isValid(), and llvm::Latency.

◆ computeInstrLatency() [3/4]

int MCSchedModel::computeInstrLatency	(	const MCSubtargetInfo &	STI,
		const MCSchedClassDesc &	SCDesc
	)

static

Returns the latency value for the scheduling class.

Definition at line 42 of file MCSchedule.cpp.

References llvm::MCWriteLatencyEntry::Cycles, llvm::MCSubtargetInfo::getWriteLatencyEntry(), llvm::Latency, and llvm::MCSchedClassDesc::NumWriteLatencyEntries.

Referenced by computeInstrLatency(), llvm::TargetSchedModel::computeInstrLatency(), llvm::mca::computeMaxLatency(), emitComments(), and emitLatency().

◆ computeInstrLatency() [4/4]

int MCSchedModel::computeInstrLatency	(	const MCSubtargetInfo &	STI,
		unsigned	SClass
	)		const

Definition at line 58 of file MCSchedule.cpp.

References computeInstrLatency(), getSchedClassDesc(), llvm::MCSchedClassDesc::isValid(), llvm::MCSchedClassDesc::isVariant(), and llvm_unreachable.

◆ getExtraProcessorInfo()

const MCExtraProcessorInfo & llvm::MCSchedModel::getExtraProcessorInfo ( ) const

inline

Definition at line 339 of file MCSchedule.h.

References assert(), ExtraProcessorInfo, and hasExtraProcessorInfo().

Referenced by llvm::mca::LSUnitBase::LSUnitBase(), and llvm::mca::RetireControlUnit::RetireControlUnit().

◆ getForwardingDelayCycles()

unsigned MCSchedModel::getForwardingDelayCycles	(	ArrayRef< MCReadAdvanceEntry >	Entries,
		unsigned	WriteResourceIdx = `0`
	)

static

Returns the maximum forwarding delay for register reads dependent on writes of scheduling class WriteResourceIdx.

Definition at line 163 of file MCSchedule.cpp.

◆ getNumProcResourceKinds()

unsigned llvm::MCSchedModel::getNumProcResourceKinds ( ) const

inline

Definition at line 352 of file MCSchedule.h.

References NumProcResourceKinds.

Referenced by llvm::ResourceManager::calculateResMII(), llvm::mca::computeBlockRThroughput(), llvm::mca::computeProcResourceMasks(), llvm::TargetSchedModel::getNumProcResourceKinds(), llvm::TargetSchedModel::init(), llvm::ResourceManager::init(), llvm::mca::initializeUsedResources(), llvm::ResourceManager::initProcResourceVectors(), llvm::mca::InstrBuilder::InstrBuilder(), and llvm::mca::ResourceManager::ResourceManager().

◆ getProcessorID()

unsigned llvm::MCSchedModel::getProcessorID ( ) const

inline

Definition at line 334 of file MCSchedule.h.

References ProcID.

Referenced by computeInstrLatency(), llvm::mca::InstrBuilder::createInstruction(), llvm::TargetSchedModel::getProcessorID(), and getReciprocalThroughput().

◆ getProcResource()

const MCProcResourceDesc * llvm::MCSchedModel::getProcResource ( unsigned ProcResourceIdx ) const

inline

◆ getReciprocalThroughput() [1/3]

double MCSchedModel::getReciprocalThroughput	(	const MCSubtargetInfo &	STI,
		const MCInstrInfo &	MCII,
		const MCInst &	Inst
	)		const

Definition at line 119 of file MCSchedule.cpp.

References llvm::MCInstrInfo::get(), llvm::MCInst::getOpcode(), getProcessorID(), getReciprocalThroughput(), llvm::MCInstrDesc::getSchedClass(), getSchedClassDesc(), IssueWidth, llvm::MCSchedClassDesc::isValid(), llvm::MCSchedClassDesc::isVariant(), llvm_unreachable, and llvm::MCSubtargetInfo::resolveVariantSchedClass().

◆ getReciprocalThroughput() [2/3]

double MCSchedModel::getReciprocalThroughput	(	const MCSubtargetInfo &	STI,
		const MCSchedClassDesc &	SCDesc
	)

static

Definition at line 97 of file MCSchedule.cpp.

References getProcResource(), llvm::MCSubtargetInfo::getSchedModel(), llvm::MCSubtargetInfo::getWriteProcResBegin(), llvm::MCSubtargetInfo::getWriteProcResEnd(), I, IssueWidth, llvm::MCSchedClassDesc::NumMicroOps, and llvm::MCProcResourceDesc::NumUnits.

Referenced by llvm::TargetSchedModel::computeReciprocalThroughput(), and getReciprocalThroughput().

◆ getReciprocalThroughput() [3/3]

double MCSchedModel::getReciprocalThroughput	(	unsigned	SchedClass,
		const InstrItineraryData &	IID
	)

static

Definition at line 143 of file MCSchedule.cpp.

References llvm::InstrItineraryData::beginStage(), DefaultIssueWidth, llvm::InstrItineraryData::endStage(), I, and llvm::popcount().

◆ getSchedClassDesc()

const MCSchedClassDesc * llvm::MCSchedModel::getSchedClassDesc ( unsigned SchedClassIdx ) const

inline

Definition at line 363 of file MCSchedule.h.

References assert(), hasInstrSchedModel(), NumSchedClasses, and SchedClassTable.

Referenced by llvm::mca::RegisterFile::addRegisterRead(), llvm::mca::RegisterFile::checkRAWHazards(), llvm::mca::RegisterFile::collectWrites(), computeInstrLatency(), llvm::TargetSchedModel::computeReciprocalThroughput(), llvm::mca::InstrBuilder::createInstruction(), getReciprocalThroughput(), and llvm::TargetSchedModel::resolveSchedClass().

◆ hasExtraProcessorInfo()

bool llvm::MCSchedModel::hasExtraProcessorInfo ( ) const

inline

Definition at line 332 of file MCSchedule.h.

References ExtraProcessorInfo.

Referenced by getExtraProcessorInfo(), llvm::mca::LSUnitBase::LSUnitBase(), and llvm::mca::RetireControlUnit::RetireControlUnit().

◆ hasInstrSchedModel()

bool llvm::MCSchedModel::hasInstrSchedModel ( ) const

inline

Does this machine model include instruction-level scheduling.

Definition at line 337 of file MCSchedule.h.

References SchedClassTable.

Referenced by computeInstrLatency(), getProcResource(), getSchedClassDesc(), and llvm::TargetSchedModel::hasInstrSchedModel().

◆ isComplete()

bool llvm::MCSchedModel::isComplete ( ) const

inline

Return true if this machine model data for all instructions with a scheduling class (itinerary class or SchedRW list).

Definition at line 347 of file MCSchedule.h.

References CompleteModel.

Referenced by llvm::TargetSchedModel::computeOperandLatency().

◆ isOutOfOrder()

bool llvm::MCSchedModel::isOutOfOrder ( ) const

inline

Return true if machine supports out of order execution.

Definition at line 350 of file MCSchedule.h.

References MicroOpBufferSize.

Referenced by llvm::TargetSchedModel::computeOutputLatency(), llvm::mca::Context::createDefaultPipeline(), and llvm::mca::RetireControlUnit::RetireControlUnit().

Friends And Related Function Documentation

◆ InstrItineraryData

friend class InstrItineraryData

friend

Definition at line 327 of file MCSchedule.h.

Referenced by computeInstrLatency().

Member Data Documentation

◆ CompleteModel

bool llvm::MCSchedModel::CompleteModel

Definition at line 314 of file MCSchedule.h.

Referenced by isComplete().

◆ Default

const MCSchedModel MCSchedModel::Default

static

Initial value:

= {DefaultIssueWidth,
                                            DefaultMicroOpBufferSize,
                                            DefaultLoopMicroOpBufferSize,
                                            DefaultLoadLatency,
                                            DefaultHighLatency,
                                            DefaultMispredictPenalty,
                                            false,
                                            true,
                                            false,
                                            0,
                                            nullptr,
                                            nullptr,
                                            0,
                                            0,
                                            nullptr,
                                            nullptr}

Returns the default initialized model.

Definition at line 406 of file MCSchedule.h.

Referenced by llvm::MCSubtargetInfo::getSchedModelForCPU(), and llvm::MCSubtargetInfo::InitMCProcessorInfo().

◆ DefaultHighLatency

const unsigned llvm::MCSchedModel::DefaultHighLatency = 10

static

Definition at line 305 of file MCSchedule.h.

◆ DefaultIssueWidth

const unsigned llvm::MCSchedModel::DefaultIssueWidth = 1

static

Definition at line 269 of file MCSchedule.h.

Referenced by getReciprocalThroughput().

◆ DefaultLoadLatency

const unsigned llvm::MCSchedModel::DefaultLoadLatency = 4

static

Definition at line 298 of file MCSchedule.h.

◆ DefaultLoopMicroOpBufferSize

const unsigned llvm::MCSchedModel::DefaultLoopMicroOpBufferSize = 0

static

Definition at line 294 of file MCSchedule.h.

◆ DefaultMicroOpBufferSize

const unsigned llvm::MCSchedModel::DefaultMicroOpBufferSize = 0

static

Definition at line 286 of file MCSchedule.h.

◆ DefaultMispredictPenalty

const unsigned llvm::MCSchedModel::DefaultMispredictPenalty = 10

static

Definition at line 310 of file MCSchedule.h.

◆ EnableIntervals

bool llvm::MCSchedModel::EnableIntervals

Definition at line 319 of file MCSchedule.h.

Referenced by llvm::TargetSchedModel::enableIntervals().

◆ ExtraProcessorInfo

const MCExtraProcessorInfo* llvm::MCSchedModel::ExtraProcessorInfo

Definition at line 330 of file MCSchedule.h.

Referenced by getExtraProcessorInfo(), and hasExtraProcessorInfo().

◆ HighLatency

unsigned llvm::MCSchedModel::HighLatency

Definition at line 304 of file MCSchedule.h.

Referenced by llvm::TargetInstrInfo::defaultDefLatency().

◆ InstrItineraries

const InstrItinerary* llvm::MCSchedModel::InstrItineraries

Definition at line 328 of file MCSchedule.h.

Referenced by llvm::HexagonMCInstrInfo::getCVIResources(), llvm::HexagonMCInstrInfo::getOtherReservedSlots(), and llvm::HexagonMCInstrInfo::getUnits().

◆ IssueWidth

unsigned llvm::MCSchedModel::IssueWidth

Definition at line 268 of file MCSchedule.h.

Referenced by llvm::mca::DispatchStage::DispatchStage(), llvm::TargetSchedModel::getIssueWidth(), llvm::mca::InOrderIssueStage::getIssueWidth(), getReciprocalThroughput(), llvm::TargetSchedModel::init(), llvm::ResourcePriorityQueue::reserveResources(), and llvm::ScoreboardHazardRecognizer::ScoreboardHazardRecognizer().

◆ LoadLatency

unsigned llvm::MCSchedModel::LoadLatency

Definition at line 297 of file MCSchedule.h.

Referenced by llvm::TargetInstrInfo::defaultDefLatency().

◆ LoopMicroOpBufferSize

unsigned llvm::MCSchedModel::LoopMicroOpBufferSize

Definition at line 293 of file MCSchedule.h.

◆ MicroOpBufferSize

unsigned llvm::MCSchedModel::MicroOpBufferSize

Definition at line 285 of file MCSchedule.h.

Referenced by llvm::TargetSchedModel::getMicroOpBufferSize(), and isOutOfOrder().

◆ MispredictPenalty

unsigned llvm::MCSchedModel::MispredictPenalty

Definition at line 309 of file MCSchedule.h.

Referenced by llvm::ARMSubtarget::getMispredictionPenalty().

◆ NumProcResourceKinds

unsigned llvm::MCSchedModel::NumProcResourceKinds

Definition at line 324 of file MCSchedule.h.

Referenced by getNumProcResourceKinds(), and getProcResource().

◆ NumSchedClasses

unsigned llvm::MCSchedModel::NumSchedClasses

Definition at line 325 of file MCSchedule.h.

Referenced by getSchedClassDesc().

◆ PostRAScheduler

bool llvm::MCSchedModel::PostRAScheduler

Definition at line 312 of file MCSchedule.h.

Referenced by llvm::TargetSubtargetInfo::enablePostRAScheduler().

◆ ProcID

unsigned llvm::MCSchedModel::ProcID

Definition at line 321 of file MCSchedule.h.

Referenced by getProcessorID().

◆ ProcResourceTable

const MCProcResourceDesc* llvm::MCSchedModel::ProcResourceTable

Definition at line 322 of file MCSchedule.h.

Referenced by getProcResource().

◆ SchedClassTable

const MCSchedClassDesc* llvm::MCSchedModel::SchedClassTable

Definition at line 323 of file MCSchedule.h.

Referenced by getSchedClassDesc(), and hasInstrSchedModel().

The documentation for this struct was generated from the following files:

include/llvm/MC/MCSchedule.h
lib/MC/MCSchedule.cpp

Public Attributes
unsigned	IssueWidth

unsigned	MicroOpBufferSize

unsigned	LoopMicroOpBufferSize

unsigned	LoadLatency

unsigned	HighLatency

unsigned	MispredictPenalty

bool	PostRAScheduler

bool	CompleteModel

bool	EnableIntervals

unsigned	ProcID

const MCProcResourceDesc *	ProcResourceTable

const MCSchedClassDesc *	SchedClassTable

unsigned	NumProcResourceKinds

unsigned	NumSchedClasses

const InstrItinerary *	InstrItineraries

const MCExtraProcessorInfo *	ExtraProcessorInfo

Public Member Functions

Static Public Member Functions

Public Attributes

Static Public Attributes

Friends

Detailed Description

Member Function Documentation

◆ computeInstrLatency() [1/4]

◆ computeInstrLatency() [2/4]

◆ computeInstrLatency() [3/4]

◆ computeInstrLatency() [4/4]

◆ getExtraProcessorInfo()

◆ getForwardingDelayCycles()

◆ getNumProcResourceKinds()

◆ getProcessorID()

◆ getProcResource()

◆ getReciprocalThroughput() [1/3]

◆ getReciprocalThroughput() [2/3]

◆ getReciprocalThroughput() [3/3]

◆ getSchedClassDesc()

◆ hasExtraProcessorInfo()

◆ hasInstrSchedModel()

◆ isComplete()

◆ isOutOfOrder()

Friends And Related Function Documentation

◆ InstrItineraryData

Member Data Documentation

◆ CompleteModel

◆ Default

◆ DefaultHighLatency

◆ DefaultIssueWidth

◆ DefaultLoadLatency

◆ DefaultLoopMicroOpBufferSize

◆ DefaultMicroOpBufferSize

◆ DefaultMispredictPenalty

◆ EnableIntervals

◆ ExtraProcessorInfo

◆ HighLatency

◆ InstrItineraries

◆ IssueWidth

◆ LoadLatency

◆ LoopMicroOpBufferSize

◆ MicroOpBufferSize

◆ MispredictPenalty

◆ NumProcResourceKinds

◆ NumSchedClasses

◆ PostRAScheduler

◆ ProcID

◆ ProcResourceTable

◆ SchedClassTable