Go to the documentation of this file.
36 return Register != Hexagon::NoRegister;
41 : MCII(MCII), BundleCurrent(Inst.
begin() +
43 BundleEnd(Inst.
end()), DuplexCurrent(Inst.
end()), DuplexEnd(Inst.
end()) {}
46 MCInst const &Inst, std::nullptr_t)
47 : MCII(MCII), BundleCurrent(Inst.
end()), BundleEnd(Inst.
end()),
48 DuplexCurrent(Inst.
end()), DuplexEnd(Inst.
end()) {}
51 if (DuplexCurrent != DuplexEnd) {
53 if (DuplexCurrent == DuplexEnd) {
54 DuplexCurrent = BundleEnd;
55 DuplexEnd = BundleEnd;
61 if (BundleCurrent != BundleEnd) {
62 MCInst const &Inst = *BundleCurrent->getInst();
64 DuplexCurrent = Inst.
begin();
65 DuplexEnd = Inst.
end();
72 if (DuplexCurrent != DuplexEnd)
73 return *DuplexCurrent->getInst();
74 return *BundleCurrent->getInst();
78 return BundleCurrent ==
Other.BundleCurrent && BundleEnd ==
Other.BundleEnd &&
79 DuplexCurrent ==
Other.DuplexCurrent && DuplexEnd ==
Other.DuplexEnd;
128 bool CheckOk =
Check ?
Check->check(
false) :
true;
157 Check->reportError(
"invalid instruction packet: out of slots");
175 bool AttemptCompatibility) {
177 if (!AttemptCompatibility || ArchSTI ==
nullptr)
178 return canonicalizePacketImpl(MCII, STI,
Context, MCB,
Check);
184 if (canonicalizePacketImpl(MCII, STI,
Context, MCB, &PerfCheck))
188 return canonicalizePacketImpl(MCII, *ArchSTI,
Context, MCB, &ArchCheck);
211 assert((iClass <= 0xf) &&
"iClass must have range of 0 to 0xf");
213 duplexInst->
setOpcode(Hexagon::DuplexIClass0 + iClass);
261 using namespace Hexagon;
311 const auto &HExpr = cast<HexagonMCExpr>(Expr);
313 return *HExpr.getExpr();
442 unsigned Stage = II[SchedClass].
LastStage - 1;
471 for (
unsigned Stage = II[SchedClass].FirstStage + 1;
472 Stage < II[SchedClass].
LastStage; ++Stage) {
540 auto Result = Hexagon::BUNDLE == MCI.
getOpcode();
552 if (isa<HexagonMCExpr>(MO.
getExpr()) &&
568 if (isa<HexagonMCExpr>(MO.
getExpr()) &&
576 return (MinValue >
Value ||
Value > MaxValue);
612 return ((
Reg >= Hexagon::D0 &&
Reg <= Hexagon::D3) ||
613 (
Reg >= Hexagon::D8 &&
Reg <= Hexagon::D11));
643 return MCI.
getOpcode() == Hexagon::A4_ext;
653 return (
Reg >= Hexagon::R0 &&
Reg <= Hexagon::R31);
657 return ((
Reg >= Hexagon::R0 &&
Reg <= Hexagon::R7) ||
658 (
Reg >= Hexagon::R16 &&
Reg <= Hexagon::R23));
676 MCInst const &MCI,
unsigned short O) {
687 return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) ||
688 (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
692 return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
696 return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31);
699 std::pair<unsigned, unsigned>
702 "VecRegPair must be a vector register pair");
705 const unsigned PairIndex =
706 2 * (IsRev ? VecRegPair - Hexagon::WR0 : VecRegPair - Hexagon::W0);
708 return IsRev ? std::make_pair(PairIndex, PairIndex + 1)
709 : std::make_pair(PairIndex + 1, PairIndex);
716 ? Producer - Hexagon::WR0
717 : Producer - Hexagon::W0;
718 const unsigned ConsumerSingleIndex = (Consumer - Hexagon::V0) >> 1;
720 return ConsumerSingleIndex == ProdPairIndex;
756 auto &PredRegClass =
MRI.
getRegClass(Hexagon::PredRegsRegClassID);
761 MCInst const &Inst,
unsigned I) {
805 case Hexagon::SA1_addi:
806 case Hexagon::SA1_addrx:
807 case Hexagon::SA1_addsp:
808 case Hexagon::SA1_and1:
809 case Hexagon::SA1_clrf:
810 case Hexagon::SA1_clrfnew:
811 case Hexagon::SA1_clrt:
812 case Hexagon::SA1_clrtnew:
813 case Hexagon::SA1_cmpeqi:
814 case Hexagon::SA1_combine0i:
815 case Hexagon::SA1_combine1i:
816 case Hexagon::SA1_combine2i:
817 case Hexagon::SA1_combine3i:
818 case Hexagon::SA1_combinerz:
819 case Hexagon::SA1_combinezr:
820 case Hexagon::SA1_dec:
821 case Hexagon::SA1_inc:
822 case Hexagon::SA1_seti:
823 case Hexagon::SA1_setin1:
824 case Hexagon::SA1_sxtb:
825 case Hexagon::SA1_sxth:
826 case Hexagon::SA1_tfr:
827 case Hexagon::SA1_zxtb:
828 case Hexagon::SA1_zxth:
829 case Hexagon::SL1_loadri_io:
830 case Hexagon::SL1_loadrub_io:
831 case Hexagon::SL2_deallocframe:
832 case Hexagon::SL2_jumpr31:
833 case Hexagon::SL2_jumpr31_f:
834 case Hexagon::SL2_jumpr31_fnew:
835 case Hexagon::SL2_jumpr31_t:
836 case Hexagon::SL2_jumpr31_tnew:
837 case Hexagon::SL2_loadrb_io:
838 case Hexagon::SL2_loadrd_sp:
839 case Hexagon::SL2_loadrh_io:
840 case Hexagon::SL2_loadri_sp:
841 case Hexagon::SL2_loadruh_io:
842 case Hexagon::SL2_return:
843 case Hexagon::SL2_return_f:
844 case Hexagon::SL2_return_fnew:
845 case Hexagon::SL2_return_t:
846 case Hexagon::SL2_return_tnew:
847 case Hexagon::SS1_storeb_io:
848 case Hexagon::SS1_storew_io:
849 case Hexagon::SS2_allocframe:
850 case Hexagon::SS2_storebi0:
851 case Hexagon::SS2_storebi1:
852 case Hexagon::SS2_stored_sp:
853 case Hexagon::SS2_storeh_io:
854 case Hexagon::SS2_storew_sp:
855 case Hexagon::SS2_storewi0:
856 case Hexagon::SS2_storewi1:
917 .
Case(
"hexagonv67t", 3)
923 Nop.setOpcode(Hexagon::A2_nop);
932 return {0, 0,
false};
937 return {0, 0,
false};
950 case Hexagon::V6_vgathermh:
951 case Hexagon::V6_vgathermhq:
952 case Hexagon::V6_vgathermhw:
953 case Hexagon::V6_vgathermhwq:
954 case Hexagon::V6_vgathermw:
955 case Hexagon::V6_vgathermwq:
970 const bool NoSlotReqd = Hexagon::A4_ext == OpCode ||
971 (IsTiny && Hexagon::A2_nop == OpCode) ||
972 (IsTiny && Hexagon::J4_hintjumpr == OpCode);
980 unsigned slotsUsed = 0;
982 MCInst const &MCI = *HMI.getInst();
1002 assert(Duplex !=
nullptr);
1028 unsigned Producer2) {
1032 return (Consumer - Hexagon::V0) & 0x1;
1033 if (Producer2 != Hexagon::NoRegister)
1034 return Consumer == Producer;
StringSwitch & Case(StringLiteral S, T Value)
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
bool mustNotExtend(MCExpr const &Expr)
void setMustExtend(MCExpr const &Expr, bool Val=true)
This is an optimization pass for GlobalISel generic memory operations.
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t minConstant(MCInst const &MCI, size_t Index)
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
static MCOperand createExpr(const MCExpr *Val)
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg)
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
cl::opt< bool > HexagonDisableCompound
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &I)
unsigned getDuplexRegisterNumbering(unsigned Reg)
static MCOperand createImm(int64_t Val)
Context object for machine code objects.
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
LLVM_NODISCARD R Default(T Value)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getCVIResources(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the resources used by this instruction.
bool HexagonMCShuffle(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
const MCInst & operator*() const
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
const_iterator end(StringRef path)
Get end iterator over path.
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
bool isPredicated() const
bool isImmext(MCInst const &MCI)
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
bool isSubInstruction(MCInst const &MCI)
static LLVM_ATTRIBUTE_UNUSED unsigned getMemAccessSizeInBytes(MemAccessSize S)
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
const MCInst * extenderForIndex(MCInst const &MCB, size_t Index)
void setInnerLoop(MCInst &MCI)
Instances of this class represent a single low-level machine instruction.
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
const MCSubtargetInfo * getArchSubtarget(MCSubtargetInfo const *STI)
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of.
void setOpcode(unsigned Op)
bool isMemReorderDisabled(MCInst const &MCI)
bool isDblRegForSubInst(unsigned Reg)
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
An itinerary represents the scheduling information for an instruction.
#define HEXAGON_PRESHUFFLE_PACKET_SIZE
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)
bool s27_2_reloc(MCExpr const &Expr)
bool hasImmExt(MCInst const &MCI)
bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI)
void setMemReorderDisabled(MCInst &MCI)
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
const MCInst * getInst() const
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBundle(MCInst const &MCI)
PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
Describe properties that are true of each instruction in the target description file.
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
const FeatureBitset & getFeatureBits() const
constexpr int64_t memReorderDisabledMask
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI)
bool operator==(PacketIterator const &Other) const
bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI)
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
bool IsVecRegSingle(unsigned VecReg)
bool LoopNeedsPadding(MCInst const &MCB)
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
size_t bundleSize(MCInst const &MCI)
static MCOperand createInst(const MCInst *Val)
void addOperand(const MCOperand Op)
void setInst(const MCInst *Val)
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
bool isIntRegForSubInst(unsigned Reg)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)
Return whether the operand is extendable.
bool mustExtend(MCExpr const &Expr)
MCInst deriveSubInst(MCInst const &Inst)
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
unsigned packetSize(StringRef CPU)
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
bool isCall() const
Return true if the instruction is a call.
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker, bool AttemptCompatibility=false)
@ RestrictNoSlot1StorePos
uint16_t FirstStage
Index of first stage in itinerary.
void setMustNotExtend(bool Val=true)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned HexagonGetLastSlot()
PacketIterator & operator++()
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool IsReverseVecRegPair(unsigned VecReg)
constexpr int64_t outerLoopMask
bool isIntReg(unsigned Reg)
constexpr int64_t innerLoopMask
bool IsVecRegPair(unsigned VecReg)
const MCOperandInfo * OpInfo
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
static bool isBranch(unsigned Opcode)
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
@ RestrictNoSlot1StoreMask
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)
Return the new value or the newly produced value.
bool isOuterLoop(MCInst const &MCI)
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static MCOperand createReg(unsigned Reg)
const InstrStage HexagonStages[]
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
const MCOperand & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
void setS27_2_reloc(bool Val=true)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
void setOuterLoop(MCInst &MCI)
unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI)
bool mustNotExtend() const
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
#define HEXAGON_PACKET_INNER_SIZE
const MCOperand & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
const unsigned TypeCVI_FIRST
Interface to description of machine instruction set.
Check for a valid bundle.
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
const MCExpr * getExpr() const
unsigned getOpcode() const
const MCOperand & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer)
unsigned packetSizeSlots(MCSubtargetInfo const &STI)
const MCInst & instruction(MCInst const &MCB, size_t Index)
#define HEXAGON_PACKET_OUTER_SIZE
bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI)
Return true if the operand is a new-value store insn.
bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI)
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the maximum value of an extendable operand.
constexpr size_t bundleInstructionsOffset
void padEndloop(MCInst &MCI, MCContext &Context)
const MCOperand & getOperand(unsigned i) const
const MCExpr & getExpr(MCExpr const &Expr)
A range adaptor for a pair of iterators.
uint16_t LastStage
Index of last + 1 stage in itinerary.
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the minimum value of an extendable operand.
A switch()-like statement whose cases are string literals.
bool isReturn() const
Return true if the instruction is a return.
Instances of this class represent operands of the MCInst class.
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
const unsigned TypeCVI_LAST
bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I)
#define HEXAGON_PACKET_SIZE
std::pair< unsigned, unsigned > GetVecRegPairIndices(unsigned VecRegPair)
Returns an ordered pair of the constituent register ordinals for each of the elements of VecRegPair.
PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst)
unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
Generic base class for all target subtargets.
const InstrItinerary * InstrItineraries
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
void setMustExtend(bool Val=true)
LLVM Value Representation.
Base class for the full range of assembler expressions which are needed for parsing.
Optional< std::vector< StOtherPiece > > Other
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getReg() const
Returns the register number.
bool isInnerLoop(MCInst const &MCI)