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HexagonMCChecker.h
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1 //===- HexagonMCChecker.h - Instruction bundle checking ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the checking of insns inside a bundle according to the
10 // packet constraint rules of the Hexagon ISA.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCHECKER_H
15 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCHECKER_H
16 
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/Support/SMLoc.h"
22 #include <set>
23 #include <utility>
24 
25 namespace llvm {
26 
27 class MCContext;
28 class MCInst;
29 class MCInstrInfo;
30 class MCRegisterInfo;
31 class MCSubtargetInfo;
32 
33 /// Check for a valid bundle.
35  MCContext &Context;
36  MCInst &MCB;
37  const MCRegisterInfo &RI;
38  MCInstrInfo const &MCII;
39  MCSubtargetInfo const &STI;
40  bool ReportErrors;
41 
42  /// Set of definitions: register #, if predicated, if predicated true.
43  using PredSense = std::pair<unsigned, bool>;
44  static const PredSense Unconditional;
45  using PredSet = std::multiset<PredSense>;
46  using PredSetIterator = std::multiset<PredSense>::iterator;
47 
48  using DefsIterator = DenseMap<unsigned, PredSet>::iterator;
50 
51  /// Set of weak definitions whose clashes should be enforced selectively.
52  using SoftDefsIterator = std::set<unsigned>::iterator;
53  std::set<unsigned> SoftDefs;
54 
55  /// Set of temporary definitions not committed to the register file.
56  using TmpDefsIterator = std::set<unsigned>::iterator;
57  std::set<unsigned> TmpDefs;
58 
59  /// Set of new predicates used.
60  using NewPredsIterator = std::set<unsigned>::iterator;
61  std::set<unsigned> NewPreds;
62 
63  /// Set of predicates defined late.
64  using LatePredsIterator = std::multiset<unsigned>::iterator;
65  std::multiset<unsigned> LatePreds;
66 
67  /// Set of uses.
68  using UsesIterator = std::set<unsigned>::iterator;
69  std::set<unsigned> Uses;
70 
71  /// Pre-defined set of read-only registers.
72  using ReadOnlyIterator = std::set<unsigned>::iterator;
73  std::set<unsigned> ReadOnly;
74 
75  // Contains the vector-pair-registers with the even number
76  // first ("v0:1", e.g.) used/def'd in this packet.
77  std::set<unsigned> ReversePairs;
78 
79  void init();
80  void init(MCInst const &);
81  void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue);
82 
83  bool registerUsed(unsigned Register);
84 
85  /// \return a tuple of: pointer to the producer instruction or nullptr if
86  /// none was found, the operand index, and the PredicateInfo for the
87  /// producer.
88  std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo>
89  registerProducer(unsigned Register,
91 
92  // Checks performed.
93  bool checkBranches();
94  bool checkPredicates();
95  bool checkNewValues();
96  bool checkRegisters();
97  bool checkRegistersReadOnly();
98  void checkRegisterCurDefs();
99  bool checkSolo();
100  bool checkShuffle();
101  bool checkSlots();
102  bool checkAXOK();
103  bool checkHWLoop();
104  bool checkCOFMax1();
105  bool checkLegalVecRegPair();
106  bool checkValidTmpDst();
107  bool checkHVXAccum();
108 
109  static void compoundRegisterMap(unsigned &);
110 
111  bool isLoopRegister(unsigned R) const {
112  return (Hexagon::SA0 == R || Hexagon::LC0 == R || Hexagon::SA1 == R ||
113  Hexagon::LC1 == R);
114  }
115 
116 public:
117  explicit HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII,
118  MCSubtargetInfo const &STI, MCInst &mcb,
119  const MCRegisterInfo &ri, bool ReportErrors = true);
120  explicit HexagonMCChecker(HexagonMCChecker const &Check,
121  MCSubtargetInfo const &STI, bool CopyReportErrors);
122 
123  bool check(bool FullCheck = true);
124  void reportErrorRegisters(unsigned Register);
125  void reportErrorNewValue(unsigned Register);
126  void reportError(SMLoc Loc, Twine const &Msg);
127  void reportNote(SMLoc Loc, Twine const &Msg);
128  void reportError(Twine const &Msg);
129  void reportWarning(Twine const &Msg);
130  void reportBranchErrors();
131 };
132 
133 } // end namespace llvm
134 
135 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCHECKER_H
HexagonMCTargetDesc.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::HexagonMCChecker::reportError
void reportError(SMLoc Loc, Twine const &Msg)
Definition: HexagonMCChecker.cpp:790
DenseMap.h
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::HexagonMCChecker::reportNote
void reportNote(SMLoc Loc, Twine const &Msg)
Definition: HexagonMCChecker.cpp:795
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::HexagonMCInstrInfo::PredicateInfo
Definition: HexagonMCInstrInfo.h:334
llvm::HexagonMCChecker::reportWarning
void reportWarning(Twine const &Msg)
Definition: HexagonMCChecker.cpp:803
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
HexagonMCInstrInfo.h
Check
#define Check(C,...)
Definition: Lint.cpp:170
llvm::HexagonMCChecker::check
bool check(bool FullCheck=true)
Definition: HexagonMCChecker.cpp:220
SMLoc.h
llvm::HexagonMCChecker::reportErrorNewValue
void reportErrorNewValue(unsigned Register)
Definition: HexagonMCChecker.cpp:780
llvm::DenseMap
Definition: DenseMap.h:714
llvm::HexagonMCChecker::reportBranchErrors
void reportBranchErrors()
Definition: HexagonMCChecker.cpp:326
llvm::HexagonMCChecker::HexagonMCChecker
HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &mcb, const MCRegisterInfo &ri, bool ReportErrors=true)
Definition: HexagonMCChecker.cpp:204
llvm::HexagonMCChecker::reportErrorRegisters
void reportErrorRegisters(unsigned Register)
Definition: HexagonMCChecker.cpp:775
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::HexagonMCChecker
Check for a valid bundle.
Definition: HexagonMCChecker.h:34
LC0
into eax xorps xmm0 xmm0 eax xmm0 eax xmm0 ret esp eax movdqa LC0
Definition: README-SSE.txt:632
SmallVector.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:77