LLVM  16.0.0git
HexagonMCInstrInfo.h
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1 //===- HexagonMCInstrInfo.cpp - Utility functions on Hexagon MCInsts ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Utility functions for Hexagon specific MCInst queries
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
14 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
15 
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/iterator.h"
20 #include "llvm/MC/MCInst.h"
22 #include <cstddef>
23 #include <cstdint>
24 
25 namespace llvm {
26 
27 class HexagonMCChecker;
28 class MCContext;
29 class MCExpr;
30 class MCInstrDesc;
31 class MCInstrInfo;
32 class MCRegisterInfo;
33 class MCSubtargetInfo;
34 
36 public:
38 
39  DuplexCandidate(unsigned i, unsigned j, unsigned iClass)
41 };
42 
43 namespace Hexagon {
44 
47  PacketIterator, std::forward_iterator_tag, const MCInst> {
48  MCInstrInfo const &MCII;
49  MCInst::const_iterator BundleCurrent;
50  MCInst::const_iterator BundleEnd;
51  MCInst::const_iterator DuplexCurrent;
52  MCInst::const_iterator DuplexEnd;
53 
54 public:
55  PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
56  PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst, std::nullptr_t);
57 
59  MCInst const &operator*() const;
60  bool operator==(PacketIterator const &Other) const;
61 };
62 
63 } // end namespace Hexagon
64 
65 namespace HexagonMCInstrInfo {
66 
67 constexpr size_t innerLoopOffset = 0;
68 constexpr int64_t innerLoopMask = 1 << innerLoopOffset;
69 
70 constexpr size_t outerLoopOffset = 1;
71 constexpr int64_t outerLoopMask = 1 << outerLoopOffset;
72 
73 // do not reorder memory load/stores by default load/stores are re-ordered
74 // and by default loads can be re-ordered
75 constexpr size_t memReorderDisabledOffset = 2;
77 
78 constexpr size_t splitNoMemOrderOffset = 3;
79 constexpr int64_t splitNoMemorderMask = 1 << splitNoMemOrderOffset;
80 
81 constexpr size_t noShuffleOffset = 4;
82 constexpr int64_t noShuffleMask = 1 << noShuffleOffset;
83 
84 constexpr size_t bundleInstructionsOffset = 1;
85 
87 void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
88  MCInst const &MCI);
89 
90 // Returns a iterator range of instructions in this bundle
92 bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI);
94 
95 // Returns the number of instructions in the bundle
96 size_t bundleSize(MCInst const &MCI);
97 
98 // Put the packet in to canonical form, compound, duplex, pad, and shuffle
99 bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
100  MCContext &Context, MCInst &MCB,
101  HexagonMCChecker *Checker,
102  bool AttemptCompatibility = false);
103 bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
104  MCInst const &I);
105 
106 // Create a duplex instruction given the two subinsts
107 MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0,
108  MCInst const &inst1);
109 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
110  MCOperand const &MO);
111 
112 // Convert this instruction in to a duplex subinst
113 MCInst deriveSubInst(MCInst const &Inst);
114 
115 // Return the extender for instruction at Index or nullptr if none
116 MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
117 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
118  MCInst const &MCI);
119 
120 // Return memory access size in bytes
121 unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI);
122 
123 // Return memory access size
124 unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI);
125 
126 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
127 
128 // Return which duplex group this instruction belongs to
129 unsigned getDuplexCandidateGroup(MCInst const &MI);
130 
131 // Return a list of all possible instruction duplex combinations
133 getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
134  MCInst const &MCB);
135 unsigned getDuplexRegisterNumbering(unsigned Reg);
136 
137 MCExpr const &getExpr(MCExpr const &Expr);
138 
139 // Return the index of the extendable operand
140 unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI);
141 
142 // Return a reference to the extendable operand
143 MCOperand const &getExtendableOperand(MCInstrInfo const &MCII,
144  MCInst const &MCI);
145 
146 // Return the implicit alignment of the extendable operand
147 unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI);
148 
149 // Return the number of logical bits of the extendable operand
150 unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI);
151 
152 // Check if the extendable operand is signed.
153 bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI);
154 
155 // Return the max value that a constant extendable operand can have
156 // without being extended.
157 int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI);
158 
159 // Return the min value that a constant extendable operand can have
160 // without being extended.
161 int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI);
162 
163 // Return instruction name
164 StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI);
165 
166 // Return the operand index for the new value.
167 unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI);
168 
169 // Return the operand that consumes or produces a new value.
170 MCOperand const &getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI);
171 unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI);
172 MCOperand const &getNewValueOperand2(MCInstrInfo const &MCII,
173  MCInst const &MCI);
174 
175 // Return the Hexagon ISA class for the insn.
176 unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI);
177 
178 /// Return the resources used by this instruction
179 unsigned getCVIResources(MCInstrInfo const &MCII,
180  MCSubtargetInfo const &STI,
181  MCInst const &MCI);
182 
183 /// Return the slots used by the insn.
184 unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
185  MCInst const &MCI);
186 unsigned getOtherReservedSlots(MCInstrInfo const &MCII,
187  MCSubtargetInfo const &STI, MCInst const &MCI);
188 bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
189 
190 // Does the packet have an extender for the instruction at Index
191 bool hasExtenderForIndex(MCInst const &MCB, size_t Index);
192 
193 bool hasImmExt(MCInst const &MCI);
194 
195 // Return whether the instruction is a legal new-value producer.
196 bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
197 bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI);
198 bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI);
199 bool hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI);
200 unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb);
201 
202 int64_t minConstant(MCInst const &MCI, size_t Index);
203 template <unsigned N, unsigned S>
204 bool inRange(MCInst const &MCI, size_t Index) {
205  return isShiftedUInt<N, S>(minConstant(MCI, Index));
206 }
207 template <unsigned N, unsigned S>
208 bool inSRange(MCInst const &MCI, size_t Index) {
209  return isShiftedInt<N, S>(minConstant(MCI, Index));
210 }
211 template <unsigned N> bool inRange(MCInst const &MCI, size_t Index) {
212  return isUInt<N>(minConstant(MCI, Index));
213 }
214 
215 // Return the instruction at Index
216 MCInst const &instruction(MCInst const &MCB, size_t Index);
217 bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI);
218 
219 // Returns whether this MCInst is a wellformed bundle
220 bool isBundle(MCInst const &MCI);
221 
222 // Return whether the insn is an actual insn.
223 bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
224 bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI);
225 bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI);
226 bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI);
227 bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI);
228 
229 // Return whether the instruction needs to be constant extended.
230 bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI);
231 bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI);
232 
233 // Is this double register suitable for use in a duplex subinst
234 bool isDblRegForSubInst(unsigned Reg);
235 
236 // Is this a duplex instruction
237 bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
238 
239 // Can these instructions be duplexed
240 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
241 
242 // Can these duplex classes be combine in to a duplex instruction
243 bool isDuplexPairMatch(unsigned Ga, unsigned Gb);
244 
245 // Return true if the insn may be extended based on the operand value.
246 bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI);
247 
248 // Return whether the instruction must be always extended.
249 bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI);
250 
251 /// Return whether it is a floating-point insn.
252 bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI);
253 
254 bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI);
255 
256 // Returns whether this instruction is an immediate extender
257 bool isImmext(MCInst const &MCI);
258 
259 // Returns whether this bundle is an endloop0
260 bool isInnerLoop(MCInst const &MCI);
261 
262 // Is this an integer register
263 bool isIntReg(unsigned Reg);
264 
265 // Is this register suitable for use in a duplex subinst
266 bool isIntRegForSubInst(unsigned Reg);
267 bool isMemReorderDisabled(MCInst const &MCI);
268 
269 // Return whether the insn is a new-value consumer.
270 bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
271 /// Return true if the operand is a new-value store insn.
272 bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI);
273 bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short);
274 
275 // Can these two instructions be duplexed
276 bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
277  bool ExtendedA, MCInst const &MIb, bool ExtendedB,
278  bool bisReversable, MCSubtargetInfo const &STI);
279 
280 // Returns whether this bundle is an endloop1
281 bool isOuterLoop(MCInst const &MCI);
282 
283 // Return whether this instruction is predicated
284 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
285 bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI);
286 bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI);
287 
288 // Return whether the predicate sense is true
289 bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI);
290 
291 // Return true if this is a scalar predicate register.
292 bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg);
293 
294 // Returns true if the Ith operand is a predicate register.
295 bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I);
296 
297 // Return whether the insn is a prefix.
298 bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI);
299 
300 // Return whether the insn is solo, i.e., cannot be in a packet.
301 bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI);
302 
303 /// Return whether the insn can be packaged only with A and X-type insns.
304 bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI);
305 
306 /// Return whether the insn can be packaged only with an A-type insn in slot #1.
307 bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI);
308 bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI);
309 bool isSubInstruction(MCInst const &MCI);
310 bool isVector(MCInstrInfo const &MCII, MCInst const &MCI);
311 bool mustExtend(MCExpr const &Expr);
312 bool mustNotExtend(MCExpr const &Expr);
313 
314 // Returns true if this instruction requires a slot to execute.
315 bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI);
316 
317 
318 // Returns true if \a MCB would require endloop padding.
319 bool LoopNeedsPadding(MCInst const &MCB);
320 
321 unsigned packetSize(StringRef CPU);
322 
323 // Returns the maximum number of slots available in the given
324 // subtarget's packets.
325 unsigned packetSizeSlots(MCSubtargetInfo const &STI);
326 
327 // Returns the number of slots consumed by this packet, considering duplexed
328 // and compound instructions.
329 unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
330  MCInst const &MCI);
331 
332 // Pad the bundle with nops to satisfy endloop requirements.
333 void padEndloop(MCInst &MCI, MCContext &Context);
335 public:
337  PredicateInfo(unsigned Register, unsigned Operand, bool PredicatedTrue)
339  bool isPredicated() const;
340  unsigned Register;
341  unsigned Operand;
343 };
344 PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI);
345 bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI);
346 
347 // Replace the instructions inside MCB, represented by Candidate
348 void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate);
349 
350 bool s27_2_reloc(MCExpr const &Expr);
351 // Marks a bundle as endloop0
352 void setInnerLoop(MCInst &MCI);
353 void setMemReorderDisabled(MCInst &MCI);
354 void setMustExtend(MCExpr const &Expr, bool Val = true);
355 void setMustNotExtend(MCExpr const &Expr, bool Val = true);
356 void setS27_2_reloc(MCExpr const &Expr, bool Val = true);
357 
358 // Marks a bundle as endloop1
359 void setOuterLoop(MCInst &MCI);
360 
361 // Would duplexing this instruction create a requirement to extend
362 bool subInstWouldBeExtended(MCInst const &potentialDuplex);
363 unsigned SubregisterBit(unsigned Consumer, unsigned Producer,
364  unsigned Producer2);
365 
366 bool IsVecRegSingle(unsigned VecReg);
367 bool IsVecRegPair(unsigned VecReg);
368 bool IsReverseVecRegPair(unsigned VecReg);
369 bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer);
370 
371 /// Returns an ordered pair of the constituent register ordinals for
372 /// each of the elements of \a VecRegPair. For example, Hexagon::W0 ("v0:1")
373 /// returns { 0, 1 } and Hexagon::W1 ("v3:2") returns { 3, 2 }.
374 std::pair<unsigned, unsigned> GetVecRegPairIndices(unsigned VecRegPair);
375 
376 // Attempt to find and replace compound pairs
377 void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
378  MCContext &Context, MCInst &MCI);
379 
380 } // end namespace HexagonMCInstrInfo
381 
382 } // end namespace llvm
383 
384 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
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Definition: README.txt:29
llvm::HexagonMCInstrInfo::mustNotExtend
bool mustNotExtend(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:893
llvm::HexagonMCInstrInfo::setMustExtend
void setMustExtend(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:880
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
MathExtras.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::HexagonMCInstrInfo::getDesc
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:255
llvm::DuplexCandidate
Definition: HexagonMCInstrInfo.h:35
llvm::HexagonMCInstrInfo::minConstant
int64_t minConstant(MCInst const &MCI, size_t Index)
Definition: HexagonMCInstrInfo.cpp:866
llvm::HexagonMCInstrInfo::isAccumulator
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
Definition: HexagonMCInstrInfo.cpp:533
llvm::HexagonMCInstrInfo::setMustNotExtend
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:889
llvm::MCInst::const_iterator
SmallVectorImpl< MCOperand >::const_iterator const_iterator
Definition: MCInst.h:213
llvm::HexagonMCInstrInfo::isPredReg
bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:755
llvm::HexagonMCInstrInfo::isRestrictSlot1AOK
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
Definition: HexagonMCInstrInfo.cpp:775
llvm::HexagonMCInstrInfo::IsABranchingInst
bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &I)
Definition: HexagonMCInstrInfo.cpp:1046
llvm::HexagonMCInstrInfo::getDuplexRegisterNumbering
unsigned getDuplexRegisterNumbering(unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:260
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::HexagonMCInstrInfo::subInstWouldBeExtended
bool subInstWouldBeExtended(MCInst const &potentialDuplex)
Definition: HexagonMCDuplexInfo.cpp:535
StringRef.h
llvm::HexagonMCInstrInfo::isCofMax1
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:584
llvm::HexagonMCInstrInfo::hasDuplex
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:484
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::HexagonMCInstrInfo::memReorderDisabledOffset
constexpr size_t memReorderDisabledOffset
Definition: HexagonMCInstrInfo.h:75
llvm::HexagonMCInstrInfo::isCofRelax2
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:595
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::HexagonMCInstrInfo::getCVIResources
unsigned getCVIResources(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the resources used by this instruction.
Definition: HexagonMCInstrInfo.cpp:430
llvm::HexagonMCInstrInfo::isDuplexPair
bool isDuplexPair(MCInst const &MIa, MCInst const &MIb)
Symmetrical. See if these two instructions are fit for duplex pair.
Definition: HexagonMCDuplexInfo.cpp:651
llvm::Hexagon::PacketIterator::operator*
const MCInst & operator*() const
Definition: HexagonMCInstrInfo.cpp:71
llvm::HexagonMCInstrInfo::splitNoMemorderMask
constexpr int64_t splitNoMemorderMask
Definition: HexagonMCInstrInfo.h:79
llvm::HexagonMCInstrInfo::getNewValueOp
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:379
llvm::HexagonMCInstrInfo::inSRange
bool inSRange(MCInst const &MCI, size_t Index)
Definition: HexagonMCInstrInfo.h:208
llvm::HexagonMCInstrInfo::hasTmpDst
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:946
llvm::HexagonMCInstrInfo::getMemAccessSize
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:241
llvm::HexagonMCInstrInfo::getExtentAlignment
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:334
llvm::HexagonMCInstrInfo::addConstExtender
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:87
llvm::HexagonMCInstrInfo::PredicateInfo::PredicateInfo
PredicateInfo(unsigned Register, unsigned Operand, bool PredicatedTrue)
Definition: HexagonMCInstrInfo.h:337
llvm::HexagonMCInstrInfo::hasExtenderForIndex
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:496
llvm::HexagonMCInstrInfo::PredicateInfo::isPredicated
bool isPredicated() const
Definition: HexagonMCInstrInfo.cpp:35
llvm::HexagonMCInstrInfo::isImmext
bool isImmext(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:642
llvm::HexagonMCInstrInfo::extendIfNeeded
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:234
llvm::HexagonMCInstrInfo::isSubInstruction
bool isSubInstruction(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:801
llvm::HexagonMCInstrInfo::extenderForIndex
const MCInst * extenderForIndex(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:222
llvm::HexagonMCInstrInfo::setInnerLoop
void setInnerLoop(MCInst &MCI)
Definition: HexagonMCInstrInfo.cpp:1007
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::HexagonMCInstrInfo::replaceDuplex
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
Definition: HexagonMCInstrInfo.cpp:993
llvm::HexagonMCInstrInfo::prefersSlot3
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:940
llvm::HexagonMCInstrInfo::isCofRelax1
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:589
llvm::HexagonMCInstrInfo::getOtherReservedSlots
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of.
Definition: HexagonMCInstrInfo.cpp:461
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::HexagonMCInstrInfo::PredicateInfo::PredicatedTrue
bool PredicatedTrue
Definition: HexagonMCInstrInfo.h:342
llvm::HexagonMCInstrInfo::isMemReorderDisabled
bool isMemReorderDisabled(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:795
llvm::HexagonMCInstrInfo::innerLoopOffset
constexpr size_t innerLoopOffset
Definition: HexagonMCInstrInfo.h:67
llvm::HexagonMCInstrInfo::isDblRegForSubInst
bool isDblRegForSubInst(unsigned Reg)
Definition: HexagonMCInstrInfo.cpp:611
llvm::HexagonMCInstrInfo::setS27_2_reloc
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
Definition: HexagonMCInstrInfo.cpp:897
llvm::HexagonMCInstrInfo::PredicateInfo
Definition: HexagonMCInstrInfo.h:334
llvm::HexagonMCInstrInfo::isDuplexPairMatch
bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
Definition: HexagonMCDuplexInfo.cpp:89
llvm::HexagonMCInstrInfo::isPredicatedTrue
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:748
llvm::HexagonMCInstrInfo::s27_2_reloc
bool s27_2_reloc(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:902
llvm::HexagonMCInstrInfo::hasImmExt
bool hasImmExt(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:500
llvm::HexagonMCInstrInfo::requiresSlot
bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:966
llvm::HexagonMCInstrInfo::setMemReorderDisabled
void setMemReorderDisabled(MCInst &MCI)
Definition: HexagonMCInstrInfo.cpp:1013
llvm::HexagonMCInstrInfo::hasNewValue2
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
Definition: HexagonMCInstrInfo.cpp:520
llvm::HexagonMCInstrInfo::isNewValue
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
Definition: HexagonMCInstrInfo.cpp:662
llvm::HexagonMCInstrInfo::isPredicated
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:725
llvm::HexagonMCInstrInfo::isVector
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:861
llvm::HexagonMCInstrInfo::isBundle
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Definition: HexagonMCInstrInfo.cpp:539
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Definition: HexagonMCInstrInfo.h:82
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Definition: HexagonMCInstrInfo.cpp:930
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Definition: StackSlotColoring.cpp:141
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Definition: HexagonMCInstrInfo.cpp:374
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Definition: Dwarf.h:472
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Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
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Definition: HexagonMCInstrInfo.cpp:579
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Definition: HexagonMCInstrInfo.cpp:103
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Definition: HexagonMCInstrInfo.h:76
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Definition: HexagonMCInstrInfo.cpp:340
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Definition: HexagonMCInstrInfo.cpp:77
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Definition: HexagonMCInstrInfo.h:37
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Definition: HexagonMCDuplexInfo.cpp:1028
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Definition: HexagonMCInstrInfo.cpp:656
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Definition: HexagonMCInstrInfo.cpp:675
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Definition: HexagonMCInstrInfo.cpp:885
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Definition: HexagonMCDuplexInfo.cpp:696
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Definition: HexagonMCInstrInfo.cpp:769
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Definition: HexagonMCInstrInfo.cpp:915
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Definition: HexagonMCInstrInfo.cpp:606
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Definition: HexagonMCInstrInfo.h:45
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Definition: HexagonMCCompound.cpp:401
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Definition: HexagonMCInstrInfo.cpp:1026
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Definition: HexagonMCInstrInfo.cpp:171
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non-Symmetrical. See if these two instructions are fit for duplex pair.
Definition: HexagonMCDuplexInfo.cpp:572
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constexpr size_t outerLoopOffset
Definition: HexagonMCInstrInfo.h:70
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Definition: HexagonMCInstrInfo.h:37
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#define I(x, y, z)
Definition: MD5.cpp:58
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Definition: iterator.h:80
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Definition: HexagonMCInstrInfo.cpp:616
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Definition: HexagonMCInstrInfo.cpp:50
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Definition: HexagonMCInstrInfo.cpp:191
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Definition: HexagonMCInstrInfo.cpp:691
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Definition: HexagonMCInstrInfo.h:71
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Definition: HexagonMCInstrInfo.cpp:652
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Definition: HexagonMCInstrInfo.h:68
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Definition: HexagonMCInstrInfo.cpp:686
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bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
Definition: HexagonMCInstrInfo.cpp:632
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Definition: HexagonMCInstrInfo.h:204
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Return the new value or the newly produced value.
Definition: HexagonMCInstrInfo.cpp:404
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Definition: HexagonMCInstrInfo.cpp:680
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Definition: HexagonMCInstrInfo.cpp:731
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Definition: HexagonMCInstrInfo.cpp:346
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Definition: HexagonMCInstrInfo.h:340
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StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
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constexpr size_t splitNoMemOrderOffset
Definition: HexagonMCInstrInfo.h:78
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const MCOperand & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:385
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Definition: MCRegisterInfo.h:135
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Definition: HexagonMCInstrInfo.cpp:316
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Definition: HexagonMCInstrInfo.cpp:1020
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Definition: HexagonMCInstrInfo.cpp:248
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unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
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Wrapper class representing virtual and physical registers.
Definition: Register.h:19
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const MCOperand & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:411
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return j(j<< 16)
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Definition: HexagonMCInstrInfo.h:336
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Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
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Definition: HexagonMCInstrInfo.h:37
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Check for a valid bundle.
Definition: HexagonMCChecker.h:34
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unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
Definition: HexagonMCInstrInfo.cpp:423
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MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
Definition: HexagonMCInstrInfo.cpp:208
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constexpr size_t noShuffleOffset
Definition: HexagonMCInstrInfo.h:81
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Definition: HexagonMCDuplexInfo.cpp:189
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const MCOperand & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:323
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unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
Definition: HexagonMCInstrInfo.cpp:450
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bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer)
Definition: HexagonMCInstrInfo.cpp:712
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Definition: HexagonMCInstrInfo.cpp:909
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const MCInst & instruction(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:526
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Return true if the operand is a new-value store insn.
Definition: HexagonMCInstrInfo.cpp:668
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bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:637
llvm::HexagonMCInstrInfo::getMaxValue
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the maximum value of an extendable operand.
Definition: HexagonMCInstrInfo.cpp:353
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constexpr size_t bundleInstructionsOffset
Definition: HexagonMCInstrInfo.h:84
SmallVector.h
llvm::HexagonMCInstrInfo::padEndloop
void padEndloop(MCInst &MCI, MCContext &Context)
Definition: HexagonMCInstrInfo.cpp:921
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const MCExpr & getExpr(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:310
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A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::HexagonMCInstrInfo::getMinValue
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the minimum value of an extendable operand.
Definition: HexagonMCInstrInfo.cpp:364
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Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::HexagonMCInstrInfo::isExtended
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:626
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Definition: HexagonMCDuplexInfo.cpp:114
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bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
Definition: HexagonMCInstrInfo.cpp:790
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bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I)
Definition: HexagonMCInstrInfo.cpp:760
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std::pair< unsigned, unsigned > GetVecRegPairIndices(unsigned VecRegPair)
Returns an ordered pair of the constituent register ordinals for each of the elements of VecRegPair.
Definition: HexagonMCInstrInfo.cpp:700
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PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst)
Definition: HexagonMCInstrInfo.cpp:39
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unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:977
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bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:735
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Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:77
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::HexagonMCInstrInfo::PredicateInfo::Operand
unsigned Operand
Definition: HexagonMCInstrInfo.h:341
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Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1251
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Return whether the insn is newly predicated.
Definition: HexagonMCInstrInfo.cpp:742
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Definition: HexagonMCInstrInfo.h:39
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Definition: HexagonMCInstrInfo.cpp:620
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Definition: HexagonMCInstrInfo.cpp:646