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13 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
14 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
26 class HexagonMCChecker;
32 class MCSubtargetInfo;
60 return !(*
this ==
Other);
66 namespace HexagonMCInstrInfo {
103 bool AttemptCompatibility =
false);
204 template <
unsigned N,
unsigned S>
208 template <
unsigned N,
unsigned S>
278 bool ExtendedA,
MCInst const &MIb,
bool ExtendedB,
385 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
bool mustNotExtend(MCExpr const &Expr)
void setMustExtend(MCExpr const &Expr, bool Val=true)
This is an optimization pass for GlobalISel generic memory operations.
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t minConstant(MCInst const &MCI, size_t Index)
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
SmallVectorImpl< MCOperand >::const_iterator const_iterator
bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg)
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &I)
unsigned getDuplexRegisterNumbering(unsigned Reg)
Context object for machine code objects.
bool subInstWouldBeExtended(MCInst const &potentialDuplex)
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
constexpr size_t memReorderDisabledOffset
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getCVIResources(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the resources used by this instruction.
bool isDuplexPair(MCInst const &MIa, MCInst const &MIb)
Symmetrical. See if these two instructions are fit for duplex pair.
const MCInst & operator*() const
constexpr int64_t splitNoMemorderMask
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
bool inSRange(MCInst const &MCI, size_t Index)
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
PredicateInfo(unsigned Register, unsigned Operand, bool PredicatedTrue)
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
bool isPredicated() const
bool isImmext(MCInst const &MCI)
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
bool isSubInstruction(MCInst const &MCI)
const MCInst * extenderForIndex(MCInst const &MCB, size_t Index)
void setInnerLoop(MCInst &MCI)
Instances of this class represent a single low-level machine instruction.
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of.
bool isMemReorderDisabled(MCInst const &MCI)
constexpr size_t innerLoopOffset
bool isDblRegForSubInst(unsigned Reg)
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
bool s27_2_reloc(MCExpr const &Expr)
bool hasImmExt(MCInst const &MCI)
bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI)
void setMemReorderDisabled(MCInst &MCI)
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBundle(MCInst const &MCI)
constexpr int64_t noShuffleMask
PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
Describe properties that are true of each instruction in the target description file.
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
constexpr int64_t memReorderDisabledMask
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI)
bool operator==(PacketIterator const &Other) const
bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI)
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
bool IsVecRegSingle(unsigned VecReg)
bool LoopNeedsPadding(MCInst const &MCB)
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
size_t bundleSize(MCInst const &MCI)
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
bool isIntRegForSubInst(unsigned Reg)
bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)
Return whether the operand is extendable.
bool mustExtend(MCExpr const &Expr)
bool operator!=(PacketIterator const &Other) const
MCInst deriveSubInst(MCInst const &Inst)
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
unsigned packetSize(StringRef CPU)
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker, bool AttemptCompatibility=false)
bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, bool bisReversable, MCSubtargetInfo const &STI)
non-Symmetrical. See if these two instructions are fit for duplex pair.
constexpr size_t outerLoopOffset
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
PacketIterator & operator++()
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
bool IsReverseVecRegPair(unsigned VecReg)
constexpr int64_t outerLoopMask
bool isIntReg(unsigned Reg)
constexpr int64_t innerLoopMask
bool IsVecRegPair(unsigned VecReg)
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
bool inRange(MCInst const &MCI, size_t Index)
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)
Return the new value or the newly produced value.
bool isOuterLoop(MCInst const &MCI)
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t splitNoMemOrderOffset
const MCOperand & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
void setOuterLoop(MCInst &MCI)
unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
const MCOperand & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Interface to description of machine instruction set.
Check for a valid bundle.
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
constexpr size_t noShuffleOffset
unsigned getDuplexCandidateGroup(MCInst const &MI)
const MCOperand & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer)
unsigned packetSizeSlots(MCSubtargetInfo const &STI)
const MCInst & instruction(MCInst const &MCB, size_t Index)
bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI)
Return true if the operand is a new-value store insn.
bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI)
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the maximum value of an extendable operand.
constexpr size_t bundleInstructionsOffset
void padEndloop(MCInst &MCI, MCContext &Context)
const MCExpr & getExpr(MCExpr const &Expr)
A range adaptor for a pair of iterators.
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the minimum value of an extendable operand.
Instances of this class represent operands of the MCInst class.
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb)
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I)
std::pair< unsigned, unsigned > GetVecRegPairIndices(unsigned VecRegPair)
Returns an ordered pair of the constituent register ordinals for each of the elements of VecRegPair.
PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst)
unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
Generic base class for all target subtargets.
LLVM Value Representation.
Base class for the full range of assembler expressions which are needed for parsing.
Optional< std::vector< StOtherPiece > > Other
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
DuplexCandidate(unsigned i, unsigned j, unsigned iClass)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
bool isInnerLoop(MCInst const &MCI)