LLVM 19.0.0git
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1//===- HexagonMCInstrInfo.cpp - Utility functions on Hexagon MCInsts ------===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9// Utility functions for Hexagon specific MCInst queries
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/iterator.h"
20#include "llvm/MC/MCInst.h"
22#include <cstddef>
23#include <cstdint>
25namespace llvm {
27class HexagonMCChecker;
28class MCContext;
29class MCExpr;
30class MCInstrDesc;
31class MCInstrInfo;
32class MCRegisterInfo;
33class MCSubtargetInfo;
39 DuplexCandidate(unsigned i, unsigned j, unsigned iClass)
43namespace Hexagon {
47 PacketIterator, std::forward_iterator_tag, const MCInst> {
48 MCInstrInfo const &MCII;
49 MCInst::const_iterator BundleCurrent;
50 MCInst::const_iterator BundleEnd;
51 MCInst::const_iterator DuplexCurrent;
52 MCInst::const_iterator DuplexEnd;
55 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
56 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst, std::nullptr_t);
59 MCInst const &operator*() const;
60 bool operator==(PacketIterator const &Other) const;
63} // end namespace Hexagon
65namespace HexagonMCInstrInfo {
67constexpr size_t innerLoopOffset = 0;
68constexpr int64_t innerLoopMask = 1 << innerLoopOffset;
70constexpr size_t outerLoopOffset = 1;
71constexpr int64_t outerLoopMask = 1 << outerLoopOffset;
73// do not reorder memory load/stores by default load/stores are re-ordered
74// and by default loads can be re-ordered
75constexpr size_t memReorderDisabledOffset = 2;
78constexpr size_t splitNoMemOrderOffset = 3;
81constexpr size_t noShuffleOffset = 4;
82constexpr int64_t noShuffleMask = 1 << noShuffleOffset;
84constexpr size_t bundleInstructionsOffset = 1;
87void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
88 MCInst const &MCI);
90// Returns a iterator range of instructions in this bundle
92bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI);
95// Returns the number of instructions in the bundle
96size_t bundleSize(MCInst const &MCI);
98// Put the packet in to canonical form, compound, duplex, pad, and shuffle
99bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
100 MCContext &Context, MCInst &MCB,
101 HexagonMCChecker *Checker,
102 bool AttemptCompatibility = false);
103bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
104 MCInst const &I);
106// Create a duplex instruction given the two subinsts
107MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0,
108 MCInst const &inst1);
109MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
110 MCOperand const &MO);
112// Convert this instruction in to a duplex subinst
113MCInst deriveSubInst(MCInst const &Inst);
115// Return the extender for instruction at Index or nullptr if none
116MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
117void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
118 MCInst const &MCI);
120// Return memory access size in bytes
121unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI);
123// Return memory access size
124unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI);
126MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
128// Return which duplex group this instruction belongs to
129unsigned getDuplexCandidateGroup(MCInst const &MI);
131// Return a list of all possible instruction duplex combinations
134 MCInst const &MCB);
135unsigned getDuplexRegisterNumbering(unsigned Reg);
137MCExpr const &getExpr(MCExpr const &Expr);
139// Return the index of the extendable operand
140unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI);
142// Return a reference to the extendable operand
144 MCInst const &MCI);
146// Return the implicit alignment of the extendable operand
147unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI);
149// Return the number of logical bits of the extendable operand
150unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI);
152// Check if the extendable operand is signed.
153bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI);
155// Return the max value that a constant extendable operand can have
156// without being extended.
157int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI);
159// Return the min value that a constant extendable operand can have
160// without being extended.
161int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI);
163// Return instruction name
164StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI);
166// Return the operand index for the new value.
167unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI);
169// Return the operand that consumes or produces a new value.
170MCOperand const &getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI);
171unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI);
172MCOperand const &getNewValueOperand2(MCInstrInfo const &MCII,
173 MCInst const &MCI);
175// Return the Hexagon ISA class for the insn.
176unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI);
178/// Return the resources used by this instruction
179unsigned getCVIResources(MCInstrInfo const &MCII,
180 MCSubtargetInfo const &STI,
181 MCInst const &MCI);
183/// Return the slots used by the insn.
184unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
185 MCInst const &MCI);
186unsigned getOtherReservedSlots(MCInstrInfo const &MCII,
187 MCSubtargetInfo const &STI, MCInst const &MCI);
188bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
190// Does the packet have an extender for the instruction at Index
191bool hasExtenderForIndex(MCInst const &MCB, size_t Index);
193bool hasImmExt(MCInst const &MCI);
195// Return whether the instruction is a legal new-value producer.
196bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
197bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI);
198bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI);
199bool hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI);
200unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb);
202int64_t minConstant(MCInst const &MCI, size_t Index);
203template <unsigned N, unsigned S>
204bool inRange(MCInst const &MCI, size_t Index) {
205 return isShiftedUInt<N, S>(minConstant(MCI, Index));
207template <unsigned N, unsigned S>
208bool inSRange(MCInst const &MCI, size_t Index) {
209 return isShiftedInt<N, S>(minConstant(MCI, Index));
211template <unsigned N> bool inRange(MCInst const &MCI, size_t Index) {
212 return isUInt<N>(minConstant(MCI, Index));
215// Return the instruction at Index
216MCInst const &instruction(MCInst const &MCB, size_t Index);
217bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI);
219// Returns whether this MCInst is a wellformed bundle
220bool isBundle(MCInst const &MCI);
222// Return whether the insn is an actual insn.
223bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
224bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI);
225bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI);
226bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI);
227bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI);
229// Return whether the instruction needs to be constant extended.
230bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI);
231bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI);
233// Is this double register suitable for use in a duplex subinst
234bool isDblRegForSubInst(unsigned Reg);
236// Is this a duplex instruction
237bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
239// Can these instructions be duplexed
240bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
242// Can these duplex classes be combine in to a duplex instruction
243bool isDuplexPairMatch(unsigned Ga, unsigned Gb);
245// Return true if the insn may be extended based on the operand value.
246bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI);
248// Return whether the instruction must be always extended.
249bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI);
251/// Return whether it is a floating-point insn.
252bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI);
254bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI);
256// Returns whether this instruction is an immediate extender
257bool isImmext(MCInst const &MCI);
259// Returns whether this bundle is an endloop0
260bool isInnerLoop(MCInst const &MCI);
262// Is this an integer register
263bool isIntReg(unsigned Reg);
265// Is this register suitable for use in a duplex subinst
266bool isIntRegForSubInst(unsigned Reg);
267bool isMemReorderDisabled(MCInst const &MCI);
269// Return whether the insn is a new-value consumer.
270bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
271/// Return true if the operand is a new-value store insn.
272bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI);
273bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short);
275// Can these two instructions be duplexed
276bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
277 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
278 bool bisReversable, MCSubtargetInfo const &STI);
280// Returns whether this bundle is an endloop1
281bool isOuterLoop(MCInst const &MCI);
283// Return whether this instruction is predicated
284bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
285bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI);
286bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI);
288// Return whether the predicate sense is true
289bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI);
291// Return true if this is a scalar predicate register.
292bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg);
294// Returns true if the Ith operand is a predicate register.
295bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I);
297// Return whether the insn is a prefix.
298bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI);
300// Return whether the insn is solo, i.e., cannot be in a packet.
301bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI);
303/// Return whether the insn can be packaged only with A and X-type insns.
304bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI);
306/// Return whether the insn can be packaged only with an A-type insn in slot #1.
307bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI);
308bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI);
309bool isSubInstruction(MCInst const &MCI);
310bool isVector(MCInstrInfo const &MCII, MCInst const &MCI);
311bool mustExtend(MCExpr const &Expr);
312bool mustNotExtend(MCExpr const &Expr);
314// Returns true if this instruction requires a slot to execute.
315bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI);
318// Returns true if \a MCB would require endloop padding.
319bool LoopNeedsPadding(MCInst const &MCB);
321unsigned packetSize(StringRef CPU);
323// Returns the maximum number of slots available in the given
324// subtarget's packets.
325unsigned packetSizeSlots(MCSubtargetInfo const &STI);
327// Returns the number of slots consumed by this packet, considering duplexed
328// and compound instructions.
329unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
330 MCInst const &MCI);
332// Pad the bundle with nops to satisfy endloop requirements.
333void padEndloop(MCInst &MCI, MCContext &Context);
339 bool isPredicated() const;
340 unsigned Register;
341 unsigned Operand;
344PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI);
345bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI);
347// Replace the instructions inside MCB, represented by Candidate
348void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate);
350bool s27_2_reloc(MCExpr const &Expr);
351// Marks a bundle as endloop0
352void setInnerLoop(MCInst &MCI);
354void setMustExtend(MCExpr const &Expr, bool Val = true);
355void setMustNotExtend(MCExpr const &Expr, bool Val = true);
356void setS27_2_reloc(MCExpr const &Expr, bool Val = true);
358// Marks a bundle as endloop1
359void setOuterLoop(MCInst &MCI);
361// Would duplexing this instruction create a requirement to extend
362bool subInstWouldBeExtended(MCInst const &potentialDuplex);
363unsigned SubregisterBit(unsigned Consumer, unsigned Producer,
364 unsigned Producer2);
366bool IsVecRegSingle(unsigned VecReg);
367bool IsVecRegPair(unsigned VecReg);
368bool IsReverseVecRegPair(unsigned VecReg);
369bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer);
371/// Returns an ordered pair of the constituent register ordinals for
372/// each of the elements of \a VecRegPair. For example, Hexagon::W0 ("v0:1")
373/// returns { 0, 1 } and Hexagon::W1 ("v3:2") returns { 3, 2 }.
374std::pair<unsigned, unsigned> GetVecRegPairIndices(unsigned VecRegPair);
376// Attempt to find and replace compound pairs
377void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
378 MCContext &Context, MCInst &MCI);
380} // end namespace HexagonMCInstrInfo
382} // end namespace llvm
unsigned const MachineRegisterInfo * MRI
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned Reg
This file defines the SmallVector class.
DuplexCandidate(unsigned i, unsigned j, unsigned iClass)
Check for a valid bundle.
PredicateInfo(unsigned Register, unsigned Operand, bool PredicatedTrue)
bool operator==(PacketIterator const &Other) const
MCInst const & operator*() const
Context object for machine code objects.
Definition: MCContext.h:81
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
SmallVectorImpl< MCOperand >::const_iterator const_iterator
Definition: MCInst.h:213
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
LLVM Value Representation.
Definition: Value.h:74
CRTP base class which implements the entire standard iterator facade in terms of a minimal subset of ...
Definition: iterator.h:80
A range adaptor for a pair of iterators.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
bool IsReverseVecRegPair(unsigned VecReg)
bool isDblRegForSubInst(unsigned Reg)
bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, bool bisReversable, MCSubtargetInfo const &STI)
non-Symmetrical. See if these two instructions are fit for duplex pair.
bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
bool subInstWouldBeExtended(MCInst const &potentialDuplex)
bool isExtentSigned(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst deriveSubInst(MCInst const &Inst)
bool hasHvxTmp(MCInstrInfo const &MCII, MCInst const &MCI)
bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is solo, i.e., cannot be in a packet.
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
bool isOuterLoop(MCInst const &MCI)
bool inRange(MCInst const &MCI, size_t Index)
bool isIntRegForSubInst(unsigned Reg)
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI)
size_t bundleSize(MCInst const &MCI)
bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &I)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
bool IsVecRegPair(unsigned VecReg)
unsigned getCVIResources(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the resources used by this instruction.
void padEndloop(MCInst &MCI, MCContext &Context)
constexpr int64_t memReorderDisabledMask
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)
Return the new value or the newly produced value.
bool inSRange(MCInst const &MCI, size_t Index)
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg)
bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI)
bool isMemReorderDisabled(MCInst const &MCI)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
std::pair< unsigned, unsigned > GetVecRegPairIndices(unsigned VecRegPair)
Returns an ordered pair of the constituent register ordinals for each of the elements of VecRegPair.
constexpr size_t splitNoMemOrderOffset
bool mustNotExtend(MCExpr const &Expr)
bool isNewValueStore(MCInstrInfo const &MCII, MCInst const &MCI)
Return true if the operand is a new-value store insn.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
bool LoopNeedsPadding(MCInst const &MCB)
void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
constexpr size_t memReorderDisabledOffset
void setMemReorderDisabled(MCInst &MCI)
constexpr size_t noShuffleOffset
bool isBundle(MCInst const &MCI)
int64_t minConstant(MCInst const &MCI, size_t Index)
bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI)
MCExpr const & getExpr(MCExpr const &Expr)
bool IsSingleConsumerRefPairProducer(unsigned Producer, unsigned Consumer)
bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)
Return whether the operand is extendable.
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the minimum value of an extendable operand.
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
bool isDuplexPair(MCInst const &MIa, MCInst const &MIb)
Symmetrical. See if these two instructions are fit for duplex pair.
constexpr int64_t noShuffleMask
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
bool isImmext(MCInst const &MCI)
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredRegister(MCInstrInfo const &MCII, MCInst const &Inst, unsigned I)
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
constexpr int64_t innerLoopMask
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
constexpr int64_t splitNoMemorderMask
constexpr size_t bundleInstructionsOffset
bool s27_2_reloc(MCExpr const &Expr)
bool hasImmExt(MCInst const &MCI)
bool isInnerLoop(MCInst const &MCI)
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI)
constexpr size_t innerLoopOffset
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker, bool AttemptCompatibility=false)
unsigned getOtherReservedSlots(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots this instruction consumes in addition to the slot(s) it can execute out of.
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
constexpr size_t outerLoopOffset
unsigned slotsConsumed(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return the maximum value of an extendable operand.
void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
bool requiresSlot(MCSubtargetInfo const &STI, MCInst const &MCI)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI)
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned packetSizeSlots(MCSubtargetInfo const &STI)
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI)
constexpr int64_t outerLoopMask
MCInst const & instruction(MCInst const &MCB, size_t Index)
bool IsVecRegSingle(unsigned VecReg)
bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI)
Return where the instruction is an accumulator.
bool mustExtend(MCExpr const &Expr)
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getDuplexCandidateGroup(MCInst const &MI)
unsigned getDuplexRegisterNumbering(unsigned Reg)
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
bool isSubInstruction(MCInst const &MCI)
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
void setMustExtend(MCExpr const &Expr, bool Val=true)
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
bool isCVINew(MCInstrInfo const &MCII, MCInst const &MCI)
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb)
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
unsigned packetSize(StringRef CPU)
bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Other
Any other memory.