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13 #ifndef LLVM_MC_MCSUBTARGETINFO_H
14 #define LLVM_MC_MCSUBTARGETINFO_H
90 const unsigned *OperandCycles;
91 const unsigned *ForwardingPaths;
93 std::string FeatureString;
102 const unsigned *
OC,
const unsigned *
FP);
114 FeatureBits = FeatureBits_;
120 return FeatureBits[Feature];
169 return &WriteProcResTable[
SC->WriteProcResIdx];
177 unsigned DefIdx)
const {
178 assert(DefIdx < SC->NumWriteLatencyEntries &&
179 "MachineModel does not specify a WriteResource for DefIdx");
181 return &WriteLatencyTable[
SC->WriteLatencyIdx + DefIdx];
185 unsigned WriteResID)
const {
190 *
E =
I +
SC->NumReadAdvanceEntries;
I !=
E; ++
I) {
191 if (
I->UseIdx < UseIdx)
193 if (
I->UseIdx > UseIdx)
196 if (!
I->WriteResourceID ||
I->WriteResourceID == WriteResID) {
207 if (!
SC.NumReadAdvanceEntries)
210 SC.NumReadAdvanceEntries);
223 unsigned CPUID)
const {
230 return Found != ProcDesc.
end() &&
StringRef(Found->Key) == CPU;
239 virtual std::optional<unsigned>
getCacheSize(
unsigned Level)
const;
282 unsigned NumStridedMemAccesses,
283 unsigned NumPrefetches,
292 #endif // LLVM_MC_MCSUBTARGETINFO_H
virtual bool enableWritePrefetching() const
virtual ~MCSubtargetInfo()=default
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
This is an optimization pass for GlobalISel generic memory operations.
bool operator<(const SubtargetFeatureKV &Other) const
Compare routine for std::is_sorted.
virtual unsigned getCacheLineSize() const
Return the target cache line size in bytes.
unsigned Value
K-V integer value.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
StringRef getTuneCPU() const
Triple - Helper class for working with autoconf configuration names.
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
Container class for subtarget features.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
virtual std::optional< unsigned > getCacheAssociativity(unsigned Level) const
Return the cache associatvity for the given level of cache.
void setFeatureBits(const FeatureBitset &FeatureBits_)
Instances of this class represent a single low-level machine instruction.
virtual unsigned getHwMode() const
virtual std::optional< unsigned > getCacheSize(unsigned Level) const
Return the cache size in bytes for the given level of cache.
const MCSchedModel * SchedModel
const char * Key
K-V key string.
virtual unsigned getMaxPrefetchIterationsAhead() const
Return the maximum prefetch distance in terms of loop iterations.
virtual unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const
Resolve a variant scheduling class for the given MCInst and CPU.
virtual unsigned getPrefetchDistance() const
Return the preferred prefetch distance in terms of instructions.
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
Summarize the scheduling resources required for an instruction of a particular scheduling class.
const FeatureBitset & getFeatureBits() const
bool isCPUStringValid(StringRef CPU) const
Check whether the CPU string is valid.
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
const MCSchedModel & getSchedModelForCPU(StringRef CPU) const
Get the machine model of a CPU.
Used to provide key value pairs for feature and CPU bit flags.
FeatureBitset ApplyFeatureFlag(StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by t...
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
Specify the latency in cpu cycles for a particular scheduling class and def index.
bool operator<(const SubtargetSubTypeKV &Other) const
Compare routine for std::is_sorted.
MCSubtargetInfo & operator=(const MCSubtargetInfo &)=delete
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS)
Initialize the scheduling model and feature bits.
FeatureBitset ClearFeatureBitsTransitively(const FeatureBitset &FB)
SI optimize exec mask operations pre RA
Used to provide key value pairs for feature and CPU bit flags.
FeatureBitArray Implies
K-V bit mask.
virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Return the minimum stride necessary to trigger software prefetching.
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
StringRef getFeatureString() const
const char * Desc
Help descriptor.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
StringRef - Represent a constant reference to a string, i.e.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
FeatureBitset SetFeatureBitsTransitively(const FeatureBitset &FB)
Set/clear additional feature bits, including all other bits they imply.
These values represent a non-pipelined step in the execution of an instruction.
Interface to description of machine instruction set.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Machine model for scheduling, bundling, and heuristics.
const char * Key
K-V key string.
bool checkFeatures(StringRef FS) const
Check whether the subtarget features are enabled/disabled as per the provided string,...
FeatureBitArray Implies
K-V bit mask.
std::optional< std::vector< StOtherPiece > > Other
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
bool operator<(StringRef S) const
Compare routine for std::lower_bound.
ArrayRef< MCReadAdvanceEntry > getReadAdvanceEntries(const MCSchedClassDesc &SC) const
Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.
FeatureBitArray TuneImplies
K-V bit mask.
void setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.
bool operator<(StringRef S) const
Compare routine for std::lower_bound.
Generic base class for all target subtargets.
Itinerary data supplied by a subtarget to be used by a target.
virtual bool shouldPrefetchAddressSpace(unsigned AS) const
Class used to store the subtarget bits in the tables created by tablegen.