#include "AArch64MachineFunctionInfo.h"#include "AArch64TargetMachine.h"#include "MCTargetDesc/AArch64AddressingModes.h"#include "llvm/ADT/APSInt.h"#include "llvm/CodeGen/SelectionDAGISel.h"#include "llvm/IR/Function.h"#include "llvm/IR/GlobalValue.h"#include "llvm/IR/Intrinsics.h"#include "llvm/IR/IntrinsicsAArch64.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/KnownBits.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include "AArch64GenDAGISel.inc"
Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "aarch64-isel" |
Functions | |
| static bool | isIntImmediate (const SDNode *N, uint64_t &Imm) |
| isIntImmediate - This method tests to see if the node is a constant operand. More... | |
| static bool | isIntImmediate (SDValue N, uint64_t &Imm) |
| static bool | isOpcWithIntImmediate (const SDNode *N, unsigned Opc, uint64_t &Imm) |
| static bool | isIntImmediateEq (SDValue N, const uint64_t ImmExpected) |
| static AArch64_AM::ShiftExtendType | getShiftTypeForNode (SDValue N) |
| getShiftTypeForNode - Translate a shift node to the corresponding ShiftType value. More... | |
| static bool | isWorthFoldingSHL (SDValue V) |
| Determine whether it is worth it to fold SHL into the addressing mode. More... | |
| static AArch64_AM::ShiftExtendType | getExtendTypeForNode (SDValue N, bool IsLoadStore=false) |
| getExtendTypeForNode - Translate an extend node to the corresponding ExtendType value. More... | |
| static bool | checkHighLaneIndex (SDNode *DL, SDValue &LaneOp, int &LaneIdx) |
| static bool | checkV64LaneV128 (SDValue Op0, SDValue Op1, SDValue &StdOp, SDValue &LaneOp, int &LaneIdx) |
| static SDValue | narrowIfNeeded (SelectionDAG *CurDAG, SDValue N) |
| Instructions that accept extend modifiers like UXTW expect the register being extended to be a GPR32, but the incoming DAG might be acting on a GPR64 (either via SEXT_INREG or AND). More... | |
| static bool | isWorthFoldingADDlow (SDValue N) |
| If there's a use of this ADDlow that's not itself a load/store then we'll need to create a real ADD instruction from it anyway and there's no point in folding it into the mem op. More... | |
| static SDValue | Widen (SelectionDAG *CurDAG, SDValue N) |
| static bool | isPreferredADD (int64_t ImmOff) |
| static SDValue | NarrowVector (SDValue V128Reg, SelectionDAG &DAG) |
| NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class. More... | |
| static bool | isBitfieldExtractOpFromAnd (SelectionDAG *CurDAG, SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &LSB, unsigned &MSB, unsigned NumberOfIgnoredLowBits, bool BiggerPattern) |
| static bool | isBitfieldExtractOpFromSExtInReg (SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms) |
| static bool | isSeveralBitsExtractOpFromShr (SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &LSB, unsigned &MSB) |
| static bool | isBitfieldExtractOpFromShr (SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms, bool BiggerPattern) |
| static bool | isBitfieldExtractOp (SelectionDAG *CurDAG, SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms, unsigned NumberOfIgnoredLowBits=0, bool BiggerPattern=false) |
| static bool | isBitfieldDstMask (uint64_t DstMask, const APInt &BitsToBeInserted, unsigned NumberOfIgnoredHighBits, EVT VT) |
| Does DstMask form a complementary pair with the mask provided by BitsToBeInserted, suitable for use in a BFI instruction. More... | |
| static void | getUsefulBits (SDValue Op, APInt &UsefulBits, unsigned Depth=0) |
| static void | getUsefulBitsFromAndWithImmediate (SDValue Op, APInt &UsefulBits, unsigned Depth) |
| static void | getUsefulBitsFromBitfieldMoveOpd (SDValue Op, APInt &UsefulBits, uint64_t Imm, uint64_t MSB, unsigned Depth) |
| static void | getUsefulBitsFromUBFM (SDValue Op, APInt &UsefulBits, unsigned Depth) |
| static void | getUsefulBitsFromOrWithShiftedReg (SDValue Op, APInt &UsefulBits, unsigned Depth) |
| static void | getUsefulBitsFromBFM (SDValue Op, SDValue Orig, APInt &UsefulBits, unsigned Depth) |
| static void | getUsefulBitsForUse (SDNode *UserNode, APInt &UsefulBits, SDValue Orig, unsigned Depth) |
| static SDValue | getLeftShift (SelectionDAG *CurDAG, SDValue Op, int ShlAmount) |
| Create a machine node performing a notional SHL of Op by ShlAmount. More... | |
| static bool | isBitfieldPositioningOpFromAnd (SelectionDAG *CurDAG, SDValue Op, bool BiggerPattern, const uint64_t NonZeroBits, SDValue &Src, int &DstLSB, int &Width) |
| static bool | isBitfieldPositioningOpFromShl (SelectionDAG *CurDAG, SDValue Op, bool BiggerPattern, const uint64_t NonZeroBits, SDValue &Src, int &DstLSB, int &Width) |
| static bool | isBitfieldPositioningOp (SelectionDAG *CurDAG, SDValue Op, bool BiggerPattern, SDValue &Src, int &DstLSB, int &Width) |
| Does this tree qualify as an attempt to move a bitfield into position, essentially "(and (shl VAL, N), Mask)" or (shl VAL, N). More... | |
| static bool | isSeveralBitsPositioningOpFromShl (const uint64_t ShlImm, SDValue Op, SDValue &Src, int &DstLSB, int &Width) |
| static bool | isShiftedMask (uint64_t Mask, EVT VT) |
| static bool | tryBitfieldInsertOpFromOrAndImm (SDNode *N, SelectionDAG *CurDAG) |
| static bool | isWorthFoldingIntoOrrWithShift (SDValue Dst, SelectionDAG *CurDAG, SDValue &ShiftedOperand, uint64_t &EncodedShiftImm) |
| static bool | tryOrrWithShift (SDNode *N, SDValue OrOpd0, SDValue OrOpd1, SDValue Src, SDValue Dst, SelectionDAG *CurDAG, const bool BiggerPattern) |
| static bool | tryBitfieldInsertOpFromOr (SDNode *N, const APInt &UsefulBits, SelectionDAG *CurDAG) |
| static int | getIntOperandFromRegisterString (StringRef RegString) |
| static SDNode * | extractSubReg (SelectionDAG *DAG, EVT VT, SDValue V) |
| static SDNode * | insertSubReg (SelectionDAG *DAG, EVT VT, SDValue V) |
| static EVT | getPackedVectorTypeFromPredicateType (LLVMContext &Ctx, EVT PredVT, unsigned NumVec) |
When PredVT is a scalable vector predicate in the form MVT::nx<M>xi1, it builds the correspondent scalable vector of integers MVT::nx<M>xi<bits> s.t. More... | |
| static EVT | getMemVTFromNode (LLVMContext &Ctx, SDNode *Root) |
Return the EVT of the data associated to a memory operation in Root. More... | |
Macro Definition Documentation
◆ DEBUG_TYPE
| #define DEBUG_TYPE "aarch64-isel" |
Definition at line 30 of file AArch64ISelDAGToDAG.cpp.
Function Documentation
◆ checkHighLaneIndex()
Definition at line 690 of file AArch64ISelDAGToDAG.cpp.
References DL, llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), and llvm::ISD::INSERT_SUBVECTOR.
Referenced by checkV64LaneV128().
◆ checkV64LaneV128()
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Definition at line 713 of file AArch64ISelDAGToDAG.cpp.
References checkHighLaneIndex(), llvm::SDValue::getNode(), and std::swap().
◆ extractSubReg()
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Definition at line 3797 of file AArch64ISelDAGToDAG.cpp.
References assert(), DL, llvm::TypeSize::getKnownMinSize(), llvm::SelectionDAG::getMachineNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::EVT::isFixedLengthVector(), llvm::EVT::isScalableVector(), SubReg, and llvm::AArch64::SVEBitsPerBlock.
◆ getExtendTypeForNode()
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getExtendTypeForNode - Translate an extend node to the corresponding ExtendType value.
Definition at line 638 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::AArch64_AM::InvalidShiftExtend, N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::AArch64_AM::SXTB, llvm::AArch64_AM::SXTH, llvm::AArch64_AM::SXTW, llvm::AArch64_AM::UXTB, llvm::AArch64_AM::UXTH, llvm::AArch64_AM::UXTW, and llvm::ISD::ZERO_EXTEND.
◆ getIntOperandFromRegisterString()
Definition at line 3377 of file AArch64ISelDAGToDAG.cpp.
References assert(), and llvm::StringRef::split().
◆ getLeftShift()
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Create a machine node performing a notional SHL of Op by ShlAmount.
If ShlAmount is negative, do a (logical) right-shift instead. If ShlAmount is 0, return Op unchanged.
Definition at line 2481 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::BitWidth, llvm::SelectionDAG::getMachineNode(), llvm::EVT::getSizeInBits(), and llvm::SelectionDAG::getTargetConstant().
Referenced by isBitfieldPositioningOpFromAnd(), and isBitfieldPositioningOpFromShl().
◆ getMemVTFromNode()
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Return the EVT of the data associated to a memory operation in Root.
If such EVT cannot be retrived, it returns an invalid EVT.
Definition at line 5457 of file AArch64ISelDAGToDAG.cpp.
References llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getPackedVectorTypeFromPredicateType(), llvm::SDNode::getValueType(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::AArch64ISD::LD1_MERGE_ZERO, llvm::AArch64ISD::LD1S_MERGE_ZERO, llvm::AArch64ISD::LDNF1_MERGE_ZERO, llvm::AArch64ISD::LDNF1S_MERGE_ZERO, llvm::MVT::nxv16i8, llvm::AArch64ISD::ST1_PRED, llvm::AArch64ISD::SVE_LD2_MERGE_ZERO, llvm::AArch64ISD::SVE_LD3_MERGE_ZERO, and llvm::AArch64ISD::SVE_LD4_MERGE_ZERO.
◆ getPackedVectorTypeFromPredicateType()
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When PredVT is a scalable vector predicate in the form MVT::nx<M>xi1, it builds the correspondent scalable vector of integers MVT::nx<M>xi<bits> s.t.
M x bits = 128. When targeting structured vectors (NumVec >1), the output data type is MVT::nx<M*NumVec>xi<bits> s.t. M x bits = 128. If the input PredVT is not in the form MVT::nx<M>xi1, it returns an invalid EVT.
Definition at line 5437 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::EVT::getIntegerVT(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::MVT::i1, llvm::EVT::isScalableVector(), llvm::MVT::nxv16i1, llvm::MVT::nxv2i1, llvm::MVT::nxv4i1, llvm::MVT::nxv8i1, and llvm::AArch64::SVEBitsPerBlock.
Referenced by getMemVTFromNode().
◆ getShiftTypeForNode()
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getShiftTypeForNode - Translate a shift node to the corresponding ShiftType value.
Definition at line 546 of file AArch64ISelDAGToDAG.cpp.
References llvm::AArch64_AM::ASR, llvm::AArch64_AM::InvalidShiftExtend, llvm::AArch64_AM::LSL, llvm::AArch64_AM::LSR, N, llvm::AArch64_AM::ROR, llvm::ISD::ROTR, llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.
◆ getUsefulBits()
Definition at line 2454 of file AArch64ISelDAGToDAG.cpp.
References llvm::Depth, llvm::APInt::flipAllBits(), llvm::APInt::getBitWidth(), and llvm::SelectionDAG::MaxRecursionDepth.
Referenced by getUsefulBitsFromAndWithImmediate(), getUsefulBitsFromBFM(), getUsefulBitsFromBitfieldMoveOpd(), and getUsefulBitsFromOrWithShiftedReg().
◆ getUsefulBitsForUse()
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Definition at line 2406 of file AArch64ISelDAGToDAG.cpp.
References llvm::Depth, llvm::APInt::getBitWidth(), llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), getUsefulBitsFromAndWithImmediate(), getUsefulBitsFromBFM(), getUsefulBitsFromOrWithShiftedReg(), getUsefulBitsFromUBFM(), and llvm::SDNode::isMachineOpcode().
◆ getUsefulBitsFromAndWithImmediate()
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Definition at line 2277 of file AArch64ISelDAGToDAG.cpp.
References llvm::AArch64_AM::decodeLogicalImmediate(), llvm::Depth, llvm::APInt::getBitWidth(), getUsefulBits(), and llvm::RISCVMatInt::Imm.
Referenced by getUsefulBitsForUse().
◆ getUsefulBitsFromBFM()
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Definition at line 2351 of file AArch64ISelDAGToDAG.cpp.
References llvm::Depth, llvm::APInt::flipAllBits(), llvm::APInt::getBitWidth(), getUsefulBits(), llvm::RISCVMatInt::Imm, and llvm::BitmaskEnumDetail::Mask().
Referenced by getUsefulBitsForUse().
◆ getUsefulBitsFromBitfieldMoveOpd()
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Definition at line 2286 of file AArch64ISelDAGToDAG.cpp.
References llvm::Depth, llvm::APInt::getBitWidth(), getUsefulBits(), llvm::RISCVMatInt::Imm, and llvm::APInt::lshrInPlace().
Referenced by getUsefulBitsFromUBFM().
◆ getUsefulBitsFromOrWithShiftedReg()
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Definition at line 2323 of file AArch64ISelDAGToDAG.cpp.
References llvm::Depth, llvm::AArch64_AM::getShiftType(), llvm::AArch64_AM::getShiftValue(), getUsefulBits(), llvm::AArch64_AM::LSL, llvm::AArch64_AM::LSR, and llvm::BitmaskEnumDetail::Mask().
Referenced by getUsefulBitsForUse().
◆ getUsefulBitsFromUBFM()
Definition at line 2313 of file AArch64ISelDAGToDAG.cpp.
References llvm::Depth, getUsefulBitsFromBitfieldMoveOpd(), and llvm::RISCVMatInt::Imm.
Referenced by getUsefulBitsForUse().
◆ insertSubReg()
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Definition at line 3824 of file AArch64ISelDAGToDAG.cpp.
References assert(), DL, llvm::TypeSize::getKnownMinSize(), llvm::SelectionDAG::getMachineNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::EVT::isFixedLengthVector(), llvm::EVT::isScalableVector(), SubReg, and llvm::AArch64::SVEBitsPerBlock.
◆ isBitfieldDstMask()
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Does DstMask form a complementary pair with the mask provided by BitsToBeInserted, suitable for use in a BFI instruction.
Roughly speaking, this asks whether DstMask zeroes precisely those bits that will be set by the other half.
Definition at line 2247 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::BitWidth, llvm::EVT::getSizeInBits(), llvm::MVT::i32, llvm::MVT::i64, and llvm::APInt::zextOrTrunc().
Referenced by tryBitfieldInsertOpFromOr().
◆ isBitfieldExtractOp()
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Definition at line 2174 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::MVT::i32, llvm::MVT::i64, isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromSExtInReg(), isBitfieldExtractOpFromShr(), N, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, and llvm::ISD::SRL.
Referenced by tryBitfieldInsertOpFromOr().
◆ isBitfieldExtractOpFromAnd()
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Definition at line 1882 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::dbgs(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, isOpcWithIntImmediate(), LLVM_DEBUG, N, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and Widen().
Referenced by isBitfieldExtractOp().
◆ isBitfieldExtractOpFromSExtInReg()
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Definition at line 1975 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::BitWidth, llvm::EVT::getSizeInBits(), llvm::MVT::i32, llvm::MVT::i64, isOpcWithIntImmediate(), N, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
Referenced by isBitfieldExtractOp().
◆ isBitfieldExtractOpFromShr()
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Definition at line 2054 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::dbgs(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, isIntImmediate(), isOpcWithIntImmediate(), isSeveralBitsExtractOpFromShr(), LLVM_DEBUG, N, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
Referenced by isBitfieldExtractOp().
◆ isBitfieldPositioningOp()
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Does this tree qualify as an attempt to move a bitfield into position, essentially "(and (shl VAL, N), Mask)" or (shl VAL, N).
Definition at line 2525 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, assert(), llvm::BitWidth, llvm::SelectionDAG::computeKnownBits(), llvm::EVT::getSizeInBits(), isBitfieldPositioningOpFromAnd(), isBitfieldPositioningOpFromShl(), llvm::isShiftedMask_64(), llvm::ISD::SHL, and llvm::KnownBits::Zero.
Referenced by tryBitfieldInsertOpFromOr().
◆ isBitfieldPositioningOpFromAnd()
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Definition at line 2555 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::countTrailingOnes(), llvm::countTrailingZeros(), llvm::dbgs(), getLeftShift(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, isOpcWithIntImmediate(), llvm::isShiftedMask_64(), LLVM_DEBUG, llvm::ISD::SHL, and Widen().
Referenced by isBitfieldPositioningOp().
◆ isBitfieldPositioningOpFromShl()
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Definition at line 2677 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::countTrailingOnes(), llvm::countTrailingZeros(), getLeftShift(), llvm::MVT::i32, llvm::MVT::i64, isOpcWithIntImmediate(), isSeveralBitsPositioningOpFromShl(), llvm::isShiftedMask_64(), and llvm::ISD::SHL.
Referenced by isBitfieldPositioningOp().
◆ isIntImmediate() [1/2]
isIntImmediate - This method tests to see if the node is a constant operand.
If so Imm will receive the 32-bit value.
Definition at line 422 of file AArch64ISelDAGToDAG.cpp.
References llvm::RISCVMatInt::Imm, and N.
Referenced by isBitfieldExtractOpFromShr(), isIntImmediate(), isIntImmediateEq(), isOpcWithIntImmediate(), and isSeveralBitsExtractOpFromShr().
◆ isIntImmediate() [2/2]
Definition at line 432 of file AArch64ISelDAGToDAG.cpp.
References llvm::RISCVMatInt::Imm, isIntImmediate(), and N.
◆ isIntImmediateEq()
Definition at line 448 of file AArch64ISelDAGToDAG.cpp.
References llvm::RISCVMatInt::Imm, isIntImmediate(), and N.
Referenced by isSeveralBitsPositioningOpFromShl().
◆ isOpcWithIntImmediate()
Definition at line 439 of file AArch64ISelDAGToDAG.cpp.
References llvm::RISCVMatInt::Imm, isIntImmediate(), and N.
Referenced by isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromSExtInReg(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOpFromAnd(), isBitfieldPositioningOpFromShl(), isSeveralBitsExtractOpFromShr(), isSeveralBitsPositioningOpFromShl(), isWorthFoldingIntoOrrWithShift(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), and tryOrrWithShift().
◆ isPreferredADD()
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Definition at line 1222 of file AArch64ISelDAGToDAG.cpp.
◆ isSeveralBitsExtractOpFromShr()
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Definition at line 2008 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::countLeadingOnes(), llvm::MVT::i32, isIntImmediate(), llvm::isMask_64(), isOpcWithIntImmediate(), N, and llvm::ISD::SRL.
Referenced by isBitfieldExtractOpFromShr().
◆ isSeveralBitsPositioningOpFromShl()
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Definition at line 2645 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, assert(), llvm::countTrailingOnes(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), isIntImmediateEq(), llvm::isMask_64(), isOpcWithIntImmediate(), and llvm::ISD::SHL.
Referenced by isBitfieldPositioningOpFromShl().
◆ isShiftedMask()
Definition at line 2709 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::MVT::i32, llvm::MVT::i64, llvm::isShiftedMask_32(), llvm::isShiftedMask_64(), and llvm::BitmaskEnumDetail::Mask().
Referenced by tryBitfieldInsertOpFromOr(), and tryBitfieldInsertOpFromOrAndImm().
◆ isWorthFoldingADDlow()
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If there's a use of this ADDlow that's not itself a load/store then we'll need to create a real ADD instruction from it anyway and there's no point in folding it into the mem op.
Theoretically, it shouldn't matter, but there's a single pseudo-instruction for an ADRP/ADD pair so over-aggressive folding leads to duplicated ADRP instructions.
Definition at line 933 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_STORE, llvm::isStrongerThanMonotonic(), llvm::ISD::LOAD, N, and llvm::ISD::STORE.
◆ isWorthFoldingIntoOrrWithShift()
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Definition at line 2806 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, assert(), llvm::countTrailingOnes(), llvm::countTrailingZeros(), DL, llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::AArch64_AM::getShifterImm(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, isOpcWithIntImmediate(), llvm::isShiftedMask_64(), llvm::AArch64_AM::LSL, llvm::AArch64_AM::LSR, llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by tryOrrWithShift().
◆ isWorthFoldingSHL()
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Determine whether it is worth it to fold SHL into the addressing mode.
Definition at line 563 of file AArch64ISelDAGToDAG.cpp.
References assert(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), and llvm::ISD::SHL.
◆ narrowIfNeeded()
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Instructions that accept extend modifiers like UXTW expect the register being extended to be a GPR32, but the incoming DAG might be acting on a GPR64 (either via SEXT_INREG or AND).
Extract the appropriate low bits if this is the case.
Definition at line 822 of file AArch64ISelDAGToDAG.cpp.
References llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, N, and SubReg.
◆ NarrowVector()
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NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class.
Definition at line 1715 of file AArch64ISelDAGToDAG.cpp.
References llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::MVT::getVectorVT().
◆ tryBitfieldInsertOpFromOr()
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Definition at line 2981 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, assert(), llvm::BitWidth, llvm::SelectionDAG::computeKnownBits(), llvm::APInt::countLeadingZeros(), llvm::APInt::countPopulation(), llvm::countTrailingZeros(), llvm::APInt::countTrailingZeros(), DL, llvm::APInt::getBitsSet(), llvm::KnownBits::getBitWidth(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), I, llvm::MVT::i32, llvm::MVT::i64, llvm::RISCVMatInt::Imm, isBitfieldDstMask(), isBitfieldExtractOp(), isBitfieldPositioningOp(), isOpcWithIntImmediate(), isShiftedMask(), llvm::AArch64_AM::LSR, N, llvm::ISD::OR, llvm::SelectionDAG::SelectNodeTo(), llvm::ISD::SRL, std::swap(), tryOrrWithShift(), and llvm::KnownBits::Zero.
◆ tryBitfieldInsertOpFromOrAndImm()
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Definition at line 2718 of file AArch64ISelDAGToDAG.cpp.
References llvm::And, llvm::ISD::AND, assert(), llvm::BitWidth, llvm::SelectionDAG::computeKnownBits(), llvm::APInt::countPopulation(), llvm::countTrailingOnes(), DL, llvm::SelectionDAG::getMachineNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::MVT::i32, llvm::MVT::i64, llvm::AArch64_AM::isLogicalImmediate(), isOpcWithIntImmediate(), isShiftedMask(), llvm::AArch64ISD::MOVI, N, llvm::ISD::OR, llvm::SelectionDAG::SelectNodeTo(), Shift, and llvm::KnownBits::Zero.
◆ tryOrrWithShift()
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Definition at line 2881 of file AArch64ISelDAGToDAG.cpp.
References llvm::ISD::AND, assert(), DL, llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::AArch64_AM::getShifterImm(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, llvm::isMask_64(), isOpcWithIntImmediate(), isWorthFoldingIntoOrrWithShift(), llvm::AArch64_AM::LSL, llvm::AArch64_AM::LSR, N, llvm::ISD::OR, llvm::SelectionDAG::SelectNodeTo(), llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by tryBitfieldInsertOpFromOr().
◆ Widen()
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Definition at line 1101 of file AArch64ISelDAGToDAG.cpp.
References llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::MVT::i64, N, and SubReg.
Referenced by getAVX512Node(), isBitfieldExtractOpFromAnd(), and isBitfieldPositioningOpFromAnd().
