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SelectionDAGISel.h
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1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SelectionDAGISel class, which is used as the common
10 // base class for SelectionDAG-based instruction selectors.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
15 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
16 
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/Pass.h"
22 #include <memory>
23 
24 namespace llvm {
25  class FastISel;
26  class SelectionDAGBuilder;
27  class SDValue;
28  class MachineRegisterInfo;
29  class MachineBasicBlock;
30  class MachineFunction;
31  class MachineInstr;
32  class OptimizationRemarkEmitter;
33  class TargetLowering;
34  class TargetLibraryInfo;
35  class FunctionLoweringInfo;
36  class ScheduleHazardRecognizer;
37  class SwiftErrorValueTracking;
38  class GCFunctionInfo;
39  class ScheduleDAGSDNodes;
40  class LoadInst;
41 
42 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
43 /// pattern-matching instruction selectors.
45 public:
61 
62  /// Current optimization remark emitter.
63  /// Used to report things like combines and FastISel failures.
64  std::unique_ptr<OptimizationRemarkEmitter> ORE;
65 
66  static char ID;
67 
68  explicit SelectionDAGISel(TargetMachine &tm,
70  ~SelectionDAGISel() override;
71 
72  const TargetLowering *getTargetLowering() const { return TLI; }
73 
74  void getAnalysisUsage(AnalysisUsage &AU) const override;
75 
76  bool runOnMachineFunction(MachineFunction &MF) override;
77 
78  virtual void EmitFunctionEntryCode() {}
79 
80  /// PreprocessISelDAG - This hook allows targets to hack on the graph before
81  /// instruction selection starts.
82  virtual void PreprocessISelDAG() {}
83 
84  /// PostprocessISelDAG() - This hook allows the target to hack on the graph
85  /// right after selection.
86  virtual void PostprocessISelDAG() {}
87 
88  /// Main hook for targets to transform nodes into machine nodes.
89  virtual void Select(SDNode *N) = 0;
90 
91  /// SelectInlineAsmMemoryOperand - Select the specified address as a target
92  /// addressing mode, according to the specified constraint. If this does
93  /// not match or is not implemented, return true. The resultant operands
94  /// (which will appear in the machine instruction) should be added to the
95  /// OutOps vector.
97  unsigned ConstraintID,
98  std::vector<SDValue> &OutOps) {
99  return true;
100  }
101 
102  /// IsProfitableToFold - Returns true if it's profitable to fold the specific
103  /// operand node N of U during instruction selection that starts at Root.
104  virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
105 
106  /// IsLegalToFold - Returns true if the specific operand node N of
107  /// U can be folded during instruction selection that starts at Root.
108  /// FIXME: This is a static member function because the MSP430/X86
109  /// targets, which uses it during isel. This could become a proper member.
110  static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
111  CodeGenOpt::Level OptLevel,
112  bool IgnoreChains = false);
113 
114  static void InvalidateNodeId(SDNode *N);
115  static int getUninvalidatedNodeId(SDNode *N);
116 
117  static void EnforceNodeIdInvariant(SDNode *N);
118 
119  // Opcodes used by the DAG state machine:
155 
168  // Space-optimized forms that implicitly encode number of result VTs.
171  // Space-optimized forms that implicitly encode number of result VTs.
174  // Contains offset in table for pattern being selected
176  };
177 
178  enum {
179  OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
180  OPFL_Chain = 1, // Node has a chain input.
181  OPFL_GlueInput = 2, // Node has a glue input.
182  OPFL_GlueOutput = 4, // Node has a glue output.
183  OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
184  OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
185  OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
186  OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
187  OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
188  OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
189  OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
190  OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
191 
193  };
194 
195  /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
196  /// number of fixed arity values that should be skipped when copying from the
197  /// root.
198  static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
199  return ((Flags&OPFL_VariadicInfo) >> 4)-1;
200  }
201 
202 
203 protected:
204  /// DAGSize - Size of DAG being instruction selected.
205  ///
206  unsigned DAGSize;
207 
208  /// ReplaceUses - replace all uses of the old node F with the use
209  /// of the new node T.
211  CurDAG->ReplaceAllUsesOfValueWith(F, T);
213  }
214 
215  /// ReplaceUses - replace all uses of the old nodes F with the use
216  /// of the new nodes T.
217  void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
218  CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
219  for (unsigned i = 0; i < Num; ++i)
220  EnforceNodeIdInvariant(T[i].getNode());
221  }
222 
223  /// ReplaceUses - replace all uses of the old node F with the use
224  /// of the new node T.
226  CurDAG->ReplaceAllUsesWith(F, T);
228  }
229 
230  /// Replace all uses of \c F with \c T, then remove \c F from the DAG.
232  CurDAG->ReplaceAllUsesWith(F, T);
234  CurDAG->RemoveDeadNode(F);
235  }
236 
237  /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
238  /// by tblgen. Others should not call it.
239  void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
240  const SDLoc &DL);
241 
242  /// getPatternForIndex - Patterns selected by tablegen during ISEL
243  virtual StringRef getPatternForIndex(unsigned index) {
244  llvm_unreachable("Tblgen should generate the implementation of this!");
245  }
246 
247  /// getIncludePathForIndex - get the td source location of pattern instantiation
248  virtual StringRef getIncludePathForIndex(unsigned index) {
249  llvm_unreachable("Tblgen should generate the implementation of this!");
250  }
251 public:
252  // Calls to these predicates are generated by tblgen.
253  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
254  int64_t DesiredMaskS) const;
255  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
256  int64_t DesiredMaskS) const;
257 
258 
259  /// CheckPatternPredicate - This function is generated by tblgen in the
260  /// target. It runs the specified pattern predicate and returns true if it
261  /// succeeds or false if it fails. The number is a private implementation
262  /// detail to the code tblgen produces.
263  virtual bool CheckPatternPredicate(unsigned PredNo) const {
264  llvm_unreachable("Tblgen should generate the implementation of this!");
265  }
266 
267  /// CheckNodePredicate - This function is generated by tblgen in the target.
268  /// It runs node predicate number PredNo and returns true if it succeeds or
269  /// false if it fails. The number is a private implementation
270  /// detail to the code tblgen produces.
271  virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
272  llvm_unreachable("Tblgen should generate the implementation of this!");
273  }
274 
275  /// CheckNodePredicateWithOperands - This function is generated by tblgen in
276  /// the target.
277  /// It runs node predicate number PredNo and returns true if it succeeds or
278  /// false if it fails. The number is a private implementation detail to the
279  /// code tblgen produces.
281  SDNode *N, unsigned PredNo,
282  const SmallVectorImpl<SDValue> &Operands) const {
283  llvm_unreachable("Tblgen should generate the implementation of this!");
284  }
285 
286  virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
287  unsigned PatternNo,
288  SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
289  llvm_unreachable("Tblgen should generate the implementation of this!");
290  }
291 
292  virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
293  llvm_unreachable("Tblgen should generate this!");
294  }
295 
296  void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
297  unsigned TableSize);
298 
299  /// Return true if complex patterns for this target can mutate the
300  /// DAG.
301  virtual bool ComplexPatternFuncMutatesDAG() const {
302  return false;
303  }
304 
305  bool isOrEquivalentToAdd(const SDNode *N) const;
306 
307 private:
308 
309  // Calls to these functions are generated by tblgen.
310  void Select_INLINEASM(SDNode *N, bool Branch);
311  void Select_READ_REGISTER(SDNode *Op);
312  void Select_WRITE_REGISTER(SDNode *Op);
313  void Select_UNDEF(SDNode *N);
314  void CannotYetSelect(SDNode *N);
315 
316 private:
317  void DoInstructionSelection();
318  SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
319  ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
320 
321  SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);
322 
323  /// Prepares the landing pad to take incoming values or do other EH
324  /// personality specific tasks. Returns true if the block should be
325  /// instruction selected, false if no code should be emitted for it.
326  bool PrepareEHLandingPad();
327 
328  /// Perform instruction selection on all basic blocks in the function.
329  void SelectAllBasicBlocks(const Function &Fn);
330 
331  /// Perform instruction selection on a single basic block, for
332  /// instructions between \p Begin and \p End. \p HadTailCall will be set
333  /// to true if a call in the block was translated as a tail call.
334  void SelectBasicBlock(BasicBlock::const_iterator Begin,
336  bool &HadTailCall);
337  void FinishBasicBlock();
338 
339  void CodeGenAndEmitDAG();
340 
341  /// Generate instructions for lowering the incoming arguments of the
342  /// given function.
343  void LowerArguments(const Function &F);
344 
345  void ComputeLiveOutVRegInfo();
346 
347  /// Create the scheduler. If a specific scheduler was specified
348  /// via the SchedulerRegistry, use it, otherwise select the
349  /// one preferred by the target.
350  ///
351  ScheduleDAGSDNodes *CreateScheduler();
352 
353  /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
354  /// state machines that start with a OPC_SwitchOpcode node.
355  std::vector<unsigned> OpcodeOffset;
356 
357  void UpdateChains(SDNode *NodeToMatch, SDValue InputChain,
358  SmallVectorImpl<SDNode *> &ChainNodesMatched,
359  bool isMorphNodeTo);
360 };
361 
362 }
363 
364 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */
void ReplaceUses(SDNode *F, SDNode *T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
SelectionDAGBuilder * SDB
static int getNumFixedFromVariadicInfo(unsigned Flags)
getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values ...
GCFunctionInfo * GFI
virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const
IsProfitableToFold - Returns true if it&#39;s profitable to fold the specific operand node N of U during ...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void ReplaceUses(SDValue F, SDValue T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckAndMask - The isel is trying to match something like (and X, 255).
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
virtual bool CheckNodePredicateWithOperands(SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const
CheckNodePredicateWithOperands - This function is generated by tblgen in the target.
F(f)
SDNode * getNode() const
get the SDNode which holds the desired result
MachineFunction * MF
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
const TargetLibraryInfo * LibInfo
InstListType::const_iterator const_iterator
Definition: BasicBlock.h:90
SwiftErrorValueTracking * SwiftError
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool ComplexPatternFuncMutatesDAG() const
Return true if complex patterns for this target can mutate the DAG.
static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false)
IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction sel...
const TargetLowering * TLI
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
virtual void Select(SDNode *N)=0
Main hook for targets to transform nodes into machine nodes.
static void EnforceNodeIdInvariant(SDNode *N)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
unsigned DAGSize
DAGSize - Size of DAG being instruction selected.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual StringRef getPatternForIndex(unsigned index)
getPatternForIndex - Patterns selected by tablegen during ISEL
static void InvalidateNodeId(SDNode *N)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
TargetInstrInfo - Interface to description of machine instruction set.
MachineRegisterInfo * RegInfo
virtual bool CheckPatternPredicate(unsigned PredNo) const
CheckPatternPredicate - This function is generated by tblgen in the target.
SmallPtrSet< const Instruction *, 4 > ElidedArgCopyInstrs
CodeGenOpt::Level OptLevel
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
Represent the analysis usage information of a pass.
virtual void EmitFunctionEntryCode()
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using &#39;From&#39; to use &#39;To&#39; instead.
virtual void PostprocessISelDAG()
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection...
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isOrEquivalentToAdd(const SDNode *N) const
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:417
virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode *> > &Result)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
Provides information about what library functions are available for the current target.
SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const
CheckNodePredicate - This function is generated by tblgen in the target.
std::unique_ptr< OptimizationRemarkEmitter > ORE
Current optimization remark emitter.
const TargetLowering * getTargetLowering() const
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps)
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode...
bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckOrMask - The isel is trying to match something like (or X, 255).
void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num)
ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T.
void SelectInlineAsmMemoryOperands(std::vector< SDValue > &Ops, const SDLoc &DL)
SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Garbage collection metadata for a single function.
Definition: GCMetadata.h:77
virtual void PreprocessISelDAG()
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
virtual StringRef getIncludePathForIndex(unsigned index)
getIncludePathForIndex - get the td source location of pattern instantiation
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const TargetInstrInfo * TII
FunctionLoweringInfo * FuncInfo
virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo)
void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize)
static int getUninvalidatedNodeId(SDNode *N)