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74 #include "llvm/IR/IntrinsicsWebAssembly.h"
108 using namespace llvm;
110 #define DEBUG_TYPE "isel"
112 STATISTIC(NumFastIselFailures,
"Number of instructions fast isel failed on");
113 STATISTIC(NumFastIselSuccess,
"Number of instructions fast isel selected");
114 STATISTIC(NumFastIselBlocks,
"Number of blocks selected entirely by fast isel");
115 STATISTIC(NumDAGBlocks,
"Number of blocks selected using DAG");
116 STATISTIC(NumDAGIselRetries,
"Number of times dag isel has to try another path");
117 STATISTIC(NumEntryBlocks,
"Number of entry blocks encountered");
119 "Number of entry blocks where fast isel failed to lower arguments");
123 cl::desc(
"Enable abort calls when \"fast\" instruction selection "
124 "fails to lower an instruction: 0 disable the abort, 1 will "
125 "abort but for args, calls and terminators, 2 will also "
126 "abort for argument lowering, and 3 will never fallback "
127 "to SelectionDAG."));
131 cl::desc(
"Emit a diagnostic when \"fast\" instruction selection "
132 "falls back to SelectionDAG."));
136 cl::desc(
"use Machine Branch Probability Info"),
142 cl::desc(
"Only display the basic block whose name "
143 "matches this for all view-*-dags options"));
146 cl::desc(
"Pop up a window to show dags before the first "
147 "dag combine pass"));
150 cl::desc(
"Pop up a window to show dags before legalize types"));
153 cl::desc(
"Pop up a window to show dags before the post "
154 "legalize types dag combine pass"));
157 cl::desc(
"Pop up a window to show dags before legalize"));
160 cl::desc(
"Pop up a window to show dags before the second "
161 "dag combine pass"));
164 cl::desc(
"Pop up a window to show isel dags as they are selected"));
167 cl::desc(
"Pop up a window to show sched dags as they are processed"));
170 cl::desc(
"Pop up a window to show SUnit dags after they are processed"));
195 cl::desc(
"Instruction schedulers available (before register"
217 if (NewOptLevel == SavedOptLevel)
221 LLVM_DEBUG(
dbgs() <<
"\nChanging optimization level for Function "
223 LLVM_DEBUG(
dbgs() <<
"\tBefore: -O" << SavedOptLevel <<
" ; After: -O"
224 << NewOptLevel <<
"\n");
228 dbgs() <<
"\tFastISel is "
237 LLVM_DEBUG(
dbgs() <<
"\nRestoring optimization level for Function "
240 << SavedOptLevel <<
"\n");
256 if (
auto *SchedulerCtor =
ST.getDAGScheduler(OptLevel)) {
257 return SchedulerCtor(IS, OptLevel);
261 (
ST.enableMachineScheduler() &&
ST.enableMachineSchedDefaultSched()) ||
275 "Unknown sched type!");
294 dbgs() <<
"If a target marks an instruction with "
295 "'usesCustomInserter', it must implement "
296 "TargetLowering::EmitInstrWithCustomInserter!\n";
304 "If a target marks an instruction with 'hasPostISelHook', "
305 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
350 if (!TT.isWindowsMSVCEnvironment())
358 if (
I.getType()->isFPOrFPVectorTy()) {
362 for (
const auto &
Op :
I.operands()) {
363 if (
Op->getType()->isFPOrFPVectorTy()) {
378 "-fast-isel-abort > 0 requires -fast-isel");
403 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(Fn);
404 GFI = Fn.
hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) :
nullptr;
405 ORE = std::make_unique<OptimizationRemarkEmitter>(&Fn);
406 auto *PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
409 BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
414 getAnalysisIfAvailable<LegacyDivergenceAnalysis>(), PSI,
BFI);
424 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfoWrapperPass>().getBPI();
429 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
450 if (isa<UnreachableInst>(
Term) || isa<ReturnInst>(
Term))
464 SelectAllBasicBlocks(Fn);
519 Returns.push_back(&
MBB);
527 if (!
FuncInfo->ArgDbgValues.empty())
534 for (
unsigned i = 0,
e =
FuncInfo->ArgDbgValues.size();
i !=
e; ++
i) {
536 assert(
MI->getOpcode() != TargetOpcode::DBG_VALUE_LIST &&
537 "Function parameters should not be described by DBG_VALUE_LIST.");
538 bool hasFI =
MI->getOperand(0).isFI();
548 Def->getParent()->insert(std::next(InsertPos),
MI);
560 if (LDI != LiveInMap.
end()) {
561 assert(!hasFI &&
"There's no handling of frame pointer updating here yet "
565 const MDNode *Variable =
MI->getDebugVariable();
566 const MDNode *Expr =
MI->getDebugExpression();
568 bool IsIndirect =
MI->isIndirectDebugValue();
570 assert(
MI->getOperand(1).getImm() == 0 &&
571 "DBG_VALUE with nonzero offset");
572 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
DL) &&
573 "Expected inlined-at fields to agree");
574 assert(
MI->getOpcode() != TargetOpcode::DBG_VALUE_LIST &&
575 "Didn't expect to see a DBG_VALUE_LIST here");
578 IsIndirect, LDI->second, Variable, Expr);
590 CopyUseMI =
UseMI;
continue;
593 CopyUseMI =
nullptr;
break;
616 for (
const auto &
MBB : *
MF) {
620 for (
const auto &
MI :
MBB) {
623 MI.isStackAligningInlineAsm()) {
626 if (
MI.isInlineAsm()) {
654 if (!R.getLocation().isValid() || ShouldAbort)
655 R << (
" (in function: " + MF.
getName() +
")").str();
679 HadTailCall =
SDB->HasTailCall;
680 SDB->resolveOrClearDbgInfo();
687 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
702 Worklist.push_back(
Op.getNode());
708 unsigned DestReg = cast<RegisterSDNode>(
N->getOperand(1))->getReg();
714 EVT SrcVT = Src.getValueType();
720 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, Known);
721 }
while (!Worklist.empty());
724 void SelectionDAGISel::CodeGenAndEmitDAG() {
726 StringRef GroupDescription =
"Instruction Selection and Scheduling";
727 std::string BlockName;
728 bool MatchFilterBB =
false; (void)MatchFilterBB;
731 getAnalysis<TargetTransformInfoWrapperPass>().getTTI(*
FuncInfo->Fn);
740 FuncInfo->MBB->getBasicBlock()->getName());
922 ComputeLiveOutVRegInfo();
932 DoInstructionSelection();
968 if (FirstMBB != LastMBB)
969 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
991 :
SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
1026 Nodes.push_back(Node);
1028 while (!Nodes.empty()) {
1030 for (
auto *U :
N->uses()) {
1044 int InvalidId = -(
N->getNodeId() + 1);
1045 N->setNodeId(InvalidId);
1050 int Id =
N->getNodeId();
1056 void SelectionDAGISel::DoInstructionSelection() {
1059 <<
FuncInfo->MBB->getName() <<
"'\n");
1077 ISelUpdater ISU(*
CurDAG, ISelPosition);
1084 SDNode *Node = &*--ISelPosition;
1088 if (Node->use_empty())
1093 Nodes.push_back(Node);
1095 while (!Nodes.empty()) {
1101 Nodes.push_back(
Op.getNode());
1112 "Node has already selected predecessor node");
1129 switch (Node->getOpcode()) {
1138 ActionVT = Node->getOperand(1).getValueType();
1141 ActionVT = Node->getValueType(0);
1149 LLVM_DEBUG(
dbgs() <<
"\nISEL: Starting selection on root node: ";
1165 if (
const IntrinsicInst *EHPtrCall = dyn_cast<IntrinsicInst>(U)) {
1167 if (IID == Intrinsic::eh_exceptionpointer ||
1168 IID == Intrinsic::eh_exceptioncode)
1183 bool IsSingleCatchAllClause =
1189 if (!IsSingleCatchAllClause && !IsCatchLongjmp) {
1191 bool IntrFound =
false;
1193 if (
const auto *Call = dyn_cast<IntrinsicInst>(U)) {
1195 if (IID == Intrinsic::wasm_landingpad_index) {
1196 Value *IndexArg = Call->getArgOperand(1);
1197 int Index = cast<ConstantInt>(IndexArg)->getZExtValue();
1204 assert(IntrFound &&
"wasm.landingpad.index intrinsic not found!");
1211 bool SelectionDAGISel::PrepareEHLandingPad() {
1223 if (
const auto *CPI = dyn_cast<CatchPadInst>(LLVMBB->
getFirstNonPHI())) {
1228 assert(EHPhysReg &&
"target lacks exception pointer register");
1230 unsigned VReg =
FuncInfo->getCatchPadExceptionPointerVReg(CPI, PtrRC);
1232 TII->
get(TargetOpcode::COPY), VReg)
1254 if (
const auto *CPI = dyn_cast<CatchPadInst>(LLVMBB->
getFirstNonPHI()))
1275 return !
I->mayWriteToMemory() &&
1276 !
I->isTerminator() &&
1277 !isa<DbgInfoIntrinsic>(
I) &&
1298 <<
" (bad address)\n");
1304 APInt Offset(
DL.getTypeSizeInBits(Address->getType()), 0);
1305 Address = Address->stripAndAccumulateInBoundsConstantOffsets(
DL, Offset);
1311 if (
const auto *AI = dyn_cast<AllocaInst>(Address)) {
1315 }
else if (
const auto *
Arg = dyn_cast<Argument>(Address))
1322 if (Offset.getBoolValue())
1324 Offset.getZExtValue());
1325 LLVM_DEBUG(
dbgs() <<
"processDbgDeclares: setVariableDbgInfo FI=" << FI
1326 <<
", " << *DI <<
"\n");
1332 void SelectionDAGISel::SelectAllBasicBlocks(
const Function &Fn) {
1364 ++NumFastIselFailLowerArguments;
1369 R <<
"FastISel didn't lower all arguments: "
1377 CodeGenAndEmitDAG();
1391 if (FastIS && Inserted)
1400 bool AllPredsVisited =
true;
1402 if (!
FuncInfo->VisitedBBs.count(Pred)) {
1403 AllPredsVisited =
false;
1408 if (AllPredsVisited) {
1410 FuncInfo->ComputePHILiveOutRegInfo(&PN);
1413 FuncInfo->InvalidatePHILiveOutRegInfo(&PN);
1416 FuncInfo->VisitedBBs.insert(LLVMBB);
1432 FuncInfo->ExceptionPointerVirtReg = 0;
1433 FuncInfo->ExceptionSelectorVirtReg = 0;
1435 if (!PrepareEHLandingPad())
1443 unsigned NumFastIselRemaining = std::distance(Begin, End);
1449 for (; BI != Begin; --BI) {
1455 --NumFastIselRemaining;
1465 --NumFastIselRemaining;
1466 ++NumFastIselSuccess;
1471 while (BeforeInst != &*Begin) {
1476 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1481 <<
"FastISel folded load: " << *BeforeInst <<
"\n");
1483 --NumFastIselRemaining;
1484 ++NumFastIselSuccess;
1496 if (isa<CallInst>(Inst) && !isa<GCStatepointInst>(Inst) &&
1497 !isa<GCRelocateInst>(Inst) && !isa<GCResultInst>(Inst)) {
1501 R <<
"FastISel missed call";
1504 std::string InstStrStorage;
1508 R <<
": " << InstStr.str();
1513 if (!Inst->getType()->isVoidTy() && !Inst->getType()->isTokenTy() &&
1514 !Inst->use_empty()) {
1520 bool HadTailCall =
false;
1522 SelectBasicBlock(Inst->getIterator(), BI, HadTailCall);
1534 unsigned RemainingNow = std::distance(Begin, BI);
1535 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1536 NumFastIselRemaining = RemainingNow;
1541 Inst->getDebugLoc(), LLVMBB);
1544 if (Inst->isTerminator()) {
1546 R <<
"FastISel missed terminator";
1550 R <<
"FastISel missed";
1554 std::string InstStrStorage;
1557 R <<
": " << InstStr.str();
1562 NumFastIselFailures += NumFastIselRemaining;
1570 bool FunctionBasedInstrumentation =
1572 SDB->SPDescriptor.initialize(LLVMBB,
FuncInfo->MBBMap[LLVMBB],
1573 FunctionBasedInstrumentation);
1579 ++NumFastIselBlocks;
1586 SelectBasicBlock(Begin, BI, HadTailCall);
1598 FuncInfo->PHINodesToUpdate.clear();
1607 SDB->clearDanglingDebugInfo();
1608 SDB->SPDescriptor.resetPerFunctionState();
1612 SelectionDAGISel::FinishBasicBlock() {
1614 <<
FuncInfo->PHINodesToUpdate.size() <<
"\n";
1617 <<
"Node " <<
i <<
" : (" <<
FuncInfo->PHINodesToUpdate[
i].first
1618 <<
", " <<
FuncInfo->PHINodesToUpdate[
i].second <<
")\n");
1622 for (
unsigned i = 0,
e =
FuncInfo->PHINodesToUpdate.size();
i !=
e; ++
i) {
1625 "This is not a machine PHI node that we are updating!");
1626 if (!
FuncInfo->MBB->isSuccessor(PHI->getParent()))
1632 if (
SDB->SPDescriptor.shouldEmitFunctionBasedCheckStackProtector()) {
1641 SDB->visitSPDescriptorParent(
SDB->SPDescriptor, ParentMBB);
1644 CodeGenAndEmitDAG();
1647 SDB->SPDescriptor.resetPerBBState();
1648 }
else if (
SDB->SPDescriptor.shouldEmitStackProtector()) {
1662 SuccessMBB->
splice(SuccessMBB->
end(), ParentMBB,
1669 SDB->visitSPDescriptorParent(
SDB->SPDescriptor, ParentMBB);
1672 CodeGenAndEmitDAG();
1676 if (FailureMBB->
empty()) {
1679 SDB->visitSPDescriptorFailure(
SDB->SPDescriptor);
1682 CodeGenAndEmitDAG();
1686 SDB->SPDescriptor.resetPerBBState();
1690 for (
auto &BTB :
SDB->SL->BitTestCases) {
1700 CodeGenAndEmitDAG();
1704 for (
unsigned j = 0, ej = BTB.Cases.size();
j != ej; ++
j) {
1705 UnhandledProb -= BTB.Cases[
j].ExtraProb;
1720 if ((BTB.ContiguousRange || BTB.FallthroughUnreachable) &&
j + 2 == ej) {
1723 NextMBB = BTB.Cases[
j + 1].TargetBB;
1724 }
else if (
j + 1 == ej) {
1726 NextMBB = BTB.Default;
1729 NextMBB = BTB.Cases[
j + 1].ThisBB;
1732 SDB->visitBitTestCase(BTB, NextMBB, UnhandledProb, BTB.Reg, BTB.Cases[
j],
1737 CodeGenAndEmitDAG();
1739 if ((BTB.ContiguousRange || BTB.FallthroughUnreachable) &&
j + 2 == ej) {
1741 BTB.Cases.pop_back();
1747 for (
const std::pair<MachineInstr *, unsigned> &
P :
1752 "This is not a machine PHI node that we are updating!");
1755 if (PHIBB == BTB.Default) {
1756 PHI.addReg(
P.second).addMBB(BTB.Parent);
1757 if (!BTB.ContiguousRange) {
1758 PHI.addReg(
P.second).addMBB(BTB.Cases.back().ThisBB);
1765 PHI.addReg(
P.second).addMBB(cBB);
1769 SDB->SL->BitTestCases.clear();
1774 for (
unsigned i = 0,
e =
SDB->SL->JTCases.size();
i !=
e; ++
i) {
1776 if (!
SDB->SL->JTCases[
i].first.Emitted) {
1781 SDB->visitJumpTableHeader(
SDB->SL->JTCases[
i].second,
1785 CodeGenAndEmitDAG();
1792 SDB->visitJumpTable(
SDB->SL->JTCases[
i].second);
1795 CodeGenAndEmitDAG();
1798 for (
unsigned pi = 0, pe =
FuncInfo->PHINodesToUpdate.size();
1803 "This is not a machine PHI node that we are updating!");
1805 if (PHIBB ==
SDB->SL->JTCases[
i].second.Default)
1806 PHI.addReg(
FuncInfo->PHINodesToUpdate[
pi].second)
1807 .addMBB(
SDB->SL->JTCases[
i].first.HeaderBB);
1809 if (
FuncInfo->MBB->isSuccessor(PHIBB))
1813 SDB->SL->JTCases.clear();
1817 for (
unsigned i = 0,
e =
SDB->SL->SwitchCases.size();
i !=
e; ++
i) {
1824 Succs.push_back(
SDB->SL->SwitchCases[
i].TrueBB);
1825 if (
SDB->SL->SwitchCases[
i].TrueBB !=
SDB->SL->SwitchCases[
i].FalseBB)
1826 Succs.push_back(
SDB->SL->SwitchCases[
i].FalseBB);
1832 CodeGenAndEmitDAG();
1842 for (
unsigned i = 0,
e = Succs.size();
i !=
e; ++
i) {
1853 for (
unsigned pn = 0; ; ++pn) {
1855 "Didn't find PHI entry!");
1856 if (
FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1857 PHI.addReg(
FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1865 SDB->SL->SwitchCases.clear();
1886 int64_t DesiredMaskS)
const {
1887 const APInt &ActualMask =
RHS->getAPIntValue();
1888 const APInt &DesiredMask =
APInt(
LHS.getValueSizeInBits(), DesiredMaskS);
1891 if (ActualMask == DesiredMask)
1900 APInt NeededMask = DesiredMask & ~ActualMask;
1915 int64_t DesiredMaskS)
const {
1916 const APInt &ActualMask =
RHS->getAPIntValue();
1917 const APInt &DesiredMask =
APInt(
LHS.getValueSizeInBits(), DesiredMaskS);
1920 if (ActualMask == DesiredMask)
1929 APInt NeededMask = DesiredMask & ~ActualMask;
1946 std::vector<SDValue> InOps;
1959 unsigned Flags = cast<ConstantSDNode>(InOps[
i])->getZExtValue();
1962 Ops.insert(Ops.end(), InOps.begin()+
i,
1967 "Memory operand with multiple values?");
1969 unsigned TiedToOperand;
1973 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1974 for (; TiedToOperand; --TiedToOperand) {
1976 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
1981 std::vector<SDValue> SelOps;
1998 if (
e != InOps.size())
1999 Ops.push_back(InOps.back());
2006 unsigned FlagResNo =
N->getNumValues()-1;
2009 if (
Use.getResNo() == FlagResNo)
2018 bool IgnoreChains) {
2027 Visited.
insert(ImmedUse);
2034 if (!Visited.
insert(
N).second)
2036 WorkList.push_back(
N);
2040 if (Root != ImmedUse) {
2046 if (!Visited.
insert(
N).second)
2048 WorkList.push_back(
N);
2060 return N.hasOneUse();
2067 bool IgnoreChains) {
2126 IgnoreChains =
false;
2132 void SelectionDAGISel::Select_INLINEASM(
SDNode *
N) {
2135 std::vector<SDValue> Ops(
N->op_begin(),
N->op_end());
2145 void SelectionDAGISel::Select_READ_REGISTER(
SDNode *
Op) {
2150 EVT VT =
Op->getValueType(0);
2156 Op->getOperand(0), dl,
Reg,
Op->getValueType(0));
2162 void SelectionDAGISel::Select_WRITE_REGISTER(
SDNode *
Op) {
2167 EVT VT =
Op->getOperand(2).getValueType();
2173 Op->getOperand(0), dl,
Reg,
Op->getOperand(2));
2179 void SelectionDAGISel::Select_UNDEF(
SDNode *
N) {
2183 void SelectionDAGISel::Select_FREEZE(
SDNode *
N) {
2191 void SelectionDAGISel::Select_ARITH_FENCE(
SDNode *
N) {
2196 void SelectionDAGISel::Select_STACKMAP(
SDNode *
N) {
2197 std::vector<SDValue> Ops;
2198 auto *It =
N->op_begin();
2213 Ops.push_back(Shad);
2216 for (; It !=
N->op_end(); It++) {
2217 SDNode *OpNode = It->getNode();
2228 cast<ConstantSDNode>(OpNode)->getZExtValue(),
DL, It->getValueType());
2235 Ops.push_back(Chain);
2236 Ops.push_back(InFlag);
2245 assert(Val >= 128 &&
"Not a VBR");
2251 NextBits = MatcherTable[Idx++];
2252 Val |= (NextBits&127) <<
Shift;
2254 }
while (NextBits & 128);
2261 void SelectionDAGISel::UpdateChains(
2268 if (!ChainNodesMatched.empty()) {
2270 "Matched input chains but didn't produce a chain");
2273 for (
unsigned i = 0,
e = ChainNodesMatched.size();
i !=
e; ++
i) {
2274 SDNode *ChainNode = ChainNodesMatched[
i];
2281 "Deleted node left in chain");
2285 if (ChainNode == NodeToMatch && isMorphNodeTo)
2294 std::replace(ChainNodesMatched.begin(), ChainNodesMatched.end(),
N,
2295 static_cast<SDNode *
>(
nullptr));
2301 if (ChainNode != NodeToMatch && ChainNode->
use_empty() &&
2303 NowDeadNodes.push_back(ChainNode);
2307 if (!NowDeadNodes.empty())
2326 unsigned int Max = 8192;
2329 if (ChainNodesMatched.size() == 1)
2330 return ChainNodesMatched[0]->getOperand(0);
2339 if (!Visited.
insert(V.getNode()).second)
2342 for (
const SDValue &
Op : V->op_values())
2345 InputChains.push_back(V);
2348 for (
auto *
N : ChainNodesMatched) {
2349 Worklist.push_back(
N);
2353 while (!Worklist.empty())
2357 if (InputChains.size() == 0)
2365 Worklist.push_back(V.getNode());
2367 for (
auto *
N : ChainNodesMatched)
2372 if (InputChains.size() == 1)
2373 return InputChains[0];
2379 SDNode *SelectionDAGISel::
2388 int OldGlueResultNo = -1, OldChainResultNo = -1;
2390 unsigned NTMNumResults = Node->getNumValues();
2391 if (Node->getValueType(NTMNumResults-1) ==
MVT::Glue) {
2392 OldGlueResultNo = NTMNumResults-1;
2393 if (NTMNumResults != 1 &&
2394 Node->getValueType(NTMNumResults-2) ==
MVT::Other)
2395 OldChainResultNo = NTMNumResults-2;
2396 }
else if (Node->getValueType(NTMNumResults-1) ==
MVT::Other)
2397 OldChainResultNo = NTMNumResults-1;
2415 (
unsigned)OldGlueResultNo != ResNumResults-1)
2417 SDValue(Res, ResNumResults - 1));
2423 if ((EmitNodeInfo &
OPFL_Chain) && OldChainResultNo != -1 &&
2424 (
unsigned)OldChainResultNo != ResNumResults-1)
2426 SDValue(Res, ResNumResults - 1));
2444 unsigned RecNo = MatcherTable[MatcherIndex++];
2445 assert(RecNo < RecordedNodes.size() &&
"Invalid CheckSame");
2446 return N == RecordedNodes[RecNo].first;
2451 const unsigned char *MatcherTable,
unsigned &MatcherIndex,
SDValue N,
2454 if (ChildNo >=
N.getNumOperands())
2475 CheckOpcode(
const unsigned char *MatcherTable,
unsigned &MatcherIndex,
2477 uint16_t Opc = MatcherTable[MatcherIndex++];
2478 Opc |= (
unsigned short)MatcherTable[MatcherIndex++] << 8;
2479 return N->getOpcode() == Opc;
2486 if (
N.getValueType() == VT)
return true;
2496 if (ChildNo >=
N.getNumOperands())
2505 return cast<CondCodeSDNode>(
N)->get() ==
2512 if (2 >=
N.getNumOperands())
2521 if (cast<VTSDNode>(
N)->getVT() == VT)
2542 int64_t Val = MatcherTable[MatcherIndex++];
2544 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
2549 return C &&
C->getSExtValue() == Val;
2555 if (ChildNo >=
N.getNumOperands())
2561 CheckAndImm(
const unsigned char *MatcherTable,
unsigned &MatcherIndex,
2563 int64_t Val = MatcherTable[MatcherIndex++];
2565 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
2567 if (
N->getOpcode() !=
ISD::AND)
return false;
2576 int64_t Val = MatcherTable[MatcherIndex++];
2578 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
2580 if (
N->getOpcode() !=
ISD::OR)
return false;
2597 switch (Table[
Index++]) {
2625 unsigned Res = Table[
Index++];
2682 unsigned NumRecordedNodes;
2685 unsigned NumMatchedMemRefs;
2688 SDValue InputChain, InputGlue;
2691 bool HasChainNodesMatched;
2708 :
SelectionDAG::DAGUpdateListener(DAG), NodeToMatch(NodeToMatch),
2709 RecordedNodes(
RN), MatchScopes(MS) {}
2717 if (!
E ||
E->isMachineOpcode())
2720 if (
N == *NodeToMatch)
2725 for (
auto &
I : RecordedNodes)
2726 if (
I.first.getNode() ==
N)
2729 for (
auto &
I : MatchScopes)
2730 for (
auto &J :
I.NodeStack)
2731 if (J.getNode() ==
N)
2739 const unsigned char *MatcherTable,
2740 unsigned TableSize) {
2779 Select_INLINEASM(NodeToMatch);
2782 Select_READ_REGISTER(NodeToMatch);
2785 Select_WRITE_REGISTER(NodeToMatch);
2788 Select_UNDEF(NodeToMatch);
2791 Select_FREEZE(NodeToMatch);
2794 Select_ARITH_FENCE(NodeToMatch);
2797 Select_STACKMAP(NodeToMatch);
2806 NodeStack.push_back(
N);
2824 SDValue InputChain, InputGlue;
2838 unsigned MatcherIndex = 0;
2840 if (!OpcodeOffset.empty()) {
2842 if (
N.getOpcode() < OpcodeOffset.size())
2843 MatcherIndex = OpcodeOffset[
N.getOpcode()];
2844 LLVM_DEBUG(
dbgs() <<
" Initial Opcode index to " << MatcherIndex <<
"\n");
2853 unsigned CaseSize = MatcherTable[Idx++];
2855 CaseSize =
GetVBR(CaseSize, MatcherTable, Idx);
2856 if (CaseSize == 0)
break;
2859 uint16_t Opc = MatcherTable[Idx++];
2860 Opc |= (
unsigned short)MatcherTable[Idx++] << 8;
2861 if (Opc >= OpcodeOffset.size())
2862 OpcodeOffset.resize((Opc+1)*2);
2863 OpcodeOffset[Opc] = Idx;
2868 if (
N.getOpcode() < OpcodeOffset.size())
2869 MatcherIndex = OpcodeOffset[
N.getOpcode()];
2873 assert(MatcherIndex < TableSize &&
"Invalid index");
2875 unsigned CurrentOpcodeIndex = MatcherIndex;
2888 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2889 if (NumToSkip & 128)
2890 NumToSkip =
GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2892 if (NumToSkip == 0) {
2897 FailIndex = MatcherIndex+NumToSkip;
2899 unsigned MatcherIndexOfPredicate = MatcherIndex;
2900 (void)MatcherIndexOfPredicate;
2907 Result, *
this, RecordedNodes);
2912 dbgs() <<
" Skipped scope entry (due to false predicate) at "
2913 <<
"index " << MatcherIndexOfPredicate <<
", continuing at "
2914 << FailIndex <<
"\n");
2915 ++NumDAGIselRetries;
2919 MatcherIndex = FailIndex;
2923 if (FailIndex == 0)
break;
2927 MatchScope NewEntry;
2928 NewEntry.FailIndex = FailIndex;
2929 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2930 NewEntry.NumRecordedNodes = RecordedNodes.size();
2931 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2932 NewEntry.InputChain = InputChain;
2933 NewEntry.InputGlue = InputGlue;
2934 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2935 MatchScopes.push_back(NewEntry);
2940 SDNode *Parent =
nullptr;
2941 if (NodeStack.size() > 1)
2942 Parent = NodeStack[NodeStack.size()-2].getNode();
2943 RecordedNodes.push_back(std::make_pair(
N, Parent));
2952 if (ChildNo >=
N.getNumOperands())
2955 RecordedNodes.push_back(std::make_pair(
N->getOperand(ChildNo),
2960 if (
auto *MN = dyn_cast<MemSDNode>(
N))
2961 MatchedMemRefs.push_back(MN->getMemOperand());
2971 if (
N->getNumOperands() != 0 &&
2972 N->getOperand(
N->getNumOperands()-1).getValueType() ==
MVT::Glue)
2973 InputGlue =
N->getOperand(
N->getNumOperands()-1);
2977 unsigned ChildNo = MatcherTable[MatcherIndex++];
2978 if (ChildNo >=
N.getNumOperands())
2980 N =
N.getOperand(ChildNo);
2981 NodeStack.push_back(
N);
2990 if (ChildNo >=
N.getNumOperands())
2992 N =
N.getOperand(ChildNo);
2993 NodeStack.push_back(
N);
2999 NodeStack.pop_back();
3000 assert(!NodeStack.empty() &&
"Node stack imbalance!");
3001 N = NodeStack.back();
3005 if (!::
CheckSame(MatcherTable, MatcherIndex,
N, RecordedNodes))
break;
3024 unsigned OpNum = MatcherTable[MatcherIndex++];
3027 for (
unsigned i = 0;
i < OpNum; ++
i)
3028 Operands.push_back(RecordedNodes[MatcherTable[MatcherIndex++]].first);
3030 unsigned PredNo = MatcherTable[MatcherIndex++];
3036 unsigned CPNum = MatcherTable[MatcherIndex++];
3037 unsigned RecNo = MatcherTable[MatcherIndex++];
3038 assert(RecNo < RecordedNodes.size() &&
"Invalid CheckComplexPat");
3042 std::unique_ptr<MatchStateUpdater> MSU;
3044 MSU.reset(
new MatchStateUpdater(*
CurDAG, &NodeToMatch, RecordedNodes,
3048 RecordedNodes[RecNo].first, CPNum,
3054 if (!::
CheckOpcode(MatcherTable, MatcherIndex,
N.getNode()))
break;
3064 unsigned Res = MatcherTable[MatcherIndex++];
3065 if (!::
CheckType(MatcherTable, MatcherIndex,
N.getValue(Res),
TLI,
3072 unsigned CurNodeOpcode =
N.getOpcode();
3073 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
3077 CaseSize = MatcherTable[MatcherIndex++];
3079 CaseSize =
GetVBR(CaseSize, MatcherTable, MatcherIndex);
3080 if (CaseSize == 0)
break;
3082 uint16_t Opc = MatcherTable[MatcherIndex++];
3083 Opc |= (
unsigned short)MatcherTable[MatcherIndex++] << 8;
3086 if (CurNodeOpcode == Opc)
3090 MatcherIndex += CaseSize;
3094 if (CaseSize == 0)
break;
3097 LLVM_DEBUG(
dbgs() <<
" OpcodeSwitch from " << SwitchStart <<
" to "
3098 << MatcherIndex <<
"\n");
3103 MVT CurNodeVT =
N.getSimpleValueType();
3104 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
3108 CaseSize = MatcherTable[MatcherIndex++];
3110 CaseSize =
GetVBR(CaseSize, MatcherTable, MatcherIndex);
3111 if (CaseSize == 0)
break;
3118 if (CurNodeVT == CaseVT)
3122 MatcherIndex += CaseSize;
3126 if (CaseSize == 0)
break;
3130 <<
"] from " << SwitchStart <<
" to " << MatcherIndex
3164 if (!::
CheckAndImm(MatcherTable, MatcherIndex,
N, *
this))
break;
3167 if (!::
CheckOrImm(MatcherTable, MatcherIndex,
N, *
this))
break;
3179 assert(NodeStack.size() != 1 &&
"No parent node");
3182 bool HasMultipleUses =
false;
3183 for (
unsigned i = 1,
e = NodeStack.size()-1;
i !=
e; ++
i) {
3184 unsigned NNonChainUses = 0;
3185 SDNode *NS = NodeStack[
i].getNode();
3187 if (UI.getUse().getValueType() !=
MVT::Other)
3188 if (++NNonChainUses > 1) {
3189 HasMultipleUses =
true;
3192 if (HasMultipleUses)
break;
3194 if (HasMultipleUses)
break;
3211 int64_t Val = MatcherTable[MatcherIndex++];
3213 Val =
GetVBR(Val, MatcherTable, MatcherIndex);
3216 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3224 unsigned RegNo = MatcherTable[MatcherIndex++];
3225 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3235 unsigned RegNo = MatcherTable[MatcherIndex++];
3236 RegNo |= MatcherTable[MatcherIndex++] << 8;
3237 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
3244 unsigned RecNo = MatcherTable[MatcherIndex++];
3245 assert(RecNo < RecordedNodes.size() &&
"Invalid EmitConvertToTarget");
3249 const ConstantInt *Val=cast<ConstantSDNode>(
Imm)->getConstantIntValue();
3251 Imm.getValueType());
3253 const ConstantFP *Val=cast<ConstantFPSDNode>(
Imm)->getConstantFPValue();
3255 Imm.getValueType());
3258 RecordedNodes.push_back(std::make_pair(
Imm, RecordedNodes[RecNo].second));
3267 "EmitMergeInputChains should be the first chain producing node");
3268 assert(ChainNodesMatched.empty() &&
3269 "Should only have one EmitMergeInputChains per match");
3273 assert(RecNo < RecordedNodes.size() &&
"Invalid EmitMergeInputChains");
3274 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3280 if (ChainNodesMatched.back() != NodeToMatch &&
3281 !RecordedNodes[RecNo].first.hasOneUse()) {
3282 ChainNodesMatched.
clear();
3296 "EmitMergeInputChains should be the first chain producing node");
3303 unsigned NumChains = MatcherTable[MatcherIndex++];
3304 assert(NumChains != 0 &&
"Can't TF zero chains");
3306 assert(ChainNodesMatched.empty() &&
3307 "Should only have one EmitMergeInputChains per match");
3310 for (
unsigned i = 0;
i != NumChains; ++
i) {
3311 unsigned RecNo = MatcherTable[MatcherIndex++];
3312 assert(RecNo < RecordedNodes.size() &&
"Invalid EmitMergeInputChains");
3313 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3319 if (ChainNodesMatched.back() != NodeToMatch &&
3320 !RecordedNodes[RecNo].first.hasOneUse()) {
3321 ChainNodesMatched.
clear();
3327 if (ChainNodesMatched.empty())
3341 unsigned RecNo = MatcherTable[MatcherIndex++];
3342 assert(RecNo < RecordedNodes.size() &&
"Invalid EmitCopyToReg");
3343 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3345 DestPhysReg |= MatcherTable[MatcherIndex++] << 8;
3351 DestPhysReg, RecordedNodes[RecNo].first,
3354 InputGlue = InputChain.
getValue(1);
3359 unsigned XFormNo = MatcherTable[MatcherIndex++];
3360 unsigned RecNo = MatcherTable[MatcherIndex++];
3361 assert(RecNo < RecordedNodes.size() &&
"Invalid EmitNodeXForm");
3363 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res,
nullptr));
3369 unsigned index = MatcherTable[MatcherIndex++];
3370 index |= (MatcherTable[MatcherIndex++] << 8);
3379 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3380 TargetOpc |= (
unsigned short)MatcherTable[MatcherIndex++] << 8;
3381 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3391 NumVTs = MatcherTable[MatcherIndex++];
3393 for (
unsigned i = 0;
i != NumVTs; ++
i) {
3409 if (VTs.size() == 1)
3411 else if (VTs.size() == 2)
3417 unsigned NumOps = MatcherTable[MatcherIndex++];
3419 for (
unsigned i = 0;
i != NumOps; ++
i) {
3420 unsigned RecNo = MatcherTable[MatcherIndex++];
3422 RecNo =
GetVBR(RecNo, MatcherTable, MatcherIndex);
3424 assert(RecNo < RecordedNodes.size() &&
"Invalid EmitNode");
3425 Ops.push_back(RecordedNodes[RecNo].first);
3432 FirstOpToCopy += (EmitNodeInfo &
OPFL_Chain) ? 1 : 0;
3434 "Invalid variadic node");
3447 Ops.push_back(InputChain);
3449 Ops.push_back(InputGlue);
3464 if (!IsMorphNodeTo) {
3471 for (
unsigned i = 0,
e = VTs.size();
i !=
e; ++
i) {
3473 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(
SDValue(Res,
i),
3478 "NodeToMatch was removed partway through selection");
3482 auto &Chain = ChainNodesMatched;
3484 "Chain node replaced during MorphNode");
3487 Res = cast<MachineSDNode>(MorphNode(NodeToMatch, TargetOpc, VTList,
3488 Ops, EmitNodeInfo));
3496 Res->setFlags(Flags);
3502 InputGlue =
SDValue(Res, VTs.size()-1);
3504 InputChain =
SDValue(Res, VTs.size()-2);
3506 InputChain =
SDValue(Res, VTs.size()-1);
3518 bool mayLoad = MCID.
mayLoad();
3525 if (MMO->isLoad()) {
3527 FilteredMemRefs.push_back(MMO);
3528 }
else if (MMO->isStore()) {
3530 FilteredMemRefs.push_back(MMO);
3532 FilteredMemRefs.push_back(MMO);
3539 LLVM_DEBUG(
if (!MatchedMemRefs.empty() && Res->memoperands_empty())
dbgs()
3540 <<
" Dropping mem operands\n";
3541 dbgs() <<
" " << (IsMorphNodeTo ?
"Morphed" :
"Created")
3546 if (IsMorphNodeTo) {
3548 UpdateChains(Res, InputChain, ChainNodesMatched,
true);
3558 unsigned NumResults = MatcherTable[MatcherIndex++];
3560 for (
unsigned i = 0;
i != NumResults; ++
i) {
3561 unsigned ResSlot = MatcherTable[MatcherIndex++];
3563 ResSlot =
GetVBR(ResSlot, MatcherTable, MatcherIndex);
3565 assert(ResSlot < RecordedNodes.size() &&
"Invalid CompleteMatch");
3566 SDValue Res = RecordedNodes[ResSlot].first;
3568 assert(i < NodeToMatch->getNumValues() &&
3571 "Invalid number of results to complete!");
3577 "invalid replacement");
3582 UpdateChains(NodeToMatch, InputChain, ChainNodesMatched,
false);
3595 "Didn't replace all uses of the node?");
3605 LLVM_DEBUG(
dbgs() <<
" Match failed at index " << CurrentOpcodeIndex
3607 ++NumDAGIselRetries;
3609 if (MatchScopes.empty()) {
3610 CannotYetSelect(NodeToMatch);
3616 MatchScope &LastScope = MatchScopes.back();
3617 RecordedNodes.
resize(LastScope.NumRecordedNodes);
3619 NodeStack.
append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3620 N = NodeStack.back();
3622 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3623 MatchedMemRefs.
resize(LastScope.NumMatchedMemRefs);
3624 MatcherIndex = LastScope.FailIndex;
3628 InputChain = LastScope.InputChain;
3629 InputGlue = LastScope.InputGlue;
3630 if (!LastScope.HasChainNodesMatched)
3631 ChainNodesMatched.
clear();
3636 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3637 if (NumToSkip & 128)
3638 NumToSkip =
GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3642 if (NumToSkip != 0) {
3643 LastScope.FailIndex = MatcherIndex+NumToSkip;
3649 MatchScopes.pop_back();
3657 if (
N->isMachineOpcode()) {
3664 if (
N->isTargetOpcode())
3665 return N->isTargetStrictFPOpcode();
3666 return N->isStrictFPOpcode();
3671 auto *
C = dyn_cast<ConstantSDNode>(
N->getOperand(1));
3676 if (
auto *FN = dyn_cast<FrameIndexSDNode>(
N->getOperand(0))) {
3679 int32_t Off =
C->getSExtValue();
3682 return (Off >= 0) && (((A.value() - 1) & Off) == unsigned(Off));
3687 void SelectionDAGISel::CannotYetSelect(
SDNode *
N) {
3690 Msg <<
"Cannot select: ";
3698 bool HasInputChain =
N->getOperand(0).getValueType() ==
MVT::Other;
3700 cast<ConstantSDNode>(
N->getOperand(HasInputChain))->getZExtValue();
3701 if (iid < Intrinsic::num_intrinsics)
3706 Msg <<
"unknown intrinsic #" << iid;
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
bool isDebugValue() const
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SmallVectorImpl< std::pair< SDValue, SDNode * >> &RecordedNodes)
CheckSame - Implements OP_CheckSame.
DIExpression * getExpression() const
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block.
ScheduleDAGSDNodes * createDAGLinearizer(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createDAGLinearizer - This creates a "no-scheduling" scheduler which linearize the DAG using topologi...
static bool isFoldedOrDeadInstruction(const Instruction *I, const FunctionLoweringInfo &FuncInfo)
isFoldedOrDeadInstruction - Return true if the specified instruction is side-effect free and is eithe...
bool hasProperty(Property P) const
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Represents a use of a SDNode.
bool UseInstrRefDebugInfo
const TargetLowering * TLI
This is an optimization pass for GlobalISel generic memory operations.
virtual StringRef getIncludePathForIndex(unsigned index)
getIncludePathForIndex - get the td source location of pattern instantiation
Value * getAddress() const
Diagnostic information for ISel fallback path.
unsigned AssignTopologicalOrder()
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on th...
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineInstrBuilder & UseMI
bool isOrEquivalentToAdd(const SDNode *N) const
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
@ OPC_EmitMergeInputChains1_2
A parsed version of the target data layout string in and methods for querying it.
static void EnforceNodeIdInvariant(SDNode *N)
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SmallVectorImpl< std::pair< SDValue, SDNode * >> &RecordedNodes, unsigned ChildNo)
CheckChildSame - Implements OP_CheckChildXSame.
bool hasOneUse() const
Return true if there is exactly one use of this value.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)
virtual void PostprocessISelDAG()
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
bool isStrictFPEnabled() const
Return true if the target support strict float operation.
static void computeUsesMSVCFloatingPoint(const Triple &TT, const Function &F, MachineModuleInfo &MMI)
static bool hasExceptionPointerOrCodeUser(const CatchPadInst *CPI)
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
unsigned DAGSize
DAGSize - Size of DAG being instruction selected.
static cl::opt< int > EnableFastISelAbort("fast-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"fast\" instruction selection " "fails to lower an instruction: 0 disable the abort, 1 will " "abort but for args, calls and terminators, 2 will also " "abort for argument lowering, and 3 will never fallback " "to SelectionDAG."))
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
SDNode * getNode() const
get the SDNode which holds the desired result
void VerifyDAGDivergence()
@ LIFETIME_START
This corresponds to the llvm.lifetime.
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
virtual const TargetInstrInfo * getInstrInfo() const
void SelectInlineAsmMemoryOperands(std::vector< SDValue > &Ops, const SDLoc &DL)
SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
void copyToMachineFrameInfo(MachineFrameInfo &MFI) const
A raw_ostream that writes to an std::string.
iterator_range< value_op_iterator > op_values() const
unsigned getNumArgOperands() const
getNumArgOperands - Return the number of funcletpad arguments.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool getO0WantsFastISel()
void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, LegacyDivergenceAnalysis *Divergence, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin)
Prepare this SelectionDAG to process code in the given MachineFunction.
bool useDebugInstrRef() const
Returns true if the function's variable locations should be tracked with instruction referencing.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const TargetLowering *TLI, const DataLayout &DL)
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
void finishBasicBlock()
Flush the local value map.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
bool skipFunction(const Function &F) const
Optional passes call this function to check whether the pass should be skipped.
DISubprogram * getSubprogram() const
Get the attached subprogram.
An SDNode that represents everything that will be needed to construct a MachineInstr.
ScheduleDAGSDNodes * createDefaultScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createDefaultScheduler - This creates an instruction scheduler appropriate for the target.
bool lowerArguments()
Do "fast" instruction selection for function arguments and append the machine instructions to the cur...
const BasicBlock & getEntryBlock() const
allnodes_const_iterator allnodes_begin() const
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
Reg
All possible values of the reg field in the ModR/M byte.
bool createEntriesInEntryBlock(DebugLoc DbgLoc)
Create initial definitions of swifterror values in the entry block of the current function.
void propagateVRegs()
Propagate assigned swifterror vregs through a function, synthesizing PHI nodes when needed to maintai...
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
@ OPC_CheckFoldableChainNode
defusechain_iterator - This class provides iterator support for machine operands in the function that...
This class is used to form a handle around another node that is persistent and is updated across invo...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
ScheduleDAGSDNodes * createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createFastDAGScheduler - This creates a "fast" scheduler.
Represents one node in the SelectionDAG.
Triple - Helper class for working with autoconf configuration names.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
This class provides iterator support for SDUse operands that use a specific SDNode.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool CheckPatternPredicate(unsigned PredNo) const
CheckPatternPredicate - This function is generated by tblgen in the target.
static void getLazyBFIAnalysisUsage(AnalysisUsage &AU)
Helper for client passes to set up the analysis usage on behalf of this pass.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
static cl::opt< bool > ViewSchedDAGs("view-sched-dags", cl::Hidden, cl::desc("Pop up a window to show sched dags as they are processed"))
virtual void initializeSplitCSR(MachineBasicBlock *Entry) const
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
bool TimePassesIsEnabled
If the user specifies the -time-passes argument on an LLVM tool command line then the value of this b...
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, unsigned ChildNo)
void setUsesMSVCFloatingPoint(bool b)
A description of a memory reference used in the backend.
bool isExportedInst(const Value *V) const
isExportedInst - Return true if the specified value is an instruction exported from its block.
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
static MachinePassRegistry< FunctionPassCtor > Registry
RegisterScheduler class - Track the registration of instruction schedulers.
static cl::opt< bool > ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the first " "dag combine pass"))
void setCallSiteLandingPad(MCSymbol *Sym, ArrayRef< unsigned > Sites)
Map the landing pad's EH symbol to the call site indexes.
DILocalVariable * getVariable() const
#define LLVM_ATTRIBUTE_ALWAYS_INLINE
LLVM_ATTRIBUTE_ALWAYS_INLINE - On compilers where we have a directive to do so, mark a method "always...
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
DiagnosticInfoOptimizationBase::Argument NV
bool isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are 0 o...
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
virtual bool supportSplitCSR(MachineFunction *MF) const
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
void RemoveDeadNodes()
This method deletes all unreachable nodes in the SelectionDAG.
LLVM_NODISCARD T pop_back_val()
bool succ_empty(const Instruction *I)
static void replace(Module &M, GlobalVariable *Old, GlobalVariable *New)
void initializeGCModuleInfoPass(PassRegistry &)
static void processDbgDeclares(FunctionLoweringInfo &FuncInfo)
Collect llvm.dbg.declare information.
unsigned const TargetRegisterInfo * TRI
void clear()
Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
static cl::opt< std::string > FilterDAGBasicBlockName("filter-view-dags", cl::Hidden, cl::desc("Only display the basic block whose name " "matches this for all view-*-dags options"))
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
void initializeTargetLibraryInfoWrapperPassPass(PassRegistry &)
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
virtual void PreprocessISelDAG()
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
@ ARITH_FENCE
ARITH_FENCE - This corresponds to a arithmetic fence intrinsic.
SDValue getRegister(unsigned Reg, EVT VT)
LLVM Basic Block Representation.
@ INLINEASM
INLINEASM - Represents an inline asm block.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
TargetIntrinsicInfo - Interface to description of machine instruction set.
static void mapWasmLandingPadIndex(MachineBasicBlock *MBB, const CatchPadInst *CPI)
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SelectionDAGISel &SDISel)
static cl::opt< bool > UseMBPI("use-mbpi", cl::desc("use Machine Branch Probability Info"), cl::init(true), cl::Hidden)
void setExposesReturnsTwice(bool B)
setCallsSetJmp - Set a flag that indicates if there's a call to a "returns twice" function.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
void setWasmLandingPadIndex(const MachineBasicBlock *LPad, unsigned Index)
Map the landing pad to its index. Used for Wasm exception handling.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
@ OPC_EmitMergeInputChains1_0
SmallPtrSet< const Instruction *, 4 > ElidedArgCopyInstrs
This is the shared class of boolean and integer constants.
Value * getArgOperand(unsigned i) const
getArgOperand/setArgOperand - Return/set the i-th funcletpad argument.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
const MachineBasicBlock & front() const
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static void reportFastISelFailure(MachineFunction &MF, OptimizationRemarkEmitter &ORE, OptimizationRemarkMissed &R, bool ShouldAbort)
iterator insertAfter(iterator I, MachineInstr *MI)
Insert MI into the instruction list after I.
EVT getValueType() const
Return the ValueType of the referenced return value.
static cl::opt< bool > ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the post " "legalize types dag combine pass"))
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const TargetLowering *TLI, const DataLayout &DL)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SelectionDAGISel &SDISel)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo)
std::unique_ptr< SelectionDAGBuilder > SDB
@ OPC_CheckPatternPredicate
Legacy analysis pass which computes BranchProbabilityInfo.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
bool LegalizeTypes()
This transforms the SelectionDAG into a SelectionDAG that only uses types natively supported by the t...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
MachineRegisterInfo * RegInfo
(vector float) vec_cmpeq(*A, *B) C
const MachineOperand & getOperand(unsigned i) const
CodeGenOpt::Level OptLevel
virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const
CheckNodePredicate - This function is generated by tblgen in the target.
LLT getLLTForMVT(MVT Ty)
Get a rough equivalent of an LLT for a given MVT.
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
static cl::opt< bool > ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, cl::desc("Pop up a window to show dags before legalize types"))
virtual bool ComplexPatternFuncMutatesDAG() const
Return true if complex patterns for this target can mutate the DAG.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
ScheduleDAGSDNodes * createILPListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level)
createILPListDAGScheduler - This creates a bottom up register pressure aware list scheduler that trie...
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Represent the analysis usage information of a pass.
@ Kill
The last use of a register.
void Legalize()
This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction s...
static cl::opt< bool > ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, cl::desc("Pop up a window to show dags before legalize"))
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N)
const MachineFunctionProperties & getProperties() const
Get the function properties.
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
std::unique_ptr< OptimizationRemarkEmitter > ORE
Current optimization remark emitter.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
Describe properties that are true of each instruction in the target description file.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N)
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
bool isInteger() const
Return true if this is an integer or a vector integer type.
This class contains meta information specific to a module.
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
ScheduleDAGSDNodes * createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createBURRListDAGScheduler - This creates a bottom up list scheduler that schedules nodes in source c...
bool use_empty() const
Return true if there are no uses of this node.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
iterator_range< const_phi_iterator > phis() const
Returns a range that iterates over the phis in the basic block.
STATISTIC(NumFunctions, "Total number of functions")
static uint64_t decodeSignRotatedValue(uint64_t V)
Decode a signed value stored with the sign bit in the LSB for dense VBR encoding.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, const SelectionDAGISel &SDISel)
CheckPatternPredicate - Implements OP_CheckPatternPredicate.
auto predecessors(MachineBasicBlock *BB)
ConstantFP - Floating Point Values [float, double].
User * getUser() const
Returns the User that contains this Use.
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
void preassignVRegs(MachineBasicBlock *MBB, BasicBlock::const_iterator Begin, BasicBlock::const_iterator End)
ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOpt::Level) FunctionPassCtor
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
const Instruction * getFirstNonPHI() const
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, const SelectionDAGISel &SDISel, SDNode *N)
CheckNodePredicate - Implements OP_CheckNodePredicate.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static bool findNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse, bool IgnoreChains)
findNonImmUse - Return true if "Def" is a predecessor of "Root" via a path beyond "ImmedUse".
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
static cl::opt< bool > ViewISelDAGs("view-isel-dags", cl::Hidden, cl::desc("Pop up a window to show isel dags as they are selected"))
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
RegisterPassParser class - Handle the addition of new machine passes.
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
void erase_value(Container &C, ValueType V)
Wrapper function to remove a value from a container:
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
static cl::opt< bool > ViewSUnitDAGs("view-sunit-dags", cl::Hidden, cl::desc("Pop up a window to show SUnit dags after they are processed"))
static bool isMemKind(unsigned Flag)
virtual FastISel * createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
mir Rename Register Operands
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
static void InvalidateNodeId(SDNode *N)
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
const MDOperand & getOperand(unsigned I) const
virtual void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const
Insert explicit copies in entry and exit blocks.
MachineModuleInfo & getMMI() const
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool mayLoad() const
Return true if this instruction could possibly read memory.
void setHasInlineAsm(bool B)
Set a flag that indicates that the function contains inline assembly.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
inst_range instructions(Function *F)
bool selectInstruction(const Instruction *I)
Do "fast" instruction selection for the given LLVM IR instruction and append the generated machine in...
This is an important base class in LLVM.
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const
IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during ...
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckChild2CondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N)
Representation of each machine instruction.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const TargetInstrInfo * TII
Module * getParent()
Get the module that this global value is contained inside of...
bool isCall() const
Return true if the instruction is a call.
This represents the llvm.dbg.declare instruction.
use_instr_iterator use_instr_begin(Register RegNo) const
static SDValue HandleMergeInputChains(SmallVectorImpl< SDNode * > &ChainNodesMatched, SelectionDAG *CurDAG)
HandleMergeInputChains - This implements the OPC_EmitMergeInputChains operation for when the pattern ...
bool hasGC() const
hasGC/getGC/setGC/clearGC - The name of the garbage collection algorithm to use during code generatio...
SDNode * mutateStrictFPToFP(SDNode *Node)
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain a...
std::unique_ptr< FunctionLoweringInfo > FuncInfo
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
void setNodeId(int Id)
Set unique node id.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false)
IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction sel...
bool mayRaiseFPException(SDNode *Node) const
Return whether the node may raise an FP exception.
const SDValue & getOperand(unsigned Num) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
static LLVM_ATTRIBUTE_ALWAYS_INLINE bool CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDNode *N)
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
initializer< Ty > init(const Ty &Val)
An analysis pass based on legacy pass manager to deliver ProfileSummaryInfo.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
ArrayRef< std::pair< MCRegister, Register > > liveins() const
void finalizeDebugInstrRefs()
Finalise any partially emitted debug instructions.
virtual StringRef getPatternForIndex(unsigned index)
getPatternForIndex - Patterns selected by tablegen during ISEL
SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
bool NewNodesMustHaveLegalTypes
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG n...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator find(const_arg_type_t< KeyT > Val)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
SDValue getValue(unsigned R) const
bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
CheckOrMask - The isel is trying to match something like (or X, 255).
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
~SelectionDAGISel() override
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
int getNodeId() const
Return the unique node id.
ScheduleDAGSDNodes * createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createVLIWDAGScheduler - Scheduler for VLIW targets.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
StandardInstrumentations SI(Debug, VerifyEach)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
@ OPC_EmitMergeInputChains
static unsigned getMemoryConstraintID(unsigned Flag)
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
@ BasicBlock
Various leaf nodes.
print Print MemDeps of function
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
void setFunction(MachineFunction &MF)
Initialize data structures for specified new function.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Register getReg() const
getReg - Returns the register number.
static int getUninvalidatedNodeId(SDNode *N)
SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default)
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
SDNode * SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type,...
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.
@ OPC_CheckPredicateWithOperands
Class for arbitrary precision integers.
bool mayStore() const
Return true if this instruction could possibly modify memory.
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
virtual bool CheckNodePredicateWithOperands(SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const
CheckNodePredicateWithOperands - This function is generated by tblgen in the target.
ScheduleDAGSDNodes * createHybridListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level)
createHybridListDAGScheduler - This creates a bottom up register pressure aware list scheduler that m...
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
static cl::opt< bool > ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the second " "dag combine pass"))
Machine Instruction Scheduler
MachinePassRegistry - Track the registration of machine passes.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
void initializeAAResultsWrapperPassPass(PassRegistry &)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool shouldEmitSDCheck(const BasicBlock &BB) const
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
static use_iterator use_end()
StringRef - Represent a constant reference to a string, i.e.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps)
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
MachineBasicBlock MachineBasicBlock::iterator MBBI
void setNoFPExcept(bool b)
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
static unsigned getFlagWord(unsigned Kind, unsigned NumOps)
@ STRICT_SINT_TO_FP
STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to a floating point value.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void useInstrRefDebugInfo(bool Flag)
Signal whether instruction referencing variable locations are desired for this function's debug-info.
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
virtual Register getRegisterByName(const char *RegName, LLT Ty, const MachineFunction &MF) const
Return the register ID of the name passed in.
self_iterator getIterator()
void setFunctionLoweringInfo(FunctionLoweringInfo *FuncInfo)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
void useInstrRefDebugInfo(bool Flag)
Signal whether instruction referencing variable locations are desired for this function's debug-info.
@ UNDEF
UNDEF - An undefined node.
const MachineBasicBlock * getParent() const
bool mayRaiseFPException() const
Return true if this instruction may raise a floating-point exception.
void setFastISel(bool Enable)
bool callsFunctionThatReturnsTwice() const
callsFunctionThatReturnsTwice - Return true if the function has a call to setjmp or other function th...
StringRef getName() const
Return a constant reference to the value's name.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
this could be done in SelectionDAGISel along with other special for
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
SwiftErrorValueTracking * SwiftError
TargetSubtargetInfo - Generic base class for all target subtargets.
This class is used by SelectionDAGISel to temporarily override the optimization level on a per-functi...
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint)
Augment an existing flag word returned by getFlagWord with the constraint code for a memory constrain...
const CustomOperand< const MCSubtargetInfo & > Msg[]
static cl::opt< RegisterScheduler::FunctionPassCtor, false, RegisterPassParser< RegisterScheduler > > ISHeuristic("pre-RA-sched", cl::init(&createDefaultScheduler), cl::Hidden, cl::desc("Instruction schedulers available (before register" " allocation):"))
ISHeuristic command line option for instruction schedulers.
bool hasCalls() const
Return true if the current function has any function calls.
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
@ READ_REGISTER
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
virtual Function * getSSPStackGuardCheck(const Module &