27#define DEBUG_TYPE "amdgpu-regbankselect"
43 return "AMDGPU Register Bank Select";
63 "AMDGPU Register Bank Select",
false,
false)
70char AMDGPURegBankSelect::
ID = 0;
75 return new AMDGPURegBankSelect();
93 : B(B), MRI(*B.getMRI()), ILMA(ILMA), MUI(MUI), TRI(TRI),
94 SgprRB(&RBI.getRegBank(
AMDGPU::SGPRRegBankID)),
95 VgprRB(&RBI.getRegBank(
AMDGPU::VGPRRegBankID)),
96 VccRB(&RBI.getRegBank(
AMDGPU::VCCRegBankID)) {}
106 if (!
MI->isCopy() ||
MI->getNumImplicitOperands() != 1)
109 return MI->implicit_operands().begin()->getReg() == TRI.getExec();
114 (MUI.isUniform(Reg) || ILMA.isS32S64LaneMask(Reg)))
136 LLT Ty = MRI.getType(Reg);
137 Register NewReg = MRI.createVirtualRegister({RB, Ty});
140 auto &
MBB = *
MI.getParent();
141 B.setInsertPt(
MBB,
MBB.SkipPHIsAndLabels(std::next(
MI.getIterator())));
142 B.buildCopy(Reg, NewReg);
155 if (
UseMI.isPreISelOpcode()) {
157 if (
Op.isReg() &&
Op.getReg() == Reg)
172 LLT Ty = MRI.getType(Reg);
173 Register NewReg = MRI.createVirtualRegister({RB, Ty});
177 auto DefMI = MRI.getVRegDef(Reg)->getIterator();
184 B.buildCopy(NewReg, Reg);
194 if (!
Reg.isVirtual())
205 const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
206 GISelCSEAnalysisWrapper &
Wrapper =
207 getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
209 GISelObserverWrapper Observer;
213 B.setCSEInfo(&CSEInfo);
214 B.setChangeObserver(Observer);
216 RAIIDelegateInstaller DelegateInstaller(MF, &Observer);
217 RAIIMFObserverInstaller MFObserverInstaller(MF, Observer);
219 IntrinsicLaneMaskAnalyzer ILMA(MF);
221 getAnalysis<MachineUniformityAnalysisPass>().getUniformityInfo();
222 MachineRegisterInfo &
MRI = *
B.getMRI();
224 RegBankSelectHelper RBSHelper(
B, ILMA, MUI, *
ST.getRegisterInfo(),
225 *
ST.getRegBankInfo());
230 for (MachineBasicBlock &
MBB : MF) {
231 for (MachineInstr &
MI :
MBB) {
236 if (!DefReg.
isValid() ||
MRI.getRegClassOrNull(DefReg))
240 MRI.setRegBank(DefReg, *RBSHelper.getRegBankToAssign(DefReg));
244 if (!
MI.isPreISelOpcode())
257 for (MachineOperand &DefOP :
MI.defs()) {
262 const RegisterBank *RB = RBSHelper.getRegBankToAssign(DefReg);
263 if (
MRI.getRegClassOrNull(DefReg))
264 RBSHelper.reAssignRegBankOnDef(
MI, DefOP, RB);
267 MRI.setRegBank(DefReg, *RB);
273 for (MachineOperand &UseOP :
MI.uses()) {
280 MRI.getVRegDef(
UseReg)->isPreISelOpcode())
284 const RegisterBank *RB = RBSHelper.getRegBankToAssign(
UseReg);
285 RBSHelper.constrainRegBankUse(
MI, UseOP, RB);
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
static Register getVReg(MachineOperand &Op)
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Provides analysis for continuously CSEing during GISel passes.
This file implements a version of MachineIRBuilder which CSEs insts within a MachineBasicBlock.
AMD GCN specific subclass of TargetSubtarget.
static Register UseReg(const MachineOperand &MO)
Promote Memory to Register
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Target-Independent Code Generator Pass Configuration Options pass.
const RegisterBank * getRegBankToAssign(Register Reg)
void reAssignRegBankOnDef(MachineInstr &MI, MachineOperand &DefOP, const RegisterBank *RB)
RegBankSelectHelper(MachineIRBuilder &B, AMDGPU::IntrinsicLaneMaskAnalyzer &ILMA, const MachineUniformityInfo &MUI, const SIRegisterInfo &TRI, const RegisterBankInfo &RBI)
bool isTemporalDivergenceCopy(Register Reg)
void constrainRegBankUse(MachineInstr &MI, MachineOperand &UseOP, const RegisterBank *RB)
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
FunctionPass class - This class is used to implement most global optimizations.
The actual analysis pass wrapper.
void addObserver(GISelChangeObserver *O)
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
LLVM_ABI iterator SkipPHIsAndLabels(iterator I)
Return the first instruction in MBB after I that is not a PHI or a label.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Properties which a MachineFunction may have at a given point in time.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineFunctionProperties & getProperties() const
Get the function properties.
Helper class to build MachineInstr.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
LLVM_ABI void setReg(Register Reg)
Change the register this operand corresponds to.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Holds all the information related to register banks.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
constexpr bool isValid() const
StringRef - Represent a constant reference to a string, i.e.
Target-Independent Code Generator Pass Configuration Options.
virtual std::unique_ptr< CSEConfigBase > getCSEConfig() const
Returns the CSEConfig object to use for the current optimization level.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
GenericUniformityInfo< MachineSSAContext > MachineUniformityInfo
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
char & AMDGPURegBankSelectID
FunctionPass * createAMDGPURegBankSelectPass()
DWARFExpression::Operation Op