LLVM 20.0.0git
AMDGPURegBankSelect.cpp
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1//===- AMDGPURegBankSelect.cpp -----------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Use MachineUniformityAnalysis as the primary basis for making SGPR vs. VGPR
10// register bank selection. Use/def analysis as in the default RegBankSelect can
11// be useful in narrower circumstances (e.g. choosing AGPR vs. VGPR for gfx908).
12//
13//===----------------------------------------------------------------------===//
14
15#include "AMDGPURegBankSelect.h"
16#include "AMDGPU.h"
17#include "GCNSubtarget.h"
20
21#define DEBUG_TYPE "regbankselect"
22
23using namespace llvm;
24
26 : RegBankSelect(AMDGPURegBankSelect::ID, RunningMode) {}
27
29
31 return "AMDGPURegBankSelect";
32}
33
37 // TODO: Preserve DomTree
39}
40
42 "AMDGPU Register Bank Select", false, false)
46 "AMDGPU Register Bank Select", false, false)
47
48bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) {
49 // If the ISel pipeline failed, do not bother running that pass.
50 if (MF.getProperties().hasProperty(
52 return false;
53
54 LLVM_DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n');
55 const Function &F = MF.getFunction();
56 Mode SaveOptMode = OptMode;
57 if (F.hasOptNone())
58 OptMode = Mode::Fast;
59 init(MF);
60
61 assert(checkFunctionIsLegal(MF));
62
63 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
65 getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo();
66 MachineDominatorTree &DomTree =
67 getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
68
69 MachineUniformityInfo Uniformity =
71 !ST.isSingleLaneExecution(F));
72 (void)Uniformity; // TODO: Use this
73
74 assignRegisterBanks(MF);
75
76 OptMode = SaveOptMode;
77 return false;
78}
amdgpu AMDGPU Register Bank Select
#define LLVM_DEBUG(X)
Definition: Debug.h:101
AMD GCN specific subclass of TargetSubtarget.
#define DEBUG_TYPE
#define F(x, y, z)
Definition: MD5.cpp:55
Machine IR instance of the generic uniformity analysis.
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:57
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
AMDGPURegBankSelect(Mode RunningMode=Fast)
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
Legacy analysis pass which computes a MachineCycleInfo.
Analysis pass which computes a MachineDominatorTree.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineDominatorTree & getBase()
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
Mode
List of the modes supported by the RegBankSelect pass.
Definition: RegBankSelect.h:96
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
MachineUniformityInfo computeMachineUniformityInfo(MachineFunction &F, const MachineCycleInfo &cycleInfo, const MachineDominatorTree &domTree, bool HasBranchDivergence)
Compute uniformity information for a Machine IR function.