LLVM  10.0.0svn
Public Types | Public Member Functions | Static Public Member Functions | Protected Attributes | List of all members
llvm::GCNSubtarget Class Reference

#include "Target/AMDGPU/AMDGPUSubtarget.h"

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Public Types

enum  TrapHandlerAbi { TrapHandlerAbiNone = 0, TrapHandlerAbiHsa = 1 }
 
enum  TrapID {
  TrapIDHardwareReserved = 0, TrapIDHSADebugTrap = 1, TrapIDLLVMTrap = 2, TrapIDLLVMDebugTrap = 3,
  TrapIDDebugBreakpoint = 7, TrapIDDebugReserved8 = 8, TrapIDDebugReservedFE = 0xfe, TrapIDDebugReservedFF = 0xff
}
 
enum  TrapRegValues { LLVMTrapHandlerRegValue = 1 }
 
- Public Types inherited from llvm::AMDGPUSubtarget
enum  Generation {
  R600 = 0, R700 = 1, EVERGREEN = 2, NORTHERN_ISLANDS = 3,
  SOUTHERN_ISLANDS = 4, SEA_ISLANDS = 5, VOLCANIC_ISLANDS = 6, GFX9 = 7,
  GFX10 = 8
}
 

Public Member Functions

 GCNSubtarget (const Triple &TT, StringRef GPU, StringRef FS, const GCNTargetMachine &TM)
 
 ~GCNSubtarget () override
 
GCNSubtarget & initializeSubtargetDependencies (const Triple &TT, StringRef GPU, StringRef FS)
 
const SIInstrInfo * getInstrInfo () const override
 
const SIFrameLowering * getFrameLowering () const override
 
const SITargetLowering * getTargetLowering () const override
 
const SIRegisterInfo * getRegisterInfo () const override
 
const CallLowering * getCallLowering () const override
 
InstructionSelector * getInstructionSelector () const override
 
const LegalizerInfo * getLegalizerInfo () const override
 
const RegisterBankInfo * getRegBankInfo () const override
 
const SelectionDAGTargetInfo * getSelectionDAGInfo () const override
 
const InstrItineraryData * getInstrItineraryData () const override
 
void ParseSubtargetFeatures (StringRef CPU, StringRef FS)
 
Generation getGeneration () const
 
unsigned getWavefrontSizeLog2 () const
 
unsigned getKnownHighZeroBitsForFrameIndex () const
 Return the number of high bits known to be zero fror a frame index. More...
 
int getLDSBankCount () const
 
unsigned getMaxPrivateElementSize () const
 
unsigned getConstantBusLimit (unsigned Opcode) const
 
bool hasIntClamp () const
 
bool hasFP64 () const
 
bool hasMIMG_R128 () const
 
bool hasHWFP64 () const
 
bool hasFastFMAF32 () const
 
bool hasHalfRate64Ops () const
 
bool hasAddr64 () const
 
bool hasOnlyRevVALUShifts () const
 
bool hasBFE () const
 
bool hasBFI () const
 
bool hasBFM () const
 
bool hasBCNT (unsigned Size) const
 
bool hasFFBL () const
 
bool hasFFBH () const
 
bool hasMed3_16 () const
 
bool hasMin3Max3_16 () const
 
bool hasFmaMixInsts () const
 
bool hasCARRY () const
 
bool hasFMA () const
 
bool hasSwap () const
 
bool hasScalarPackInsts () const
 
bool hasScalarMulHiInsts () const
 
TrapHandlerAbi getTrapHandlerAbi () const
 
bool hasUsableDSOffset () const
 True if the offset field of DS instructions works as expected. More...
 
bool unsafeDSOffsetFoldingEnabled () const
 
bool hasUsableDivScaleConditionOutput () const
 Condition output from div_scale is usable. More...
 
bool hasReadVCCZBug () const
 Extra wait hazard is needed in some cases before s_cbranch_vccnz/s_cbranch_vccz. More...
 
bool hasSMRDReadVALUDefHazard () const
 A read of an SGPR by SMRD instruction requires 4 wait states when the SGPR was written by a VALU instruction. More...
 
bool hasVMEMReadSGPRVALUDefHazard () const
 A read of an SGPR by a VMEM instruction requires 5 wait states when the SGPR was written by a VALU Instruction. More...
 
bool hasRFEHazards () const
 
unsigned getSetRegWaitStates () const
 Number of hazard wait states for s_setreg_b32/s_setreg_imm32_b32. More...
 
bool dumpCode () const
 
unsigned getMaxLocalMemSizeWithWaveCount (unsigned WaveCount, const Function &) const
 Return the amount of LDS that can be used that will not restrict the occupancy lower than WaveCount. More...
 
bool hasFP16Denormals () const
 
bool hasFP64Denormals () const
 
bool supportsMinMaxDenormModes () const
 
bool hasDenormModeInst () const
 
bool useFlatForGlobal () const
 
bool useDS128 () const
 
bool haveRoundOpsF64 () const
 Have v_trunc_f64, v_ceil_f64, v_rndne_f64. More...
 
bool privateMemoryResourceIsRangeChecked () const
 
bool usePRTStrictNull () const
 
bool hasAutoWaitcntBeforeBarrier () const
 
bool hasCodeObjectV3 () const
 
bool hasUnalignedBufferAccess () const
 
bool hasUnalignedScratchAccess () const
 
bool hasApertureRegs () const
 
bool isTrapHandlerEnabled () const
 
bool isXNACKEnabled () const
 
bool isCuModeEnabled () const
 
bool hasFlatAddressSpace () const
 
bool hasFlatScrRegister () const
 
bool hasFlatInstOffsets () const
 
bool hasFlatGlobalInsts () const
 
bool hasFlatScratchInsts () const
 
bool hasScalarFlatScratchInsts () const
 
bool hasFlatSegmentOffsetBug () const
 
bool hasFlatLgkmVMemCountInOrder () const
 
bool hasD16LoadStore () const
 
bool d16PreservesUnusedBits () const
 
bool hasD16Images () const
 
bool ldsRequiresM0Init () const
 Return if most LDS instructions have an m0 use that require m0 to be iniitalized. More...
 
bool hasGWSAutoReplay () const
 
bool hasGWSSemaReleaseAll () const
 
bool hasAddNoCarry () const
 
bool hasUnpackedD16VMem () const
 
bool isMesaGfxShader (const Function &F) const
 
bool hasMad64_32 () const
 
bool hasSDWAOmod () const
 
bool hasSDWAScalar () const
 
bool hasSDWASdst () const
 
bool hasSDWAMac () const
 
bool hasSDWAOutModsVOPC () const
 
bool hasDLInsts () const
 
bool hasDot1Insts () const
 
bool hasDot2Insts () const
 
bool hasDot3Insts () const
 
bool hasDot4Insts () const
 
bool hasDot5Insts () const
 
bool hasDot6Insts () const
 
bool hasMAIInsts () const
 
bool hasPkFmacF16Inst () const
 
bool hasAtomicFaddInsts () const
 
bool isSRAMECCEnabled () const
 
bool hasNoSdstCMPX () const
 
bool hasVscnt () const
 
bool hasRegisterBanking () const
 
bool hasVOP3Literal () const
 
bool hasNoDataDepHazard () const
 
bool vmemWriteNeedsExpWaitcnt () const
 
Align getStackAlignment () const
 
bool enableMachineScheduler () const override
 
bool enableSubRegLiveness () const override
 
void setScalarizeGlobalBehavior (bool b)
 
bool getScalarizeGlobalBehavior () const
 
unsigned getEUsPerCU () const
 
unsigned getMaxWavesPerCU () const
 
unsigned getMaxWavesPerCU (unsigned FlatWorkGroupSize) const
 
unsigned getWavesPerWorkGroup (unsigned FlatWorkGroupSize) const
 
bool enableEarlyIfConversion () const override
 
void overrideSchedPolicy (MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
 
unsigned getMaxNumUserSGPRs () const
 
bool hasSMemRealTime () const
 
bool hasMovrel () const
 
bool hasVGPRIndexMode () const
 
bool useVGPRIndexMode (bool UserEnable) const
 
bool hasScalarCompareEq64 () const
 
bool hasScalarStores () const
 
bool hasScalarAtomics () const
 
bool hasLDSFPAtomics () const
 
bool hasDPP () const
 
bool hasDPPBroadcasts () const
 
bool hasDPPWavefrontShifts () const
 
bool hasDPP8 () const
 
bool hasR128A16 () const
 
bool hasOffset3fBug () const
 
bool hasNSAEncoding () const
 
bool hasMadF16 () const
 
bool enableSIScheduler () const
 
bool loadStoreOptEnabled () const
 
bool hasSGPRInitBug () const
 
bool hasMFMAInlineLiteralBug () const
 
bool has12DWordStoreHazard () const
 
bool hasDwordx3LoadStores () const
 
bool hasSMovFedHazard () const
 
bool hasReadM0MovRelInterpHazard () const
 
bool hasReadM0SendMsgHazard () const
 
bool hasVcmpxPermlaneHazard () const
 
bool hasVMEMtoScalarWriteHazard () const
 
bool hasSMEMtoVectorWriteHazard () const
 
bool hasLDSMisalignedBug () const
 
bool hasInstFwdPrefetchBug () const
 
bool hasVcmpxExecWARHazard () const
 
bool hasLdsBranchVmemWARHazard () const
 
bool hasNSAtoVMEMBug () const
 
unsigned getOccupancyWithNumSGPRs (unsigned SGPRs) const
 Return the maximum number of waves per SIMD for kernels using SGPRs SGPRs. More...
 
unsigned getOccupancyWithNumVGPRs (unsigned VGPRs) const
 Return the maximum number of waves per SIMD for kernels using VGPRs VGPRs. More...
 
unsigned computeOccupancy (const MachineFunction &MF, unsigned LDSSize=0, unsigned NumSGPRs=0, unsigned NumVGPRs=0) const
 Return occupancy for the given function. More...
 
bool flatScratchIsPointer () const
 
bool hasMergedShaders () const
 
unsigned getSGPRAllocGranule () const
 
unsigned getSGPREncodingGranule () const
 
unsigned getTotalNumSGPRs () const
 
unsigned getAddressableNumSGPRs () const
 
unsigned getMinNumSGPRs (unsigned WavesPerEU) const
 
unsigned getMaxNumSGPRs (unsigned WavesPerEU, bool Addressable) const
 
unsigned getReservedNumSGPRs (const MachineFunction &MF) const
 
unsigned getMaxNumSGPRs (const MachineFunction &MF) const
 
unsigned getVGPRAllocGranule () const
 
unsigned getVGPREncodingGranule () const
 
unsigned getTotalNumVGPRs () const
 
unsigned getAddressableNumVGPRs () const
 
unsigned getMinNumVGPRs (unsigned WavesPerEU) const
 
unsigned getMaxNumVGPRs (unsigned WavesPerEU) const
 
unsigned getMaxNumVGPRs (const MachineFunction &MF) const
 
void getPostRAMutations (std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
 
bool isWave32 () const
 
const TargetRegisterClass * getBoolRC () const
 
unsigned getMaxWorkGroupsPerCU (unsigned FlatWorkGroupSize) const override
 
unsigned getMinFlatWorkGroupSize () const override
 
unsigned getMaxFlatWorkGroupSize () const override
 
unsigned getMaxWavesPerEU (unsigned FlatWorkGroupSize) const override
 
unsigned getMinWavesPerEU () const override
 
- Public Member Functions inherited from llvm::AMDGPUSubtarget
 AMDGPUSubtarget (const Triple &TT)
 
std::pair< unsigned, unsigned > getDefaultFlatWorkGroupSize (CallingConv::ID CC) const
 
std::pair< unsigned, unsigned > getFlatWorkGroupSizes (const Function &F) const
 
std::pair< unsigned, unsigned > getWavesPerEU (const Function &F) const
 
unsigned getMaxLocalMemSizeWithWaveCount (unsigned WaveCount, const Function &) const
 Return the amount of LDS that can be used that will not restrict the occupancy lower than WaveCount. More...
 
unsigned getOccupancyWithLocalMemSize (uint32_t Bytes, const Function &) const
 Inverse of getMaxLocalMemWithWaveCount. More...
 
unsigned getOccupancyWithLocalMemSize (const MachineFunction &MF) const
 
bool isAmdHsaOS () const
 
bool isAmdPalOS () const
 
bool isMesa3DOS () const
 
bool isMesaKernel (const Function &F) const
 
bool isAmdHsaOrMesa (const Function &F) const
 
bool has16BitInsts () const
 
bool hasMadMixInsts () const
 
bool hasFP32Denormals () const
 
bool hasFPExceptions () const
 
bool hasSDWA () const
 
bool hasVOP3PInsts () const
 
bool hasMulI24 () const
 
bool hasMulU24 () const
 
bool hasInv2PiInlineImm () const
 
bool hasFminFmaxLegacy () const
 
bool hasTrigReducedRange () const
 
bool isPromoteAllocaEnabled () const
 
unsigned getWavefrontSize () const
 
int getLocalMemorySize () const
 
Align getAlignmentForImplicitArgPtr () const
 
unsigned getExplicitKernelArgOffset (const Function &F) const
 Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument. More...
 
unsigned getMaxWavesPerEU () const
 
bool makeLIDRangeMetadata (Instruction *I) const
 Creates value range metadata on an workitemid.* inrinsic call or load. More...
 
unsigned getImplicitArgNumBytes (const Function &F) const
 
uint64_t getExplicitKernArgSize (const Function &F, Align &MaxAlign) const
 
unsigned getKernArgSegmentSize (const Function &F, Align &MaxAlign) const
 
virtual ~AMDGPUSubtarget ()
 

Static Public Member Functions

static bool hasHalfRate64Ops (const TargetSubtargetInfo &STI)
 
- Static Public Member Functions inherited from llvm::AMDGPUSubtarget
static const AMDGPUSubtarget & get (const MachineFunction &MF)
 
static const AMDGPUSubtarget & get (const TargetMachine &TM, const Function &F)
 

Protected Attributes

Triple TargetTriple
 
unsigned Gen
 
InstrItineraryData InstrItins
 
int LDSBankCount
 
unsigned MaxPrivateElementSize
 
bool FastFMAF32
 
bool HalfRate64Ops
 
bool FP64FP16Denormals
 
bool FlatForGlobal
 
bool AutoWaitcntBeforeBarrier
 
bool CodeObjectV3
 
bool UnalignedScratchAccess
 
bool UnalignedBufferAccess
 
bool HasApertureRegs
 
bool EnableXNACK
 
bool DoesNotSupportXNACK
 
bool EnableCuMode
 
bool TrapHandler
 
bool EnableLoadStoreOpt
 
bool EnableUnsafeDSOffsetFolding
 
bool EnableSIScheduler
 
bool EnableDS128
 
bool EnablePRTStrictNull
 
bool DumpCode
 
bool FP64
 
bool FMA
 
bool MIMG_R128
 
bool IsGCN
 
bool GCN3Encoding
 
bool CIInsts
 
bool GFX8Insts
 
bool GFX9Insts
 
bool GFX10Insts
 
bool GFX7GFX8GFX9Insts
 
bool SGPRInitBug
 
bool HasSMemRealTime
 
bool HasIntClamp
 
bool HasFmaMixInsts
 
bool HasMovrel
 
bool HasVGPRIndexMode
 
bool HasScalarStores
 
bool HasScalarAtomics
 
bool HasSDWAOmod
 
bool HasSDWAScalar
 
bool HasSDWASdst
 
bool HasSDWAMac
 
bool HasSDWAOutModsVOPC
 
bool HasDPP
 
bool HasDPP8
 
bool HasR128A16
 
bool HasNSAEncoding
 
bool HasDLInsts
 
bool HasDot1Insts
 
bool HasDot2Insts
 
bool HasDot3Insts
 
bool HasDot4Insts
 
bool HasDot5Insts
 
bool HasDot6Insts
 
bool HasMAIInsts
 
bool HasPkFmacF16Inst
 
bool HasAtomicFaddInsts
 
bool EnableSRAMECC
 
bool DoesNotSupportSRAMECC
 
bool HasNoSdstCMPX
 
bool HasVscnt
 
bool HasRegisterBanking
 
bool HasVOP3Literal
 
bool HasNoDataDepHazard
 
bool FlatAddressSpace
 
bool FlatInstOffsets
 
bool FlatGlobalInsts
 
bool FlatScratchInsts
 
bool ScalarFlatScratchInsts
 
bool AddNoCarryInsts
 
bool HasUnpackedD16VMem
 
bool R600ALUInst
 
bool CaymanISA
 
bool CFALUBug
 
bool LDSMisalignedBug
 
bool HasMFMAInlineLiteralBug
 
bool HasVertexCache
 
short TexVTXClauseSize
 
bool ScalarizeGlobal
 
bool HasVcmpxPermlaneHazard
 
bool HasVMEMtoScalarWriteHazard
 
bool HasSMEMtoVectorWriteHazard
 
bool HasInstFwdPrefetchBug
 
bool HasVcmpxExecWARHazard
 
bool HasLdsBranchVmemWARHazard
 
bool HasNSAtoVMEMBug
 
bool HasOffset3fBug
 
bool HasFlatSegmentOffsetBug
 
bool FeatureDisable
 
SelectionDAGTargetInfo TSInfo
 
- Protected Attributes inherited from llvm::AMDGPUSubtarget
bool Has16BitInsts
 
bool HasMadMixInsts
 
bool FP32Denormals
 
bool FPExceptions
 
bool HasSDWA
 
bool HasVOP3PInsts
 
bool HasMulI24
 
bool HasMulU24
 
bool HasInv2PiInlineImm
 
bool HasFminFmaxLegacy
 
bool EnablePromoteAlloca
 
bool HasTrigReducedRange
 
unsigned MaxWavesPerEU
 
int LocalMemorySize
 
unsigned WavefrontSize
 

Detailed Description

Definition at line 247 of file AMDGPUSubtarget.h.

Member Enumeration Documentation

◆ TrapHandlerAbi

enum llvm::GCNSubtarget::TrapHandlerAbi
Enumerator
TrapHandlerAbiNone 
TrapHandlerAbiHsa 

Definition at line 253 of file AMDGPUSubtarget.h.

◆ TrapID

enum llvm::GCNSubtarget::TrapID
Enumerator
TrapIDHardwareReserved 
TrapIDHSADebugTrap 
TrapIDLLVMTrap 
TrapIDLLVMDebugTrap 
TrapIDDebugBreakpoint 
TrapIDDebugReserved8 
TrapIDDebugReservedFE 
TrapIDDebugReservedFF 

Definition at line 258 of file AMDGPUSubtarget.h.

◆ TrapRegValues

enum llvm::GCNSubtarget::TrapRegValues
Enumerator
LLVMTrapHandlerRegValue 

Definition at line 269 of file AMDGPUSubtarget.h.

Constructor & Destructor Documentation

◆ GCNSubtarget()

GCNSubtarget::GCNSubtarget ( const Triple &  TT,
StringRef  GPU,
StringRef  FS,
const GCNTargetMachine &  TM 
)

Definition at line 183 of file AMDGPUSubtarget.cpp.

References llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), getTargetLowering(), and llvm::AMDGPUSubtarget::MaxWavesPerEU.

◆ ~GCNSubtarget()

GCNSubtarget::~GCNSubtarget ( )
overridedefault

Member Function Documentation

◆ computeOccupancy()

unsigned GCNSubtarget::computeOccupancy ( const MachineFunction &  MF,
unsigned  LDSSize = 0,
unsigned  NumSGPRs = 0,
unsigned  NumVGPRs = 0 
) const

Return occupancy for the given function.

Used LDS and a number of registers if provided. Note, occupancy can be affected by the scratch allocation as well, but we do not have enough information to compute it.

Definition at line 622 of file AMDGPUSubtarget.cpp.

References llvm::MachineFunction::getFunction(), llvm::AMDGPUSubtarget::getMaxWavesPerEU(), and llvm::AMDGPUSubtarget::getOccupancyWithLocalMemSize().

Referenced by hasAnyNonFlatUseOfReg(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ d16PreservesUnusedBits()

bool llvm::GCNSubtarget::d16PreservesUnusedBits ( ) const
inline

Definition at line 728 of file AMDGPUSubtarget.h.

◆ dumpCode()

bool llvm::GCNSubtarget::dumpCode ( ) const
inline

Definition at line 606 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::getMaxLocalMemSizeWithWaveCount().

Referenced by llvm::AMDGPUAsmPrinter::runOnMachineFunction().

◆ enableEarlyIfConversion()

bool llvm::GCNSubtarget::enableEarlyIfConversion ( ) const
inlineoverride

Definition at line 910 of file AMDGPUSubtarget.h.

◆ enableMachineScheduler()

bool llvm::GCNSubtarget::enableMachineScheduler ( ) const
inlineoverride

Definition at line 871 of file AMDGPUSubtarget.h.

◆ enableSIScheduler()

bool llvm::GCNSubtarget::enableSIScheduler ( ) const
inline

Definition at line 983 of file AMDGPUSubtarget.h.

Referenced by llvm::R600TargetMachine::createPassConfig().

◆ enableSubRegLiveness()

bool llvm::GCNSubtarget::enableSubRegLiveness ( ) const
inlineoverride

Definition at line 875 of file AMDGPUSubtarget.h.

◆ flatScratchIsPointer()

bool llvm::GCNSubtarget::flatScratchIsPointer ( ) const
inline
Returns
true if the flat_scratch register should be initialized with the pointer to the wave's scratch memory rather than a size and offset.

Definition at line 1070 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX9.

Referenced by buildEpilogReload().

◆ getAddressableNumSGPRs()

unsigned llvm::GCNSubtarget::getAddressableNumSGPRs ( ) const
inline
Returns
Addressable number of SGPRs supported by the subtarget.

Definition at line 1096 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs().

Referenced by hasAnyNonFlatUseOfReg().

◆ getAddressableNumVGPRs()

unsigned llvm::GCNSubtarget::getAddressableNumVGPRs ( ) const
inline
Returns
Addressable number of VGPRs supported by the subtarget.

Definition at line 1141 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs().

◆ getBoolRC()

const TargetRegisterClass* llvm::GCNSubtarget::getBoolRC ( ) const
inline

Definition at line 1175 of file AMDGPUSubtarget.h.

◆ getCallLowering()

const CallLowering* llvm::GCNSubtarget::getCallLowering ( ) const
inlineoverride

Definition at line 420 of file AMDGPUSubtarget.h.

◆ getConstantBusLimit()

unsigned GCNSubtarget::getConstantBusLimit ( unsigned  Opcode) const

Definition at line 291 of file AMDGPUSubtarget.cpp.

References getGeneration(), and llvm::AMDGPUSubtarget::GFX10.

Referenced by llvm::SIInstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::FoldImmediate(), hoistAndMergeSGPRInits(), llvm::SIInstrInfo::isOperandLegal(), and llvm::SIInstrInfo::verifyInstruction().

◆ getEUsPerCU()

unsigned llvm::GCNSubtarget::getEUsPerCU ( ) const
inline
Returns
Number of execution units per compute unit supported by the subtarget.

Definition at line 884 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getEUsPerCU().

◆ getFrameLowering()

const SIFrameLowering* llvm::GCNSubtarget::getFrameLowering ( ) const
inlineoverride

Definition at line 408 of file AMDGPUSubtarget.h.

Referenced by insertCSRRestores(), and reservePrivateMemoryRegs().

◆ getGeneration()

Generation llvm::GCNSubtarget::getGeneration ( ) const
inline

Definition at line 447 of file AMDGPUSubtarget.h.

Referenced by buildEpilogReload(), llvm::SITargetLowering::getAddrModeArguments(), getBufferOffsetForMMO(), getConstantBusLimit(), getLoadExtOrTrunc(), hasAnyNonFlatUseOfReg(), llvm::SITargetLowering::isLegalAddressingMode(), llvm::SITargetLowering::LowerFormalArguments(), matchSwap(), parseTexFail(), llvm::SIMachineFunctionInfo::SIMachineFunctionInfo(), llvm::AMDGPU::splitMUBUFOffset(), and subtargetEncodingFamily().

◆ getInstrInfo()

const SIInstrInfo* llvm::GCNSubtarget::getInstrInfo ( ) const
inlineoverride

Definition at line 404 of file AMDGPUSubtarget.h.

Referenced by addRegsToSet(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), bitOpWithConstantIsReducible(), buildEpilogReload(), buildMUBUFOffsetLoadStore(), llvm::SITargetLowering::bundleInstWithWaitcnt(), checkRegOnlyPHIInputs(), combineKnownAdjacentMMOs(), llvm::createSIAddIMGInitPass(), llvm::createSIModeRegisterPass(), llvm::SIFrameLowering::eliminateCallFramePseudoInstr(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), llvm::SIFrameLowering::emitEpilogue(), llvm::SITargetLowering::emitGWSMemViolTestLoop(), emitIndirectDst(), emitIndirectSrc(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::SIFrameLowering::emitPrologue(), findSingleRegDef(), fixupGlobalSaddr(), getPermuteMask(), llvm::SITargetLowering::getPrefLoopAlignment(), getSplatConstantFP(), llvm::SITargetLowering::getTgtMemIntrinsic(), hoistAndMergeSGPRInits(), llvm::SITargetLowering::insertCopiesSplitCSR(), insertCSRRestores(), insertUndefLaneMask(), isLiveOut(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), matchSwap(), llvm::SIRegisterInfo::materializeFrameBaseRegister(), optimizeVcndVcmpPair(), llvm::SITargetLowering::PostISelFolding(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::SIRegisterInfo::restoreSGPR(), llvm::AMDGPUAsmPrinter::runOnMachineFunction(), shrinkScalarCompare(), llvm::SIRegisterInfo::spillSGPR(), spillVGPRtoAGPR(), llvm::SITargetLowering::splitKillBlock(), and llvm::SITargetLowering::wrapAddr64Rsrc().

◆ getInstrItineraryData()

const InstrItineraryData* llvm::GCNSubtarget::getInstrItineraryData ( ) const
inlineoverride

Definition at line 441 of file AMDGPUSubtarget.h.

◆ getInstructionSelector()

InstructionSelector* llvm::GCNSubtarget::getInstructionSelector ( ) const
inlineoverride

Definition at line 424 of file AMDGPUSubtarget.h.

◆ getKnownHighZeroBitsForFrameIndex()

unsigned llvm::GCNSubtarget::getKnownHighZeroBitsForFrameIndex ( ) const
inline

Return the number of high bits known to be zero fror a frame index.

Definition at line 456 of file AMDGPUSubtarget.h.

References llvm::countLeadingZeros().

Referenced by llvm::SITargetLowering::LowerFormalArguments().

◆ getLDSBankCount()

int llvm::GCNSubtarget::getLDSBankCount ( ) const
inline

Definition at line 460 of file AMDGPUSubtarget.h.

Referenced by parseTexFail().

◆ getLegalizerInfo()

const LegalizerInfo* llvm::GCNSubtarget::getLegalizerInfo ( ) const
inlineoverride

Definition at line 428 of file AMDGPUSubtarget.h.

◆ getMaxFlatWorkGroupSize()

unsigned llvm::GCNSubtarget::getMaxFlatWorkGroupSize ( ) const
inlineoverridevirtual
Returns
Maximum flat work group size supported by the subtarget.

Implements llvm::AMDGPUSubtarget.

Definition at line 1191 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize().

Referenced by llvm::AMDGPUSubtarget::getFlatWorkGroupSizes().

◆ getMaxLocalMemSizeWithWaveCount()

unsigned llvm::GCNSubtarget::getMaxLocalMemSizeWithWaveCount ( unsigned  WaveCount,
const Function &   
) const

Return the amount of LDS that can be used that will not restrict the occupancy lower than WaveCount.

◆ getMaxNumSGPRs() [1/2]

unsigned llvm::GCNSubtarget::getMaxNumSGPRs ( unsigned  WavesPerEU,
bool  Addressable 
) const
inline
Returns
Maximum number of SGPRs that meets the given number of waves per execution unit requirement supported by the subtarget.

Definition at line 1108 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getMaxNumSGPRs().

Referenced by getAllSGPR128(), getAllSGPRs(), llvm::SIRegisterInfo::getRegPressureLimit(), llvm::SIRegisterInfo::getReservedRegs(), llvm::GCNMaxOccupancySchedStrategy::initialize(), llvm::SIRegisterInfo::reservedPrivateSegmentBufferReg(), and llvm::SIRegisterInfo::reservedPrivateSegmentWaveByteOffsetReg().

◆ getMaxNumSGPRs() [2/2]

unsigned GCNSubtarget::getMaxNumSGPRs ( const MachineFunction &  MF) const
Returns
Maximum number of SGPRs that meets number of waves per execution unit requirement for function MF, or number of SGPRs explicitly requested using "amdgpu-num-sgpr" attribute attached to function MF.
Value that meets number of waves per execution unit requirement if explicitly requested value cannot be converted to integer, violates subtarget's specifications, or does not meet number of waves per execution unit requirement.

Definition at line 636 of file AMDGPUSubtarget.cpp.

References F(), llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG, llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::AMDGPU::getIntegerAttribute(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), llvm::SIMachineFunctionInfo::getNumPreloadedSGPRs(), llvm::SIMachineFunctionInfo::getWavesPerEU(), and llvm::Function::hasFnAttribute().

◆ getMaxNumUserSGPRs()

unsigned llvm::GCNSubtarget::getMaxNumUserSGPRs ( ) const
inline

Definition at line 917 of file AMDGPUSubtarget.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ getMaxNumVGPRs() [1/2]

unsigned llvm::GCNSubtarget::getMaxNumVGPRs ( unsigned  WavesPerEU) const
inline
Returns
Maximum number of VGPRs that meets given number of waves per execution unit requirement supported by the subtarget.

Definition at line 1153 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getMaxNumVGPRs().

Referenced by llvm::SIRegisterInfo::getRegPressureLimit(), llvm::SIRegisterInfo::getReservedRegs(), and llvm::GCNMaxOccupancySchedStrategy::initialize().

◆ getMaxNumVGPRs() [2/2]

unsigned GCNSubtarget::getMaxNumVGPRs ( const MachineFunction &  MF) const
Returns
Maximum number of VGPRs that meets number of waves per execution unit requirement for function MF, or number of VGPRs explicitly requested using "amdgpu-num-vgpr" attribute attached to function MF.
Value that meets number of waves per execution unit requirement if explicitly requested value cannot be converted to integer, violates subtarget's specifications, or does not meet number of waves per execution unit requirement.

Definition at line 686 of file AMDGPUSubtarget.cpp.

References llvm::SUnit::addPred(), llvm::SUnit::addPredBarrier(), llvm::cl::apply(), llvm::SDep::Artificial, llvm::SmallPtrSetImpl< PtrType >::count(), llvm::dbgs(), DisablePowerSched, llvm::ScheduleDAGInstrs::dumpNode(), E, llvm::ScheduleDAG::ExitSU, F(), llvm::find(), From, llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::SUnit::getInstr(), llvm::AMDGPU::getIntegerAttribute(), llvm::AMDGPU::IsaInfo::getMaxNumVGPRs(), llvm::AMDGPU::IsaInfo::getMinNumVGPRs(), llvm::MachineInstr::getOpcode(), llvm::ScheduleDAGInstrs::getSchedModel(), llvm::MachineFunction::getSubtarget(), llvm::SDep::getSUnit(), llvm::SIMachineFunctionInfo::getWavesPerEU(), llvm::Function::hasFnAttribute(), hasMAIInsts(), I, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SIInstrInfo::isDS(), llvm::SIInstrInfo::isFLAT(), llvm::SIInstrInfo::isMAI(), llvm::SIInstrInfo::isSALU(), llvm::SIInstrInfo::isSMRD(), llvm::MachineInstr::isTerminator(), llvm::SIInstrInfo::isVALU(), llvm::SIInstrInfo::isVMEM(), LLVM_DEBUG, llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayStore(), llvm::ScheduleDAG::MF, MI, llvm::SUnit::NodeNum, llvm::SUnit::Preds, SI, llvm::ARM_MB::ST, llvm::SUnit::Succs, llvm::ScheduleDAG::SUnits, and TII.

◆ getMaxPrivateElementSize()

unsigned llvm::GCNSubtarget::getMaxPrivateElementSize ( ) const
inline

Definition at line 464 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::canMergeStoresTo(), getLoadExtOrTrunc(), and getSPDenormModeValue().

◆ getMaxWavesPerCU() [1/2]

unsigned llvm::GCNSubtarget::getMaxWavesPerCU ( ) const
inline
Returns
Maximum number of waves per compute unit supported by the subtarget without any kind of limitation.

Definition at line 890 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getMaxWavesPerCU().

◆ getMaxWavesPerCU() [2/2]

unsigned llvm::GCNSubtarget::getMaxWavesPerCU ( unsigned  FlatWorkGroupSize) const
inline
Returns
Maximum number of waves per compute unit supported by the subtarget and limited by given FlatWorkGroupSize.

Definition at line 896 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getMaxWavesPerCU().

◆ getMaxWavesPerEU()

unsigned llvm::GCNSubtarget::getMaxWavesPerEU ( unsigned  FlatWorkGroupSize) const
inlineoverridevirtual
Returns
Maximum number of waves per execution unit supported by the subtarget and limited by given FlatWorkGroupSize.

Implements llvm::AMDGPUSubtarget.

Definition at line 1197 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getMaxWavesPerEU().

◆ getMaxWorkGroupsPerCU()

unsigned llvm::GCNSubtarget::getMaxWorkGroupsPerCU ( unsigned  FlatWorkGroupSize) const
inlineoverridevirtual
Returns
Maximum number of work groups per compute unit supported by the subtarget and limited by given FlatWorkGroupSize.

Implements llvm::AMDGPUSubtarget.

Definition at line 1181 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU().

Referenced by llvm::AMDGPUSubtarget::getMaxLocalMemSizeWithWaveCount(), and llvm::AMDGPUSubtarget::getOccupancyWithLocalMemSize().

◆ getMinFlatWorkGroupSize()

unsigned llvm::GCNSubtarget::getMinFlatWorkGroupSize ( ) const
inlineoverridevirtual
Returns
Minimum flat work group size supported by the subtarget.

Implements llvm::AMDGPUSubtarget.

Definition at line 1186 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize().

Referenced by llvm::AMDGPUSubtarget::getFlatWorkGroupSizes().

◆ getMinNumSGPRs()

unsigned llvm::GCNSubtarget::getMinNumSGPRs ( unsigned  WavesPerEU) const
inline
Returns
Minimum number of SGPRs that meets the given number of waves per execution unit requirement supported by the subtarget.

Definition at line 1102 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getMinNumSGPRs().

Referenced by hasAnyNonFlatUseOfReg().

◆ getMinNumVGPRs()

unsigned llvm::GCNSubtarget::getMinNumVGPRs ( unsigned  WavesPerEU) const
inline
Returns
Minimum number of VGPRs that meets given number of waves per execution unit requirement supported by the subtarget.

Definition at line 1147 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getMinNumVGPRs().

Referenced by hasAnyNonFlatUseOfReg().

◆ getMinWavesPerEU()

unsigned llvm::GCNSubtarget::getMinWavesPerEU ( ) const
inlineoverridevirtual
Returns
Minimum number of waves per execution unit supported by the subtarget.

Implements llvm::AMDGPUSubtarget.

Definition at line 1203 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getMinWavesPerEU().

Referenced by llvm::AMDGPUSubtarget::getWavesPerEU().

◆ getOccupancyWithNumSGPRs()

unsigned GCNSubtarget::getOccupancyWithNumSGPRs ( unsigned  SGPRs) const

Return the maximum number of waves per SIMD for kernels using SGPRs SGPRs.

Definition at line 570 of file AMDGPUSubtarget.cpp.

References llvm::R600Subtarget::getGeneration(), llvm::AMDGPUSubtarget::getMaxWavesPerEU(), llvm::AMDGPUSubtarget::GFX10, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by llvm::GCNRegPressure::getOccupancy(), llvm::GCNRegPressure::less(), and llvm::GCNRegPressure::print().

◆ getOccupancyWithNumVGPRs()

unsigned GCNSubtarget::getOccupancyWithNumVGPRs ( unsigned  VGPRs) const

Return the maximum number of waves per SIMD for kernels using VGPRs VGPRs.

Definition at line 596 of file AMDGPUSubtarget.cpp.

References llvm::AMDGPUSubtarget::getMaxWavesPerEU(), llvm::AMDGPU::IsaInfo::getTotalNumVGPRs(), llvm::AMDGPU::IsaInfo::getVGPRAllocGranule(), and llvm::max().

Referenced by llvm::GCNRegPressure::getOccupancy(), llvm::GCNRegPressure::less(), and llvm::GCNRegPressure::print().

◆ getPostRAMutations()

void GCNSubtarget::getPostRAMutations ( std::vector< std::unique_ptr< ScheduleDAGMutation >> &  Mutations) const
override

Definition at line 883 of file AMDGPUSubtarget.cpp.

◆ getRegBankInfo()

const RegisterBankInfo* llvm::GCNSubtarget::getRegBankInfo ( ) const
inlineoverride

Definition at line 432 of file AMDGPUSubtarget.h.

◆ getRegisterInfo()

const SIRegisterInfo* llvm::GCNSubtarget::getRegisterInfo ( ) const
inlineoverride

Definition at line 416 of file AMDGPUSubtarget.h.

References llvm::SIInstrInfo::getRegisterInfo().

Referenced by addRegsToSet(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::SIMachineFunctionInfo::allocateSGPRSpillToVGPR(), llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR(), callWaitsOnFunctionReturn(), checkRegOnlyPHIInputs(), llvm::createSIAddIMGInitPass(), llvm::createSIPreAllocateWWMRegsPass(), llvm::createSIWholeQuadModePass(), llvm::SIFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::determineCalleeSavesSGPR(), llvm::SIFrameLowering::emitEpilogue(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), emitLoadM0FromVGPRLoop(), emitLoadSRsrcFromVGPRLoop(), llvm::SITargetLowering::finalizeLowering(), findSingleRegDef(), fixupGlobalSaddr(), getOModValue(), llvm::SITargetLowering::getRegClassFor(), llvm::SITargetLowering::getRegisterByName(), getWaitStatesSince(), hoistAndMergeSGPRInits(), llvm::SITargetLowering::insertCopiesSplitCSR(), insertCSRRestores(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), isLiveOut(), loadM0FromVGPR(), loadSRsrcFromVGPR(), llvm::SITargetLowering::LowerCall(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArgumentsKernel(), llvm::SITargetLowering::LowerReturn(), optimizeVcndVcmpPair(), llvm::SITargetLowering::passSpecialInputs(), llvm::SIFrameLowering::processFunctionBeforeFrameFinalized(), llvm::SITargetLowering::requiresUniformRegister(), selectSGPRVectorRegClassID(), llvm::SITargetLowering::shouldEmitPCReloc(), and llvm::SITargetLowering::SITargetLowering().

◆ getReservedNumSGPRs()

unsigned GCNSubtarget::getReservedNumSGPRs ( const MachineFunction &  MF) const
Returns
Reserved number of SGPRs for given function MF.

Definition at line 605 of file AMDGPUSubtarget.cpp.

References llvm::R600Subtarget::getGeneration(), llvm::MachineFunction::getInfo(), llvm::AMDGPUSubtarget::GFX10, llvm::SIMachineFunctionInfo::hasFlatScratchInit(), llvm::AMDGPUSubtarget::SEA_ISLANDS, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

◆ getScalarizeGlobalBehavior()

bool llvm::GCNSubtarget::getScalarizeGlobalBehavior ( ) const
inline

Definition at line 880 of file AMDGPUSubtarget.h.

References ScalarizeGlobal.

Referenced by getLoadExtOrTrunc().

◆ getSelectionDAGInfo()

const SelectionDAGTargetInfo* llvm::GCNSubtarget::getSelectionDAGInfo ( ) const
inlineoverride

Definition at line 437 of file AMDGPUSubtarget.h.

◆ getSetRegWaitStates()

unsigned llvm::GCNSubtarget::getSetRegWaitStates ( ) const
inline

Number of hazard wait states for s_setreg_b32/s_setreg_imm32_b32.

Definition at line 602 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::SEA_ISLANDS.

Referenced by addRegsToSet().

◆ getSGPRAllocGranule()

unsigned llvm::GCNSubtarget::getSGPRAllocGranule ( ) const
inline
Returns
SGPR allocation granularity supported by the subtarget.

Definition at line 1081 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getSGPRAllocGranule().

◆ getSGPREncodingGranule()

unsigned llvm::GCNSubtarget::getSGPREncodingGranule ( ) const
inline
Returns
SGPR encoding granularity supported by the subtarget.

Definition at line 1086 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getSGPREncodingGranule().

◆ getStackAlignment()

Align llvm::GCNSubtarget::getStackAlignment ( ) const
inline

Definition at line 869 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align.

Referenced by llvm::SITargetLowering::LowerCall().

◆ getTargetLowering()

const SITargetLowering* llvm::GCNSubtarget::getTargetLowering ( ) const
inlineoverride

Definition at line 412 of file AMDGPUSubtarget.h.

Referenced by combineKnownAdjacentMMOs(), GCNSubtarget(), and llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast().

◆ getTotalNumSGPRs()

unsigned llvm::GCNSubtarget::getTotalNumSGPRs ( ) const
inline
Returns
Total number of SGPRs supported by the subtarget.

Definition at line 1091 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getTotalNumSGPRs().

◆ getTotalNumVGPRs()

unsigned llvm::GCNSubtarget::getTotalNumVGPRs ( ) const
inline
Returns
Total number of VGPRs supported by the subtarget.

Definition at line 1136 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getTotalNumVGPRs().

◆ getTrapHandlerAbi()

TrapHandlerAbi llvm::GCNSubtarget::getTrapHandlerAbi ( ) const
inline

Definition at line 560 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::isAmdHsaOS().

Referenced by llvm::SITargetLowering::shouldEmitPCReloc().

◆ getVGPRAllocGranule()

unsigned llvm::GCNSubtarget::getVGPRAllocGranule ( ) const
inline
Returns
VGPR allocation granularity supported by the subtarget.

Definition at line 1126 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getVGPRAllocGranule().

◆ getVGPREncodingGranule()

unsigned llvm::GCNSubtarget::getVGPREncodingGranule ( ) const
inline
Returns
VGPR encoding granularity supported by the subtarget.

Definition at line 1131 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getVGPREncodingGranule().

◆ getWavefrontSizeLog2()

unsigned llvm::GCNSubtarget::getWavefrontSizeLog2 ( ) const
inline

Definition at line 451 of file AMDGPUSubtarget.h.

References llvm::Log2_32(), and llvm::AMDGPUSubtarget::WavefrontSize.

Referenced by llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), and llvm::SIRegisterInfo::eliminateFrameIndex().

◆ getWavesPerWorkGroup()

unsigned llvm::GCNSubtarget::getWavesPerWorkGroup ( unsigned  FlatWorkGroupSize) const
inline
Returns
Number of waves per work group supported by the subtarget and limited by given FlatWorkGroupSize.

Definition at line 902 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup().

◆ has12DWordStoreHazard()

bool llvm::GCNSubtarget::has12DWordStoreHazard ( ) const
inline

Definition at line 999 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::SOUTHERN_ISLANDS.

Referenced by addRegsToSet().

◆ hasAddNoCarry()

bool llvm::GCNSubtarget::hasAddNoCarry ( ) const
inline

Definition at line 756 of file AMDGPUSubtarget.h.

Referenced by getLogicalBitOpcode().

◆ hasAddr64()

bool llvm::GCNSubtarget::hasAddr64 ( ) const
inline

Definition at line 494 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by llvm::SITargetLowering::isLegalGlobalAddressingMode().

◆ hasApertureRegs()

bool llvm::GCNSubtarget::hasApertureRegs ( ) const
inline

Definition at line 676 of file AMDGPUSubtarget.h.

Referenced by llvm::AMDGPULegalizerInfo::getSegmentAperture(), and llvm::SITargetLowering::shouldEmitPCReloc().

◆ hasAtomicFaddInsts()

bool llvm::GCNSubtarget::hasAtomicFaddInsts ( ) const
inline

Definition at line 829 of file AMDGPUSubtarget.h.

◆ hasAutoWaitcntBeforeBarrier()

bool llvm::GCNSubtarget::hasAutoWaitcntBeforeBarrier ( ) const
inline

Definition at line 659 of file AMDGPUSubtarget.h.

◆ hasBCNT()

bool llvm::GCNSubtarget::hasBCNT ( unsigned  Size) const
inline

Definition at line 516 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::SITargetLowering().

◆ hasBFE()

bool llvm::GCNSubtarget::hasBFE ( ) const
inline

Definition at line 504 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::SITargetLowering().

◆ hasBFI()

bool llvm::GCNSubtarget::hasBFI ( ) const
inline

Definition at line 508 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::SITargetLowering().

◆ hasBFM()

bool llvm::GCNSubtarget::hasBFM ( ) const
inline

Definition at line 512 of file AMDGPUSubtarget.h.

◆ hasCARRY()

bool llvm::GCNSubtarget::hasCARRY ( ) const
inline

Definition at line 540 of file AMDGPUSubtarget.h.

◆ hasCodeObjectV3()

bool llvm::GCNSubtarget::hasCodeObjectV3 ( ) const
inline

Definition at line 663 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::isAmdHsaOS().

Referenced by llvm::AMDGPUAsmPrinter::EmitFunctionBodyStart().

◆ hasD16Images()

bool llvm::GCNSubtarget::hasD16Images ( ) const
inline

Definition at line 732 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by parseTexFail().

◆ hasD16LoadStore()

bool llvm::GCNSubtarget::hasD16LoadStore ( ) const
inline

Definition at line 724 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX9.

◆ hasDenormModeInst()

bool llvm::GCNSubtarget::hasDenormModeInst ( ) const
inline
Returns
If target supports S_DENORM_MODE.

Definition at line 628 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX10.

Referenced by getSPDenormModeValue().

◆ hasDLInsts()

bool llvm::GCNSubtarget::hasDLInsts ( ) const
inline

Definition at line 793 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd().

◆ hasDot1Insts()

bool llvm::GCNSubtarget::hasDot1Insts ( ) const
inline

Definition at line 797 of file AMDGPUSubtarget.h.

◆ hasDot2Insts()

bool llvm::GCNSubtarget::hasDot2Insts ( ) const
inline

Definition at line 801 of file AMDGPUSubtarget.h.

◆ hasDot3Insts()

bool llvm::GCNSubtarget::hasDot3Insts ( ) const
inline

Definition at line 805 of file AMDGPUSubtarget.h.

◆ hasDot4Insts()

bool llvm::GCNSubtarget::hasDot4Insts ( ) const
inline

Definition at line 809 of file AMDGPUSubtarget.h.

◆ hasDot5Insts()

bool llvm::GCNSubtarget::hasDot5Insts ( ) const
inline

Definition at line 813 of file AMDGPUSubtarget.h.

◆ hasDot6Insts()

bool llvm::GCNSubtarget::hasDot6Insts ( ) const
inline

Definition at line 817 of file AMDGPUSubtarget.h.

◆ hasDPP()

bool llvm::GCNSubtarget::hasDPP ( ) const
inline

Definition at line 953 of file AMDGPUSubtarget.h.

◆ hasDPP8()

bool llvm::GCNSubtarget::hasDPP8 ( ) const
inline

Definition at line 965 of file AMDGPUSubtarget.h.

◆ hasDPPBroadcasts()

bool llvm::GCNSubtarget::hasDPPBroadcasts ( ) const
inline

Definition at line 957 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX10.

◆ hasDPPWavefrontShifts()

bool llvm::GCNSubtarget::hasDPPWavefrontShifts ( ) const
inline

Definition at line 961 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX10.

◆ hasDwordx3LoadStores()

bool llvm::GCNSubtarget::hasDwordx3LoadStores ( ) const
inline

Definition at line 1004 of file AMDGPUSubtarget.h.

Referenced by combineKnownAdjacentMMOs(), getBufferOffsetForMMO(), getLoadExtOrTrunc(), and getSPDenormModeValue().

◆ hasFastFMAF32()

bool llvm::GCNSubtarget::hasFastFMAF32 ( ) const
inline

Definition at line 486 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd().

◆ hasFFBH()

bool llvm::GCNSubtarget::hasFFBH ( ) const
inline

Definition at line 524 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::SITargetLowering().

◆ hasFFBL()

bool llvm::GCNSubtarget::hasFFBL ( ) const
inline

Definition at line 520 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::SITargetLowering().

◆ hasFlatAddressSpace()

bool llvm::GCNSubtarget::hasFlatAddressSpace ( ) const
inline

Definition at line 692 of file AMDGPUSubtarget.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::SIMachineFunctionInfo::SIMachineFunctionInfo(), and llvm::SITargetLowering::SITargetLowering().

◆ hasFlatGlobalInsts()

bool llvm::GCNSubtarget::hasFlatGlobalInsts ( ) const
inline

Definition at line 704 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::isLegalGlobalAddressingMode().

◆ hasFlatInstOffsets()

bool llvm::GCNSubtarget::hasFlatInstOffsets ( ) const
inline

Definition at line 700 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::getAddrModeArguments(), and llvm::AMDGPUInstructionSelector::select().

◆ hasFlatLgkmVMemCountInOrder()

bool llvm::GCNSubtarget::hasFlatLgkmVMemCountInOrder ( ) const
inline

Definition at line 720 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX9.

◆ hasFlatScratchInsts()

bool llvm::GCNSubtarget::hasFlatScratchInsts ( ) const
inline

Definition at line 708 of file AMDGPUSubtarget.h.

◆ hasFlatScrRegister()

bool llvm::GCNSubtarget::hasFlatScrRegister ( ) const
inline

Definition at line 696 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::getRegisterByName().

◆ hasFlatSegmentOffsetBug()

bool llvm::GCNSubtarget::hasFlatSegmentOffsetBug ( ) const
inline

Definition at line 716 of file AMDGPUSubtarget.h.

◆ hasFMA()

bool llvm::GCNSubtarget::hasFMA ( ) const
inline

Definition at line 544 of file AMDGPUSubtarget.h.

References llvm::ISD::FMA.

◆ hasFmaMixInsts()

bool llvm::GCNSubtarget::hasFmaMixInsts ( ) const
inline

Definition at line 536 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::isFPExtFoldable().

◆ hasFP16Denormals()

bool llvm::GCNSubtarget::hasFP16Denormals ( ) const
inline

Definition at line 615 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::denormalsEnabledForType(), isClampZeroToOne(), llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(), and llvm::SITargetLowering::SITargetLowering().

◆ hasFP64()

bool llvm::GCNSubtarget::hasFP64 ( ) const
inline

Definition at line 474 of file AMDGPUSubtarget.h.

◆ hasFP64Denormals()

bool llvm::GCNSubtarget::hasFP64Denormals ( ) const
inline

Definition at line 619 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::denormalsEnabledForType(), getFPMode(), and getSPDenormModeValue().

◆ hasGWSAutoReplay()

bool llvm::GCNSubtarget::hasGWSAutoReplay ( ) const
inline

Definition at line 747 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX9.

◆ hasGWSSemaReleaseAll()

bool llvm::GCNSubtarget::hasGWSSemaReleaseAll ( ) const
inline
Returns
if target has ds_gws_sema_release_all instruction.

Definition at line 752 of file AMDGPUSubtarget.h.

◆ hasHalfRate64Ops() [1/2]

bool llvm::GCNSubtarget::hasHalfRate64Ops ( ) const
inline

Definition at line 490 of file AMDGPUSubtarget.h.

◆ hasHalfRate64Ops() [2/2]

static bool llvm::GCNSubtarget::hasHalfRate64Ops ( const TargetSubtargetInfo &  STI)
static

◆ hasHWFP64()

bool llvm::GCNSubtarget::hasHWFP64 ( ) const
inline

Definition at line 482 of file AMDGPUSubtarget.h.

◆ hasInstFwdPrefetchBug()

bool llvm::GCNSubtarget::hasInstFwdPrefetchBug ( ) const
inline

Definition at line 1037 of file AMDGPUSubtarget.h.

◆ hasIntClamp()

bool llvm::GCNSubtarget::hasIntClamp ( ) const
inline

Definition at line 470 of file AMDGPUSubtarget.h.

◆ hasLdsBranchVmemWARHazard()

bool llvm::GCNSubtarget::hasLdsBranchVmemWARHazard ( ) const
inline

Definition at line 1045 of file AMDGPUSubtarget.h.

Referenced by addRegsToSet().

◆ hasLDSFPAtomics()

bool llvm::GCNSubtarget::hasLDSFPAtomics ( ) const
inline

Definition at line 949 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::shouldExpandAtomicRMWInIR().

◆ hasLDSMisalignedBug()

bool llvm::GCNSubtarget::hasLDSMisalignedBug ( ) const
inline

Definition at line 1033 of file AMDGPUSubtarget.h.

Referenced by getLoadExtOrTrunc(), and getSPDenormModeValue().

◆ hasMad64_32()

bool llvm::GCNSubtarget::hasMad64_32 ( ) const
inline

Definition at line 769 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::SEA_ISLANDS.

Referenced by getMad64_32().

◆ hasMadF16()

bool GCNSubtarget::hasMadF16 ( ) const

Definition at line 566 of file AMDGPUSubtarget.cpp.

Referenced by isClampZeroToOne(), and llvm::SITargetLowering::SITargetLowering().

◆ hasMAIInsts()

bool llvm::GCNSubtarget::hasMAIInsts ( ) const
inline

Definition at line 821 of file AMDGPUSubtarget.h.

Referenced by addRegsToSet(), llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR(), getMaxNumVGPRs(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::SIRegisterInfo::getReservedRegs(), insertCSRRestores(), llvm::AMDGPUAsmPrinter::runOnMachineFunction(), and llvm::SITargetLowering::SITargetLowering().

◆ hasMed3_16()

bool llvm::GCNSubtarget::hasMed3_16 ( ) const
inline

Definition at line 528 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX9.

Referenced by getSplatConstantFP(), and minMaxOpcToMin3Max3Opc().

◆ hasMergedShaders()

bool llvm::GCNSubtarget::hasMergedShaders ( ) const
inline
Returns
true if the machine has merged shaders in which s0-s7 are reserved by the hardware and user SGPRs start at s8

Definition at line 1076 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX9.

Referenced by llvm::SIFrameLowering::emitEntryFunctionPrologue().

◆ hasMFMAInlineLiteralBug()

bool llvm::GCNSubtarget::hasMFMAInlineLiteralBug ( ) const
inline

Definition at line 995 of file AMDGPUSubtarget.h.

Referenced by llvm::SIInstrInfo::isImmOperandLegal(), and llvm::SIRegisterInfo::opCanUseInlineConstant().

◆ hasMIMG_R128()

bool llvm::GCNSubtarget::hasMIMG_R128 ( ) const
inline

Definition at line 478 of file AMDGPUSubtarget.h.

◆ hasMin3Max3_16()

bool llvm::GCNSubtarget::hasMin3Max3_16 ( ) const
inline

Definition at line 532 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX9.

Referenced by getSplatConstantFP().

◆ hasMovrel()

bool llvm::GCNSubtarget::hasMovrel ( ) const
inline

Definition at line 925 of file AMDGPUSubtarget.h.

◆ hasNoDataDepHazard()

bool llvm::GCNSubtarget::hasNoDataDepHazard ( ) const
inline

Definition at line 853 of file AMDGPUSubtarget.h.

Referenced by llvm::GCNHazardRecognizer::getHazardType(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().

◆ hasNoSdstCMPX()

bool llvm::GCNSubtarget::hasNoSdstCMPX ( ) const
inline

Definition at line 837 of file AMDGPUSubtarget.h.

◆ hasNSAEncoding()

bool llvm::GCNSubtarget::hasNSAEncoding ( ) const
inline

Definition at line 977 of file AMDGPUSubtarget.h.

◆ hasNSAtoVMEMBug()

bool llvm::GCNSubtarget::hasNSAtoVMEMBug ( ) const
inline

Definition at line 1049 of file AMDGPUSubtarget.h.

References llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumSGPRs, and llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumVGPRs.

Referenced by addRegsToSet(), llvm::GCNHazardRecognizer::getHazardType(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().

◆ hasOffset3fBug()

bool llvm::GCNSubtarget::hasOffset3fBug ( ) const
inline

Definition at line 973 of file AMDGPUSubtarget.h.

◆ hasOnlyRevVALUShifts()

bool llvm::GCNSubtarget::hasOnlyRevVALUShifts ( ) const
inline

Definition at line 500 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

◆ hasPkFmacF16Inst()

bool llvm::GCNSubtarget::hasPkFmacF16Inst ( ) const
inline

Definition at line 825 of file AMDGPUSubtarget.h.

◆ hasR128A16()

bool llvm::GCNSubtarget::hasR128A16 ( ) const
inline

Definition at line 969 of file AMDGPUSubtarget.h.

◆ hasReadM0MovRelInterpHazard()

bool llvm::GCNSubtarget::hasReadM0MovRelInterpHazard ( ) const
inline

Definition at line 1012 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX9.

Referenced by llvm::GCNHazardRecognizer::getHazardType(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().

◆ hasReadM0SendMsgHazard()

bool llvm::GCNSubtarget::hasReadM0SendMsgHazard ( ) const
inline

Definition at line 1016 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX9, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by llvm::GCNHazardRecognizer::getHazardType(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().

◆ hasReadVCCZBug()

bool llvm::GCNSubtarget::hasReadVCCZBug ( ) const
inline

Extra wait hazard is needed in some cases before s_cbranch_vccnz/s_cbranch_vccz.

Definition at line 581 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::SEA_ISLANDS.

◆ hasRegisterBanking()

bool llvm::GCNSubtarget::hasRegisterBanking ( ) const
inline

Definition at line 845 of file AMDGPUSubtarget.h.

◆ hasRFEHazards()

bool llvm::GCNSubtarget::hasRFEHazards ( ) const
inline

Definition at line 597 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by addRegsToSet().

◆ hasScalarAtomics()

bool llvm::GCNSubtarget::hasScalarAtomics ( ) const
inline

Definition at line 945 of file AMDGPUSubtarget.h.

◆ hasScalarCompareEq64()

bool llvm::GCNSubtarget::hasScalarCompareEq64 ( ) const
inline

Definition at line 937 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by llvm::AMDGPURegisterBankInfo::getInstrMapping(), and getV_CMPOpcode().

◆ hasScalarFlatScratchInsts()

bool llvm::GCNSubtarget::hasScalarFlatScratchInsts ( ) const
inline

Definition at line 712 of file AMDGPUSubtarget.h.

◆ hasScalarMulHiInsts()

bool llvm::GCNSubtarget::hasScalarMulHiInsts ( ) const
inline

Definition at line 556 of file AMDGPUSubtarget.h.

Referenced by llvm::AMDGPURegisterBankInfo::getInstrMapping().

◆ hasScalarPackInsts()

bool llvm::GCNSubtarget::hasScalarPackInsts ( ) const
inline

Definition at line 552 of file AMDGPUSubtarget.h.

◆ hasScalarStores()

bool llvm::GCNSubtarget::hasScalarStores ( ) const
inline

Definition at line 941 of file AMDGPUSubtarget.h.

◆ hasSDWAMac()

bool llvm::GCNSubtarget::hasSDWAMac ( ) const
inline

Definition at line 785 of file AMDGPUSubtarget.h.

Referenced by findSingleRegDef().

◆ hasSDWAOmod()

bool llvm::GCNSubtarget::hasSDWAOmod ( ) const
inline

Definition at line 773 of file AMDGPUSubtarget.h.

Referenced by findSingleRegDef(), and llvm::SIInstrInfo::verifyInstruction().

◆ hasSDWAOutModsVOPC()

bool llvm::GCNSubtarget::hasSDWAOutModsVOPC ( ) const
inline

Definition at line 789 of file AMDGPUSubtarget.h.

Referenced by findSingleRegDef(), and llvm::SIInstrInfo::verifyInstruction().

◆ hasSDWAScalar()

bool llvm::GCNSubtarget::hasSDWAScalar ( ) const
inline

Definition at line 777 of file AMDGPUSubtarget.h.

Referenced by findSingleRegDef(), and llvm::SIInstrInfo::verifyInstruction().

◆ hasSDWASdst()

bool llvm::GCNSubtarget::hasSDWASdst ( ) const
inline

Definition at line 781 of file AMDGPUSubtarget.h.

Referenced by findSingleRegDef(), and llvm::SIInstrInfo::verifyInstruction().

◆ hasSGPRInitBug()

bool llvm::GCNSubtarget::hasSGPRInitBug ( ) const
inline

Definition at line 991 of file AMDGPUSubtarget.h.

Referenced by buildEpilogReload(), and hasAnyNonFlatUseOfReg().

◆ hasSMemRealTime()

bool llvm::GCNSubtarget::hasSMemRealTime ( ) const
inline

Definition at line 921 of file AMDGPUSubtarget.h.

◆ hasSMEMtoVectorWriteHazard()

bool llvm::GCNSubtarget::hasSMEMtoVectorWriteHazard ( ) const
inline

Definition at line 1029 of file AMDGPUSubtarget.h.

Referenced by addRegsToSet().

◆ hasSMovFedHazard()

bool llvm::GCNSubtarget::hasSMovFedHazard ( ) const
inline

Definition at line 1008 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX9.

Referenced by addRegsToSet().

◆ hasSMRDReadVALUDefHazard()

bool llvm::GCNSubtarget::hasSMRDReadVALUDefHazard ( ) const
inline

A read of an SGPR by SMRD instruction requires 4 wait states when the SGPR was written by a VALU instruction.

Definition at line 587 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::SOUTHERN_ISLANDS.

Referenced by addRegsToSet().

◆ hasSwap()

bool llvm::GCNSubtarget::hasSwap ( ) const
inline

Definition at line 548 of file AMDGPUSubtarget.h.

Referenced by matchSwap().

◆ hasUnalignedBufferAccess()

bool llvm::GCNSubtarget::hasUnalignedBufferAccess ( ) const
inline

Definition at line 668 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl().

◆ hasUnalignedScratchAccess()

bool llvm::GCNSubtarget::hasUnalignedScratchAccess ( ) const
inline

Definition at line 672 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl().

◆ hasUnpackedD16VMem()

bool llvm::GCNSubtarget::hasUnpackedD16VMem ( ) const
inline

Definition at line 760 of file AMDGPUSubtarget.h.

Referenced by adjustLoadValueTypeImpl(), llvm::createSIAddIMGInitPass(), getBufferOffsetForMMO(), parseTexFail(), substituteSimpleCopyRegs(), and llvm::SIInstrInfo::verifyInstruction().

◆ hasUsableDivScaleConditionOutput()

bool llvm::GCNSubtarget::hasUsableDivScaleConditionOutput ( ) const
inline

Condition output from div_scale is usable.

Definition at line 575 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::SOUTHERN_ISLANDS.

Referenced by getSPDenormModeValue().

◆ hasUsableDSOffset()

bool llvm::GCNSubtarget::hasUsableDSOffset ( ) const
inline

True if the offset field of DS instructions works as expected.

On SI, the offset uses a 16-bit adder and does not always wrap properly.

Definition at line 566 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::SEA_ISLANDS.

Referenced by getSPDenormModeValue(), and isStackPtrRelative().

◆ hasVcmpxExecWARHazard()

bool llvm::GCNSubtarget::hasVcmpxExecWARHazard ( ) const
inline

Definition at line 1041 of file AMDGPUSubtarget.h.

Referenced by addRegsToSet().

◆ hasVcmpxPermlaneHazard()

bool llvm::GCNSubtarget::hasVcmpxPermlaneHazard ( ) const
inline

Definition at line 1021 of file AMDGPUSubtarget.h.

Referenced by addRegsToSet().

◆ hasVGPRIndexMode()

bool llvm::GCNSubtarget::hasVGPRIndexMode ( ) const
inline

Definition at line 929 of file AMDGPUSubtarget.h.

◆ hasVMEMReadSGPRVALUDefHazard()

bool llvm::GCNSubtarget::hasVMEMReadSGPRVALUDefHazard ( ) const
inline

A read of an SGPR by a VMEM instruction requires 5 wait states when the SGPR was written by a VALU Instruction.

Definition at line 593 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by addRegsToSet().

◆ hasVMEMtoScalarWriteHazard()

bool llvm::GCNSubtarget::hasVMEMtoScalarWriteHazard ( ) const
inline

Definition at line 1025 of file AMDGPUSubtarget.h.

Referenced by addRegsToSet().

◆ hasVOP3Literal()

bool llvm::GCNSubtarget::hasVOP3Literal ( ) const
inline

Definition at line 849 of file AMDGPUSubtarget.h.

Referenced by llvm::SIInstrInfo::isImmOperandLegal(), llvm::SIInstrInfo::isOperandLegal(), and llvm::SIInstrInfo::verifyInstruction().

◆ hasVscnt()

bool llvm::GCNSubtarget::hasVscnt ( ) const
inline

Definition at line 841 of file AMDGPUSubtarget.h.

◆ haveRoundOpsF64()

bool llvm::GCNSubtarget::haveRoundOpsF64 ( ) const
inline

Have v_trunc_f64, v_ceil_f64, v_rndne_f64.

Definition at line 643 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::SITargetLowering().

◆ initializeSubtargetDependencies()

GCNSubtarget & GCNSubtarget::initializeSubtargetDependencies ( const Triple &  TT,
StringRef  GPU,
StringRef  FS 
)

Definition at line 71 of file AMDGPUSubtarget.cpp.

References llvm::Triple::amdgcn, assert(), llvm::StringRef::contains(), llvm::StringRef::find_lower(), llvm::Triple::getArch(), llvm::R600Subtarget::getGeneration(), llvm::AMDGPUSubtarget::HasFminFmaxLegacy, llvm::AMDGPUSubtarget::isAmdHsaOS(), llvm::AMDGPUSubtarget::LocalMemorySize, llvm::StringRef::npos, llvm::R600Subtarget::ParseSubtargetFeatures(), llvm::AMDGPUSubtarget::SOUTHERN_ISLANDS, llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS, and llvm::AMDGPUSubtarget::WavefrontSize.

◆ isCuModeEnabled()

bool llvm::GCNSubtarget::isCuModeEnabled ( ) const
inline

Definition at line 688 of file AMDGPUSubtarget.h.

Referenced by hasAnyNonFlatUseOfReg().

◆ isMesaGfxShader()

bool llvm::GCNSubtarget::isMesaGfxShader ( const Function &  F) const
inline

Definition at line 765 of file AMDGPUSubtarget.h.

References llvm::Function::getCallingConv(), llvm::AMDGPUSubtarget::isMesa3DOS(), and llvm::AMDGPU::isShader().

Referenced by llvm::SIFrameLowering::emitEntryFunctionPrologue(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ isSRAMECCEnabled()

bool llvm::GCNSubtarget::isSRAMECCEnabled ( ) const
inline

Definition at line 833 of file AMDGPUSubtarget.h.

◆ isTrapHandlerEnabled()

bool llvm::GCNSubtarget::isTrapHandlerEnabled ( ) const
inline

Definition at line 680 of file AMDGPUSubtarget.h.

Referenced by hasAnyNonFlatUseOfReg(), and llvm::SITargetLowering::shouldEmitPCReloc().

◆ isWave32()

bool llvm::GCNSubtarget::isWave32 ( ) const
inline

Definition at line 1171 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::WavefrontSize.

Referenced by createLaneMaskReg(), llvm::AMDGPUAsmPrinter::doFinalization(), llvm::SIFrameLowering::emitEpilogue(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), emitLoadM0FromVGPRLoop(), emitLoadSRsrcFromVGPRLoop(), llvm::SIFrameLowering::emitPrologue(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::fixImplicitOperands(), getHalfSizedType(), getOrNonExecReg(), getRsrcReg(), isCopyToExec(), isEndCF(), isFullExecCopy(), isLiveOut(), loadM0FromVGPR(), loadSRsrcFromVGPR(), matchSwap(), and optimizeVcndVcmpPair().

◆ isXNACKEnabled()

bool llvm::GCNSubtarget::isXNACKEnabled ( ) const
inline

Definition at line 684 of file AMDGPUSubtarget.h.

Referenced by addRegsToSet().

◆ ldsRequiresM0Init()

bool llvm::GCNSubtarget::ldsRequiresM0Init ( ) const
inline

Return if most LDS instructions have an m0 use that require m0 to be iniitalized.

Definition at line 738 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX9.

Referenced by combineKnownAdjacentMMOs(), and isConstant().

◆ loadStoreOptEnabled()

bool llvm::GCNSubtarget::loadStoreOptEnabled ( ) const
inline

Definition at line 987 of file AMDGPUSubtarget.h.

References EnableLoadStoreOpt.

Referenced by combineKnownAdjacentMMOs().

◆ overrideSchedPolicy()

void GCNSubtarget::overrideSchedPolicy ( MachineSchedPolicy &  Policy,
unsigned  NumRegionInstrs 
) const
override

Definition at line 549 of file AMDGPUSubtarget.cpp.

References llvm::MachineSchedPolicy::OnlyBottomUp, llvm::MachineSchedPolicy::OnlyTopDown, llvm::MachineSchedPolicy::ShouldTrackLaneMasks, and llvm::MachineSchedPolicy::ShouldTrackPressure.

◆ ParseSubtargetFeatures()

void llvm::GCNSubtarget::ParseSubtargetFeatures ( StringRef  CPU,
StringRef  FS 
)

◆ privateMemoryResourceIsRangeChecked()

bool llvm::GCNSubtarget::privateMemoryResourceIsRangeChecked ( ) const
inline
Returns
If MUBUF instructions always perform range checking, even for buffer resources used for private memory access.

Definition at line 649 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX9.

Referenced by isStackPtrRelative().

◆ setScalarizeGlobalBehavior()

void llvm::GCNSubtarget::setScalarizeGlobalBehavior ( bool  b)
inline

Definition at line 879 of file AMDGPUSubtarget.h.

◆ supportsMinMaxDenormModes()

bool llvm::GCNSubtarget::supportsMinMaxDenormModes ( ) const
inline

Definition at line 623 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::GFX9.

Referenced by llvm::SITargetLowering::isCanonicalized().

◆ unsafeDSOffsetFoldingEnabled()

bool llvm::GCNSubtarget::unsafeDSOffsetFoldingEnabled ( ) const
inline

Definition at line 570 of file AMDGPUSubtarget.h.

Referenced by isStackPtrRelative().

◆ useDS128()

bool llvm::GCNSubtarget::useDS128 ( ) const
inline
Returns
If target supports ds_read/write_b128 and user enables generation of ds_read/write_b128.

Definition at line 638 of file AMDGPUSubtarget.h.

Referenced by getLoadExtOrTrunc(), and getSPDenormModeValue().

◆ useFlatForGlobal()

bool llvm::GCNSubtarget::useFlatForGlobal ( ) const
inline

Definition at line 632 of file AMDGPUSubtarget.h.

Referenced by llvm::SITargetLowering::isLegalGlobalAddressingMode().

◆ usePRTStrictNull()

bool llvm::GCNSubtarget::usePRTStrictNull ( ) const
inline
Returns
If target requires PRT Struct NULL support (zero result registers for sparse texture support).

Definition at line 655 of file AMDGPUSubtarget.h.

Referenced by llvm::createSIAddIMGInitPass().

◆ useVGPRIndexMode()

bool llvm::GCNSubtarget::useVGPRIndexMode ( bool  UserEnable) const
inline

Definition at line 933 of file AMDGPUSubtarget.h.

Referenced by emitIndirectDst(), and emitIndirectSrc().

◆ vmemWriteNeedsExpWaitcnt()

bool llvm::GCNSubtarget::vmemWriteNeedsExpWaitcnt ( ) const
inline

Definition at line 857 of file AMDGPUSubtarget.h.

References llvm::AMDGPUSubtarget::SEA_ISLANDS.

Member Data Documentation

◆ AddNoCarryInsts

bool llvm::GCNSubtarget::AddNoCarryInsts
protected

Definition at line 363 of file AMDGPUSubtarget.h.

◆ AutoWaitcntBeforeBarrier

bool llvm::GCNSubtarget::AutoWaitcntBeforeBarrier
protected

Definition at line 295 of file AMDGPUSubtarget.h.

◆ CaymanISA

bool llvm::GCNSubtarget::CaymanISA
protected

Definition at line 366 of file AMDGPUSubtarget.h.

◆ CFALUBug

bool llvm::GCNSubtarget::CFALUBug
protected

Definition at line 367 of file AMDGPUSubtarget.h.

◆ CIInsts

bool llvm::GCNSubtarget::CIInsts
protected

Definition at line 319 of file AMDGPUSubtarget.h.

◆ CodeObjectV3

bool llvm::GCNSubtarget::CodeObjectV3
protected

Definition at line 296 of file AMDGPUSubtarget.h.

◆ DoesNotSupportSRAMECC

bool llvm::GCNSubtarget::DoesNotSupportSRAMECC
protected

Definition at line 352 of file AMDGPUSubtarget.h.

◆ DoesNotSupportXNACK

bool llvm::GCNSubtarget::DoesNotSupportXNACK
protected

Definition at line 301 of file AMDGPUSubtarget.h.

◆ DumpCode

bool llvm::GCNSubtarget::DumpCode
protected

Definition at line 311 of file AMDGPUSubtarget.h.

◆ EnableCuMode

bool llvm::GCNSubtarget::EnableCuMode
protected

Definition at line 302 of file AMDGPUSubtarget.h.

◆ EnableDS128

bool llvm::GCNSubtarget::EnableDS128
protected

Definition at line 309 of file AMDGPUSubtarget.h.

◆ EnableLoadStoreOpt

bool llvm::GCNSubtarget::EnableLoadStoreOpt
protected

Definition at line 306 of file AMDGPUSubtarget.h.

◆ EnablePRTStrictNull

bool llvm::GCNSubtarget::EnablePRTStrictNull
protected

Definition at line 310 of file AMDGPUSubtarget.h.

◆ EnableSIScheduler

bool llvm::GCNSubtarget::EnableSIScheduler
protected

Definition at line 308 of file AMDGPUSubtarget.h.

◆ EnableSRAMECC

bool llvm::GCNSubtarget::EnableSRAMECC
protected

Definition at line 351 of file AMDGPUSubtarget.h.

◆ EnableUnsafeDSOffsetFolding

bool llvm::GCNSubtarget::EnableUnsafeDSOffsetFolding
protected

Definition at line 307 of file AMDGPUSubtarget.h.

◆ EnableXNACK

bool llvm::GCNSubtarget::EnableXNACK
protected

Definition at line 300 of file AMDGPUSubtarget.h.

◆ FastFMAF32

bool llvm::GCNSubtarget::FastFMAF32
protected

Definition at line 289 of file AMDGPUSubtarget.h.

◆ FeatureDisable

bool llvm::GCNSubtarget::FeatureDisable
protected

Definition at line 385 of file AMDGPUSubtarget.h.

◆ FlatAddressSpace

bool llvm::GCNSubtarget::FlatAddressSpace
protected

Definition at line 358 of file AMDGPUSubtarget.h.

◆ FlatForGlobal

bool llvm::GCNSubtarget::FlatForGlobal
protected

Definition at line 294 of file AMDGPUSubtarget.h.

◆ FlatGlobalInsts

bool llvm::GCNSubtarget::FlatGlobalInsts
protected

Definition at line 360 of file AMDGPUSubtarget.h.

◆ FlatInstOffsets

bool llvm::GCNSubtarget::FlatInstOffsets
protected

Definition at line 359 of file AMDGPUSubtarget.h.

◆ FlatScratchInsts

bool llvm::GCNSubtarget::FlatScratchInsts
protected

Definition at line 361 of file AMDGPUSubtarget.h.

◆ FMA

bool llvm::GCNSubtarget::FMA
protected

Definition at line 315 of file AMDGPUSubtarget.h.

◆ FP64

bool llvm::GCNSubtarget::FP64
protected

Definition at line 314 of file AMDGPUSubtarget.h.

◆ FP64FP16Denormals

bool llvm::GCNSubtarget::FP64FP16Denormals
protected

Definition at line 293 of file AMDGPUSubtarget.h.

◆ GCN3Encoding

bool llvm::GCNSubtarget::GCN3Encoding
protected

Definition at line 318 of file AMDGPUSubtarget.h.

◆ Gen

unsigned llvm::GCNSubtarget::Gen
protected

Definition at line 283 of file AMDGPUSubtarget.h.

◆ GFX10Insts

bool llvm::GCNSubtarget::GFX10Insts
protected

Definition at line 322 of file AMDGPUSubtarget.h.

◆ GFX7GFX8GFX9Insts

bool llvm::GCNSubtarget::GFX7GFX8GFX9Insts
protected

Definition at line 323 of file AMDGPUSubtarget.h.

◆ GFX8Insts

bool llvm::GCNSubtarget::GFX8Insts
protected

Definition at line 320 of file AMDGPUSubtarget.h.

◆ GFX9Insts

bool llvm::GCNSubtarget::GFX9Insts
protected

Definition at line 321 of file AMDGPUSubtarget.h.

◆ HalfRate64Ops

bool llvm::GCNSubtarget::HalfRate64Ops
protected

Definition at line 290 of file AMDGPUSubtarget.h.

◆ HasApertureRegs

bool llvm::GCNSubtarget::HasApertureRegs
protected

Definition at line 299 of file AMDGPUSubtarget.h.

◆ HasAtomicFaddInsts

bool llvm::GCNSubtarget::HasAtomicFaddInsts
protected

Definition at line 350 of file AMDGPUSubtarget.h.

◆ HasDLInsts

bool llvm::GCNSubtarget::HasDLInsts
protected

Definition at line 341 of file AMDGPUSubtarget.h.

◆ HasDot1Insts

bool llvm::GCNSubtarget::HasDot1Insts
protected

Definition at line 342 of file AMDGPUSubtarget.h.

◆ HasDot2Insts

bool llvm::GCNSubtarget::HasDot2Insts
protected

Definition at line 343 of file AMDGPUSubtarget.h.

◆ HasDot3Insts

bool llvm::GCNSubtarget::HasDot3Insts
protected

Definition at line 344 of file AMDGPUSubtarget.h.

◆ HasDot4Insts

bool llvm::GCNSubtarget::HasDot4Insts
protected

Definition at line 345 of file AMDGPUSubtarget.h.

◆ HasDot5Insts

bool llvm::GCNSubtarget::HasDot5Insts
protected

Definition at line 346 of file AMDGPUSubtarget.h.

◆ HasDot6Insts

bool llvm::GCNSubtarget::HasDot6Insts
protected

Definition at line 347 of file AMDGPUSubtarget.h.

◆ HasDPP

bool llvm::GCNSubtarget::HasDPP
protected

Definition at line 337 of file AMDGPUSubtarget.h.

◆ HasDPP8

bool llvm::GCNSubtarget::HasDPP8
protected

Definition at line 338 of file AMDGPUSubtarget.h.

◆ HasFlatSegmentOffsetBug

bool llvm::GCNSubtarget::HasFlatSegmentOffsetBug
protected

Definition at line 382 of file AMDGPUSubtarget.h.

◆ HasFmaMixInsts

bool llvm::GCNSubtarget::HasFmaMixInsts
protected

Definition at line 327 of file AMDGPUSubtarget.h.

◆ HasInstFwdPrefetchBug

bool llvm::GCNSubtarget::HasInstFwdPrefetchBug
protected

Definition at line 377 of file AMDGPUSubtarget.h.

◆ HasIntClamp

bool llvm::GCNSubtarget::HasIntClamp
protected

Definition at line 326 of file AMDGPUSubtarget.h.

◆ HasLdsBranchVmemWARHazard

bool llvm::GCNSubtarget::HasLdsBranchVmemWARHazard
protected

Definition at line 379 of file AMDGPUSubtarget.h.

◆ HasMAIInsts

bool llvm::GCNSubtarget::HasMAIInsts
protected

Definition at line 348 of file AMDGPUSubtarget.h.

◆ HasMFMAInlineLiteralBug

bool llvm::GCNSubtarget::HasMFMAInlineLiteralBug
protected

Definition at line 369 of file AMDGPUSubtarget.h.

◆ HasMovrel

bool llvm::GCNSubtarget::HasMovrel
protected

Definition at line 328 of file AMDGPUSubtarget.h.

◆ HasNoDataDepHazard

bool llvm::GCNSubtarget::HasNoDataDepHazard
protected

Definition at line 357 of file AMDGPUSubtarget.h.

◆ HasNoSdstCMPX

bool llvm::GCNSubtarget::HasNoSdstCMPX
protected

Definition at line 353 of file AMDGPUSubtarget.h.

◆ HasNSAEncoding

bool llvm::GCNSubtarget::HasNSAEncoding
protected

Definition at line 340 of file AMDGPUSubtarget.h.

◆ HasNSAtoVMEMBug

bool llvm::GCNSubtarget::HasNSAtoVMEMBug
protected

Definition at line 380 of file AMDGPUSubtarget.h.

◆ HasOffset3fBug

bool llvm::GCNSubtarget::HasOffset3fBug
protected

Definition at line 381 of file AMDGPUSubtarget.h.

◆ HasPkFmacF16Inst

bool llvm::GCNSubtarget::HasPkFmacF16Inst
protected

Definition at line 349 of file AMDGPUSubtarget.h.

◆ HasR128A16

bool llvm::GCNSubtarget::HasR128A16
protected

Definition at line 339 of file AMDGPUSubtarget.h.

◆ HasRegisterBanking

bool llvm::GCNSubtarget::HasRegisterBanking
protected

Definition at line 355 of file AMDGPUSubtarget.h.

◆ HasScalarAtomics

bool llvm::GCNSubtarget::HasScalarAtomics
protected

Definition at line 331 of file AMDGPUSubtarget.h.

◆ HasScalarStores

bool llvm::GCNSubtarget::HasScalarStores
protected

Definition at line 330 of file AMDGPUSubtarget.h.

◆ HasSDWAMac

bool llvm::GCNSubtarget::HasSDWAMac
protected

Definition at line 335 of file AMDGPUSubtarget.h.

◆ HasSDWAOmod

bool llvm::GCNSubtarget::HasSDWAOmod
protected

Definition at line 332 of file AMDGPUSubtarget.h.

◆ HasSDWAOutModsVOPC

bool llvm::GCNSubtarget::HasSDWAOutModsVOPC
protected

Definition at line 336 of file AMDGPUSubtarget.h.

◆ HasSDWAScalar

bool llvm::GCNSubtarget::HasSDWAScalar
protected

Definition at line 333 of file AMDGPUSubtarget.h.

◆ HasSDWASdst

bool llvm::GCNSubtarget::HasSDWASdst
protected

Definition at line 334 of file AMDGPUSubtarget.h.

◆ HasSMemRealTime

bool llvm::GCNSubtarget::HasSMemRealTime
protected

Definition at line 325 of file AMDGPUSubtarget.h.

◆ HasSMEMtoVectorWriteHazard

bool llvm::GCNSubtarget::HasSMEMtoVectorWriteHazard
protected

Definition at line 376 of file AMDGPUSubtarget.h.

◆ HasUnpackedD16VMem

bool llvm::GCNSubtarget::HasUnpackedD16VMem
protected

Definition at line 364 of file AMDGPUSubtarget.h.

◆ HasVcmpxExecWARHazard

bool llvm::GCNSubtarget::HasVcmpxExecWARHazard
protected

Definition at line 378 of file AMDGPUSubtarget.h.

◆ HasVcmpxPermlaneHazard

bool llvm::GCNSubtarget::HasVcmpxPermlaneHazard
protected

Definition at line 374 of file AMDGPUSubtarget.h.

◆ HasVertexCache

bool llvm::GCNSubtarget::HasVertexCache
protected

Definition at line 370 of file AMDGPUSubtarget.h.

◆ HasVGPRIndexMode

bool llvm::GCNSubtarget::HasVGPRIndexMode
protected

Definition at line 329 of file AMDGPUSubtarget.h.

◆ HasVMEMtoScalarWriteHazard

bool llvm::GCNSubtarget::HasVMEMtoScalarWriteHazard
protected

Definition at line 375 of file AMDGPUSubtarget.h.

◆ HasVOP3Literal

bool llvm::GCNSubtarget::HasVOP3Literal
protected

Definition at line 356 of file AMDGPUSubtarget.h.

◆ HasVscnt

bool llvm::GCNSubtarget::HasVscnt
protected

Definition at line 354 of file AMDGPUSubtarget.h.

◆ InstrItins

InstrItineraryData llvm::GCNSubtarget::InstrItins
protected

Definition at line 284 of file AMDGPUSubtarget.h.

◆ IsGCN

bool llvm::GCNSubtarget::IsGCN
protected

Definition at line 317 of file AMDGPUSubtarget.h.

◆ LDSBankCount

int llvm::GCNSubtarget::LDSBankCount
protected

Definition at line 285 of file AMDGPUSubtarget.h.

◆ LDSMisalignedBug

bool llvm::GCNSubtarget::LDSMisalignedBug
protected

Definition at line 368 of file AMDGPUSubtarget.h.

◆ MaxPrivateElementSize

unsigned llvm::GCNSubtarget::MaxPrivateElementSize
protected

Definition at line 286 of file AMDGPUSubtarget.h.

◆ MIMG_R128

bool llvm::GCNSubtarget::MIMG_R128
protected

Definition at line 316 of file AMDGPUSubtarget.h.

◆ R600ALUInst

bool llvm::GCNSubtarget::R600ALUInst
protected

Definition at line 365 of file AMDGPUSubtarget.h.

◆ ScalarFlatScratchInsts

bool llvm::GCNSubtarget::ScalarFlatScratchInsts
protected

Definition at line 362 of file AMDGPUSubtarget.h.

◆ ScalarizeGlobal

bool llvm::GCNSubtarget::ScalarizeGlobal
protected

Definition at line 372 of file AMDGPUSubtarget.h.

◆ SGPRInitBug

bool llvm::GCNSubtarget::SGPRInitBug
protected

Definition at line 324 of file AMDGPUSubtarget.h.

◆ TargetTriple

Triple llvm::GCNSubtarget::TargetTriple
protected

Definition at line 282 of file AMDGPUSubtarget.h.

◆ TexVTXClauseSize

short llvm::GCNSubtarget::TexVTXClauseSize
protected

Definition at line 371 of file AMDGPUSubtarget.h.

◆ TrapHandler

bool llvm::GCNSubtarget::TrapHandler
protected

Definition at line 303 of file AMDGPUSubtarget.h.

◆ TSInfo

SelectionDAGTargetInfo llvm::GCNSubtarget::TSInfo
protected

Definition at line 387 of file AMDGPUSubtarget.h.

◆ UnalignedBufferAccess

bool llvm::GCNSubtarget::UnalignedBufferAccess
protected

Definition at line 298 of file AMDGPUSubtarget.h.

◆ UnalignedScratchAccess

bool llvm::GCNSubtarget::UnalignedScratchAccess
protected

Definition at line 297 of file AMDGPUSubtarget.h.

The documentation for this class was generated from the following files:
Generated on Mon Nov 4 2019 00:44:37 for LLVM by   doxygen 1.8.13