LLVM  13.0.0git
AMDGPUTargetMachine.cpp
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1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600MachineScheduler.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIMachineScheduler.h"
37 #include "llvm/IR/PassManager.h"
38 #include "llvm/InitializePasses.h"
41 #include "llvm/Transforms/IPO.h"
46 #include "llvm/Transforms/Scalar.h"
49 #include "llvm/Transforms/Utils.h"
52 
53 using namespace llvm;
54 
56  "r600-ir-structurize",
57  cl::desc("Use StructurizeCFG IR pass"),
58  cl::init(true));
59 
61  "amdgpu-sroa",
62  cl::desc("Run SROA after promote alloca pass"),
64  cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68  cl::desc("Run early if-conversion"),
69  cl::init(false));
70 
71 static cl::opt<bool>
72 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
73  cl::desc("Run pre-RA exec mask optimizations"),
74  cl::init(true));
75 
77  "r600-if-convert",
78  cl::desc("Use if conversion pass"),
80  cl::init(true));
81 
82 // Option to disable vectorizer for tests.
84  "amdgpu-load-store-vectorizer",
85  cl::desc("Enable load store vectorizer"),
86  cl::init(true),
87  cl::Hidden);
88 
89 // Option to control global loads scalarization
91  "amdgpu-scalarize-global-loads",
92  cl::desc("Enable global load scalarization"),
93  cl::init(true),
94  cl::Hidden);
95 
96 // Option to run internalize pass.
98  "amdgpu-internalize-symbols",
99  cl::desc("Enable elimination of non-kernel functions and unused globals"),
100  cl::init(false),
101  cl::Hidden);
102 
103 // Option to inline all early.
105  "amdgpu-early-inline-all",
106  cl::desc("Inline all functions early"),
107  cl::init(false),
108  cl::Hidden);
109 
111  "amdgpu-sdwa-peephole",
112  cl::desc("Enable SDWA peepholer"),
113  cl::init(true));
114 
116  "amdgpu-dpp-combine",
117  cl::desc("Enable DPP combiner"),
118  cl::init(true));
119 
120 // Enable address space based alias analysis
121 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
122  cl::desc("Enable AMDGPU Alias Analysis"),
123  cl::init(true));
124 
125 // Option to run late CFG structurizer
127  "amdgpu-late-structurize",
128  cl::desc("Enable late CFG structurization"),
130  cl::Hidden);
131 
133  "amdgpu-function-calls",
134  cl::desc("Enable AMDGPU function call support"),
136  cl::init(true),
137  cl::Hidden);
138 
140  "amdgpu-fixed-function-abi",
141  cl::desc("Enable all implicit function arguments"),
143  cl::init(false),
144  cl::Hidden);
145 
146 // Enable lib calls simplifications
148  "amdgpu-simplify-libcall",
149  cl::desc("Enable amdgpu library simplifications"),
150  cl::init(true),
151  cl::Hidden);
152 
154  "amdgpu-ir-lower-kernel-arguments",
155  cl::desc("Lower kernel argument loads in IR pass"),
156  cl::init(true),
157  cl::Hidden);
158 
160  "amdgpu-reassign-regs",
161  cl::desc("Enable register reassign optimizations on gfx10+"),
162  cl::init(true),
163  cl::Hidden);
164 
165 // Enable atomic optimization
167  "amdgpu-atomic-optimizations",
168  cl::desc("Enable atomic optimizations"),
169  cl::init(false),
170  cl::Hidden);
171 
172 // Enable Mode register optimization
174  "amdgpu-mode-register",
175  cl::desc("Enable mode register pass"),
176  cl::init(true),
177  cl::Hidden);
178 
179 // Option is used in lit tests to prevent deadcoding of patterns inspected.
180 static cl::opt<bool>
181 EnableDCEInRA("amdgpu-dce-in-ra",
182  cl::init(true), cl::Hidden,
183  cl::desc("Enable machine DCE inside regalloc"));
184 
186  "amdgpu-scalar-ir-passes",
187  cl::desc("Enable scalar IR passes"),
188  cl::init(true),
189  cl::Hidden);
190 
192  "amdgpu-enable-structurizer-workarounds",
193  cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
194  cl::Hidden);
195 
197  "amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"),
199  cl::Hidden);
200 
202  // Register the target
205 
266 }
267 
268 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
269  return std::make_unique<AMDGPUTargetObjectFile>();
270 }
271 
273  return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
274 }
275 
277  return new SIScheduleDAGMI(C);
278 }
279 
280 static ScheduleDAGInstrs *
282  ScheduleDAGMILive *DAG =
283  new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
287  return DAG;
288 }
289 
290 static ScheduleDAGInstrs *
292  auto DAG = new GCNIterativeScheduler(C,
294  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
295  return DAG;
296 }
297 
299  return new GCNIterativeScheduler(C,
301 }
302 
303 static ScheduleDAGInstrs *
305  auto DAG = new GCNIterativeScheduler(C,
307  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
308  DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
309  return DAG;
310 }
311 
313 R600SchedRegistry("r600", "Run R600's custom scheduler",
315 
317 SISchedRegistry("si", "Run SI's custom scheduler",
319 
321 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
322  "Run GCN scheduler to maximize occupancy",
324 
326 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
327  "Run GCN scheduler to maximize occupancy (experimental)",
329 
331 GCNMinRegSchedRegistry("gcn-minreg",
332  "Run GCN iterative scheduler for minimal register usage (experimental)",
334 
336 GCNILPSchedRegistry("gcn-ilp",
337  "Run GCN iterative scheduler for ILP scheduling (experimental)",
339 
340 static StringRef computeDataLayout(const Triple &TT) {
341  if (TT.getArch() == Triple::r600) {
342  // 32-bit pointers.
343  return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
344  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
345  }
346 
347  // 32-bit private, local, and region pointers. 64-bit global, constant and
348  // flat, non-integral buffer fat pointers.
349  return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
350  "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
351  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
352  "-ni:7";
353 }
354 
356 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
357  if (!GPU.empty())
358  return GPU;
359 
360  // Need to default to a target with flat support for HSA.
361  if (TT.getArch() == Triple::amdgcn)
362  return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
363 
364  return "r600";
365 }
366 
368  // The AMDGPU toolchain only supports generating shared objects, so we
369  // must always use PIC.
370  return Reloc::PIC_;
371 }
372 
374  StringRef CPU, StringRef FS,
378  CodeGenOpt::Level OptLevel)
381  getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
382  TLOF(createTLOF(getTargetTriple())) {
383  initAsmInfo();
384  if (TT.getArch() == Triple::amdgcn) {
385  if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
387  else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
389  }
390 }
391 
396 
398 
400  Attribute GPUAttr = F.getFnAttribute("target-cpu");
401  return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
402 }
403 
405  Attribute FSAttr = F.getFnAttribute("target-features");
406 
407  return FSAttr.isValid() ? FSAttr.getValueAsString()
409 }
410 
411 /// Predicate for Internalize pass.
412 static bool mustPreserveGV(const GlobalValue &GV) {
413  if (const Function *F = dyn_cast<Function>(&GV))
414  return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
415 
416  return !GV.use_empty();
417 }
418 
420  Builder.DivergentTarget = true;
421 
422  bool EnableOpt = getOptLevel() > CodeGenOpt::None;
423  bool Internalize = InternalizeSymbols;
424  bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
425  bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
426  bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
427 
428  if (EnableFunctionCalls) {
429  delete Builder.Inliner;
431  }
432 
433  Builder.addExtension(
435  [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
437  if (AMDGPUAA) {
440  }
443  if (Internalize)
446  if (Internalize)
447  PM.add(createGlobalDCEPass());
448  if (EarlyInline)
450  });
451 
452  Builder.addExtension(
454  [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
456  if (AMDGPUAA) {
459  }
462  if (LibCallSimplify)
464  });
465 
466  Builder.addExtension(
468  [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
469  // Add infer address spaces pass to the opt pipeline after inlining
470  // but before SROA to increase SROA opportunities.
472 
473  // This should run after inlining to have any chance of doing anything,
474  // and before other cleanup optimizations.
476 
477  // Promote alloca to vector before SROA and loop unroll. If we manage
478  // to eliminate allocas before unroll we may choose to unroll less.
479  if (EnableOpt)
481  });
482 }
483 
486 }
487 
492  if (PassName == "amdgpu-propagate-attributes-late") {
494  return true;
495  }
496  if (PassName == "amdgpu-unify-metadata") {
498  return true;
499  }
500  if (PassName == "amdgpu-printf-runtime-binding") {
502  return true;
503  }
504  if (PassName == "amdgpu-always-inline") {
506  return true;
507  }
508  if (PassName == "amdgpu-lower-module-lds") {
510  return true;
511  }
512  return false;
513  });
517  if (PassName == "amdgpu-simplifylib") {
519  return true;
520  }
521  if (PassName == "amdgpu-usenative") {
523  return true;
524  }
525  if (PassName == "amdgpu-promote-alloca") {
526  PM.addPass(AMDGPUPromoteAllocaPass(*this));
527  return true;
528  }
529  if (PassName == "amdgpu-promote-alloca-to-vector") {
531  return true;
532  }
533  if (PassName == "amdgpu-lower-kernel-attributes") {
535  return true;
536  }
537  if (PassName == "amdgpu-propagate-attributes-early") {
539  return true;
540  }
541  return false;
542  });
543 
545  FAM.registerPass([&] { return AMDGPUAA(); });
546  });
547 
548  PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
549  if (AAName == "amdgpu-aa") {
551  return true;
552  }
553  return false;
554  });
555 
561  if (EnableLibCallSimplify &&
565  });
566 
570  return;
571 
574 
575  if (InternalizeSymbols) {
576  // Global variables may have dead uses which need to be removed.
577  // Otherwise these useless global variables will not get internalized.
578  PM.addPass(GlobalDCEPass());
580  }
582  if (InternalizeSymbols) {
583  PM.addPass(GlobalDCEPass());
584  }
587  });
588 
592  return;
593 
595 
596  // Add infer address spaces pass to the opt pipeline after inlining
597  // but before SROA to increase SROA opportunities.
599 
600  // This should run after inlining to have any chance of doing
601  // anything, and before other cleanup optimizations.
603 
605  // Promote alloca to vector before SROA and loop unroll. If we
606  // manage to eliminate allocas before unroll we may choose to unroll
607  // less.
609  }
610 
612  });
613 }
614 
615 //===----------------------------------------------------------------------===//
616 // R600 Target Machine (R600 -> Cayman)
617 //===----------------------------------------------------------------------===//
618 
620  StringRef CPU, StringRef FS,
624  CodeGenOpt::Level OL, bool JIT)
625  : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
627 
628  // Override the default since calls aren't supported for r600.
629  if (EnableFunctionCalls &&
630  EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
631  EnableFunctionCalls = false;
632 }
633 
635  const Function &F) const {
636  StringRef GPU = getGPUName(F);
638 
639  SmallString<128> SubtargetKey(GPU);
640  SubtargetKey.append(FS);
641 
642  auto &I = SubtargetMap[SubtargetKey];
643  if (!I) {
644  // This needs to be done before we create a new subtarget since any
645  // creation will depend on the TM and the code generation flags on the
646  // function that reside in TargetOptions.
648  I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
649  }
650 
651  return I.get();
652 }
653 
654 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
655  return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
656  AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
657  AddrSpace == AMDGPUAS::REGION_ADDRESS)
658  ? -1
659  : 0;
660 }
661 
663  unsigned DestAS) const {
664  return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
666 }
667 
669  const auto *LD = dyn_cast<LoadInst>(V);
670  if (!LD)
672 
673  // It must be a generic pointer loaded.
674  assert(V->getType()->isPointerTy() &&
676 
677  const auto *Ptr = LD->getPointerOperand();
678  if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
680  // For a generic pointer loaded from the constant memory, it could be assumed
681  // as a global pointer since the constant memory is only populated on the
682  // host side. As implied by the offload programming model, only global
683  // pointers could be referenced on the host side.
685 }
686 
689  return TargetTransformInfo(R600TTIImpl(this, F));
690 }
691 
692 //===----------------------------------------------------------------------===//
693 // GCN Target Machine (SI+)
694 //===----------------------------------------------------------------------===//
695 
697  StringRef CPU, StringRef FS,
701  CodeGenOpt::Level OL, bool JIT)
702  : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
703 
705  StringRef GPU = getGPUName(F);
707 
708  SmallString<128> SubtargetKey(GPU);
709  SubtargetKey.append(FS);
710 
711  auto &I = SubtargetMap[SubtargetKey];
712  if (!I) {
713  // This needs to be done before we create a new subtarget since any
714  // creation will depend on the TM and the code generation flags on the
715  // function that reside in TargetOptions.
717  I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
718  }
719 
720  I->setScalarizeGlobalBehavior(ScalarizeGlobal);
721 
722  return I.get();
723 }
724 
727  return TargetTransformInfo(GCNTTIImpl(this, F));
728 }
729 
730 //===----------------------------------------------------------------------===//
731 // AMDGPU Pass Setup
732 //===----------------------------------------------------------------------===//
733 
734 namespace {
735 
736 class AMDGPUPassConfig : public TargetPassConfig {
737 public:
738  AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
739  : TargetPassConfig(TM, PM) {
740  // Exceptions and StackMaps are not supported, so these passes will never do
741  // anything.
742  disablePass(&StackMapLivenessID);
743  disablePass(&FuncletLayoutID);
744  }
745 
746  AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
747  return getTM<AMDGPUTargetMachine>();
748  }
749 
751  createMachineScheduler(MachineSchedContext *C) const override {
754  return DAG;
755  }
756 
757  void addEarlyCSEOrGVNPass();
758  void addStraightLineScalarOptimizationPasses();
759  void addIRPasses() override;
760  void addCodeGenPrepare() override;
761  bool addPreISel() override;
762  bool addInstSelector() override;
763  bool addGCPasses() override;
764 
765  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
766 };
767 
768 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
769  return getStandardCSEConfigForOpt(TM->getOptLevel());
770 }
771 
772 class R600PassConfig final : public AMDGPUPassConfig {
773 public:
774  R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
775  : AMDGPUPassConfig(TM, PM) {}
776 
777  ScheduleDAGInstrs *createMachineScheduler(
778  MachineSchedContext *C) const override {
780  }
781 
782  bool addPreISel() override;
783  bool addInstSelector() override;
784  void addPreRegAlloc() override;
785  void addPreSched2() override;
786  void addPreEmitPass() override;
787 };
788 
789 class GCNPassConfig final : public AMDGPUPassConfig {
790 public:
791  GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
792  : AMDGPUPassConfig(TM, PM) {
793  // It is necessary to know the register usage of the entire call graph. We
794  // allow calls without EnableAMDGPUFunctionCalls if they are marked
795  // noinline, so this is always required.
796  setRequiresCodeGenSCCOrder(true);
797  }
798 
799  GCNTargetMachine &getGCNTargetMachine() const {
800  return getTM<GCNTargetMachine>();
801  }
802 
804  createMachineScheduler(MachineSchedContext *C) const override;
805 
806  bool addPreISel() override;
807  void addMachineSSAOptimization() override;
808  bool addILPOpts() override;
809  bool addInstSelector() override;
810  bool addIRTranslator() override;
811  void addPreLegalizeMachineIR() override;
812  bool addLegalizeMachineIR() override;
813  void addPreRegBankSelect() override;
814  bool addRegBankSelect() override;
815  void addPreGlobalInstructionSelect() override;
816  bool addGlobalInstructionSelect() override;
817  void addFastRegAlloc() override;
818  void addOptimizedRegAlloc() override;
819  void addPreRegAlloc() override;
820  bool addPreRewrite() override;
821  void addPostRegAlloc() override;
822  void addPreSched2() override;
823  void addPreEmitPass() override;
824 };
825 
826 } // end anonymous namespace
827 
828 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
829  if (getOptLevel() == CodeGenOpt::Aggressive)
830  addPass(createGVNPass());
831  else
832  addPass(createEarlyCSEPass());
833 }
834 
835 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
836  addPass(createLICMPass());
839  // ReassociateGEPs exposes more opportunites for SLSR. See
840  // the example in reassociate-geps-and-slsr.ll.
842  // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
843  // EarlyCSE can reuse.
844  addEarlyCSEOrGVNPass();
845  // Run NaryReassociate after EarlyCSE/GVN to be more effective.
846  addPass(createNaryReassociatePass());
847  // NaryReassociate on GEPs creates redundant common expressions, so run
848  // EarlyCSE after it.
849  addPass(createEarlyCSEPass());
850 }
851 
852 void AMDGPUPassConfig::addIRPasses() {
853  const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
854 
855  // There is no reason to run these.
856  disablePass(&StackMapLivenessID);
857  disablePass(&FuncletLayoutID);
858  disablePass(&PatchableFunctionID);
859 
861 
862  // This must occur before inlining, as the inliner will not look through
863  // bitcast calls.
865 
866  // A call to propagate attributes pass in the backend in case opt was not run.
868 
869  addPass(createAtomicExpandPass());
870 
871 
873 
874  // Function calls are not supported, so make sure we inline everything.
875  addPass(createAMDGPUAlwaysInlinePass());
877  // We need to add the barrier noop pass, otherwise adding the function
878  // inlining pass will cause all of the PassConfigs passes to be run
879  // one function at a time, which means if we have a nodule with two
880  // functions, then we will generate code for the first function
881  // without ever running any passes on the second.
882  addPass(createBarrierNoopPass());
883 
884  // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
885  if (TM.getTargetTriple().getArch() == Triple::r600)
887 
888  // Replace OpenCL enqueued block function pointers with global variables.
890 
891  // Can increase LDS used by kernel so runs before PromoteAlloca
894 
895  if (TM.getOptLevel() > CodeGenOpt::None) {
896  addPass(createInferAddressSpacesPass());
897  addPass(createAMDGPUPromoteAlloca());
898 
899  if (EnableSROA)
900  addPass(createSROAPass());
903  : TM.getOptLevel() > CodeGenOpt::Less)
904  addStraightLineScalarOptimizationPasses();
905 
907  addPass(createAMDGPUAAWrapperPass());
909  AAResults &AAR) {
910  if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
911  AAR.addAAResult(WrapperPass->getResult());
912  }));
913  }
914  }
915 
916  if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
917  // TODO: May want to move later or split into an early and late one.
919  }
920 
922 
923  // EarlyCSE is not always strong enough to clean up what LSR produces. For
924  // example, GVN can combine
925  //
926  // %0 = add %a, %b
927  // %1 = add %b, %a
928  //
929  // and
930  //
931  // %0 = shl nsw %a, 2
932  // %1 = shl %a, 2
933  //
934  // but EarlyCSE can do neither of them.
937  : TM.getOptLevel() > CodeGenOpt::Less)
938  addEarlyCSEOrGVNPass();
939 }
940 
941 void AMDGPUPassConfig::addCodeGenPrepare() {
942  if (TM->getTargetTriple().getArch() == Triple::amdgcn)
944 
945  if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
948 
949  addPass(&AMDGPUPerfHintAnalysisID);
950 
952 
955  : TM->getOptLevel() > CodeGenOpt::Less)
957 
958  // LowerSwitch pass may introduce unreachable blocks that can
959  // cause unexpected behavior for subsequent passes. Placing it
960  // here seems better that these blocks would get cleaned up by
961  // UnreachableBlockElim inserted next in the pass flow.
962  addPass(createLowerSwitchPass());
963 }
964 
965 bool AMDGPUPassConfig::addPreISel() {
966  addPass(createFlattenCFGPass());
967  return false;
968 }
969 
970 bool AMDGPUPassConfig::addInstSelector() {
971  // Defer the verifier until FinalizeISel.
972  addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
973  return false;
974 }
975 
976 bool AMDGPUPassConfig::addGCPasses() {
977  // Do nothing. GC is not supported.
978  return false;
979 }
980 
981 //===----------------------------------------------------------------------===//
982 // R600 Pass Setup
983 //===----------------------------------------------------------------------===//
984 
985 bool R600PassConfig::addPreISel() {
986  AMDGPUPassConfig::addPreISel();
987 
989  addPass(createStructurizeCFGPass());
990  return false;
991 }
992 
993 bool R600PassConfig::addInstSelector() {
994  addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
995  return false;
996 }
997 
998 void R600PassConfig::addPreRegAlloc() {
999  addPass(createR600VectorRegMerger());
1000 }
1001 
1002 void R600PassConfig::addPreSched2() {
1003  addPass(createR600EmitClauseMarkers(), false);
1004  if (EnableR600IfConvert)
1005  addPass(&IfConverterID, false);
1006  addPass(createR600ClauseMergePass(), false);
1007 }
1008 
1009 void R600PassConfig::addPreEmitPass() {
1010  addPass(createAMDGPUCFGStructurizerPass(), false);
1011  addPass(createR600ExpandSpecialInstrsPass(), false);
1012  addPass(&FinalizeMachineBundlesID, false);
1013  addPass(createR600Packetizer(), false);
1014  addPass(createR600ControlFlowFinalizer(), false);
1015 }
1016 
1018  return new R600PassConfig(*this, PM);
1019 }
1020 
1021 //===----------------------------------------------------------------------===//
1022 // GCN Pass Setup
1023 //===----------------------------------------------------------------------===//
1024 
1025 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1026  MachineSchedContext *C) const {
1027  const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1028  if (ST.enableSIScheduler())
1029  return createSIMachineScheduler(C);
1031 }
1032 
1033 bool GCNPassConfig::addPreISel() {
1034  AMDGPUPassConfig::addPreISel();
1035 
1039  }
1040 
1041  // FIXME: We need to run a pass to propagate the attributes when calls are
1042  // supported.
1043 
1044  addPass(createSinkingPass());
1045  // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1046  // regions formed by them.
1048  if (!LateCFGStructurize) {
1050  addPass(createFixIrreduciblePass());
1051  addPass(createUnifyLoopExitsPass());
1052  }
1053  addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1054  }
1056  if (!LateCFGStructurize) {
1058  }
1059  addPass(createLCSSAPass());
1060 
1061  return false;
1062 }
1063 
1064 void GCNPassConfig::addMachineSSAOptimization() {
1066 
1067  // We want to fold operands after PeepholeOptimizer has run (or as part of
1068  // it), because it will eliminate extra copies making it easier to fold the
1069  // real source operand. We want to eliminate dead instructions after, so that
1070  // we see fewer uses of the copies. We then need to clean up the dead
1071  // instructions leftover after the operands are folded as well.
1072  //
1073  // XXX - Can we get away without running DeadMachineInstructionElim again?
1074  addPass(&SIFoldOperandsID);
1075  if (EnableDPPCombine)
1076  addPass(&GCNDPPCombineID);
1077  addPass(&SILoadStoreOptimizerID);
1080  : TM->getOptLevel() > CodeGenOpt::Less) {
1081  addPass(&SIPeepholeSDWAID);
1082  addPass(&EarlyMachineLICMID);
1083  addPass(&MachineCSEID);
1084  addPass(&SIFoldOperandsID);
1085  }
1086  addPass(&DeadMachineInstructionElimID);
1087  addPass(createSIShrinkInstructionsPass());
1088 }
1089 
1090 bool GCNPassConfig::addILPOpts() {
1092  addPass(&EarlyIfConverterID);
1093 
1095  return false;
1096 }
1097 
1098 bool GCNPassConfig::addInstSelector() {
1099  AMDGPUPassConfig::addInstSelector();
1100  addPass(&SIFixSGPRCopiesID);
1101  addPass(createSILowerI1CopiesPass());
1102  return false;
1103 }
1104 
1105 bool GCNPassConfig::addIRTranslator() {
1106  addPass(new IRTranslator(getOptLevel()));
1107  return false;
1108 }
1109 
1110 void GCNPassConfig::addPreLegalizeMachineIR() {
1111  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1112  addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1113  addPass(new Localizer());
1114 }
1115 
1116 bool GCNPassConfig::addLegalizeMachineIR() {
1117  addPass(new Legalizer());
1118  return false;
1119 }
1120 
1121 void GCNPassConfig::addPreRegBankSelect() {
1122  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1123  addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1124 }
1125 
1126 bool GCNPassConfig::addRegBankSelect() {
1127  addPass(new RegBankSelect());
1128  return false;
1129 }
1130 
1131 void GCNPassConfig::addPreGlobalInstructionSelect() {
1132  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1133  addPass(createAMDGPURegBankCombiner(IsOptNone));
1134 }
1135 
1136 bool GCNPassConfig::addGlobalInstructionSelect() {
1137  addPass(new InstructionSelect(getOptLevel()));
1138  return false;
1139 }
1140 
1141 void GCNPassConfig::addPreRegAlloc() {
1142  if (LateCFGStructurize) {
1144  }
1145 }
1146 
1147 void GCNPassConfig::addFastRegAlloc() {
1148  // FIXME: We have to disable the verifier here because of PHIElimination +
1149  // TwoAddressInstructions disabling it.
1150 
1151  // This must be run immediately after phi elimination and before
1152  // TwoAddressInstructions, otherwise the processing of the tied operand of
1153  // SI_ELSE will introduce a copy of the tied operand source after the else.
1154  insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1155 
1158 
1160 }
1161 
1162 void GCNPassConfig::addOptimizedRegAlloc() {
1163  // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1164  // instructions that cause scheduling barriers.
1165  insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1167 
1168  if (OptExecMaskPreRA)
1170 
1171  // This is not an essential optimization and it has a noticeable impact on
1172  // compilation time, so we only enable it from O2.
1173  if (TM->getOptLevel() > CodeGenOpt::Less)
1175 
1176  // This must be run immediately after phi elimination and before
1177  // TwoAddressInstructions, otherwise the processing of the tied operand of
1178  // SI_ELSE will introduce a copy of the tied operand source after the else.
1179  insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1180 
1181  if (EnableDCEInRA)
1183 
1185 }
1186 
1187 bool GCNPassConfig::addPreRewrite() {
1188  if (EnableRegReassign)
1189  addPass(&GCNNSAReassignID);
1190  return true;
1191 }
1192 
1193 void GCNPassConfig::addPostRegAlloc() {
1194  addPass(&SIFixVGPRCopiesID);
1195  if (getOptLevel() > CodeGenOpt::None)
1196  addPass(&SIOptimizeExecMaskingID);
1198 
1199  // Equivalent of PEI for SGPRs.
1200  addPass(&SILowerSGPRSpillsID);
1201 }
1202 
1203 void GCNPassConfig::addPreSched2() {
1204  addPass(&SIPostRABundlerID);
1205 }
1206 
1207 void GCNPassConfig::addPreEmitPass() {
1208  addPass(createSIMemoryLegalizerPass());
1209  addPass(createSIInsertWaitcntsPass());
1210  addPass(createSIShrinkInstructionsPass());
1211  addPass(createSIModeRegisterPass());
1212 
1213  if (getOptLevel() > CodeGenOpt::None)
1214  addPass(&SIInsertHardClausesID);
1215 
1216  addPass(&SILateBranchLoweringPassID);
1217  if (getOptLevel() > CodeGenOpt::None)
1218  addPass(&SIPreEmitPeepholeID);
1219  // The hazard recognizer that runs as part of the post-ra scheduler does not
1220  // guarantee to be able handle all hazards correctly. This is because if there
1221  // are multiple scheduling regions in a basic block, the regions are scheduled
1222  // bottom up, so when we begin to schedule a region we don't know what
1223  // instructions were emitted directly before it.
1224  //
1225  // Here we add a stand-alone hazard recognizer pass which can handle all
1226  // cases.
1227  addPass(&PostRAHazardRecognizerID);
1228  addPass(&BranchRelaxationPassID);
1229 }
1230 
1232  return new GCNPassConfig(*this, PM);
1233 }
1234 
1236  return new yaml::SIMachineFunctionInfo();
1237 }
1238 
1242  return new yaml::SIMachineFunctionInfo(
1243  *MFI, *MF.getSubtarget().getRegisterInfo(), MF);
1244 }
1245 
1248  SMDiagnostic &Error, SMRange &SourceRange) const {
1249  const yaml::SIMachineFunctionInfo &YamlMFI =
1250  reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1251  MachineFunction &MF = PFS.MF;
1253 
1254  if (MFI->initializeBaseYamlFields(YamlMFI, MF, PFS, Error, SourceRange))
1255  return true;
1256 
1257  if (MFI->Occupancy == 0) {
1258  // Fixup the subtarget dependent default value.
1259  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1260  MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1261  }
1262 
1263  auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1264  Register TempReg;
1265  if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1266  SourceRange = RegName.SourceRange;
1267  return true;
1268  }
1269  RegVal = TempReg;
1270 
1271  return false;
1272  };
1273 
1274  auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1275  // Create a diagnostic for a the register string literal.
1276  const MemoryBuffer &Buffer =
1277  *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1278  Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1279  RegName.Value.size(), SourceMgr::DK_Error,
1280  "incorrect register class for field", RegName.Value,
1281  None, None);
1282  SourceRange = RegName.SourceRange;
1283  return true;
1284  };
1285 
1286  if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1287  parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1288  parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1289  return true;
1290 
1291  if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1292  !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1293  return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1294  }
1295 
1296  if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1297  !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1298  return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1299  }
1300 
1301  if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1302  !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1303  return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1304  }
1305 
1306  auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1307  const TargetRegisterClass &RC,
1308  ArgDescriptor &Arg, unsigned UserSGPRs,
1309  unsigned SystemSGPRs) {
1310  // Skip parsing if it's not present.
1311  if (!A)
1312  return false;
1313 
1314  if (A->IsRegister) {
1315  Register Reg;
1316  if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1317  SourceRange = A->RegisterName.SourceRange;
1318  return true;
1319  }
1320  if (!RC.contains(Reg))
1321  return diagnoseRegisterClass(A->RegisterName);
1323  } else
1324  Arg = ArgDescriptor::createStack(A->StackOffset);
1325  // Check and apply the optional mask.
1326  if (A->Mask)
1327  Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1328 
1329  MFI->NumUserSGPRs += UserSGPRs;
1330  MFI->NumSystemSGPRs += SystemSGPRs;
1331  return false;
1332  };
1333 
1334  if (YamlMFI.ArgInfo &&
1335  (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1336  AMDGPU::SGPR_128RegClass,
1337  MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1338  parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1339  AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1340  2, 0) ||
1341  parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1342  MFI->ArgInfo.QueuePtr, 2, 0) ||
1343  parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1344  AMDGPU::SReg_64RegClass,
1345  MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1346  parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1347  AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1348  2, 0) ||
1349  parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1350  AMDGPU::SReg_64RegClass,
1351  MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1352  parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1353  AMDGPU::SGPR_32RegClass,
1354  MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1355  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1356  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1357  0, 1) ||
1358  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1359  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1360  0, 1) ||
1361  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1362  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1363  0, 1) ||
1364  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1365  AMDGPU::SGPR_32RegClass,
1366  MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1367  parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1368  AMDGPU::SGPR_32RegClass,
1369  MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1370  parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1371  AMDGPU::SReg_64RegClass,
1372  MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1373  parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1374  AMDGPU::SReg_64RegClass,
1375  MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1376  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1377  AMDGPU::VGPR_32RegClass,
1378  MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1379  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1380  AMDGPU::VGPR_32RegClass,
1381  MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1382  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1383  AMDGPU::VGPR_32RegClass,
1384  MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1385  return true;
1386 
1387  MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1388  MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1393 
1394  return false;
1395 }
llvm::AAResults::addAAResult
void addAAResult(AAResultT &AAResult)
Register a specific AA result.
Definition: AliasAnalysis.h:465
llvm::initializeR600ControlFlowFinalizerPass
void initializeR600ControlFlowFinalizerPass(PassRegistry &)
llvm::TargetPassConfig::addPostRegAlloc
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Definition: TargetPassConfig.h:419
llvm::createR600ExpandSpecialInstrsPass
FunctionPass * createR600ExpandSpecialInstrsPass()
Definition: R600ExpandSpecialInstrs.cpp:57
EnableDCEInRA
static cl::opt< bool > EnableDCEInRA("amdgpu-dce-in-ra", cl::init(true), cl::Hidden, cl::desc("Enable machine DCE inside regalloc"))
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:198
llvm::AAManager
A manager for alias analyses.
Definition: AliasAnalysis.h:1233
llvm::AMDGPUAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: AMDGPUAliasAnalysis.h:50
llvm::ArgDescriptor::createStack
static constexpr ArgDescriptor createStack(unsigned Offset, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:49
llvm::AMDGPUFunctionArgInfo::QueuePtr
ArgDescriptor QueuePtr
Definition: AMDGPUArgumentUsageInfo.h:126
llvm::AMDGPUTargetMachine::EnableFixedFunctionABI
static bool EnableFixedFunctionABI
Definition: AMDGPUTargetMachine.h:37
EnableLowerModuleLDS
static cl::opt< bool, true > EnableLowerModuleLDS("amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"), cl::location(AMDGPUTargetMachine::EnableLowerModuleLDS), cl::init(true), cl::Hidden)
llvm::initializeR600PacketizerPass
void initializeR600PacketizerPass(PassRegistry &)
LLVMInitializeAMDGPUTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget()
Definition: AMDGPUTargetMachine.cpp:201
llvm::AMDGPUAS::UNKNOWN_ADDRESS_SPACE
@ UNKNOWN_ADDRESS_SPACE
Definition: AMDGPU.h:400
llvm::InferAddressSpacesPass
Definition: InferAddressSpaces.h:16
EnableSIModeRegisterPass
static cl::opt< bool > EnableSIModeRegisterPass("amdgpu-mode-register", cl::desc("Enable mode register pass"), cl::init(true), cl::Hidden)
llvm::PerFunctionMIParsingState::SM
SourceMgr * SM
Definition: MIParser.h:163
llvm
Definition: AllocatorList.h:23
PassBuilder.h
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:155
llvm::AMDGPUTargetMachine::registerDefaultAliasAnalyses
void registerDefaultAliasAnalyses(AAManager &) override
Allow the target to register alias analyses with the AAManager for use with the new pass manager.
Definition: AMDGPUTargetMachine.cpp:484
mustPreserveGV
static bool mustPreserveGV(const GlobalValue &GV)
Predicate for Internalize pass.
Definition: AMDGPUTargetMachine.cpp:412
llvm::createSeparateConstOffsetFromGEPPass
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Definition: SeparateConstOffsetFromGEP.cpp:499
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:156
llvm::GCNTargetMachine::convertFuncInfoToYAML
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
Definition: AMDGPUTargetMachine.cpp:1240
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Definition: AMDGPU.h:152
llvm::initializeR600ExpandSpecialInstrsPassPass
void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &)
llvm::initializeAMDGPUPostLegalizerCombinerPass
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
llvm::initializeAMDGPUPromoteAllocaPass
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
llvm::createSIMemoryLegalizerPass
FunctionPass * createSIMemoryLegalizerPass()
Definition: SIMemoryLegalizer.cpp:1791
llvm::SILowerSGPRSpillsID
char & SILowerSGPRSpillsID
Definition: SILowerSGPRSpills.cpp:78
llvm::Wave32
@ Wave32
Definition: AMDGPUMCTargetDesc.h:34
llvm::PassBuilder::registerPipelineStartEPCallback
void registerPipelineStartEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:607
llvm::Type::isPointerTy
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:229
llvm::TargetOptions
Definition: TargetOptions.h:119
llvm::AMDGPUAlwaysInlinePass
Definition: AMDGPU.h:260
llvm::yaml::SIMachineFunctionInfo::ArgInfo
Optional< SIArgumentInfo > ArgInfo
Definition: SIMachineFunctionInfo.h:290
SIMachineFunctionInfo.h
Scalar.h
llvm::ArgDescriptor::createArg
static constexpr ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask)
Definition: AMDGPUArgumentUsageInfo.h:54
createMinRegScheduler
static ScheduleDAGInstrs * createMinRegScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:298
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::Function
Definition: Function.h:61
llvm::cl::location
LocationClass< Ty > location(Ty &L)
Definition: CommandLine.h:459
llvm::Attribute
Definition: Attributes.h:52
llvm::AMDGPU::SIModeRegisterDefaults::FP32OutputDenormals
bool FP32OutputDenormals
Definition: AMDGPUBaseInfo.h:916
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::initializeAMDGPUAlwaysInlinePass
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
llvm::yaml::MachineFunctionInfo
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Definition: MIRYamlMapping.h:670
llvm::PHIEliminationID
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
Definition: PHIElimination.cpp:129
llvm::initializeSIInsertHardClausesPass
void initializeSIInsertHardClausesPass(PassRegistry &)
llvm::initializeAMDGPUOpenCLEnqueuedBlockLoweringPass
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
llvm::initializeSIPreAllocateWWMRegsPass
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::initializeAMDGPUPropagateAttributesLatePass
void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &)
InferAddressSpaces.h
llvm::AMDGPU::SIModeRegisterDefaults::IEEE
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
Definition: AMDGPUBaseInfo.h:907
llvm::createAlwaysInlinerLegacyPass
Pass * createAlwaysInlinerLegacyPass(bool InsertLifetime=true)
Create a legacy pass manager instance of a pass to inline and remove functions marked as "always_inli...
Definition: AlwaysInliner.cpp:169
getGPUOrDefault
static LLVM_READNONE StringRef getGPUOrDefault(const Triple &TT, StringRef GPU)
Definition: AMDGPUTargetMachine.cpp:356
R600MachineScheduler.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:124
llvm::AMDGPUPromoteAllocaToVectorPass
Definition: AMDGPU.h:245
llvm::initializeAMDGPULateCodeGenPreparePass
void initializeAMDGPULateCodeGenPreparePass(PassRegistry &)
llvm::createFixIrreduciblePass
FunctionPass * createFixIrreduciblePass()
Definition: FixIrreducible.cpp:103
llvm::MachineSchedRegistry
MachineSchedRegistry provides a selection of available machine instruction schedulers.
Definition: MachineScheduler.h:136
llvm::Triple::amdgcn
@ amdgcn
Definition: Triple.h:72
GCNSchedStrategy.h
llvm::GCNIterativeScheduler::SCHEDULE_ILP
@ SCHEDULE_ILP
Definition: GCNIterativeScheduler.h:37
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:708
llvm::createAMDGPULateCodeGenPreparePass
FunctionPass * createAMDGPULateCodeGenPreparePass()
Definition: AMDGPULateCodeGenPrepare.cpp:193
llvm::createSILowerI1CopiesPass
FunctionPass * createSILowerI1CopiesPass()
Definition: SILowerI1Copies.cpp:413
llvm::initializeR600ClauseMergePassPass
void initializeR600ClauseMergePassPass(PassRegistry &)
llvm::GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY
@ SCHEDULE_LEGACYMAXOCCUPANCY
Definition: GCNIterativeScheduler.h:36
llvm::createFlattenCFGPass
FunctionPass * createFlattenCFGPass()
Definition: FlattenCFGPass.cpp:52
llvm::InternalizePass
A pass that internalizes all functions and variables other than those that must be preserved accordin...
Definition: Internalize.h:36
llvm::initializeSIOptimizeExecMaskingPreRAPass
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
llvm::AMDGPUFunctionArgInfo::FlatScratchInit
ArgDescriptor FlatScratchInit
Definition: AMDGPUArgumentUsageInfo.h:129
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
FAM
FunctionAnalysisManager FAM
Definition: PassBuilderBindings.cpp:59
llvm::createEarlyCSEPass
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1699
llvm::Wave64
@ Wave64
Definition: AMDGPUMCTargetDesc.h:34
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::initializeSILowerI1CopiesPass
void initializeSILowerI1CopiesPass(PassRegistry &)
llvm::SIPreEmitPeepholeID
char & SIPreEmitPeepholeID
llvm::createAMDGPUPostLegalizeCombiner
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPostLegalizerCombiner.cpp:400
llvm::initializeAMDGPUDAGToDAGISelPass
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
llvm::initializeSIPeepholeSDWAPass
void initializeSIPeepholeSDWAPass(PassRegistry &)
llvm::SILowerControlFlowID
char & SILowerControlFlowID
Definition: SILowerControlFlow.cpp:165
llvm::yaml::SIMachineFunctionInfo
Definition: SIMachineFunctionInfo.h:270
llvm::AMDGPUMachineFunction::getLDSSize
unsigned getLDSSize() const
Definition: AMDGPUMachineFunction.h:70
llvm::createAMDGPUUnifyMetadataPass
ModulePass * createAMDGPUUnifyMetadataPass()
InstructionSelect.h
EnableStructurizerWorkarounds
static cl::opt< bool > EnableStructurizerWorkarounds("amdgpu-enable-structurizer-workarounds", cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true), cl::Hidden)
llvm::AMDGPUAAWrapperPass
Legacy wrapper pass to provide the AMDGPUAAResult object.
Definition: AMDGPUAliasAnalysis.h:64
llvm::createCGSCCToFunctionPassAdaptor
CGSCCToFunctionPassAdaptor createCGSCCToFunctionPassAdaptor(FunctionPassT Pass)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: CGSCCPassManager.h:506
EnableAtomicOptimizations
static cl::opt< bool > EnableAtomicOptimizations("amdgpu-atomic-optimizations", cl::desc("Enable atomic optimizations"), cl::init(false), cl::Hidden)
createGCNMaxOccupancyMachineScheduler
static ScheduleDAGInstrs * createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:281
llvm::Optional< Reloc::Model >
llvm::GCNScheduleDAGMILive
Definition: GCNSchedStrategy.h:73
llvm::initializeSIFoldOperandsPass
void initializeSIFoldOperandsPass(PassRegistry &)
llvm::createBarrierNoopPass
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
Definition: BarrierNoopPass.cpp:43
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::createAMDGPUISelDag
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
Definition: AMDGPUISelDAGToDAG.cpp:380
InternalizeSymbols
static cl::opt< bool > InternalizeSymbols("amdgpu-internalize-symbols", cl::desc("Enable elimination of non-kernel functions and unused globals"), cl::init(false), cl::Hidden)
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
llvm::AMDGPU::SIModeRegisterDefaults::FP32InputDenormals
bool FP32InputDenormals
If this is set, neither input or output denormals are flushed for most f32 instructions.
Definition: AMDGPUBaseInfo.h:915
llvm::PassBuilder::registerAnalysisRegistrationCallback
void registerAnalysisRegistrationCallback(const std::function< void(CGSCCAnalysisManager &)> &C)
{{@ Register callbacks for analysis registration with this PassBuilder instance.
Definition: PassBuilder.h:640
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
SIMachineScheduler.h
llvm::yaml::SIMode::FP32OutputDenormals
bool FP32OutputDenormals
Definition: SIMachineFunctionInfo.h:234
llvm::createGVNPass
FunctionPass * createGVNPass(bool NoMemDepAnalysis=false)
Create a legacy GVN pass.
Definition: GVN.cpp:3059
llvm::AMDGPUFunctionArgInfo::PrivateSegmentSize
ArgDescriptor PrivateSegmentSize
Definition: AMDGPUArgumentUsageInfo.h:130
llvm::createR600OpenCLImageTypeLoweringPass
ModulePass * createR600OpenCLImageTypeLoweringPass()
Definition: R600OpenCLImageTypeLoweringPass.cpp:372
llvm::createR600ClauseMergePass
FunctionPass * createR600ClauseMergePass()
Definition: R600ClauseMergePass.cpp:209
llvm::AMDGPUUseNativeCallsPass
Definition: AMDGPU.h:85
llvm::AMDGPUFunctionArgInfo::DispatchPtr
ArgDescriptor DispatchPtr
Definition: AMDGPUArgumentUsageInfo.h:125
llvm::initializeAMDGPUPropagateAttributesEarlyPass
void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &)
llvm::SIPreAllocateWWMRegsID
char & SIPreAllocateWWMRegsID
Definition: SIPreAllocateWWMRegs.cpp:81
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::SIPostRABundlerID
char & SIPostRABundlerID
Definition: SIPostRABundler.cpp:69
llvm::initializeSIShrinkInstructionsPass
void initializeSIShrinkInstructionsPass(PassRegistry &)
LegacyPassManager.h
llvm::TwoAddressInstructionPassID
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Definition: TwoAddressInstructionPass.cpp:192
PassManagerBuilder.h
llvm::cl::ReallyHidden
@ ReallyHidden
Definition: CommandLine.h:144
llvm::GCNTargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: AMDGPUTargetMachine.cpp:1246
llvm::initializeAMDGPUSimplifyLibCallsPass
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
Internalize.h
createSIMachineScheduler
static ScheduleDAGInstrs * createSIMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:276
llvm::MemoryBuffer
This interface provides simple read-only access to a block of memory, and provides simple methods for...
Definition: MemoryBuffer.h:50
llvm::AMDGPUMachineFunction::Mode
AMDGPU::SIModeRegisterDefaults Mode
Definition: AMDGPUMachineFunction.h:44
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::createAMDGPUExternalAAWrapperPass
ImmutablePass * createAMDGPUExternalAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:36
llvm::AMDGPUFunctionArgInfo::DispatchID
ArgDescriptor DispatchID
Definition: AMDGPUArgumentUsageInfo.h:128
llvm::initializeAMDGPULowerIntrinsicsPass
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
llvm::initializeGCNDPPCombinePass
void initializeGCNDPPCombinePass(PassRegistry &)
llvm::AMDGPUUnifyMetadataPass
Definition: AMDGPU.h:284
llvm::PassBuilder::OptimizationLevel::O0
static const OptimizationLevel O0
Disable as many optimizations as possible.
Definition: PassBuilder.h:182
llvm::AMDGPUFunctionArgInfo::ImplicitArgPtr
ArgDescriptor ImplicitArgPtr
Definition: AMDGPUArgumentUsageInfo.h:141
EnableSDWAPeephole
static cl::opt< bool > EnableSDWAPeephole("amdgpu-sdwa-peephole", cl::desc("Enable SDWA peepholer"), cl::init(true))
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::SIOptimizeExecMaskingID
char & SIOptimizeExecMaskingID
Definition: SIOptimizeExecMasking.cpp:52
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::initializeAMDGPUUnifyMetadataPass
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
llvm::yaml::SIMachineFunctionInfo::FrameOffsetReg
StringValue FrameOffsetReg
Definition: SIMachineFunctionInfo.h:287
llvm::initializeAMDGPUArgumentUsageInfoPass
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
SISchedRegistry
static MachineSchedRegistry SISchedRegistry("si", "Run SI's custom scheduler", createSIMachineScheduler)
GCNIterativeScheduler.h
llvm::AMDGPUFunctionArgInfo::WorkGroupIDX
ArgDescriptor WorkGroupIDX
Definition: AMDGPUArgumentUsageInfo.h:133
llvm::GCNTargetMachine::GCNTargetMachine
GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AMDGPUTargetMachine.cpp:696
llvm::createInferAddressSpacesPass
FunctionPass * createInferAddressSpacesPass(unsigned AddressSpace=~0u)
Definition: InferAddressSpaces.cpp:1199
llvm::initializeSILateBranchLoweringPass
void initializeSILateBranchLoweringPass(PassRegistry &)
AMDGPUAliasAnalysis.h
llvm::AMDGPUTargetMachine
Definition: AMDGPUTargetMachine.h:27
llvm::createAMDGPUUseNativeCallsPass
FunctionPass * createAMDGPUUseNativeCallsPass()
Definition: AMDGPULibCalls.cpp:1702
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::createR600Packetizer
FunctionPass * createR600Packetizer()
Definition: R600Packetizer.cpp:411
AlwaysInliner.h
llvm::R600TargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: AMDGPUTargetMachine.cpp:688
llvm::AAResults
Definition: AliasAnalysis.h:456
llvm::yaml::SIMode::FP32InputDenormals
bool FP32InputDenormals
Definition: SIMachineFunctionInfo.h:233
llvm::PassBuilder::registerParseAACallback
void registerParseAACallback(const std::function< bool(StringRef Name, AAManager &AA)> &C)
Register a callback for parsing an AliasAnalysis Name to populate the given AAManager AA.
Definition: PassBuilder.h:632
ScalarizeGlobal
static cl::opt< bool > ScalarizeGlobal("amdgpu-scalarize-global-loads", cl::desc("Enable global load scalarization"), cl::init(true), cl::Hidden)
llvm::createNaryReassociatePass
FunctionPass * createNaryReassociatePass()
Definition: NaryReassociate.cpp:165
llvm::PostRAHazardRecognizerID
char & PostRAHazardRecognizerID
PostRAHazardRecognizer - This pass runs the post-ra hazard recognizer.
Definition: PostRAHazardRecognizer.cpp:64
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:656
llvm::initializeAMDGPULowerKernelArgumentsPass
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
llvm::initializeSIWholeQuadModePass
void initializeSIWholeQuadModePass(PassRegistry &)
llvm::initializeAMDGPUAtomicOptimizerPass
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
llvm::getTheAMDGPUTarget
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
Definition: AMDGPUTargetInfo.cpp:20
llvm::Legalizer
Definition: Legalizer.h:31
llvm::AMDGPUFunctionArgInfo::WorkItemIDX
ArgDescriptor WorkItemIDX
Definition: AMDGPUArgumentUsageInfo.h:148
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
EnableAMDGPUAliasAnalysis
static cl::opt< bool > EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden, cl::desc("Enable AMDGPU Alias Analysis"), cl::init(true))
EnableLowerKernelArguments
static cl::opt< bool > EnableLowerKernelArguments("amdgpu-ir-lower-kernel-arguments", cl::desc("Lower kernel argument loads in IR pass"), cl::init(true), cl::Hidden)
EnableLoadStoreVectorizer
static cl::opt< bool > EnableLoadStoreVectorizer("amdgpu-load-store-vectorizer", cl::desc("Enable load store vectorizer"), cl::init(true), cl::Hidden)
AMDGPUTargetInfo.h
llvm::createAMDGPULowerModuleLDSPass
ModulePass * createAMDGPULowerModuleLDSPass()
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
AMDGPUMacroFusion.h
llvm::initializeAMDGPUUseNativeCallsPass
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
llvm::createSIInsertWaitcntsPass
FunctionPass * createSIInsertWaitcntsPass()
Definition: SIInsertWaitcnts.cpp:802
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::PassBuilder
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:139
EnableRegReassign
static cl::opt< bool > EnableRegReassign("amdgpu-reassign-regs", cl::desc("Enable register reassign optimizations on gfx10+"), cl::init(true), cl::Hidden)
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:251
llvm::yaml::SIMode::FP64FP16InputDenormals
bool FP64FP16InputDenormals
Definition: SIMachineFunctionInfo.h:235
llvm::createAMDGPUAnnotateUniformValues
FunctionPass * createAMDGPUAnnotateUniformValues()
Definition: AMDGPUAnnotateUniformValues.cpp:150
llvm::AMDGPUAS::GLOBAL_ADDRESS
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:360
llvm::createR600EmitClauseMarkers
FunctionPass * createR600EmitClauseMarkers()
Definition: R600EmitClauseMarkers.cpp:336
llvm::initializeAMDGPUUnifyDivergentExitNodesPass
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:784
llvm::AMDGPUPromoteAllocaPass
Definition: AMDGPU.h:237
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:31
llvm::AMDGPUTargetMachine::getNullPointerValue
static int64_t getNullPointerValue(unsigned AddrSpace)
Get the integer value of a null pointer in the given address space.
Definition: AMDGPUTargetMachine.cpp:654
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1133
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:318
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::Triple::r600
@ r600
Definition: Triple.h:71
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createUnifyLoopExitsPass
FunctionPass * createUnifyLoopExitsPass()
Definition: UnifyLoopExits.cpp:53
llvm::GCNIterativeScheduler
Definition: GCNIterativeScheduler.h:29
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: AMDGPUTargetMachine.cpp:268
llvm::SourceMgr::getMainFileID
unsigned getMainFileID() const
Definition: SourceMgr.h:129
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:404
AMDGPUTargetObjectFile.h
llvm::AMDGPULowerKernelAttributesPass
Definition: AMDGPU.h:120
GVN.h
llvm::createAMDGPUPropagateAttributesLatePass
ModulePass * createAMDGPUPropagateAttributesLatePass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:406
llvm::initializeSIMemoryLegalizerPass
void initializeSIMemoryLegalizerPass(PassRegistry &)
llvm::createLoadStoreVectorizerPass
Pass * createLoadStoreVectorizerPass()
Create a legacy pass manager instance of the LoadStoreVectorizer pass.
EnableDPPCombine
static cl::opt< bool > EnableDPPCombine("amdgpu-dpp-combine", cl::desc("Enable DPP combiner"), cl::init(true))
llvm::createAMDGPULowerIntrinsicsPass
ModulePass * createAMDGPULowerIntrinsicsPass()
Definition: AMDGPULowerIntrinsics.cpp:180
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
llvm::createAMDGPUAnnotateKernelFeaturesPass
Pass * createAMDGPUAnnotateKernelFeaturesPass()
Definition: AMDGPUAnnotateKernelFeatures.cpp:426
llvm::AMDGPUTargetMachine::~AMDGPUTargetMachine
~AMDGPUTargetMachine() override
llvm::AMDGPUTargetMachine::getSubtargetImpl
const TargetSubtargetInfo * getSubtargetImpl() const
llvm::createSinkingPass
FunctionPass * createSinkingPass()
Definition: Sink.cpp:284
llvm::AMDGPUAS::REGION_ADDRESS
@ REGION_ADDRESS
Address space for region memory. (GDS)
Definition: AMDGPU.h:361
llvm::createSpeculativeExecutionPass
FunctionPass * createSpeculativeExecutionPass()
Definition: SpeculativeExecution.cpp:325
Utils.h
llvm::SILoadStoreOptimizerID
char & SILoadStoreOptimizerID
Definition: SILoadStoreOptimizer.cpp:576
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
llvm::None
const NoneType None
Definition: None.h:23
llvm::Value::use_empty
bool use_empty() const
Definition: Value.h:357
llvm::createAMDGPUExportClusteringDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAMDGPUExportClusteringDAGMutation()
Definition: AMDGPUExportClustering.cpp:144
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1370
llvm::SmallString< 128 >
llvm::SourceMgr::getMemoryBuffer
const MemoryBuffer * getMemoryBuffer(unsigned i) const
Definition: SourceMgr.h:122
llvm::createFunctionInliningPass
Pass * createFunctionInliningPass()
createFunctionInliningPass - Return a new pass object that uses a heuristic to inline direct function...
Definition: InlineSimple.cpp:97
llvm::legacy::PassManagerBase::add
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
llvm::R600TTIImpl
Definition: AMDGPUTargetTransformInfo.h:225
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:365
llvm::MemoryBuffer::getBufferIdentifier
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
Definition: MemoryBuffer.h:75
llvm::createAMDGPUAAWrapperPass
ImmutablePass * createAMDGPUAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:32
llvm::PassManagerBuilder
PassManagerBuilder - This class is used to set up a standard optimization sequence for languages like...
Definition: PassManagerBuilder.h:59
llvm::createLowerSwitchPass
FunctionPass * createLowerSwitchPass()
Definition: LowerSwitch.cpp:582
llvm::createAMDGPUPrintfRuntimeBinding
ModulePass * createAMDGPUPrintfRuntimeBinding()
Definition: AMDGPUPrintfRuntimeBinding.cpp:92
AMDGPUTargetTransformInfo.h
PB
PassBuilder PB(Machine, PassOpts->PTO, None, &PIC)
llvm::Triple::AMDHSA
@ AMDHSA
Definition: Triple.h:190
llvm::createAMDGPUAlwaysInlinePass
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPUAlwaysInlinePass.cpp:158
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::SmallString::append
void append(StringRef RHS)
Append from a StringRef.
Definition: SmallString.h:67
llvm::initializeSILowerSGPRSpillsPass
void initializeSILowerSGPRSpillsPass(PassRegistry &)
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:558
llvm::PassBuilder::registerPipelineEarlySimplificationEPCallback
void registerPipelineEarlySimplificationEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:616
llvm::AMDGPUTargetMachine::getFeatureString
StringRef getFeatureString(const Function &F) const
Definition: AMDGPUTargetMachine.cpp:404
R600SchedRegistry
static MachineSchedRegistry R600SchedRegistry("r600", "Run R600's custom scheduler", createR600MachineScheduler)
llvm::cl::opt< bool >
llvm::createLCSSAPass
Pass * createLCSSAPass()
Definition: LCSSA.cpp:484
EnableR600StructurizeCFG
static cl::opt< bool > EnableR600StructurizeCFG("r600-ir-structurize", cl::desc("Use StructurizeCFG IR pass"), cl::init(true))
llvm::createModuleToFunctionPassAdaptor
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT Pass)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:1209
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
OptExecMaskPreRA
static cl::opt< bool > OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden, cl::desc("Run pre-RA exec mask optimizations"), cl::init(true))
llvm::R600Subtarget
Definition: R600Subtarget.h:36
llvm::yaml::SIMachineFunctionInfo::ScratchRSrcReg
StringValue ScratchRSrcReg
Definition: SIMachineFunctionInfo.h:286
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::AMDGPUUnifyDivergentExitNodesID
char & AMDGPUUnifyDivergentExitNodesID
Definition: AMDGPUUnifyDivergentExitNodes.cpp:79
llvm::R600TargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: AMDGPUTargetMachine.cpp:1017
llvm::initializeSIInsertWaitcntsPass
void initializeSIInsertWaitcntsPass(PassRegistry &)
llvm::TargetMachine::setRequiresStructuredCFG
void setRequiresStructuredCFG(bool Value)
Definition: TargetMachine.h:214
llvm::initializeSIAnnotateControlFlowPass
void initializeSIAnnotateControlFlowPass(PassRegistry &)
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3485
llvm::AMDGPUFunctionArgInfo::WorkGroupIDZ
ArgDescriptor WorkGroupIDZ
Definition: AMDGPUArgumentUsageInfo.h:135
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:525
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::DetectDeadLanesID
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
Definition: DetectDeadLanes.cpp:128
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::TargetMachine::getMCSubtargetInfo
const MCSubtargetInfo * getMCSubtargetInfo() const
Definition: TargetMachine.h:206
llvm::AMDGPUFunctionArgInfo::PrivateSegmentBuffer
ArgDescriptor PrivateSegmentBuffer
Definition: AMDGPUArgumentUsageInfo.h:124
llvm::createAMDGPUAtomicOptimizerPass
FunctionPass * createAMDGPUAtomicOptimizerPass()
Definition: AMDGPUAtomicOptimizer.cpp:707
llvm::initializeR600VectorRegMergerPass
void initializeR600VectorRegMergerPass(PassRegistry &)
IPO.h
llvm::SIPeepholeSDWAID
char & SIPeepholeSDWAID
Definition: SIPeepholeSDWA.cpp:191
llvm::SIMachineFunctionInfo::initializeBaseYamlFields
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
Definition: SIMachineFunctionInfo.cpp:578
llvm::createGlobalDCEPass
ModulePass * createGlobalDCEPass()
createGlobalDCEPass - This transform is designed to eliminate unreachable internal globals (functions...
llvm::FinalizeMachineBundlesID
char & FinalizeMachineBundlesID
FinalizeMachineBundles - This pass finalize machine instruction bundles (created earlier,...
Definition: MachineInstrBundle.cpp:98
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::GCNTTIImpl
Definition: AMDGPUTargetTransformInfo.h:62
llvm::SIFixVGPRCopiesID
char & SIFixVGPRCopiesID
Definition: SIFixVGPRCopies.cpp:45
llvm::initializeAMDGPURewriteOutArgumentsPass
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
CGSCCPassManager.h
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:120
llvm::GCNIterativeScheduler::SCHEDULE_MINREGFORCED
@ SCHEDULE_MINREGFORCED
Definition: GCNIterativeScheduler.h:35
createR600MachineScheduler
static ScheduleDAGInstrs * createR600MachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:272
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::AMDGPUSimplifyLibCallsPass
Definition: AMDGPU.h:77
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:800
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::TargetPassConfig::addOptimizedRegAlloc
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: TargetPassConfig.cpp:1362
llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset
ArgDescriptor PrivateSegmentWaveByteOffset
Definition: AMDGPUArgumentUsageInfo.h:137
llvm::SIFormMemoryClausesID
char & SIFormMemoryClausesID
Definition: SIFormMemoryClauses.cpp:91
LateCFGStructurize
static cl::opt< bool, true > LateCFGStructurize("amdgpu-late-structurize", cl::desc("Enable late CFG structurization"), cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG), cl::Hidden)
TargetPassConfig.h
llvm::createExternalAAWrapperPass
ImmutablePass * createExternalAAWrapperPass(std::function< void(Pass &, Function &, AAResults &)> Callback)
A wrapper pass around a callback which can be used to populate the AAResults in the AAResultsWrapperP...
llvm::SIFixSGPRCopiesID
char & SIFixSGPRCopiesID
Definition: SIFixSGPRCopies.cpp:121
llvm::AMDGPUFunctionArgInfo::WorkGroupIDY
ArgDescriptor WorkGroupIDY
Definition: AMDGPUArgumentUsageInfo.h:134
Localizer.h
llvm::MachineCSEID
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:153
llvm::GCNDPPCombineID
char & GCNDPPCombineID
Definition: GCNDPPCombine.cpp:111
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:929
llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:911
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SIInsertHardClausesID
char & SIInsertHardClausesID
Definition: SIInsertHardClauses.cpp:209
GCNMinRegSchedRegistry
static MachineSchedRegistry GCNMinRegSchedRegistry("gcn-minreg", "Run GCN iterative scheduler for minimal register usage (experimental)", createMinRegScheduler)
llvm::AMDGPU::isFlatGlobalAddrSpace
bool isFlatGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:407
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
Definition: AMDGPUBaseInfo.h:920
llvm::getTheGCNTarget
Target & getTheGCNTarget()
The target for GCN GPUs.
Definition: AMDGPUTargetInfo.cpp:25
llvm::initializeSIOptimizeExecMaskingPass
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
llvm::initializeSIPostRABundlerPass
void initializeSIPostRABundlerPass(PassRegistry &)
llvm::SIScheduleDAGMI
Definition: SIMachineScheduler.h:426
llvm::PassBuilder::registerPipelineParsingCallback
void registerPipelineParsingCallback(const std::function< bool(StringRef Name, CGSCCPassManager &, ArrayRef< PipelineElement >)> &C)
{{@ Register pipeline parsing callbacks with this pass builder instance.
Definition: PassBuilder.h:662
llvm::initializeAMDGPUAAWrapperPassPass
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
llvm::initializeAMDGPUCodeGenPreparePass
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
llvm::createAMDGPUOpenCLEnqueuedBlockLoweringPass
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
llvm::initializeGCNNSAReassignPass
void initializeGCNNSAReassignPass(PassRegistry &)
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::AMDGPUTargetMachine::EnableLowerModuleLDS
static bool EnableLowerModuleLDS
Definition: AMDGPUTargetMachine.h:38
llvm::yaml::StringValue
A wrapper around std::string which contains a source range that's being set during parsing.
Definition: MIRYamlMapping.h:34
llvm::GlobalDCEPass
Pass to remove unused function declarations.
Definition: GlobalDCE.h:29
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
IterativeGCNMaxOccupancySchedRegistry
static MachineSchedRegistry IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental", "Run GCN scheduler to maximize occupancy (experimental)", createIterativeGCNMaxOccupancyMachineScheduler)
AMDGPUExportClustering.h
llvm::AMDGPUFunctionArgInfo::WorkItemIDZ
ArgDescriptor WorkItemIDZ
Definition: AMDGPUArgumentUsageInfo.h:150
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::createSIShrinkInstructionsPass
FunctionPass * createSIShrinkInstructionsPass()
llvm::createAMDGPUMachineCFGStructurizerPass
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
Definition: AMDGPUMachineCFGStructurizer.cpp:2886
llvm::GCNTargetMachine
Definition: AMDGPUTargetMachine.h:95
EnableAMDGPUFunctionCallsOpt
static cl::opt< bool, true > EnableAMDGPUFunctionCallsOpt("amdgpu-function-calls", cl::desc("Enable AMDGPU function call support"), cl::location(AMDGPUTargetMachine::EnableFunctionCalls), cl::init(true), cl::Hidden)
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:471
llvm::ScheduleDAG::TRI
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:559
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::initializeSIFormMemoryClausesPass
void initializeSIFormMemoryClausesPass(PassRegistry &)
computeDataLayout
static StringRef computeDataLayout(const Triple &TT)
Definition: AMDGPUTargetMachine.cpp:340
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::initializeAMDGPUExternalAAWrapperPass
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
AMDGPU.h
llvm::GCNTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: AMDGPUTargetMachine.cpp:726
llvm::yaml::SIMachineFunctionInfo::StackPtrOffsetReg
StringValue StackPtrOffsetReg
Definition: SIMachineFunctionInfo.h:288
SimplifyLibCalls.h
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
GlobalDCE.h
llvm::yaml::SIMachineFunctionInfo::Mode
SIMode Mode
Definition: SIMachineFunctionInfo.h:291
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:74
llvm::createAMDGPURegBankCombiner
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
Definition: AMDGPURegBankCombiner.cpp:273
IRTranslator.h
llvm::TargetMachine::getTargetFeatureString
StringRef getTargetFeatureString() const
Definition: TargetMachine.h:125
EarlyInlineAll
static cl::opt< bool > EarlyInlineAll("amdgpu-early-inline-all", cl::desc("Inline all functions early"), cl::init(false), cl::Hidden)
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::AMDGPUFunctionArgInfo::ImplicitBufferPtr
ArgDescriptor ImplicitBufferPtr
Definition: AMDGPUArgumentUsageInfo.h:144
llvm::SIWholeQuadModeID
char & SIWholeQuadModeID
Definition: SIWholeQuadMode.cpp:265
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:39
EnableSROA
static cl::opt< bool > EnableSROA("amdgpu-sroa", cl::desc("Run SROA after promote alloca pass"), cl::ReallyHidden, cl::init(true))
llvm::initializeAMDGPULowerKernelAttributesPass
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:473
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
llvm::initializeAMDGPUAnnotateUniformValuesPass
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
llvm::AMDGPUPrintfRuntimeBindingPass
Definition: AMDGPU.h:275
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::createStructurizeCFGPass
Pass * createStructurizeCFGPass(bool SkipUniformRegions=false)
When SkipUniformRegions is true the structizer will not structurize regions that only contain uniform...
Definition: StructurizeCFG.cpp:1086
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: AMDGPUBaseInfo.h:921
llvm::GCNTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: AMDGPUTargetMachine.cpp:1231
llvm::PassManager< Module >
llvm::createAMDGPULowerKernelAttributesPass
ModulePass * createAMDGPULowerKernelAttributesPass()
Definition: AMDGPULowerKernelAttributes.cpp:258
llvm::initializeSIFixSGPRCopiesPass
void initializeSIFixSGPRCopiesPass(PassRegistry &)
llvm::PerFunctionMIParsingState
Definition: MIParser.h:160
llvm::AMDGPUFunctionArgInfo::WorkGroupInfo
ArgDescriptor WorkGroupInfo
Definition: AMDGPUArgumentUsageInfo.h:136
llvm::createAMDGPUPromoteAllocaToVector
FunctionPass * createAMDGPUPromoteAllocaToVector()
Definition: AMDGPUPromoteAlloca.cpp:1149
llvm::R600TargetMachine::R600TargetMachine
R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AMDGPUTargetMachine.cpp:619
llvm::createR600VectorRegMerger
FunctionPass * createR600VectorRegMerger()
Definition: R600OptimizeVectorRegisters.cpp:385
llvm::initializeAMDGPULowerModuleLDSPass
void initializeAMDGPULowerModuleLDSPass(PassRegistry &)
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:205
createIterativeILPMachineScheduler
static ScheduleDAGInstrs * createIterativeILPMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:304
llvm::parseNamedRegisterReference
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
Definition: MIParser.cpp:3238
EnableEarlyIfConversion
static cl::opt< bool > EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(false))
llvm::initializeSIFixVGPRCopiesPass
void initializeSIFixVGPRCopiesPass(PassRegistry &)
llvm::yaml::SIMode::DX10Clamp
bool DX10Clamp
Definition: SIMachineFunctionInfo.h:232
llvm::initializeAMDGPUPromoteAllocaToVectorPass
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)
EnableScalarIRPasses
static cl::opt< bool > EnableScalarIRPasses("amdgpu-scalar-ir-passes", cl::desc("Enable scalar IR passes"), cl::init(true), cl::Hidden)
EnableR600IfConvert
static cl::opt< bool > EnableR600IfConvert("r600-if-convert", cl::desc("Use if conversion pass"), cl::ReallyHidden, cl::init(true))
llvm::initializeSIPreEmitPeepholePass
void initializeSIPreEmitPeepholePass(PassRegistry &)
createIterativeGCNMaxOccupancyMachineScheduler
static ScheduleDAGInstrs * createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:291
llvm::PassBuilder::OptimizationLevel
LLVM-provided high-level optimization levels.
Definition: PassBuilder.h:163
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:524
llvm::createR600ControlFlowFinalizer
FunctionPass * createR600ControlFlowFinalizer()
Definition: R600ControlFlowFinalizer.cpp:689
llvm::AMDGPUTargetMachine::registerPassBuilderCallbacks
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline with New Pass Manager (similar to adjustPassManager for ...
Definition: AMDGPUTargetMachine.cpp:488
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1216
llvm::createAMDGPUPropagateAttributesEarlyPass
FunctionPass * createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:401
llvm::AMDGPUPropagateAttributesEarlyPass
Definition: AMDGPU.h:128
llvm::initializeSIModeRegisterPass
void initializeSIModeRegisterPass(PassRegistry &)
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:364
llvm::createLoadClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1573
RegBankSelect.h
llvm::ScheduleDAG::TII
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
GCNMaxOccupancySchedRegistry
static MachineSchedRegistry GCNMaxOccupancySchedRegistry("gcn-max-occupancy", "Run GCN scheduler to maximize occupancy", createGCNMaxOccupancyMachineScheduler)
llvm::createAMDGPULowerKernelArgumentsPass
FunctionPass * createAMDGPULowerKernelArgumentsPass()
Definition: AMDGPULowerKernelArguments.cpp:248
llvm::AMDGPUTargetMachine::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: AMDGPUTargetMachine.cpp:662
llvm::PassManagerBuilder::EP_ModuleOptimizerEarly
@ EP_ModuleOptimizerEarly
EP_ModuleOptimizerEarly - This extension point allows adding passes just before the main module-level...
Definition: PassManagerBuilder.h:76
llvm::createSIModeRegisterPass
FunctionPass * createSIModeRegisterPass()
Definition: SIModeRegister.cpp:157
llvm::ArgDescriptor::createRegister
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
PassManager.h
llvm::createInternalizePass
ModulePass * createInternalizePass(std::function< bool(const GlobalValue &)> MustPreserveGV)
createInternalizePass - This pass loops over all of the functions in the input module,...
Definition: Internalize.cpp:288
llvm::SourceMgr::DK_Error
@ DK_Error
Definition: SourceMgr.h:34
llvm::AMDGPUTargetMachine::adjustPassManager
void adjustPassManager(PassManagerBuilder &) override
Allow the target to modify the pass manager, e.g.
Definition: AMDGPUTargetMachine.cpp:419
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:385
llvm::DeadMachineInstructionElimID
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Definition: DeadMachineInstructionElim.cpp:57
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:162
GCNILPSchedRegistry
static MachineSchedRegistry GCNILPSchedRegistry("gcn-ilp", "Run GCN iterative scheduler for ILP scheduling (experimental)", createIterativeILPMachineScheduler)
llvm::AnalysisManager::registerPass
bool registerPass(PassBuilderT &&PassBuilder)
Register an analysis pass with the manager.
Definition: PassManager.h:831
llvm::AMDGPUFunctionArgInfo::KernargSegmentPtr
ArgDescriptor KernargSegmentPtr
Definition: AMDGPUArgumentUsageInfo.h:127
llvm::createAMDGPUPromoteAlloca
FunctionPass * createAMDGPUPromoteAlloca()
Definition: AMDGPUPromoteAlloca.cpp:1145
llvm::initializeAMDGPUPrintfRuntimeBindingPass
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
llvm::AAManager::registerFunctionAnalysis
void registerFunctionAnalysis()
Register a specific AA result.
Definition: AliasAnalysis.h:1238
llvm::BranchRelaxationPassID
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Definition: BranchRelaxation.cpp:119
llvm::initializeAMDGPUPreLegalizerCombinerPass
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)
llvm::createAMDGPUCodeGenPreparePass
FunctionPass * createAMDGPUCodeGenPreparePass()
Definition: AMDGPUCodeGenPrepare.cpp:1418
llvm::MachineSchedulerID
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
Definition: MachineScheduler.cpp:210
llvm::AMDGPUTargetMachine::EnableFunctionCalls
static bool EnableFunctionCalls
Definition: AMDGPUTargetMachine.h:36
Legalizer.h
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::createLICMPass
Pass * createLICMPass()
Definition: LICM.cpp:310
llvm::createAMDGPUFixFunctionBitcastsPass
ModulePass * createAMDGPUFixFunctionBitcastsPass()
llvm::GCNNSAReassignID
char & GCNNSAReassignID
Definition: GCNNSAReassign.cpp:104
llvm::TargetMachine::getTargetCPU
StringRef getTargetCPU() const
Definition: TargetMachine.h:124
llvm::PassManagerBuilder::EP_EarlyAsPossible
@ EP_EarlyAsPossible
EP_EarlyAsPossible - This extension point allows adding passes before any other transformations,...
Definition: PassManagerBuilder.h:72
llvm::initializeAMDGPUAnnotateKernelFeaturesPass
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
llvm::AMDGPUFunctionArgInfo::WorkItemIDY
ArgDescriptor WorkItemIDY
Definition: AMDGPUArgumentUsageInfo.h:149
llvm::createAMDGPUPreLegalizeCombiner
FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPreLegalizerCombiner.cpp:296
llvm::AMDGPUTargetMachine::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const override
If the specified generic pointer could be assumed as a pointer to a specific address space,...
Definition: AMDGPUTargetMachine.cpp:668
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::createStraightLineStrengthReducePass
FunctionPass * createStraightLineStrengthReducePass()
Definition: StraightLineStrengthReduce.cpp:269
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:335
llvm::initializeAMDGPUFixFunctionBitcastsPass
void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &)
llvm::initializeSILoadStoreOptimizerPass
void initializeSILoadStoreOptimizerPass(PassRegistry &)
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::IRTranslator
Definition: IRTranslator.h:62
llvm::PassBuilder::registerCGSCCOptimizerLateEPCallback
void registerCGSCCOptimizerLateEPCallback(const std::function< void(CGSCCPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:586
llvm::initializeAMDGPURegBankCombinerPass
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
RegName
#define RegName(no)
llvm::createSIAnnotateControlFlowPass
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
Definition: SIAnnotateControlFlow.cpp:374
Vectorize.h
llvm::yaml::SIMode::IEEE
bool IEEE
Definition: SIMachineFunctionInfo.h:231
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:44
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SIFoldOperandsID
char & SIFoldOperandsID
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::AMDGPUAS::FLAT_ADDRESS
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:359
llvm::EarlyMachineLICMID
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
Definition: MachineLICM.cpp:295
llvm::AMDGPUTargetMachine::getGPUName
StringRef getGPUName(const Function &F) const
Definition: AMDGPUTargetMachine.cpp:399
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:363
llvm::cl::desc
Definition: CommandLine.h:414
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:385
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::PassManagerBuilder::EP_CGSCCOptimizerLate
@ EP_CGSCCOptimizerLate
EP_CGSCCOptimizerLate - This extension point allows adding CallGraphSCC passes at the end of the main...
Definition: PassManagerBuilder.h:117
llvm::createAMDGPUCFGStructurizerPass
FunctionPass * createAMDGPUCFGStructurizerPass()
Definition: AMDILCFGStructurizer.cpp:1654
llvm::createR600ISelDag
FunctionPass * createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a R600-specific.
Definition: AMDGPUISelDAGToDAG.cpp:387
llvm::IfConverterID
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
Definition: IfConversion.cpp:436
llvm::CodeGenOpt::Less
@ Less
Definition: CodeGen.h:54
llvm::AMDGPUTargetMachine::AMDGPUTargetMachine
AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL)
Definition: AMDGPUTargetMachine.cpp:373
llvm::TargetPassConfig::addFastRegAlloc
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: TargetPassConfig.cpp:1352
llvm::AMDGPUPerfHintAnalysisID
char & AMDGPUPerfHintAnalysisID
Definition: AMDGPUPerfHintAnalysis.cpp:57
TargetRegistry.h
llvm::createSROAPass
FunctionPass * createSROAPass()
Definition: SROA.cpp:4829
llvm::AMDGPUPropagateAttributesLatePass
Definition: AMDGPU.h:140
EnableLibCallSimplify
static cl::opt< bool > EnableLibCallSimplify("amdgpu-simplify-libcall", cl::desc("Enable amdgpu library simplifications"), cl::init(true), cl::Hidden)
InitializePasses.h
llvm::yaml::SIMode::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: SIMachineFunctionInfo.h:236
llvm::SIOptimizeExecMaskingPreRAID
char & SIOptimizeExecMaskingPreRAID
Definition: SIOptimizeExecMaskingPreRA.cpp:75
llvm::createGCNMCRegisterInfo
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)
Definition: AMDGPUMCTargetDesc.cpp:68
llvm::TargetMachine::MRI
std::unique_ptr< const MCRegisterInfo > MRI
Definition: TargetMachine.h:106
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
EnableAMDGPUFixedFunctionABIOpt
static cl::opt< bool, true > EnableAMDGPUFixedFunctionABIOpt("amdgpu-fixed-function-abi", cl::desc("Enable all implicit function arguments"), cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI), cl::init(false), cl::Hidden)
llvm::AMDGPUTargetMachine::EnableLateStructurizeCFG
static bool EnableLateStructurizeCFG
Definition: AMDGPUTargetMachine.h:35
llvm::TargetPassConfig::addILPOpts
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
Definition: TargetPassConfig.h:373
AMDGPUTargetMachine.h
llvm::GCNTargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: AMDGPUTargetMachine.cpp:1235
llvm::PassManager::addPass
std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT Pass)
Definition: PassManager.h:542
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:669
llvm::initializeSILowerControlFlowPass
void initializeSILowerControlFlowPass(PassRegistry &)
llvm::SILateBranchLoweringPassID
char & SILateBranchLoweringPassID
Definition: SILateBranchLowering.cpp:66
llvm::createAMDGPUSimplifyLibCallsPass
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetMachine *)
Definition: AMDGPULibCalls.cpp:1698
MIParser.h
llvm::Localizer
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:40
llvm::createAMDGPUMacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAMDGPUMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAMDGPUMacroFusionDAGMutation()); to AMDGPUPassConfig...
Definition: AMDGPUMacroFusion.cpp:62