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AMDGPUTargetMachine.cpp
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1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information needed to emit code for SI+ GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUIGroupLP.h"
20 #include "AMDGPUMacroFusion.h"
21 #include "AMDGPUTargetObjectFile.h"
23 #include "GCNIterativeScheduler.h"
24 #include "GCNSchedStrategy.h"
25 #include "GCNVOPDUtils.h"
26 #include "R600.h"
27 #include "R600TargetMachine.h"
28 #include "SIMachineFunctionInfo.h"
29 #include "SIMachineScheduler.h"
31 #include "Utils/AMDGPUBaseInfo.h"
40 #include "llvm/CodeGen/Passes.h"
43 #include "llvm/IR/IntrinsicsAMDGPU.h"
45 #include "llvm/IR/PassManager.h"
46 #include "llvm/IR/PatternMatch.h"
47 #include "llvm/InitializePasses.h"
48 #include "llvm/MC/TargetRegistry.h"
50 #include "llvm/Transforms/IPO.h"
54 #include "llvm/Transforms/Scalar.h"
57 #include "llvm/Transforms/Utils.h"
60 
61 using namespace llvm;
62 using namespace llvm::PatternMatch;
63 
64 namespace {
65 class SGPRRegisterRegAlloc : public RegisterRegAllocBase<SGPRRegisterRegAlloc> {
66 public:
67  SGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
68  : RegisterRegAllocBase(N, D, C) {}
69 };
70 
71 class VGPRRegisterRegAlloc : public RegisterRegAllocBase<VGPRRegisterRegAlloc> {
72 public:
73  VGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
74  : RegisterRegAllocBase(N, D, C) {}
75 };
76 
77 static bool onlyAllocateSGPRs(const TargetRegisterInfo &TRI,
78  const TargetRegisterClass &RC) {
79  return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
80 }
81 
82 static bool onlyAllocateVGPRs(const TargetRegisterInfo &TRI,
83  const TargetRegisterClass &RC) {
84  return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
85 }
86 
87 
88 /// -{sgpr|vgpr}-regalloc=... command line option.
89 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
90 
91 /// A dummy default pass factory indicates whether the register allocator is
92 /// overridden on the command line.
93 static llvm::once_flag InitializeDefaultSGPRRegisterAllocatorFlag;
94 static llvm::once_flag InitializeDefaultVGPRRegisterAllocatorFlag;
95 
96 static SGPRRegisterRegAlloc
97 defaultSGPRRegAlloc("default",
98  "pick SGPR register allocator based on -O option",
100 
101 static cl::opt<SGPRRegisterRegAlloc::FunctionPassCtor, false,
103 SGPRRegAlloc("sgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
104  cl::desc("Register allocator to use for SGPRs"));
105 
106 static cl::opt<VGPRRegisterRegAlloc::FunctionPassCtor, false,
108 VGPRRegAlloc("vgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
109  cl::desc("Register allocator to use for VGPRs"));
110 
111 
112 static void initializeDefaultSGPRRegisterAllocatorOnce() {
113  RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
114 
115  if (!Ctor) {
116  Ctor = SGPRRegAlloc;
117  SGPRRegisterRegAlloc::setDefault(SGPRRegAlloc);
118  }
119 }
120 
121 static void initializeDefaultVGPRRegisterAllocatorOnce() {
122  RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
123 
124  if (!Ctor) {
125  Ctor = VGPRRegAlloc;
126  VGPRRegisterRegAlloc::setDefault(VGPRRegAlloc);
127  }
128 }
129 
130 static FunctionPass *createBasicSGPRRegisterAllocator() {
131  return createBasicRegisterAllocator(onlyAllocateSGPRs);
132 }
133 
134 static FunctionPass *createGreedySGPRRegisterAllocator() {
135  return createGreedyRegisterAllocator(onlyAllocateSGPRs);
136 }
137 
138 static FunctionPass *createFastSGPRRegisterAllocator() {
139  return createFastRegisterAllocator(onlyAllocateSGPRs, false);
140 }
141 
142 static FunctionPass *createBasicVGPRRegisterAllocator() {
143  return createBasicRegisterAllocator(onlyAllocateVGPRs);
144 }
145 
146 static FunctionPass *createGreedyVGPRRegisterAllocator() {
147  return createGreedyRegisterAllocator(onlyAllocateVGPRs);
148 }
149 
150 static FunctionPass *createFastVGPRRegisterAllocator() {
151  return createFastRegisterAllocator(onlyAllocateVGPRs, true);
152 }
153 
154 static SGPRRegisterRegAlloc basicRegAllocSGPR(
155  "basic", "basic register allocator", createBasicSGPRRegisterAllocator);
156 static SGPRRegisterRegAlloc greedyRegAllocSGPR(
157  "greedy", "greedy register allocator", createGreedySGPRRegisterAllocator);
158 
159 static SGPRRegisterRegAlloc fastRegAllocSGPR(
160  "fast", "fast register allocator", createFastSGPRRegisterAllocator);
161 
162 
163 static VGPRRegisterRegAlloc basicRegAllocVGPR(
164  "basic", "basic register allocator", createBasicVGPRRegisterAllocator);
165 static VGPRRegisterRegAlloc greedyRegAllocVGPR(
166  "greedy", "greedy register allocator", createGreedyVGPRRegisterAllocator);
167 
168 static VGPRRegisterRegAlloc fastRegAllocVGPR(
169  "fast", "fast register allocator", createFastVGPRRegisterAllocator);
170 }
171 
173  "amdgpu-sroa",
174  cl::desc("Run SROA after promote alloca pass"),
176  cl::init(true));
177 
178 static cl::opt<bool>
179 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
180  cl::desc("Run early if-conversion"),
181  cl::init(false));
182 
183 static cl::opt<bool>
184 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
185  cl::desc("Run pre-RA exec mask optimizations"),
186  cl::init(true));
187 
188 // Option to disable vectorizer for tests.
190  "amdgpu-load-store-vectorizer",
191  cl::desc("Enable load store vectorizer"),
192  cl::init(true),
193  cl::Hidden);
194 
195 // Option to control global loads scalarization
197  "amdgpu-scalarize-global-loads",
198  cl::desc("Enable global load scalarization"),
199  cl::init(true),
200  cl::Hidden);
201 
202 // Option to run internalize pass.
204  "amdgpu-internalize-symbols",
205  cl::desc("Enable elimination of non-kernel functions and unused globals"),
206  cl::init(false),
207  cl::Hidden);
208 
209 // Option to inline all early.
211  "amdgpu-early-inline-all",
212  cl::desc("Inline all functions early"),
213  cl::init(false),
214  cl::Hidden);
215 
217  "amdgpu-sdwa-peephole",
218  cl::desc("Enable SDWA peepholer"),
219  cl::init(true));
220 
222  "amdgpu-dpp-combine",
223  cl::desc("Enable DPP combiner"),
224  cl::init(true));
225 
226 // Enable address space based alias analysis
227 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
228  cl::desc("Enable AMDGPU Alias Analysis"),
229  cl::init(true));
230 
231 // Option to run late CFG structurizer
233  "amdgpu-late-structurize",
234  cl::desc("Enable late CFG structurization"),
236  cl::Hidden);
237 
238 // Enable lib calls simplifications
240  "amdgpu-simplify-libcall",
241  cl::desc("Enable amdgpu library simplifications"),
242  cl::init(true),
243  cl::Hidden);
244 
246  "amdgpu-ir-lower-kernel-arguments",
247  cl::desc("Lower kernel argument loads in IR pass"),
248  cl::init(true),
249  cl::Hidden);
250 
252  "amdgpu-reassign-regs",
253  cl::desc("Enable register reassign optimizations on gfx10+"),
254  cl::init(true),
255  cl::Hidden);
256 
258  "amdgpu-opt-vgpr-liverange",
259  cl::desc("Enable VGPR liverange optimizations for if-else structure"),
260  cl::init(true), cl::Hidden);
261 
262 // Enable atomic optimization
264  "amdgpu-atomic-optimizations",
265  cl::desc("Enable atomic optimizations"),
266  cl::init(false),
267  cl::Hidden);
268 
269 // Enable Mode register optimization
271  "amdgpu-mode-register",
272  cl::desc("Enable mode register pass"),
273  cl::init(true),
274  cl::Hidden);
275 
276 // Enable GFX11+ s_delay_alu insertion
277 static cl::opt<bool>
278  EnableInsertDelayAlu("amdgpu-enable-delay-alu",
279  cl::desc("Enable s_delay_alu insertion"),
280  cl::init(true), cl::Hidden);
281 
282 // Enable GFX11+ VOPD
283 static cl::opt<bool>
284  EnableVOPD("amdgpu-enable-vopd",
285  cl::desc("Enable VOPD, dual issue of VALU in wave32"),
286  cl::init(true), cl::Hidden);
287 
288 // Option is used in lit tests to prevent deadcoding of patterns inspected.
289 static cl::opt<bool>
290 EnableDCEInRA("amdgpu-dce-in-ra",
291  cl::init(true), cl::Hidden,
292  cl::desc("Enable machine DCE inside regalloc"));
293 
294 static cl::opt<bool> EnableSetWavePriority("amdgpu-set-wave-priority",
295  cl::desc("Adjust wave priority"),
296  cl::init(false), cl::Hidden);
297 
299  "amdgpu-scalar-ir-passes",
300  cl::desc("Enable scalar IR passes"),
301  cl::init(true),
302  cl::Hidden);
303 
305  "amdgpu-enable-structurizer-workarounds",
306  cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
307  cl::Hidden);
308 
310  "amdgpu-enable-lds-replace-with-pointer",
311  cl::desc("Enable LDS replace with pointer pass"), cl::init(false),
312  cl::Hidden);
313 
315  "amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"),
317  cl::Hidden);
318 
320  "amdgpu-enable-pre-ra-optimizations",
321  cl::desc("Enable Pre-RA optimizations pass"), cl::init(true),
322  cl::Hidden);
323 
325  "amdgpu-enable-promote-kernel-arguments",
326  cl::desc("Enable promotion of flat kernel pointer arguments to global"),
327  cl::Hidden, cl::init(true));
328 
330  "amdgpu-enable-max-ilp-scheduling-strategy",
331  cl::desc("Enable scheduling strategy to maximize ILP for a single wave."),
332  cl::Hidden, cl::init(false));
333 
335  // Register the target
338 
409 }
410 
411 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
412  return std::make_unique<AMDGPUTargetObjectFile>();
413 }
414 
416  return new SIScheduleDAGMI(C);
417 }
418 
419 static ScheduleDAGInstrs *
421  const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
422  ScheduleDAGMILive *DAG =
423  new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
424  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
425  if (ST.shouldClusterStores())
426  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
427  DAG->addMutation(createIGroupLPDAGMutation());
428  DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
429  DAG->addMutation(createAMDGPUExportClusteringDAGMutation());
430  return DAG;
431 }
432 
433 static ScheduleDAGInstrs *
435  ScheduleDAGMILive *DAG =
436  new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxILPSchedStrategy>(C));
438  return DAG;
439 }
440 
441 static ScheduleDAGInstrs *
443  const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
444  auto DAG = new GCNIterativeScheduler(C,
446  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
447  if (ST.shouldClusterStores())
448  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
449  return DAG;
450 }
451 
453  return new GCNIterativeScheduler(C,
455 }
456 
457 static ScheduleDAGInstrs *
459  const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
460  auto DAG = new GCNIterativeScheduler(C,
462  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
463  if (ST.shouldClusterStores())
464  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
465  DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
466  return DAG;
467 }
468 
470 SISchedRegistry("si", "Run SI's custom scheduler",
472 
474 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
475  "Run GCN scheduler to maximize occupancy",
477 
479  GCNMaxILPSchedRegistry("gcn-max-ilp", "Run GCN scheduler to maximize ilp",
481 
483  "gcn-iterative-max-occupancy-experimental",
484  "Run GCN scheduler to maximize occupancy (experimental)",
486 
488  "gcn-iterative-minreg",
489  "Run GCN iterative scheduler for minimal register usage (experimental)",
491 
493  "gcn-iterative-ilp",
494  "Run GCN iterative scheduler for ILP scheduling (experimental)",
496 
497 static StringRef computeDataLayout(const Triple &TT) {
498  if (TT.getArch() == Triple::r600) {
499  // 32-bit pointers.
500  return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
501  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
502  }
503 
504  // 32-bit private, local, and region pointers. 64-bit global, constant and
505  // flat, non-integral buffer fat pointers.
506  return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
507  "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
508  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
509  "-ni:7";
510 }
511 
513 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
514  if (!GPU.empty())
515  return GPU;
516 
517  // Need to default to a target with flat support for HSA.
518  if (TT.getArch() == Triple::amdgcn)
519  return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
520 
521  return "r600";
522 }
523 
525  // The AMDGPU toolchain only supports generating shared objects, so we
526  // must always use PIC.
527  return Reloc::PIC_;
528 }
529 
531  StringRef CPU, StringRef FS,
535  CodeGenOpt::Level OptLevel)
538  getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
539  TLOF(createTLOF(getTargetTriple())) {
540  initAsmInfo();
541  if (TT.getArch() == Triple::amdgcn) {
542  if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
544  else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
546  }
547 }
548 
552 
554 
556  Attribute GPUAttr = F.getFnAttribute("target-cpu");
557  return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
558 }
559 
561  Attribute FSAttr = F.getFnAttribute("target-features");
562 
563  return FSAttr.isValid() ? FSAttr.getValueAsString()
565 }
566 
567 /// Predicate for Internalize pass.
568 static bool mustPreserveGV(const GlobalValue &GV) {
569  if (const Function *F = dyn_cast<Function>(&GV))
570  return F->isDeclaration() || F->getName().startswith("__asan_") ||
571  F->getName().startswith("__sanitizer_") ||
572  AMDGPU::isEntryFunctionCC(F->getCallingConv());
573 
575  return !GV.use_empty();
576 }
577 
580 }
581 
586  if (PassName == "amdgpu-propagate-attributes-late") {
588  return true;
589  }
590  if (PassName == "amdgpu-unify-metadata") {
592  return true;
593  }
594  if (PassName == "amdgpu-printf-runtime-binding") {
596  return true;
597  }
598  if (PassName == "amdgpu-always-inline") {
600  return true;
601  }
602  if (PassName == "amdgpu-replace-lds-use-with-pointer") {
604  return true;
605  }
606  if (PassName == "amdgpu-lower-module-lds") {
608  return true;
609  }
610  return false;
611  });
615  if (PassName == "amdgpu-simplifylib") {
617  return true;
618  }
619  if (PassName == "amdgpu-usenative") {
621  return true;
622  }
623  if (PassName == "amdgpu-promote-alloca") {
624  PM.addPass(AMDGPUPromoteAllocaPass(*this));
625  return true;
626  }
627  if (PassName == "amdgpu-promote-alloca-to-vector") {
629  return true;
630  }
631  if (PassName == "amdgpu-lower-kernel-attributes") {
633  return true;
634  }
635  if (PassName == "amdgpu-propagate-attributes-early") {
637  return true;
638  }
639  if (PassName == "amdgpu-promote-kernel-arguments") {
641  return true;
642  }
643  return false;
644  });
645 
647  FAM.registerPass([&] { return AMDGPUAA(); });
648  });
649 
650  PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
651  if (AAName == "amdgpu-aa") {
653  return true;
654  }
655  return false;
656  });
657 
659  [this](ModulePassManager &PM, OptimizationLevel Level) {
666  });
667 
669  [this](ModulePassManager &PM, OptimizationLevel Level) {
670  if (Level == OptimizationLevel::O0)
671  return;
672 
675 
676  if (InternalizeSymbols) {
678  }
680  if (InternalizeSymbols) {
681  PM.addPass(GlobalDCEPass());
682  }
685  });
686 
688  [this](CGSCCPassManager &PM, OptimizationLevel Level) {
689  if (Level == OptimizationLevel::O0)
690  return;
691 
693 
694  // Add promote kernel arguments pass to the opt pipeline right before
695  // infer address spaces which is needed to do actual address space
696  // rewriting.
697  if (Level.getSpeedupLevel() > OptimizationLevel::O1.getSpeedupLevel() &&
700 
701  // Add infer address spaces pass to the opt pipeline after inlining
702  // but before SROA to increase SROA opportunities.
704 
705  // This should run after inlining to have any chance of doing
706  // anything, and before other cleanup optimizations.
708 
709  if (Level != OptimizationLevel::O0) {
710  // Promote alloca to vector before SROA and loop unroll. If we
711  // manage to eliminate allocas before unroll we may choose to unroll
712  // less.
714  }
715 
717  });
718 }
719 
720 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
721  return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
722  AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
723  AddrSpace == AMDGPUAS::REGION_ADDRESS)
724  ? -1
725  : 0;
726 }
727 
729  unsigned DestAS) const {
730  return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
732 }
733 
735  const auto *LD = dyn_cast<LoadInst>(V);
736  if (!LD)
738 
739  // It must be a generic pointer loaded.
740  assert(V->getType()->isPointerTy() &&
742 
743  const auto *Ptr = LD->getPointerOperand();
744  if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
746  // For a generic pointer loaded from the constant memory, it could be assumed
747  // as a global pointer since the constant memory is only populated on the
748  // host side. As implied by the offload programming model, only global
749  // pointers could be referenced on the host side.
751 }
752 
753 std::pair<const Value *, unsigned>
755  if (auto *II = dyn_cast<IntrinsicInst>(V)) {
756  switch (II->getIntrinsicID()) {
757  case Intrinsic::amdgcn_is_shared:
758  return std::make_pair(II->getArgOperand(0), AMDGPUAS::LOCAL_ADDRESS);
759  case Intrinsic::amdgcn_is_private:
760  return std::make_pair(II->getArgOperand(0), AMDGPUAS::PRIVATE_ADDRESS);
761  default:
762  break;
763  }
764  return std::make_pair(nullptr, -1);
765  }
766  // Check the global pointer predication based on
767  // (!is_share(p) && !is_private(p)). Note that logic 'and' is commutative and
768  // the order of 'is_shared' and 'is_private' is not significant.
769  Value *Ptr;
770  if (match(
771  const_cast<Value *>(V),
772  m_c_And(m_Not(m_Intrinsic<Intrinsic::amdgcn_is_shared>(m_Value(Ptr))),
773  m_Not(m_Intrinsic<Intrinsic::amdgcn_is_private>(
774  m_Deferred(Ptr))))))
775  return std::make_pair(Ptr, AMDGPUAS::GLOBAL_ADDRESS);
776 
777  return std::make_pair(nullptr, -1);
778 }
779 
780 unsigned
782  switch (Kind) {
792  }
793  return AMDGPUAS::FLAT_ADDRESS;
794 }
795 
796 //===----------------------------------------------------------------------===//
797 // GCN Target Machine (SI+)
798 //===----------------------------------------------------------------------===//
799 
801  StringRef CPU, StringRef FS,
805  CodeGenOpt::Level OL, bool JIT)
806  : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
807 
808 const TargetSubtargetInfo *
810  StringRef GPU = getGPUName(F);
812 
813  SmallString<128> SubtargetKey(GPU);
814  SubtargetKey.append(FS);
815 
816  auto &I = SubtargetMap[SubtargetKey];
817  if (!I) {
818  // This needs to be done before we create a new subtarget since any
819  // creation will depend on the TM and the code generation flags on the
820  // function that reside in TargetOptions.
822  I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
823  }
824 
825  I->setScalarizeGlobalBehavior(ScalarizeGlobal);
826 
827  return I.get();
828 }
829 
832  return TargetTransformInfo(GCNTTIImpl(this, F));
833 }
834 
835 //===----------------------------------------------------------------------===//
836 // AMDGPU Pass Setup
837 //===----------------------------------------------------------------------===//
838 
839 std::unique_ptr<CSEConfigBase> llvm::AMDGPUPassConfig::getCSEConfig() const {
841 }
842 
843 namespace {
844 
845 class GCNPassConfig final : public AMDGPUPassConfig {
846 public:
847  GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
848  : AMDGPUPassConfig(TM, PM) {
849  // It is necessary to know the register usage of the entire call graph. We
850  // allow calls without EnableAMDGPUFunctionCalls if they are marked
851  // noinline, so this is always required.
852  setRequiresCodeGenSCCOrder(true);
853  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
854  }
855 
856  GCNTargetMachine &getGCNTargetMachine() const {
857  return getTM<GCNTargetMachine>();
858  }
859 
861  createMachineScheduler(MachineSchedContext *C) const override;
862 
864  createPostMachineScheduler(MachineSchedContext *C) const override {
866  C, std::make_unique<PostGenericScheduler>(C),
867  /*RemoveKillFlags=*/true);
868  const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
870  if (ST.shouldClusterStores())
872  DAG->addMutation(ST.createFillMFMAShadowMutation(DAG->TII));
874  if (isPassEnabled(EnableVOPD, CodeGenOpt::Less))
876  return DAG;
877  }
878 
879  bool addPreISel() override;
880  void addMachineSSAOptimization() override;
881  bool addILPOpts() override;
882  bool addInstSelector() override;
883  bool addIRTranslator() override;
884  void addPreLegalizeMachineIR() override;
885  bool addLegalizeMachineIR() override;
886  void addPreRegBankSelect() override;
887  bool addRegBankSelect() override;
888  void addPreGlobalInstructionSelect() override;
889  bool addGlobalInstructionSelect() override;
890  void addFastRegAlloc() override;
891  void addOptimizedRegAlloc() override;
892 
893  FunctionPass *createSGPRAllocPass(bool Optimized);
894  FunctionPass *createVGPRAllocPass(bool Optimized);
895  FunctionPass *createRegAllocPass(bool Optimized) override;
896 
897  bool addRegAssignAndRewriteFast() override;
898  bool addRegAssignAndRewriteOptimized() override;
899 
900  void addPreRegAlloc() override;
901  bool addPreRewrite() override;
902  void addPostRegAlloc() override;
903  void addPreSched2() override;
904  void addPreEmitPass() override;
905 };
906 
907 } // end anonymous namespace
908 
910  : TargetPassConfig(TM, PM) {
911  // Exceptions and StackMaps are not supported, so these passes will never do
912  // anything.
915  // Garbage collection is not supported.
918 }
919 
923  else
925 }
926 
930  // ReassociateGEPs exposes more opportunities for SLSR. See
931  // the example in reassociate-geps-and-slsr.ll.
933  // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
934  // EarlyCSE can reuse.
936  // Run NaryReassociate after EarlyCSE/GVN to be more effective.
938  // NaryReassociate on GEPs creates redundant common expressions, so run
939  // EarlyCSE after it.
941 }
942 
945 
946  // There is no reason to run these.
950 
953 
954  // A call to propagate attributes pass in the backend in case opt was not run.
956 
958 
959  // Function calls are not supported, so make sure we inline everything.
962  // We need to add the barrier noop pass, otherwise adding the function
963  // inlining pass will cause all of the PassConfigs passes to be run
964  // one function at a time, which means if we have a module with two
965  // functions, then we will generate code for the first function
966  // without ever running any passes on the second.
968 
969  // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
972 
973  // Replace OpenCL enqueued block function pointers with global variables.
975 
976  // Can increase LDS used by kernel so runs before PromoteAlloca
977  if (EnableLowerModuleLDS) {
978  // The pass "amdgpu-replace-lds-use-with-pointer" need to be run before the
979  // pass "amdgpu-lower-module-lds", and also it required to be run only if
980  // "amdgpu-lower-module-lds" pass is enabled.
983 
985  }
986 
989 
991 
992  if (TM.getOptLevel() > CodeGenOpt::None) {
994 
995  if (EnableSROA)
999 
1003  AAResults &AAR) {
1004  if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
1005  AAR.addAAResult(WrapperPass->getResult());
1006  }));
1007  }
1008 
1010  // TODO: May want to move later or split into an early and late one.
1012  }
1013  }
1014 
1016 
1017  // EarlyCSE is not always strong enough to clean up what LSR produces. For
1018  // example, GVN can combine
1019  //
1020  // %0 = add %a, %b
1021  // %1 = add %b, %a
1022  //
1023  // and
1024  //
1025  // %0 = shl nsw %a, 2
1026  // %1 = shl %a, 2
1027  //
1028  // but EarlyCSE can do neither of them.
1031 }
1032 
1034  if (TM->getTargetTriple().getArch() == Triple::amdgcn) {
1036 
1037  // FIXME: This pass adds 2 hacky attributes that can be replaced with an
1038  // analysis, and should be removed.
1040  }
1041 
1042  if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
1045 
1047 
1050 
1051  // LowerSwitch pass may introduce unreachable blocks that can
1052  // cause unexpected behavior for subsequent passes. Placing it
1053  // here seems better that these blocks would get cleaned up by
1054  // UnreachableBlockElim inserted next in the pass flow.
1056 }
1057 
1059  if (TM->getOptLevel() > CodeGenOpt::None)
1061  return false;
1062 }
1063 
1066  return false;
1067 }
1068 
1070  // Do nothing. GC is not supported.
1071  return false;
1072 }
1073 
1076  const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1078  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1079  if (ST.shouldClusterStores())
1080  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1081  return DAG;
1082 }
1083 
1084 //===----------------------------------------------------------------------===//
1085 // GCN Pass Setup
1086 //===----------------------------------------------------------------------===//
1087 
1088 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1089  MachineSchedContext *C) const {
1090  const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1091  if (ST.enableSIScheduler())
1092  return createSIMachineScheduler(C);
1093 
1096 
1098 }
1099 
1100 bool GCNPassConfig::addPreISel() {
1102 
1103  if (TM->getOptLevel() > CodeGenOpt::None)
1105 
1106  if (isPassEnabled(EnableAtomicOptimizations, CodeGenOpt::Less)) {
1108  }
1109 
1110  if (TM->getOptLevel() > CodeGenOpt::None)
1111  addPass(createSinkingPass());
1112 
1113  // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1114  // regions formed by them.
1116  if (!LateCFGStructurize) {
1118  addPass(createFixIrreduciblePass());
1119  addPass(createUnifyLoopExitsPass());
1120  }
1121  addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1122  }
1124  if (!LateCFGStructurize) {
1126  // TODO: Move this right after structurizeCFG to avoid extra divergence
1127  // analysis. This depends on stopping SIAnnotateControlFlow from making
1128  // control flow modifications.
1130  }
1131  addPass(createLCSSAPass());
1132 
1133  if (TM->getOptLevel() > CodeGenOpt::Less)
1134  addPass(&AMDGPUPerfHintAnalysisID);
1135 
1136  return false;
1137 }
1138 
1139 void GCNPassConfig::addMachineSSAOptimization() {
1141 
1142  // We want to fold operands after PeepholeOptimizer has run (or as part of
1143  // it), because it will eliminate extra copies making it easier to fold the
1144  // real source operand. We want to eliminate dead instructions after, so that
1145  // we see fewer uses of the copies. We then need to clean up the dead
1146  // instructions leftover after the operands are folded as well.
1147  //
1148  // XXX - Can we get away without running DeadMachineInstructionElim again?
1149  addPass(&SIFoldOperandsID);
1150  if (EnableDPPCombine)
1151  addPass(&GCNDPPCombineID);
1152  addPass(&SILoadStoreOptimizerID);
1153  if (isPassEnabled(EnableSDWAPeephole)) {
1154  addPass(&SIPeepholeSDWAID);
1155  addPass(&EarlyMachineLICMID);
1156  addPass(&MachineCSEID);
1157  addPass(&SIFoldOperandsID);
1158  }
1159  addPass(&DeadMachineInstructionElimID);
1160  addPass(createSIShrinkInstructionsPass());
1161 }
1162 
1163 bool GCNPassConfig::addILPOpts() {
1165  addPass(&EarlyIfConverterID);
1166 
1168  return false;
1169 }
1170 
1171 bool GCNPassConfig::addInstSelector() {
1173  addPass(&SIFixSGPRCopiesID);
1174  addPass(createSILowerI1CopiesPass());
1175  return false;
1176 }
1177 
1178 bool GCNPassConfig::addIRTranslator() {
1179  addPass(new IRTranslator(getOptLevel()));
1180  return false;
1181 }
1182 
1183 void GCNPassConfig::addPreLegalizeMachineIR() {
1184  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1185  addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1186  addPass(new Localizer());
1187 }
1188 
1189 bool GCNPassConfig::addLegalizeMachineIR() {
1190  addPass(new Legalizer());
1191  return false;
1192 }
1193 
1194 void GCNPassConfig::addPreRegBankSelect() {
1195  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1196  addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1197 }
1198 
1199 bool GCNPassConfig::addRegBankSelect() {
1200  addPass(new RegBankSelect());
1201  return false;
1202 }
1203 
1204 void GCNPassConfig::addPreGlobalInstructionSelect() {
1205  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1206  addPass(createAMDGPURegBankCombiner(IsOptNone));
1207 }
1208 
1209 bool GCNPassConfig::addGlobalInstructionSelect() {
1210  addPass(new InstructionSelect(getOptLevel()));
1211  return false;
1212 }
1213 
1214 void GCNPassConfig::addPreRegAlloc() {
1215  if (LateCFGStructurize) {
1217  }
1218 }
1219 
1220 void GCNPassConfig::addFastRegAlloc() {
1221  // FIXME: We have to disable the verifier here because of PHIElimination +
1222  // TwoAddressInstructions disabling it.
1223 
1224  // This must be run immediately after phi elimination and before
1225  // TwoAddressInstructions, otherwise the processing of the tied operand of
1226  // SI_ELSE will introduce a copy of the tied operand source after the else.
1227  insertPass(&PHIEliminationID, &SILowerControlFlowID);
1228 
1231 
1233 }
1234 
1235 void GCNPassConfig::addOptimizedRegAlloc() {
1236  // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1237  // instructions that cause scheduling barriers.
1238  insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1240 
1241  if (OptExecMaskPreRA)
1243 
1244  if (isPassEnabled(EnablePreRAOptimizations))
1246 
1247  // This is not an essential optimization and it has a noticeable impact on
1248  // compilation time, so we only enable it from O2.
1249  if (TM->getOptLevel() > CodeGenOpt::Less)
1251 
1252  // FIXME: when an instruction has a Killed operand, and the instruction is
1253  // inside a bundle, seems only the BUNDLE instruction appears as the Kills of
1254  // the register in LiveVariables, this would trigger a failure in verifier,
1255  // we should fix it and enable the verifier.
1256  if (OptVGPRLiveRange)
1258  // This must be run immediately after phi elimination and before
1259  // TwoAddressInstructions, otherwise the processing of the tied operand of
1260  // SI_ELSE will introduce a copy of the tied operand source after the else.
1261  insertPass(&PHIEliminationID, &SILowerControlFlowID);
1262 
1263  if (EnableDCEInRA)
1265 
1267 }
1268 
1269 bool GCNPassConfig::addPreRewrite() {
1270  if (EnableRegReassign)
1271  addPass(&GCNNSAReassignID);
1272  return true;
1273 }
1274 
1275 FunctionPass *GCNPassConfig::createSGPRAllocPass(bool Optimized) {
1276  // Initialize the global default.
1277  llvm::call_once(InitializeDefaultSGPRRegisterAllocatorFlag,
1278  initializeDefaultSGPRRegisterAllocatorOnce);
1279 
1280  RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
1281  if (Ctor != useDefaultRegisterAllocator)
1282  return Ctor();
1283 
1284  if (Optimized)
1285  return createGreedyRegisterAllocator(onlyAllocateSGPRs);
1286 
1287  return createFastRegisterAllocator(onlyAllocateSGPRs, false);
1288 }
1289 
1290 FunctionPass *GCNPassConfig::createVGPRAllocPass(bool Optimized) {
1291  // Initialize the global default.
1292  llvm::call_once(InitializeDefaultVGPRRegisterAllocatorFlag,
1293  initializeDefaultVGPRRegisterAllocatorOnce);
1294 
1295  RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
1296  if (Ctor != useDefaultRegisterAllocator)
1297  return Ctor();
1298 
1299  if (Optimized)
1300  return createGreedyVGPRRegisterAllocator();
1301 
1302  return createFastVGPRRegisterAllocator();
1303 }
1304 
1305 FunctionPass *GCNPassConfig::createRegAllocPass(bool Optimized) {
1306  llvm_unreachable("should not be used");
1307 }
1308 
1309 static const char RegAllocOptNotSupportedMessage[] =
1310  "-regalloc not supported with amdgcn. Use -sgpr-regalloc and -vgpr-regalloc";
1311 
1312 bool GCNPassConfig::addRegAssignAndRewriteFast() {
1313  if (!usingDefaultRegAlloc())
1315 
1316  addPass(createSGPRAllocPass(false));
1317 
1318  // Equivalent of PEI for SGPRs.
1319  addPass(&SILowerSGPRSpillsID);
1320 
1321  addPass(createVGPRAllocPass(false));
1322  return true;
1323 }
1324 
1325 bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
1326  if (!usingDefaultRegAlloc())
1328 
1329  addPass(createSGPRAllocPass(true));
1330 
1331  // Commit allocated register changes. This is mostly necessary because too
1332  // many things rely on the use lists of the physical registers, such as the
1333  // verifier. This is only necessary with allocators which use LiveIntervals,
1334  // since FastRegAlloc does the replacements itself.
1335  addPass(createVirtRegRewriter(false));
1336 
1337  // Equivalent of PEI for SGPRs.
1338  addPass(&SILowerSGPRSpillsID);
1339 
1340  addPass(createVGPRAllocPass(true));
1341 
1342  addPreRewrite();
1343  addPass(&VirtRegRewriterID);
1344 
1345  return true;
1346 }
1347 
1348 void GCNPassConfig::addPostRegAlloc() {
1349  addPass(&SIFixVGPRCopiesID);
1350  if (getOptLevel() > CodeGenOpt::None)
1351  addPass(&SIOptimizeExecMaskingID);
1353 }
1354 
1355 void GCNPassConfig::addPreSched2() {
1356  if (TM->getOptLevel() > CodeGenOpt::None)
1357  addPass(createSIShrinkInstructionsPass());
1358  addPass(&SIPostRABundlerID);
1359 }
1360 
1361 void GCNPassConfig::addPreEmitPass() {
1362  if (isPassEnabled(EnableVOPD, CodeGenOpt::Less))
1363  addPass(&GCNCreateVOPDID);
1364  addPass(createSIMemoryLegalizerPass());
1365  addPass(createSIInsertWaitcntsPass());
1366 
1367  addPass(createSIModeRegisterPass());
1368 
1369  if (getOptLevel() > CodeGenOpt::None)
1370  addPass(&SIInsertHardClausesID);
1371 
1372  addPass(&SILateBranchLoweringPassID);
1373  if (isPassEnabled(EnableSetWavePriority, CodeGenOpt::Less))
1375  if (getOptLevel() > CodeGenOpt::None)
1376  addPass(&SIPreEmitPeepholeID);
1377  // The hazard recognizer that runs as part of the post-ra scheduler does not
1378  // guarantee to be able handle all hazards correctly. This is because if there
1379  // are multiple scheduling regions in a basic block, the regions are scheduled
1380  // bottom up, so when we begin to schedule a region we don't know what
1381  // instructions were emitted directly before it.
1382  //
1383  // Here we add a stand-alone hazard recognizer pass which can handle all
1384  // cases.
1385  addPass(&PostRAHazardRecognizerID);
1386 
1387  if (getOptLevel() > CodeGenOpt::Less)
1388  addPass(&AMDGPUReleaseVGPRsID);
1389 
1390  if (isPassEnabled(EnableInsertDelayAlu, CodeGenOpt::Less))
1391  addPass(&AMDGPUInsertDelayAluID);
1392 
1393  addPass(&BranchRelaxationPassID);
1394 }
1395 
1397  return new GCNPassConfig(*this, PM);
1398 }
1399 
1401  return new yaml::SIMachineFunctionInfo();
1402 }
1403 
1407  return new yaml::SIMachineFunctionInfo(
1408  *MFI, *MF.getSubtarget().getRegisterInfo(), MF);
1409 }
1410 
1413  SMDiagnostic &Error, SMRange &SourceRange) const {
1414  const yaml::SIMachineFunctionInfo &YamlMFI =
1415  static_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1416  MachineFunction &MF = PFS.MF;
1418 
1419  if (MFI->initializeBaseYamlFields(YamlMFI, MF, PFS, Error, SourceRange))
1420  return true;
1421 
1422  if (MFI->Occupancy == 0) {
1423  // Fixup the subtarget dependent default value.
1424  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1425  MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1426  }
1427 
1428  auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1429  Register TempReg;
1430  if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1431  SourceRange = RegName.SourceRange;
1432  return true;
1433  }
1434  RegVal = TempReg;
1435 
1436  return false;
1437  };
1438 
1439  auto parseOptionalRegister = [&](const yaml::StringValue &RegName,
1440  Register &RegVal) {
1441  return !RegName.Value.empty() && parseRegister(RegName, RegVal);
1442  };
1443 
1444  if (parseOptionalRegister(YamlMFI.VGPRForAGPRCopy, MFI->VGPRForAGPRCopy))
1445  return true;
1446 
1447  auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1448  // Create a diagnostic for a the register string literal.
1449  const MemoryBuffer &Buffer =
1450  *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1451  Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1452  RegName.Value.size(), SourceMgr::DK_Error,
1453  "incorrect register class for field", RegName.Value,
1454  None, None);
1455  SourceRange = RegName.SourceRange;
1456  return true;
1457  };
1458 
1459  if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1460  parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1461  parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1462  return true;
1463 
1464  if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1465  !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1466  return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1467  }
1468 
1469  if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1470  !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1471  return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1472  }
1473 
1474  if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1475  !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1476  return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1477  }
1478 
1479  for (const auto &YamlReg : YamlMFI.WWMReservedRegs) {
1480  Register ParsedReg;
1481  if (parseRegister(YamlReg, ParsedReg))
1482  return true;
1483 
1484  MFI->reserveWWMRegister(ParsedReg);
1485  }
1486 
1487  auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1488  const TargetRegisterClass &RC,
1489  ArgDescriptor &Arg, unsigned UserSGPRs,
1490  unsigned SystemSGPRs) {
1491  // Skip parsing if it's not present.
1492  if (!A)
1493  return false;
1494 
1495  if (A->IsRegister) {
1496  Register Reg;
1497  if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1498  SourceRange = A->RegisterName.SourceRange;
1499  return true;
1500  }
1501  if (!RC.contains(Reg))
1502  return diagnoseRegisterClass(A->RegisterName);
1504  } else
1505  Arg = ArgDescriptor::createStack(A->StackOffset);
1506  // Check and apply the optional mask.
1507  if (A->Mask)
1508  Arg = ArgDescriptor::createArg(Arg, *A->Mask);
1509 
1510  MFI->NumUserSGPRs += UserSGPRs;
1511  MFI->NumSystemSGPRs += SystemSGPRs;
1512  return false;
1513  };
1514 
1515  if (YamlMFI.ArgInfo &&
1516  (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1517  AMDGPU::SGPR_128RegClass,
1518  MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1519  parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1520  AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1521  2, 0) ||
1522  parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1523  MFI->ArgInfo.QueuePtr, 2, 0) ||
1524  parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1525  AMDGPU::SReg_64RegClass,
1526  MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1527  parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1528  AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1529  2, 0) ||
1530  parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1531  AMDGPU::SReg_64RegClass,
1532  MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1533  parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1534  AMDGPU::SGPR_32RegClass,
1535  MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1536  parseAndCheckArgument(YamlMFI.ArgInfo->LDSKernelId,
1537  AMDGPU::SGPR_32RegClass,
1538  MFI->ArgInfo.LDSKernelId, 0, 1) ||
1539  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1540  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1541  0, 1) ||
1542  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1543  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1544  0, 1) ||
1545  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1546  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1547  0, 1) ||
1548  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1549  AMDGPU::SGPR_32RegClass,
1550  MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1551  parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1552  AMDGPU::SGPR_32RegClass,
1553  MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1554  parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1555  AMDGPU::SReg_64RegClass,
1556  MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1557  parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1558  AMDGPU::SReg_64RegClass,
1559  MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1560  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1561  AMDGPU::VGPR_32RegClass,
1562  MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1563  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1564  AMDGPU::VGPR_32RegClass,
1565  MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1566  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1567  AMDGPU::VGPR_32RegClass,
1568  MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1569  return true;
1570 
1571  MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1572  MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1573  MFI->Mode.FP32InputDenormals = YamlMFI.Mode.FP32InputDenormals;
1574  MFI->Mode.FP32OutputDenormals = YamlMFI.Mode.FP32OutputDenormals;
1577 
1578  return false;
1579 }
llvm::AAResults::addAAResult
void addAAResult(AAResultT &AAResult)
Register a specific AA result.
Definition: AliasAnalysis.h:303
llvm::initializeR600ControlFlowFinalizerPass
void initializeR600ControlFlowFinalizerPass(PassRegistry &)
llvm::TargetPassConfig::addPostRegAlloc
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Definition: TargetPassConfig.h:420
EnableDCEInRA
static cl::opt< bool > EnableDCEInRA("amdgpu-dce-in-ra", cl::init(true), cl::Hidden, cl::desc("Enable machine DCE inside regalloc"))
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:182
llvm::createFastRegisterAllocator
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
Definition: RegAllocFast.cpp:1608
llvm::AAManager
A manager for alias analyses.
Definition: AliasAnalysis.h:876
llvm::AMDGPUAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: AMDGPUAliasAnalysis.h:46
llvm::ArgDescriptor::createStack
static constexpr ArgDescriptor createStack(unsigned Offset, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:49
llvm::AMDGPUFunctionArgInfo::QueuePtr
ArgDescriptor QueuePtr
Definition: AMDGPUArgumentUsageInfo.h:127
EnableLowerModuleLDS
static cl::opt< bool, true > EnableLowerModuleLDS("amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"), cl::location(AMDGPUTargetMachine::EnableLowerModuleLDS), cl::init(true), cl::Hidden)
llvm::initializeR600PacketizerPass
void initializeR600PacketizerPass(PassRegistry &)
LLVMInitializeAMDGPUTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget()
Definition: AMDGPUTargetMachine.cpp:334
llvm::createAMDGPUCtorDtorLoweringPass
ModulePass * createAMDGPUCtorDtorLoweringPass()
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:376
RegAllocOptNotSupportedMessage
static const char RegAllocOptNotSupportedMessage[]
Definition: AMDGPUTargetMachine.cpp:1309
llvm::InferAddressSpacesPass
Definition: InferAddressSpaces.h:16
EnableSIModeRegisterPass
static cl::opt< bool > EnableSIModeRegisterPass("amdgpu-mode-register", cl::desc("Enable mode register pass"), cl::init(true), cl::Hidden)
llvm::PerFunctionMIParsingState::SM
SourceMgr * SM
Definition: MIParser.h:165
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
PassBuilder.h
llvm::createGreedyRegisterAllocator
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
Definition: RegAllocGreedy.cpp:186
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:184
llvm::createAMDGPUAttributorPass
Pass * createAMDGPUAttributorPass()
Definition: AMDGPUAttributor.cpp:794
llvm::PseudoSourceValue::GlobalValueCallEntry
@ GlobalValueCallEntry
Definition: PseudoSourceValue.h:43
llvm::AMDGPUTargetMachine::registerDefaultAliasAnalyses
void registerDefaultAliasAnalyses(AAManager &) override
Allow the target to register alias analyses with the AAManager for use with the new pass manager.
Definition: AMDGPUTargetMachine.cpp:578
mustPreserveGV
static bool mustPreserveGV(const GlobalValue &GV)
Predicate for Internalize pass.
Definition: AMDGPUTargetMachine.cpp:568
llvm::createSeparateConstOffsetFromGEPPass
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Definition: SeparateConstOffsetFromGEP.cpp:498
llvm::OptimizationLevel::O1
static const OptimizationLevel O1
Optimize quickly without destroying debuggability.
Definition: OptimizationLevel.h:57
llvm::GCNTargetMachine::convertFuncInfoToYAML
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
Definition: AMDGPUTargetMachine.cpp:1405
llvm::AMDGPULowerModuleLDSPass
Definition: AMDGPU.h:155
llvm::initializeR600ExpandSpecialInstrsPassPass
void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &)
llvm::initializeAMDGPUPostLegalizerCombinerPass
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
llvm::initializeAMDGPUPromoteAllocaPass
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
llvm::createSIMemoryLegalizerPass
FunctionPass * createSIMemoryLegalizerPass()
Definition: SIMemoryLegalizer.cpp:2351
llvm::SILowerSGPRSpillsID
char & SILowerSGPRSpillsID
Definition: SILowerSGPRSpills.cpp:74
llvm::Wave32
@ Wave32
Definition: AMDGPUMCTargetDesc.h:31
llvm::createAMDGPUSetWavePriorityPass
FunctionPass * createAMDGPUSetWavePriorityPass()
llvm::initializeAMDGPUInsertDelayAluPass
void initializeAMDGPUInsertDelayAluPass(PassRegistry &)
llvm::PassBuilder::registerPipelineStartEPCallback
void registerPipelineStartEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:455
llvm::Type::isPointerTy
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:237
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::AMDGPUAlwaysInlinePass
Definition: AMDGPU.h:248
llvm::yaml::SIMachineFunctionInfo::ArgInfo
Optional< SIArgumentInfo > ArgInfo
Definition: SIMachineFunctionInfo.h:273
SIMachineFunctionInfo.h
Scalar.h
llvm::ArgDescriptor::createArg
static constexpr ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask)
Definition: AMDGPUArgumentUsageInfo.h:54
createMinRegScheduler
static ScheduleDAGInstrs * createMinRegScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:452
llvm::initializeGCNPreRAOptimizationsPass
void initializeGCNPreRAOptimizationsPass(PassRegistry &)
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::Function
Definition: Function.h:60
llvm::cl::location
LocationClass< Ty > location(Ty &L)
Definition: CommandLine.h:467
llvm::Attribute
Definition: Attributes.h:66
llvm::AMDGPU::SIModeRegisterDefaults::FP32OutputDenormals
bool FP32OutputDenormals
Definition: AMDGPUBaseInfo.h:1288
llvm::PassManager::addPass
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT &&Pass)
Definition: PassManager.h:544
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::initializeAMDGPUAlwaysInlinePass
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
llvm::yaml::MachineFunctionInfo
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Definition: MIRYamlMapping.h:676
llvm::PHIEliminationID
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
Definition: PHIElimination.cpp:128
llvm::initializeSIInsertHardClausesPass
void initializeSIInsertHardClausesPass(PassRegistry &)
llvm::initializeAMDGPUOpenCLEnqueuedBlockLoweringPass
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
llvm::AMDGPUFunctionArgInfo::LDSKernelId
ArgDescriptor LDSKernelId
Definition: AMDGPUArgumentUsageInfo.h:132
llvm::initializeSIPreAllocateWWMRegsPass
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::initializeAMDGPUPropagateAttributesLatePass
void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &)
InferAddressSpaces.h
llvm::AMDGPU::SIModeRegisterDefaults::IEEE
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
Definition: AMDGPUBaseInfo.h:1279
llvm::createAlwaysInlinerLegacyPass
Pass * createAlwaysInlinerLegacyPass(bool InsertLifetime=true)
Create a legacy pass manager instance of a pass to inline and remove functions marked as "always_inli...
Definition: AlwaysInliner.cpp:175
getGPUOrDefault
static LLVM_READNONE StringRef getGPUOrDefault(const Triple &TT, StringRef GPU)
Definition: AMDGPUTargetMachine.cpp:513
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::AMDGPUPromoteAllocaToVectorPass
Definition: AMDGPU.h:233
llvm::initializeAMDGPULateCodeGenPreparePass
void initializeAMDGPULateCodeGenPreparePass(PassRegistry &)
llvm::createFixIrreduciblePass
FunctionPass * createFixIrreduciblePass()
Definition: FixIrreducible.cpp:104
llvm::MachineSchedRegistry
MachineSchedRegistry provides a selection of available machine instruction schedulers.
Definition: MachineScheduler.h:143
llvm::createVirtRegRewriter
FunctionPass * createVirtRegRewriter(bool ClearVirtRegs=true)
Definition: VirtRegMap.cpp:646
llvm::Triple::amdgcn
@ amdgcn
Definition: Triple.h:74
GCNSchedStrategy.h
llvm::GCNIterativeScheduler::SCHEDULE_ILP
@ SCHEDULE_ILP
Definition: GCNIterativeScheduler.h:37
llvm::yaml::SIMachineFunctionInfo::VGPRForAGPRCopy
StringValue VGPRForAGPRCopy
Definition: SIMachineFunctionInfo.h:276
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:173
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:729
llvm::createAMDGPULateCodeGenPreparePass
FunctionPass * createAMDGPULateCodeGenPreparePass()
Definition: AMDGPULateCodeGenPrepare.cpp:193
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::createSILowerI1CopiesPass
FunctionPass * createSILowerI1CopiesPass()
Definition: SILowerI1Copies.cpp:404
llvm::initializeR600ClauseMergePassPass
void initializeR600ClauseMergePassPass(PassRegistry &)
llvm::GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY
@ SCHEDULE_LEGACYMAXOCCUPANCY
Definition: GCNIterativeScheduler.h:36
llvm::createFlattenCFGPass
FunctionPass * createFlattenCFGPass()
Definition: FlattenCFGPass.cpp:81
llvm::InternalizePass
A pass that internalizes all functions and variables other than those that must be preserved accordin...
Definition: Internalize.h:35
llvm::initializeSIOptimizeExecMaskingPreRAPass
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
llvm::AMDGPUFunctionArgInfo::FlatScratchInit
ArgDescriptor FlatScratchInit
Definition: AMDGPUArgumentUsageInfo.h:130
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
FAM
FunctionAnalysisManager FAM
Definition: PassBuilderBindings.cpp:59
llvm::createEarlyCSEPass
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1790
llvm::Wave64
@ Wave64
Definition: AMDGPUMCTargetDesc.h:31
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:127
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
GCNVOPDUtils.h
llvm::initializeSILowerI1CopiesPass
void initializeSILowerI1CopiesPass(PassRegistry &)
llvm::AMDGPUMachineFunction::getLDSSize
uint32_t getLDSSize() const
Definition: AMDGPUMachineFunction.h:72
EnableSetWavePriority
static cl::opt< bool > EnableSetWavePriority("amdgpu-set-wave-priority", cl::desc("Adjust wave priority"), cl::init(false), cl::Hidden)
llvm::SIPreEmitPeepholeID
char & SIPreEmitPeepholeID
llvm::createAMDGPUPostLegalizeCombiner
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPostLegalizerCombiner.cpp:454
llvm::initializeAMDGPUDAGToDAGISelPass
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
llvm::AMDGPUAS::GLOBAL_ADDRESS
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:372
llvm::initializeSIPeepholeSDWAPass
void initializeSIPeepholeSDWAPass(PassRegistry &)
llvm::ShadowStackGCLoweringID
char & ShadowStackGCLoweringID
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC.
Definition: ShadowStackGCLowering.cpp:92
llvm::SILowerControlFlowID
char & SILowerControlFlowID
Definition: SILowerControlFlow.cpp:175
llvm::yaml::SIMachineFunctionInfo
Definition: SIMachineFunctionInfo.h:247
llvm::X86AS::FS
@ FS
Definition: X86.h:200
llvm::SIOptimizeVGPRLiveRangeID
char & SIOptimizeVGPRLiveRangeID
Definition: SIOptimizeVGPRLiveRange.cpp:618
InstructionSelect.h
EnableStructurizerWorkarounds
static cl::opt< bool > EnableStructurizerWorkarounds("amdgpu-enable-structurizer-workarounds", cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true), cl::Hidden)
llvm::AMDGPUPassConfig
Definition: AMDGPUTargetMachine.h:106
llvm::AMDGPUAAWrapperPass
Legacy wrapper pass to provide the AMDGPUAAResult object.
Definition: AMDGPUAliasAnalysis.h:60
EnableAtomicOptimizations
static cl::opt< bool > EnableAtomicOptimizations("amdgpu-atomic-optimizations", cl::desc("Enable atomic optimizations"), cl::init(false), cl::Hidden)
createGCNMaxOccupancyMachineScheduler
static ScheduleDAGInstrs * createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:420
llvm::Optional< Reloc::Model >
llvm::GCNScheduleDAGMILive
Definition: GCNSchedStrategy.h:129
llvm::initializeSIFoldOperandsPass
void initializeSIFoldOperandsPass(PassRegistry &)
IterativeGCNMaxOccupancySchedRegistry
static MachineSchedRegistry IterativeGCNMaxOccupancySchedRegistry("gcn-iterative-max-occupancy-experimental", "Run GCN scheduler to maximize occupancy (experimental)", createIterativeGCNMaxOccupancyMachineScheduler)
llvm::createBarrierNoopPass
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
Definition: BarrierNoopPass.cpp:43
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::createAMDGPUISelDag
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
Definition: AMDGPUISelDAGToDAG.cpp:114
InternalizeSymbols
static cl::opt< bool > InternalizeSymbols("amdgpu-internalize-symbols", cl::desc("Enable elimination of non-kernel functions and unused globals"), cl::init(false), cl::Hidden)
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
llvm::AMDGPU::SIModeRegisterDefaults::FP32InputDenormals
bool FP32InputDenormals
If this is set, neither input or output denormals are flushed for most f32 instructions.
Definition: AMDGPUBaseInfo.h:1287
llvm::PassBuilder::registerAnalysisRegistrationCallback
void registerAnalysisRegistrationCallback(const std::function< void(CGSCCAnalysisManager &)> &C)
{{@ Register callbacks for analysis registration with this PassBuilder instance.
Definition: PassBuilder.h:515
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
SIMachineScheduler.h
llvm::yaml::SIMode::FP32OutputDenormals
bool FP32OutputDenormals
Definition: SIMachineFunctionInfo.h:211
llvm::createGVNPass
FunctionPass * createGVNPass(bool NoMemDepAnalysis=false)
Create a legacy GVN pass.
Definition: GVN.cpp:3244
llvm::AMDGPUReleaseVGPRsID
char & AMDGPUReleaseVGPRsID
Definition: AMDGPUReleaseVGPRs.cpp:154
llvm::createCGSCCToFunctionPassAdaptor
CGSCCToFunctionPassAdaptor createCGSCCToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false, bool NoRerun=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: CGSCCPassManager.h:509
llvm::AMDGPUFunctionArgInfo::PrivateSegmentSize
ArgDescriptor PrivateSegmentSize
Definition: AMDGPUArgumentUsageInfo.h:131
llvm::createR600OpenCLImageTypeLoweringPass
ModulePass * createR600OpenCLImageTypeLoweringPass()
Definition: R600OpenCLImageTypeLoweringPass.cpp:372
llvm::AMDGPUUseNativeCallsPass
Definition: AMDGPU.h:69
llvm::AMDGPUFunctionArgInfo::DispatchPtr
ArgDescriptor DispatchPtr
Definition: AMDGPUArgumentUsageInfo.h:126
llvm::PatternMatch::m_c_And
BinaryOp_match< LHS, RHS, Instruction::And, true > m_c_And(const LHS &L, const RHS &R)
Matches an And with LHS and RHS in either order.
Definition: PatternMatch.h:2251
llvm::initializeAMDGPUPropagateAttributesEarlyPass
void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &)
llvm::SIPreAllocateWWMRegsID
char & SIPreAllocateWWMRegsID
Definition: SIPreAllocateWWMRegs.cpp:84
AMDGPUIGroupLP.h
llvm::initializeAMDGPURewriteUndefForPHIPass
void initializeAMDGPURewriteUndefForPHIPass(PassRegistry &)
llvm::initializeAMDGPUPromoteKernelArgumentsPass
void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &)
llvm::SIPostRABundlerID
char & SIPostRABundlerID
Definition: SIPostRABundler.cpp:69
llvm::OptimizationLevel::O0
static const OptimizationLevel O0
Disable as many optimizations as possible.
Definition: OptimizationLevel.h:41
llvm::initializeSIShrinkInstructionsPass
void initializeSIShrinkInstructionsPass(PassRegistry &)
LegacyPassManager.h
llvm::TwoAddressInstructionPassID
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Definition: TwoAddressInstructionPass.cpp:193
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::cl::ReallyHidden
@ ReallyHidden
Definition: CommandLine.h:141
llvm::GCNTargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: AMDGPUTargetMachine.cpp:1411
llvm::initializeAMDGPUSimplifyLibCallsPass
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
Internalize.h
createSIMachineScheduler
static ScheduleDAGInstrs * createSIMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:415
llvm::PatternMatch::m_Deferred
deferredval_ty< Value > m_Deferred(Value *const &V)
Like m_Specific(), but works if the specific value to match is determined as part of the same match()...
Definition: PatternMatch.h:790
llvm::MemoryBuffer
This interface provides simple read-only access to a block of memory, and provides simple methods for...
Definition: MemoryBuffer.h:51
llvm::AMDGPUPassConfig::addGCPasses
bool addGCPasses() override
addGCPasses - Add late codegen passes that analyze code for garbage collection.
Definition: AMDGPUTargetMachine.cpp:1069
F
#define F(x, y, z)
Definition: MD5.cpp:55
EnableInsertDelayAlu
static cl::opt< bool > EnableInsertDelayAlu("amdgpu-enable-delay-alu", cl::desc("Enable s_delay_alu insertion"), cl::init(true), cl::Hidden)
llvm::AMDGPUFunctionArgInfo::DispatchID
ArgDescriptor DispatchID
Definition: AMDGPUArgumentUsageInfo.h:129
llvm::PseudoSourceValue::JumpTable
@ JumpTable
Definition: PseudoSourceValue.h:40
llvm::initializeAMDGPULowerIntrinsicsPass
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
llvm::initializeGCNDPPCombinePass
void initializeGCNDPPCombinePass(PassRegistry &)
llvm::AMDGPUUnifyMetadataPass
Definition: AMDGPU.h:274
llvm::AMDGPUFunctionArgInfo::ImplicitArgPtr
ArgDescriptor ImplicitArgPtr
Definition: AMDGPUArgumentUsageInfo.h:143
EnableSDWAPeephole
static cl::opt< bool > EnableSDWAPeephole("amdgpu-sdwa-peephole", cl::desc("Enable SDWA peepholer"), cl::init(true))
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::AMDGPUAS::REGION_ADDRESS
@ REGION_ADDRESS
Address space for region memory. (GDS)
Definition: AMDGPU.h:373
CSEInfo.h
FunctionPassCtor
llvm::SIOptimizeExecMaskingID
char & SIOptimizeExecMaskingID
Definition: SIOptimizeExecMasking.cpp:90
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::initializeAMDGPUUnifyMetadataPass
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
llvm::yaml::SIMachineFunctionInfo::FrameOffsetReg
StringValue FrameOffsetReg
Definition: SIMachineFunctionInfo.h:267
llvm::initializeAMDGPUArgumentUsageInfoPass
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
R600.h
llvm::AMDGPUPassConfig::addIRPasses
void addIRPasses() override
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: AMDGPUTargetMachine.cpp:943
SISchedRegistry
static MachineSchedRegistry SISchedRegistry("si", "Run SI's custom scheduler", createSIMachineScheduler)
GCNIterativeScheduler.h
llvm::AMDGPUFunctionArgInfo::WorkGroupIDX
ArgDescriptor WorkGroupIDX
Definition: AMDGPUArgumentUsageInfo.h:135
llvm::GCNTargetMachine::GCNTargetMachine
GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AMDGPUTargetMachine.cpp:800
llvm::createInferAddressSpacesPass
FunctionPass * createInferAddressSpacesPass(unsigned AddressSpace=~0u)
Definition: InferAddressSpaces.cpp:1309
llvm::initializeSILateBranchLoweringPass
void initializeSILateBranchLoweringPass(PassRegistry &)
llvm::TargetPassConfig::TM
LLVMTargetMachine * TM
Definition: TargetPassConfig.h:122
AMDGPUAliasAnalysis.h
llvm::AMDGPUTargetMachine
Definition: AMDGPUTargetMachine.h:28
llvm::MSP430Attrs::CodeModel
CodeModel
Definition: MSP430Attributes.h:37
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
AlwaysInliner.h
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::AAResults
Definition: AliasAnalysis.h:294
llvm::yaml::SIMode::FP32InputDenormals
bool FP32InputDenormals
Definition: SIMachineFunctionInfo.h:210
llvm::PassBuilder::registerParseAACallback
void registerParseAACallback(const std::function< bool(StringRef Name, AAManager &AA)> &C)
Register a callback for parsing an AliasAnalysis Name to populate the given AAManager AA.
Definition: PassBuilder.h:507
GCNMaxILPSchedRegistry
static MachineSchedRegistry GCNMaxILPSchedRegistry("gcn-max-ilp", "Run GCN scheduler to maximize ilp", createGCNMaxILPMachineScheduler)
ScalarizeGlobal
static cl::opt< bool > ScalarizeGlobal("amdgpu-scalarize-global-loads", cl::desc("Enable global load scalarization"), cl::init(true), cl::Hidden)
llvm::createNaryReassociatePass
FunctionPass * createNaryReassociatePass()
Definition: NaryReassociate.cpp:165
llvm::PostRAHazardRecognizerID
char & PostRAHazardRecognizerID
PostRAHazardRecognizer - This pass runs the post-ra hazard recognizer.
Definition: PostRAHazardRecognizer.cpp:61
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::initializeAMDGPULowerKernelArgumentsPass
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
llvm::initializeSIWholeQuadModePass
void initializeSIWholeQuadModePass(PassRegistry &)
llvm::initializeAMDGPUAtomicOptimizerPass
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
llvm::getTheAMDGPUTarget
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
Definition: AMDGPUTargetInfo.cpp:20
llvm::Legalizer
Definition: Legalizer.h:36
llvm::AMDGPUFunctionArgInfo::WorkItemIDX
ArgDescriptor WorkItemIDX
Definition: AMDGPUArgumentUsageInfo.h:150
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
EnableAMDGPUAliasAnalysis
static cl::opt< bool > EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden, cl::desc("Enable AMDGPU Alias Analysis"), cl::init(true))
EnableLowerKernelArguments
static cl::opt< bool > EnableLowerKernelArguments("amdgpu-ir-lower-kernel-arguments", cl::desc("Lower kernel argument loads in IR pass"), cl::init(true), cl::Hidden)
EnableLoadStoreVectorizer
static cl::opt< bool > EnableLoadStoreVectorizer("amdgpu-load-store-vectorizer", cl::desc("Enable load store vectorizer"), cl::init(true), cl::Hidden)
AMDGPUTargetInfo.h
llvm::createAMDGPULowerModuleLDSPass
ModulePass * createAMDGPULowerModuleLDSPass()
EnableMaxIlpSchedStrategy
static cl::opt< bool > EnableMaxIlpSchedStrategy("amdgpu-enable-max-ilp-scheduling-strategy", cl::desc("Enable scheduling strategy to maximize ILP for a single wave."), cl::Hidden, cl::init(false))
R600TargetMachine.h
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
AMDGPUMacroFusion.h
llvm::initializeAMDGPUUseNativeCallsPass
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
llvm::createSIInsertWaitcntsPass
FunctionPass * createSIInsertWaitcntsPass()
Definition: SIInsertWaitcnts.cpp:850
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
EnableLDSReplaceWithPointer
static cl::opt< bool > EnableLDSReplaceWithPointer("amdgpu-enable-lds-replace-with-pointer", cl::desc("Enable LDS replace with pointer pass"), cl::init(false), cl::Hidden)
llvm::PassBuilder
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:97
EnableRegReassign
static cl::opt< bool > EnableRegReassign("amdgpu-reassign-regs", cl::desc("Enable register reassign optimizations on gfx10+"), cl::init(true), cl::Hidden)
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
llvm::yaml::SIMode::FP64FP16InputDenormals
bool FP64FP16InputDenormals
Definition: SIMachineFunctionInfo.h:212
llvm::createAMDGPUAnnotateUniformValues
FunctionPass * createAMDGPUAnnotateUniformValues()
Definition: AMDGPUAnnotateUniformValues.cpp:122
llvm::initializeAMDGPUUnifyDivergentExitNodesPass
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:782
useDefaultRegisterAllocator
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Definition: TargetPassConfig.cpp:1127
llvm::AMDGPUPromoteAllocaPass
Definition: AMDGPU.h:225
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
llvm::AMDGPUTargetMachine::getNullPointerValue
static int64_t getNullPointerValue(unsigned AddrSpace)
Get the integer value of a null pointer in the given address space.
Definition: AMDGPUTargetMachine.cpp:720
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1356
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:325
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::Triple::r600
@ r600
Definition: Triple.h:73
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createUnifyLoopExitsPass
FunctionPass * createUnifyLoopExitsPass()
Definition: UnifyLoopExits.cpp:61
llvm::GCNIterativeScheduler
Definition: GCNIterativeScheduler.h:29
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: AMDGPUTargetMachine.cpp:411
llvm::PseudoSourceValue::FixedStack
@ FixedStack
Definition: PseudoSourceValue.h:42
llvm::SourceMgr::getMainFileID
unsigned getMainFileID() const
Definition: SourceMgr.h:132
AMDGPUTargetObjectFile.h
llvm::AMDGPULowerKernelAttributesPass
Definition: AMDGPU.h:115
llvm::AMDGPUTargetMachine::getAddressSpaceForPseudoSourceKind
unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override
getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g.
Definition: AMDGPUTargetMachine.cpp:781
GVN.h
llvm::initializeSIMemoryLegalizerPass
void initializeSIMemoryLegalizerPass(PassRegistry &)
llvm::createLoadStoreVectorizerPass
Pass * createLoadStoreVectorizerPass()
Create a legacy pass manager instance of the LoadStoreVectorizer pass.
llvm::initializeAMDGPUResourceUsageAnalysisPass
void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &)
EnableDPPCombine
static cl::opt< bool > EnableDPPCombine("amdgpu-dpp-combine", cl::desc("Enable DPP combiner"), cl::init(true))
llvm::createAMDGPULowerIntrinsicsPass
ModulePass * createAMDGPULowerIntrinsicsPass()
Definition: AMDGPULowerIntrinsics.cpp:175
llvm::AMDGPUPassConfig::addCodeGenPrepare
void addCodeGenPrepare() override
Add pass to prepare the LLVM IR for code generation.
Definition: AMDGPUTargetMachine.cpp:1033
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
llvm::createAMDGPUAnnotateKernelFeaturesPass
Pass * createAMDGPUAnnotateKernelFeaturesPass()
Definition: AMDGPUAnnotateKernelFeatures.cpp:137
llvm::initializeAMDGPUReplaceLDSUseWithPointerPass
void initializeAMDGPUReplaceLDSUseWithPointerPass(PassRegistry &)
PatternMatch.h
llvm::AMDGPUTargetMachine::~AMDGPUTargetMachine
~AMDGPUTargetMachine() override
llvm::AMDGPUTargetMachine::getSubtargetImpl
const TargetSubtargetInfo * getSubtargetImpl() const
llvm::createSinkingPass
FunctionPass * createSinkingPass()
Definition: Sink.cpp:277
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:354
Utils.h
llvm::SILoadStoreOptimizerID
char & SILoadStoreOptimizerID
Definition: SILoadStoreOptimizer.cpp:800
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:312
llvm::RegisterPassParser
RegisterPassParser class - Handle the addition of new machine passes.
Definition: MachinePassRegistry.h:135
llvm::Value::use_empty
bool use_empty() const
Definition: Value.h:344
llvm::createAMDGPUExportClusteringDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAMDGPUExportClusteringDAGMutation()
Definition: AMDGPUExportClustering.cpp:144
GCNILPSchedRegistry
static MachineSchedRegistry GCNILPSchedRegistry("gcn-iterative-ilp", "Run GCN iterative scheduler for ILP scheduling (experimental)", createIterativeILPMachineScheduler)
llvm::initializeSIOptimizeVGPRLiveRangePass
void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &)
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1831
llvm::SmallString< 128 >
llvm::SourceMgr::getMemoryBuffer
const MemoryBuffer * getMemoryBuffer(unsigned i) const
Definition: SourceMgr.h:125
llvm::MemoryBuffer::getBufferIdentifier
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
Definition: MemoryBuffer.h:76
llvm::createAMDGPUAAWrapperPass
ImmutablePass * createAMDGPUAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:33
llvm::createLowerSwitchPass
FunctionPass * createLowerSwitchPass()
Definition: LowerSwitch.cpp:587
llvm::createAMDGPUPrintfRuntimeBinding
ModulePass * createAMDGPUPrintfRuntimeBinding()
Definition: AMDGPUPrintfRuntimeBinding.cpp:93
AMDGPUTargetTransformInfo.h
llvm::AMDGPUPassConfig::addInstSelector
bool addInstSelector() override
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
Definition: AMDGPUTargetMachine.cpp:1064
PB
PassBuilder PB(Machine, PassOpts->PTO, None, &PIC)
Passes.h
llvm::Triple::AMDHSA
@ AMDHSA
Definition: Triple.h:210
llvm::VirtRegRewriterID
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:227
llvm::createAMDGPUAlwaysInlinePass
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPUAlwaysInlinePass.cpp:163
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::SmallString::append
void append(StringRef RHS)
Append from a StringRef.
Definition: SmallString.h:68
llvm::initializeSILowerSGPRSpillsPass
void initializeSILowerSGPRSpillsPass(PassRegistry &)
llvm::PseudoSourceValue::ExternalSymbolCallEntry
@ ExternalSymbolCallEntry
Definition: PseudoSourceValue.h:44
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::PassBuilder::registerPipelineEarlySimplificationEPCallback
void registerPipelineEarlySimplificationEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:464
llvm::AMDGPUTargetMachine::getFeatureString
StringRef getFeatureString(const Function &F) const
Definition: AMDGPUTargetMachine.cpp:560
OptVGPRLiveRange
static cl::opt< bool > OptVGPRLiveRange("amdgpu-opt-vgpr-liverange", cl::desc("Enable VGPR liverange optimizations for if-else structure"), cl::init(true), cl::Hidden)
llvm::cl::opt
Definition: CommandLine.h:1412
llvm::createLCSSAPass
Pass * createLCSSAPass()
Definition: LCSSA.cpp:491
llvm::createModuleToFunctionPassAdaptor
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:1218
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:95
OptExecMaskPreRA
static cl::opt< bool > OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden, cl::desc("Run pre-RA exec mask optimizations"), cl::init(true))
llvm::GCLoweringID
char & GCLoweringID
GCLowering Pass - Used by gc.root to perform its default lowering operations.
Definition: GCRootLowering.cpp:85
llvm::yaml::SIMachineFunctionInfo::ScratchRSrcReg
StringValue ScratchRSrcReg
Definition: SIMachineFunctionInfo.h:266
llvm::GlobalValue
Definition: GlobalValue.h:44
GCNMinRegSchedRegistry
static MachineSchedRegistry GCNMinRegSchedRegistry("gcn-iterative-minreg", "Run GCN iterative scheduler for minimal register usage (experimental)", createMinRegScheduler)
llvm::AMDGPUUnifyDivergentExitNodesID
char & AMDGPUUnifyDivergentExitNodesID
Definition: AMDGPUUnifyDivergentExitNodes.cpp:79
llvm::initializeGCNCreateVOPDPass
void initializeGCNCreateVOPDPass(PassRegistry &)
llvm::initializeSIInsertWaitcntsPass
void initializeSIInsertWaitcntsPass(PassRegistry &)
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::initializeSIAnnotateControlFlowPass
void initializeSIAnnotateControlFlowPass(PassRegistry &)
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3488
llvm::AMDGPUFunctionArgInfo::WorkGroupIDZ
ArgDescriptor WorkGroupIDZ
Definition: AMDGPUArgumentUsageInfo.h:137
llvm::RegisterRegAllocBase< RegisterRegAlloc >::FunctionPassCtor
FunctionPass *(*)() FunctionPassCtor
Definition: RegAllocRegistry.h:32
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
llvm::DetectDeadLanesID
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
Definition: DetectDeadLanes.cpp:125
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::TargetMachine::getMCSubtargetInfo
const MCSubtargetInfo * getMCSubtargetInfo() const
Definition: TargetMachine.h:208
llvm::AMDGPUFunctionArgInfo::PrivateSegmentBuffer
ArgDescriptor PrivateSegmentBuffer
Definition: AMDGPUArgumentUsageInfo.h:125
llvm::SIMachineFunctionInfo::reserveWWMRegister
void reserveWWMRegister(Register Reg)
Definition: SIMachineFunctionInfo.h:526
llvm::createAMDGPUAtomicOptimizerPass
FunctionPass * createAMDGPUAtomicOptimizerPass()
Definition: AMDGPUAtomicOptimizer.cpp:713
llvm::initializeR600VectorRegMergerPass
void initializeR600VectorRegMergerPass(PassRegistry &)
IPO.h
llvm::SIPeepholeSDWAID
char & SIPeepholeSDWAID
Definition: SIPeepholeSDWA.cpp:192
llvm::SIMachineFunctionInfo::initializeBaseYamlFields
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
Definition: SIMachineFunctionInfo.cpp:626
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::GCNTTIImpl
Definition: AMDGPUTargetTransformInfo.h:59
llvm::SIFixVGPRCopiesID
char & SIFixVGPRCopiesID
Definition: SIFixVGPRCopies.cpp:45
llvm::initializeAMDGPURewriteOutArgumentsPass
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
CGSCCPassManager.h
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:127
llvm::GCNIterativeScheduler::SCHEDULE_MINREGFORCED
@ SCHEDULE_MINREGFORCED
Definition: GCNIterativeScheduler.h:35
llvm::AMDGPUAS::UNKNOWN_ADDRESS_SPACE
@ UNKNOWN_ADDRESS_SPACE
Definition: AMDGPU.h:412
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AMDGPUSimplifyLibCallsPass
Definition: AMDGPU.h:61
llvm::AMDGPUPassConfig::createMachineScheduler
ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override
Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...
Definition: AMDGPUTargetMachine.cpp:1075
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:854
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
llvm::TargetPassConfig::addOptimizedRegAlloc
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: TargetPassConfig.cpp:1462
llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset
ArgDescriptor PrivateSegmentWaveByteOffset
Definition: AMDGPUArgumentUsageInfo.h:139
llvm::SIFormMemoryClausesID
char & SIFormMemoryClausesID
Definition: SIFormMemoryClauses.cpp:91
llvm::LiveVariablesID
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
Definition: LiveVariables.cpp:45
LateCFGStructurize
static cl::opt< bool, true > LateCFGStructurize("amdgpu-late-structurize", cl::desc("Enable late CFG structurization"), cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG), cl::Hidden)
TargetPassConfig.h
llvm::yaml::SIMachineFunctionInfo::WWMReservedRegs
SmallVector< StringValue > WWMReservedRegs
Definition: SIMachineFunctionInfo.h:264
llvm::createExternalAAWrapperPass
ImmutablePass * createExternalAAWrapperPass(std::function< void(Pass &, Function &, AAResults &)> Callback)
A wrapper pass around a callback which can be used to populate the AAResults in the AAResultsWrapperP...
llvm::SIFixSGPRCopiesID
char & SIFixSGPRCopiesID
Definition: SIFixSGPRCopies.cpp:175
llvm::AMDGPUFunctionArgInfo::WorkGroupIDY
ArgDescriptor WorkGroupIDY
Definition: AMDGPUArgumentUsageInfo.h:136
Localizer.h
EnableVOPD
static cl::opt< bool > EnableVOPD("amdgpu-enable-vopd", cl::desc("Enable VOPD, dual issue of VALU in wave32"), cl::init(true), cl::Hidden)
llvm::PseudoSourceValue::ConstantPool
@ ConstantPool
Definition: PseudoSourceValue.h:41
llvm::MachineCSEID
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:162
llvm::GCNDPPCombineID
char & GCNDPPCombineID
Definition: GCNDPPCombine.cpp:111
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:996
llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:1283
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SIInsertHardClausesID
char & SIInsertHardClausesID
Definition: SIInsertHardClauses.cpp:273
llvm::AMDGPUPassConfig::addStraightLineScalarOptimizationPasses
void addStraightLineScalarOptimizationPasses()
Definition: AMDGPUTargetMachine.cpp:927
llvm::AMDGPU::isFlatGlobalAddrSpace
bool isFlatGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:419
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
Definition: AMDGPUBaseInfo.h:1292
llvm::AMDGPUTargetMachine::getPredicatedAddrSpace
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const override
If the specified predicate checks whether a generic pointer falls within a specified address space,...
Definition: AMDGPUTargetMachine.cpp:754
llvm::getTheGCNTarget
Target & getTheGCNTarget()
The target for GCN GPUs.
Definition: AMDGPUTargetInfo.cpp:25
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:377
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::AMDGPUPassConfig::getAMDGPUTargetMachine
AMDGPUTargetMachine & getAMDGPUTargetMachine() const
Definition: AMDGPUTargetMachine.h:110
llvm::initializeSIOptimizeExecMaskingPass
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
llvm::initializeSIPostRABundlerPass
void initializeSIPostRABundlerPass(PassRegistry &)
llvm::SIScheduleDAGMI
Definition: SIMachineScheduler.h:425
llvm::PassBuilder::registerPipelineParsingCallback
void registerPipelineParsingCallback(const std::function< bool(StringRef Name, CGSCCPassManager &, ArrayRef< PipelineElement >)> &C)
{{@ Register pipeline parsing callbacks with this pass builder instance.
Definition: PassBuilder.h:537
llvm::initializeAMDGPUAAWrapperPassPass
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:273
llvm::initializeAMDGPUCodeGenPreparePass
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
llvm::AMDGPUPassConfig::AMDGPUPassConfig
AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
Definition: AMDGPUTargetMachine.cpp:909
llvm::createAMDGPUOpenCLEnqueuedBlockLoweringPass
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
llvm::initializeGCNNSAReassignPass
void initializeGCNNSAReassignPass(PassRegistry &)
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::AMDGPUTargetMachine::EnableLowerModuleLDS
static bool EnableLowerModuleLDS
Definition: AMDGPUTargetMachine.h:38
llvm::yaml::StringValue
A wrapper around std::string which contains a source range that's being set during parsing.
Definition: MIRYamlMapping.h:34
llvm::GlobalDCEPass
Pass to remove unused function declarations.
Definition: GlobalDCE.h:36
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
AMDGPUExportClustering.h
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::AMDGPUFunctionArgInfo::WorkItemIDZ
ArgDescriptor WorkItemIDZ
Definition: AMDGPUArgumentUsageInfo.h:152
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::createSIShrinkInstructionsPass
FunctionPass * createSIShrinkInstructionsPass()
llvm::createAMDGPUMachineCFGStructurizerPass
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
Definition: AMDGPUMachineCFGStructurizer.cpp:2851
llvm::GCNTargetMachine
Definition: AMDGPUTargetMachine.h:73
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:487
llvm::ScheduleDAG::TRI
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:558
llvm::TargetPassConfig::addPass
AnalysisID addPass(AnalysisID PassID)
Utilities for targets to add passes to the pass manager.
Definition: TargetPassConfig.cpp:782
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::Constant::removeDeadConstantUsers
void removeDeadConstantUsers() const
If there are any dead constant users dangling off of this constant, remove them.
Definition: Constants.cpp:702
llvm::initializeSIFormMemoryClausesPass
void initializeSIFormMemoryClausesPass(PassRegistry &)
computeDataLayout
static StringRef computeDataLayout(const Triple &TT)
Definition: AMDGPUTargetMachine.cpp:497
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::initializeAMDGPUExternalAAWrapperPass
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
AMDGPU.h
llvm::yaml::SIMachineFunctionInfo::StackPtrOffsetReg
StringValue StackPtrOffsetReg
Definition: SIMachineFunctionInfo.h:268
SimplifyLibCalls.h
llvm::AMDGPUPassConfig::addPreISel
bool addPreISel() override
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Definition: AMDGPUTargetMachine.cpp:1058
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
GlobalDCE.h
llvm::yaml::SIMachineFunctionInfo::Mode
SIMode Mode
Definition: SIMachineFunctionInfo.h:274
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:75
llvm::createAMDGPURegBankCombiner
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
Definition: AMDGPURegBankCombiner.cpp:489
EnablePreRAOptimizations
static cl::opt< bool > EnablePreRAOptimizations("amdgpu-enable-pre-ra-optimizations", cl::desc("Enable Pre-RA optimizations pass"), cl::init(true), cl::Hidden)
IRTranslator.h
llvm::TargetMachine::getTargetFeatureString
StringRef getTargetFeatureString() const
Definition: TargetMachine.h:127
EarlyInlineAll
static cl::opt< bool > EarlyInlineAll("amdgpu-early-inline-all", cl::desc("Inline all functions early"), cl::init(false), cl::Hidden)
llvm::createVOPDPairingMutation
std::unique_ptr< ScheduleDAGMutation > createVOPDPairingMutation()
Definition: GCNVOPDUtils.cpp:181
llvm::once_flag
std::once_flag once_flag
Definition: Threading.h:56
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::AMDGPUFunctionArgInfo::ImplicitBufferPtr
ArgDescriptor ImplicitBufferPtr
Definition: AMDGPUArgumentUsageInfo.h:146
llvm::SIWholeQuadModeID
char & SIWholeQuadModeID
Definition: SIWholeQuadMode.cpp:267
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
EnableSROA
static cl::opt< bool > EnableSROA("amdgpu-sroa", cl::desc("Run SROA after promote alloca pass"), cl::ReallyHidden, cl::init(true))
llvm::initializeAMDGPULowerKernelAttributesPass
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:500
llvm::AMDGPUPassConfig::getCSEConfig
std::unique_ptr< CSEConfigBase > getCSEConfig() const override
Returns the CSEConfig object to use for the current optimization level.
Definition: AMDGPUTargetMachine.cpp:839
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:62
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
llvm::initializeAMDGPUAnnotateUniformValuesPass
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
llvm::RenameIndependentSubregsID
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
Definition: RenameIndependentSubregs.cpp:113
llvm::AMDGPUPrintfRuntimeBindingPass
Definition: AMDGPU.h:265
llvm::AMDGPUReplaceLDSUseWithPointerPass
Definition: AMDGPU.h:147
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::createStructurizeCFGPass
Pass * createStructurizeCFGPass(bool SkipUniformRegions=false)
When SkipUniformRegions is true the structizer will not structurize regions that only contain uniform...
Definition: StructurizeCFG.cpp:1205
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: AMDGPUBaseInfo.h:1293
llvm::GCNTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: AMDGPUTargetMachine.cpp:1396
llvm::PassManager< Module >
llvm::GCNCreateVOPDID
char & GCNCreateVOPDID
Definition: GCNCreateVOPD.cpp:161
llvm::PseudoSourceValue::GOT
@ GOT
Definition: PseudoSourceValue.h:39
llvm::initializeSIFixSGPRCopiesPass
void initializeSIFixSGPRCopiesPass(PassRegistry &)
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::AMDGPUFunctionArgInfo::WorkGroupInfo
ArgDescriptor WorkGroupInfo
Definition: AMDGPUArgumentUsageInfo.h:138
llvm::OptimizationLevel::getSpeedupLevel
unsigned getSpeedupLevel() const
Definition: OptimizationLevel.h:121
llvm::initializeAMDGPULowerModuleLDSPass
void initializeAMDGPULowerModuleLDSPass(PassRegistry &)
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:189
createIterativeILPMachineScheduler
static ScheduleDAGInstrs * createIterativeILPMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:458
llvm::parseNamedRegisterReference
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
Definition: MIParser.cpp:3519
llvm::initializeAMDGPUReleaseVGPRsPass
void initializeAMDGPUReleaseVGPRsPass(PassRegistry &)
EnableEarlyIfConversion
static cl::opt< bool > EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(false))
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:375
llvm::initializeSIFixVGPRCopiesPass
void initializeSIFixVGPRCopiesPass(PassRegistry &)
llvm::yaml::SIMode::DX10Clamp
bool DX10Clamp
Definition: SIMachineFunctionInfo.h:209
llvm::initializeAMDGPUPromoteAllocaToVectorPass
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)
EnableScalarIRPasses
static cl::opt< bool > EnableScalarIRPasses("amdgpu-scalar-ir-passes", cl::desc("Enable scalar IR passes"), cl::init(true), cl::Hidden)
llvm::AMDGPUPromoteKernelArgumentsPass
Definition: AMDGPU.h:106
llvm::initializeSIPreEmitPeepholePass
void initializeSIPreEmitPeepholePass(PassRegistry &)
createIterativeGCNMaxOccupancyMachineScheduler
static ScheduleDAGInstrs * createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:442
llvm::call_once
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:86
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
llvm::GCNTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: AMDGPUTargetMachine.cpp:831
llvm::AMDGPUTargetMachine::registerPassBuilderCallbacks
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline.
Definition: AMDGPUTargetMachine.cpp:582
EnablePromoteKernelArguments
static cl::opt< bool > EnablePromoteKernelArguments("amdgpu-enable-promote-kernel-arguments", cl::desc("Enable promotion of flat kernel pointer arguments to global"), cl::Hidden, cl::init(true))
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1308
llvm::AMDGPUPassConfig::addEarlyCSEOrGVNPass
void addEarlyCSEOrGVNPass()
Definition: AMDGPUTargetMachine.cpp:920
llvm::createAMDGPUPropagateAttributesEarlyPass
FunctionPass * createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:400
llvm::AMDGPUPropagateAttributesEarlyPass
Definition: AMDGPU.h:123
llvm::initializeSIModeRegisterPass
void initializeSIModeRegisterPass(PassRegistry &)
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::createLoadClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1572
RegBankSelect.h
llvm::ScheduleDAG::TII
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:557
GCNMaxOccupancySchedRegistry
static MachineSchedRegistry GCNMaxOccupancySchedRegistry("gcn-max-occupancy", "Run GCN scheduler to maximize occupancy", createGCNMaxOccupancyMachineScheduler)
llvm::createAMDGPULowerKernelArgumentsPass
FunctionPass * createAMDGPULowerKernelArgumentsPass()
Definition: AMDGPULowerKernelArguments.cpp:247
llvm::AMDGPUTargetMachine::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: AMDGPUTargetMachine.cpp:728
llvm::createSIModeRegisterPass
FunctionPass * createSIModeRegisterPass()
Definition: SIModeRegister.cpp:158
llvm::OptimizationLevel
Definition: OptimizationLevel.h:22
llvm::PseudoSourceValue::Stack
@ Stack
Definition: PseudoSourceValue.h:38
llvm::ArgDescriptor::createRegister
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
PassManager.h
llvm::SourceMgr::DK_Error
@ DK_Error
Definition: SourceMgr.h:34
llvm::createAMDGPUReplaceLDSUseWithPointerPass
ModulePass * createAMDGPUReplaceLDSUseWithPointerPass()
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:639
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:408
llvm::TargetPassConfig::disablePass
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
Definition: TargetPassConfig.h:196
llvm::DeadMachineInstructionElimID
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Definition: DeadMachineInstructionElim.cpp:56
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:164
llvm::AnalysisManager::registerPass
bool registerPass(PassBuilderT &&PassBuilder)
Register an analysis pass with the manager.
Definition: PassManager.h:836
llvm::AMDGPUFunctionArgInfo::KernargSegmentPtr
ArgDescriptor KernargSegmentPtr
Definition: AMDGPUArgumentUsageInfo.h:128
llvm::createAMDGPUPromoteAlloca
FunctionPass * createAMDGPUPromoteAlloca()
Definition: AMDGPUPromoteAlloca.cpp:1136
llvm::initializeAMDGPUPrintfRuntimeBindingPass
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
llvm::AAManager::registerFunctionAnalysis
void registerFunctionAnalysis()
Register a specific AA result.
Definition: AliasAnalysis.h:881
llvm::AMDGPUPassConfig::isPassEnabled
bool isPassEnabled(const cl::opt< bool > &Opt, CodeGenOpt::Level Level=CodeGenOpt::Default) const
Check if a pass is enabled given Opt option.
Definition: AMDGPUTargetMachine.h:131
llvm::BranchRelaxationPassID
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Definition: BranchRelaxation.cpp:119
llvm::initializeAMDGPUPreLegalizerCombinerPass
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)
llvm::createAMDGPUCodeGenPreparePass
FunctionPass * createAMDGPUCodeGenPreparePass()
Definition: AMDGPUCodeGenPrepare.cpp:1467
llvm::RegisterRegAllocBase
RegisterRegAllocBase class - Track the registration of register allocators.
Definition: RegAllocRegistry.h:30
llvm::MachineSchedulerID
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
Definition: MachineScheduler.cpp:212
llvm::AMDGPUTargetMachine::EnableFunctionCalls
static bool EnableFunctionCalls
Definition: AMDGPUTargetMachine.h:37
llvm::initializeAMDGPUAttributorPass
void initializeAMDGPUAttributorPass(PassRegistry &)
Legalizer.h
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::createLICMPass
Pass * createLICMPass()
Definition: LICM.cpp:349
llvm::GCNNSAReassignID
char & GCNNSAReassignID
Definition: GCNNSAReassign.cpp:106
llvm::TargetMachine::getTargetCPU
StringRef getTargetCPU() const
Definition: TargetMachine.h:126
llvm::initializeAMDGPUAnnotateKernelFeaturesPass
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:197
llvm::AMDGPUFunctionArgInfo::WorkItemIDY
ArgDescriptor WorkItemIDY
Definition: AMDGPUArgumentUsageInfo.h:151
llvm::createAMDGPUPreLegalizeCombiner
FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPreLegalizerCombiner.cpp:299
llvm::AMDGPUTargetMachine::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const override
If the specified generic pointer could be assumed as a pointer to a specific address space,...
Definition: AMDGPUTargetMachine.cpp:734
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
N
#define N
llvm::createStraightLineStrengthReducePass
FunctionPass * createStraightLineStrengthReducePass()
Definition: StraightLineStrengthReduce.cpp:268
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:325
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:125
llvm::GCNPreRAOptimizationsID
char & GCNPreRAOptimizationsID
Definition: GCNPreRAOptimizations.cpp:79
llvm::initializeSILoadStoreOptimizerPass
void initializeSILoadStoreOptimizerPass(PassRegistry &)
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::PatternMatch
Definition: PatternMatch.h:47
llvm::createStoreClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1579
llvm::IRTranslator
Definition: IRTranslator.h:64
llvm::PassBuilder::registerCGSCCOptimizerLateEPCallback
void registerCGSCCOptimizerLateEPCallback(const std::function< void(CGSCCPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:434
llvm::initializeAMDGPURegBankCombinerPass
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
RegName
#define RegName(no)
llvm::createSIAnnotateControlFlowPass
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
Definition: SIAnnotateControlFlow.cpp:389
Vectorize.h
llvm::yaml::SIMode::IEEE
bool IEEE
Definition: SIMachineFunctionInfo.h:208
llvm::initializeAMDGPUCtorDtorLoweringPass
void initializeAMDGPUCtorDtorLoweringPass(PassRegistry &)
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:42
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SIFoldOperandsID
char & SIFoldOperandsID
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::createBasicRegisterAllocator
FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
Definition: RegAllocBasic.cpp:333
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
createGCNMaxILPMachineScheduler
static ScheduleDAGInstrs * createGCNMaxILPMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:434
llvm::MIPatternMatch::m_Not
BinaryOp_match< SrcTy, SpecificConstantMatch, TargetOpcode::G_XOR, true > m_Not(const SrcTy &&Src)
Matches a register not-ed by a G_XOR.
Definition: MIPatternMatch.h:772
llvm::EarlyMachineLICMID
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
Definition: MachineLICM.cpp:297
llvm::AMDGPUTargetMachine::getGPUName
StringRef getGPUName(const Function &F) const
Definition: AMDGPUTargetMachine.cpp:555
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:243
llvm::cl::desc
Definition: CommandLine.h:413
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:392
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:120
llvm::AMDGPUInsertDelayAluID
char & AMDGPUInsertDelayAluID
Definition: AMDGPUInsertDelayAlu.cpp:454
llvm::CodeGenOpt::Less
@ Less
Definition: CodeGen.h:54
llvm::AMDGPUTargetMachine::AMDGPUTargetMachine
AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL)
Definition: AMDGPUTargetMachine.cpp:530
llvm::TargetPassConfig::addFastRegAlloc
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: TargetPassConfig.cpp:1452
llvm::AMDGPUPerfHintAnalysisID
char & AMDGPUPerfHintAnalysisID
Definition: AMDGPUPerfHintAnalysis.cpp:58
TargetRegistry.h
llvm::createSROAPass
FunctionPass * createSROAPass()
Definition: SROA.cpp:4859
llvm::AMDGPUPropagateAttributesLatePass
Definition: AMDGPU.h:135
EnableLibCallSimplify
static cl::opt< bool > EnableLibCallSimplify("amdgpu-simplify-libcall", cl::desc("Enable amdgpu library simplifications"), cl::init(true), cl::Hidden)
InitializePasses.h
llvm::yaml::SIMode::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: SIMachineFunctionInfo.h:213
llvm::SIOptimizeExecMaskingPreRAID
char & SIOptimizeExecMaskingPreRAID
Definition: SIOptimizeExecMaskingPreRA.cpp:75
llvm::createGCNMCRegisterInfo
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)
Definition: AMDGPUMCTargetDesc.cpp:71
llvm::TargetMachine::MRI
std::unique_ptr< const MCRegisterInfo > MRI
Definition: TargetMachine.h:105
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::createAMDGPURewriteUndefForPHIPass
FunctionPass * createAMDGPURewriteUndefForPHIPass()
Definition: AMDGPURewriteUndefForPHI.cpp:179
llvm::AMDGPUTargetMachine::EnableLateStructurizeCFG
static bool EnableLateStructurizeCFG
Definition: AMDGPUTargetMachine.h:36
llvm::TargetPassConfig::addILPOpts
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
Definition: TargetPassConfig.h:374
llvm::GCNPostScheduleDAGMILive
Definition: GCNSchedStrategy.h:361
llvm::TargetPassConfig::getOptLevel
CodeGenOpt::Level getOptLevel() const
Definition: TargetPassConfig.cpp:645
AMDGPUTargetMachine.h
llvm::GCNTargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: AMDGPUTargetMachine.cpp:1400
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:671
llvm::initializeSILowerControlFlowPass
void initializeSILowerControlFlowPass(PassRegistry &)
llvm::SILateBranchLoweringPassID
char & SILateBranchLoweringPassID
Definition: SILateBranchLowering.cpp:66
llvm::createIGroupLPDAGMutation
std::unique_ptr< ScheduleDAGMutation > createIGroupLPDAGMutation()
Definition: AMDGPUIGroupLP.cpp:1156
RegAllocRegistry.h
llvm::AMDGPUAS::FLAT_ADDRESS
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:371
MIParser.h
llvm::Localizer
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:43
AMDGPUBaseInfo.h
llvm::createAMDGPUMacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAMDGPUMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAMDGPUMacroFusionDAGMutation()); to AMDGPUPassConfig...
Definition: AMDGPUMacroFusion.cpp:62