LLVM  14.0.0git
AMDGPUTargetMachine.cpp
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1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information needed to emit code for SI+ GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600.h"
25 #include "R600TargetMachine.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIMachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/IR/PassManager.h"
41 #include "llvm/InitializePasses.h"
44 #include "llvm/Transforms/IPO.h"
49 #include "llvm/Transforms/Scalar.h"
52 #include "llvm/Transforms/Utils.h"
55 
56 using namespace llvm;
57 
58 namespace {
59 class SGPRRegisterRegAlloc : public RegisterRegAllocBase<SGPRRegisterRegAlloc> {
60 public:
61  SGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
62  : RegisterRegAllocBase(N, D, C) {}
63 };
64 
65 class VGPRRegisterRegAlloc : public RegisterRegAllocBase<VGPRRegisterRegAlloc> {
66 public:
67  VGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
68  : RegisterRegAllocBase(N, D, C) {}
69 };
70 
71 static bool onlyAllocateSGPRs(const TargetRegisterInfo &TRI,
72  const TargetRegisterClass &RC) {
73  return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
74 }
75 
76 static bool onlyAllocateVGPRs(const TargetRegisterInfo &TRI,
77  const TargetRegisterClass &RC) {
78  return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
79 }
80 
81 
82 /// -{sgpr|vgpr}-regalloc=... command line option.
83 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
84 
85 /// A dummy default pass factory indicates whether the register allocator is
86 /// overridden on the command line.
87 static llvm::once_flag InitializeDefaultSGPRRegisterAllocatorFlag;
88 static llvm::once_flag InitializeDefaultVGPRRegisterAllocatorFlag;
89 
90 static SGPRRegisterRegAlloc
91 defaultSGPRRegAlloc("default",
92  "pick SGPR register allocator based on -O option",
94 
95 static cl::opt<SGPRRegisterRegAlloc::FunctionPassCtor, false,
97 SGPRRegAlloc("sgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
98  cl::desc("Register allocator to use for SGPRs"));
99 
100 static cl::opt<VGPRRegisterRegAlloc::FunctionPassCtor, false,
102 VGPRRegAlloc("vgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
103  cl::desc("Register allocator to use for VGPRs"));
104 
105 
106 static void initializeDefaultSGPRRegisterAllocatorOnce() {
107  RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
108 
109  if (!Ctor) {
110  Ctor = SGPRRegAlloc;
111  SGPRRegisterRegAlloc::setDefault(SGPRRegAlloc);
112  }
113 }
114 
115 static void initializeDefaultVGPRRegisterAllocatorOnce() {
116  RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
117 
118  if (!Ctor) {
119  Ctor = VGPRRegAlloc;
120  VGPRRegisterRegAlloc::setDefault(VGPRRegAlloc);
121  }
122 }
123 
124 static FunctionPass *createBasicSGPRRegisterAllocator() {
125  return createBasicRegisterAllocator(onlyAllocateSGPRs);
126 }
127 
128 static FunctionPass *createGreedySGPRRegisterAllocator() {
129  return createGreedyRegisterAllocator(onlyAllocateSGPRs);
130 }
131 
132 static FunctionPass *createFastSGPRRegisterAllocator() {
133  return createFastRegisterAllocator(onlyAllocateSGPRs, false);
134 }
135 
136 static FunctionPass *createBasicVGPRRegisterAllocator() {
137  return createBasicRegisterAllocator(onlyAllocateVGPRs);
138 }
139 
140 static FunctionPass *createGreedyVGPRRegisterAllocator() {
141  return createGreedyRegisterAllocator(onlyAllocateVGPRs);
142 }
143 
144 static FunctionPass *createFastVGPRRegisterAllocator() {
145  return createFastRegisterAllocator(onlyAllocateVGPRs, true);
146 }
147 
148 static SGPRRegisterRegAlloc basicRegAllocSGPR(
149  "basic", "basic register allocator", createBasicSGPRRegisterAllocator);
150 static SGPRRegisterRegAlloc greedyRegAllocSGPR(
151  "greedy", "greedy register allocator", createGreedySGPRRegisterAllocator);
152 
153 static SGPRRegisterRegAlloc fastRegAllocSGPR(
154  "fast", "fast register allocator", createFastSGPRRegisterAllocator);
155 
156 
157 static VGPRRegisterRegAlloc basicRegAllocVGPR(
158  "basic", "basic register allocator", createBasicVGPRRegisterAllocator);
159 static VGPRRegisterRegAlloc greedyRegAllocVGPR(
160  "greedy", "greedy register allocator", createGreedyVGPRRegisterAllocator);
161 
162 static VGPRRegisterRegAlloc fastRegAllocVGPR(
163  "fast", "fast register allocator", createFastVGPRRegisterAllocator);
164 }
165 
167  "amdgpu-sroa",
168  cl::desc("Run SROA after promote alloca pass"),
170  cl::init(true));
171 
172 static cl::opt<bool>
173 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
174  cl::desc("Run early if-conversion"),
175  cl::init(false));
176 
177 static cl::opt<bool>
178 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
179  cl::desc("Run pre-RA exec mask optimizations"),
180  cl::init(true));
181 
182 // Option to disable vectorizer for tests.
184  "amdgpu-load-store-vectorizer",
185  cl::desc("Enable load store vectorizer"),
186  cl::init(true),
187  cl::Hidden);
188 
189 // Option to control global loads scalarization
191  "amdgpu-scalarize-global-loads",
192  cl::desc("Enable global load scalarization"),
193  cl::init(true),
194  cl::Hidden);
195 
196 // Option to run internalize pass.
198  "amdgpu-internalize-symbols",
199  cl::desc("Enable elimination of non-kernel functions and unused globals"),
200  cl::init(false),
201  cl::Hidden);
202 
203 // Option to inline all early.
205  "amdgpu-early-inline-all",
206  cl::desc("Inline all functions early"),
207  cl::init(false),
208  cl::Hidden);
209 
211  "amdgpu-sdwa-peephole",
212  cl::desc("Enable SDWA peepholer"),
213  cl::init(true));
214 
216  "amdgpu-dpp-combine",
217  cl::desc("Enable DPP combiner"),
218  cl::init(true));
219 
220 // Enable address space based alias analysis
221 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
222  cl::desc("Enable AMDGPU Alias Analysis"),
223  cl::init(true));
224 
225 // Option to run late CFG structurizer
227  "amdgpu-late-structurize",
228  cl::desc("Enable late CFG structurization"),
230  cl::Hidden);
231 
233  "amdgpu-fixed-function-abi",
234  cl::desc("Enable all implicit function arguments"),
236  cl::init(false),
237  cl::Hidden);
238 
239 // Enable lib calls simplifications
241  "amdgpu-simplify-libcall",
242  cl::desc("Enable amdgpu library simplifications"),
243  cl::init(true),
244  cl::Hidden);
245 
247  "amdgpu-ir-lower-kernel-arguments",
248  cl::desc("Lower kernel argument loads in IR pass"),
249  cl::init(true),
250  cl::Hidden);
251 
253  "amdgpu-reassign-regs",
254  cl::desc("Enable register reassign optimizations on gfx10+"),
255  cl::init(true),
256  cl::Hidden);
257 
259  "amdgpu-opt-vgpr-liverange",
260  cl::desc("Enable VGPR liverange optimizations for if-else structure"),
261  cl::init(true), cl::Hidden);
262 
263 // Enable atomic optimization
265  "amdgpu-atomic-optimizations",
266  cl::desc("Enable atomic optimizations"),
267  cl::init(false),
268  cl::Hidden);
269 
270 // Enable Mode register optimization
272  "amdgpu-mode-register",
273  cl::desc("Enable mode register pass"),
274  cl::init(true),
275  cl::Hidden);
276 
277 // Option is used in lit tests to prevent deadcoding of patterns inspected.
278 static cl::opt<bool>
279 EnableDCEInRA("amdgpu-dce-in-ra",
280  cl::init(true), cl::Hidden,
281  cl::desc("Enable machine DCE inside regalloc"));
282 
284  "amdgpu-scalar-ir-passes",
285  cl::desc("Enable scalar IR passes"),
286  cl::init(true),
287  cl::Hidden);
288 
290  "amdgpu-enable-structurizer-workarounds",
291  cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
292  cl::Hidden);
293 
295  "amdgpu-enable-lds-replace-with-pointer",
296  cl::desc("Enable LDS replace with pointer pass"), cl::init(false),
297  cl::Hidden);
298 
300  "amdgpu-enable-lower-module-lds", cl::desc("Enable lower module lds pass"),
302  cl::Hidden);
303 
305  "amdgpu-enable-pre-ra-optimizations",
306  cl::desc("Enable Pre-RA optimizations pass"), cl::init(true),
307  cl::Hidden);
308 
310  // Register the target
313 
380 }
381 
382 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
383  return std::make_unique<AMDGPUTargetObjectFile>();
384 }
385 
387  return new SIScheduleDAGMI(C);
388 }
389 
390 static ScheduleDAGInstrs *
392  ScheduleDAGMILive *DAG =
393  new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
397  return DAG;
398 }
399 
400 static ScheduleDAGInstrs *
402  auto DAG = new GCNIterativeScheduler(C,
404  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
405  return DAG;
406 }
407 
409  return new GCNIterativeScheduler(C,
411 }
412 
413 static ScheduleDAGInstrs *
415  auto DAG = new GCNIterativeScheduler(C,
417  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
418  DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
419  return DAG;
420 }
421 
423 SISchedRegistry("si", "Run SI's custom scheduler",
425 
427 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
428  "Run GCN scheduler to maximize occupancy",
430 
432 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
433  "Run GCN scheduler to maximize occupancy (experimental)",
435 
437 GCNMinRegSchedRegistry("gcn-minreg",
438  "Run GCN iterative scheduler for minimal register usage (experimental)",
440 
442 GCNILPSchedRegistry("gcn-ilp",
443  "Run GCN iterative scheduler for ILP scheduling (experimental)",
445 
446 static StringRef computeDataLayout(const Triple &TT) {
447  if (TT.getArch() == Triple::r600) {
448  // 32-bit pointers.
449  return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
450  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
451  }
452 
453  // 32-bit private, local, and region pointers. 64-bit global, constant and
454  // flat, non-integral buffer fat pointers.
455  return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
456  "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
457  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
458  "-ni:7";
459 }
460 
462 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
463  if (!GPU.empty())
464  return GPU;
465 
466  // Need to default to a target with flat support for HSA.
467  if (TT.getArch() == Triple::amdgcn)
468  return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
469 
470  return "r600";
471 }
472 
474  // The AMDGPU toolchain only supports generating shared objects, so we
475  // must always use PIC.
476  return Reloc::PIC_;
477 }
478 
480  StringRef CPU, StringRef FS,
484  CodeGenOpt::Level OptLevel)
487  getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
488  TLOF(createTLOF(getTargetTriple())) {
489  initAsmInfo();
490  if (TT.getArch() == Triple::amdgcn) {
491  if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
493  else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
495  }
496 }
497 
502 
504 
506  Attribute GPUAttr = F.getFnAttribute("target-cpu");
507  return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
508 }
509 
511  Attribute FSAttr = F.getFnAttribute("target-features");
512 
513  return FSAttr.isValid() ? FSAttr.getValueAsString()
515 }
516 
517 /// Predicate for Internalize pass.
518 static bool mustPreserveGV(const GlobalValue &GV) {
519  if (const Function *F = dyn_cast<Function>(&GV))
520  return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
521 
523  return !GV.use_empty();
524 }
525 
527  Builder.DivergentTarget = true;
528 
529  bool EnableOpt = getOptLevel() > CodeGenOpt::None;
530  bool Internalize = InternalizeSymbols;
531  bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
532  bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
533  bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
534 
535  if (EnableFunctionCalls) {
536  delete Builder.Inliner;
538  }
539 
540  Builder.addExtension(
542  [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
544  if (AMDGPUAA) {
547  }
550  if (Internalize)
553  if (Internalize)
554  PM.add(createGlobalDCEPass());
555  if (EarlyInline)
557  });
558 
559  Builder.addExtension(
561  [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
563  if (AMDGPUAA) {
566  }
569  if (LibCallSimplify)
571  });
572 
573  Builder.addExtension(
575  [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
576  // Add infer address spaces pass to the opt pipeline after inlining
577  // but before SROA to increase SROA opportunities.
579 
580  // This should run after inlining to have any chance of doing anything,
581  // and before other cleanup optimizations.
583 
584  // Promote alloca to vector before SROA and loop unroll. If we manage
585  // to eliminate allocas before unroll we may choose to unroll less.
586  if (EnableOpt)
588  });
589 }
590 
593 }
594 
599  if (PassName == "amdgpu-propagate-attributes-late") {
601  return true;
602  }
603  if (PassName == "amdgpu-unify-metadata") {
605  return true;
606  }
607  if (PassName == "amdgpu-printf-runtime-binding") {
609  return true;
610  }
611  if (PassName == "amdgpu-always-inline") {
613  return true;
614  }
615  if (PassName == "amdgpu-replace-lds-use-with-pointer") {
617  return true;
618  }
619  if (PassName == "amdgpu-lower-module-lds") {
621  return true;
622  }
623  return false;
624  });
628  if (PassName == "amdgpu-simplifylib") {
630  return true;
631  }
632  if (PassName == "amdgpu-usenative") {
634  return true;
635  }
636  if (PassName == "amdgpu-promote-alloca") {
637  PM.addPass(AMDGPUPromoteAllocaPass(*this));
638  return true;
639  }
640  if (PassName == "amdgpu-promote-alloca-to-vector") {
642  return true;
643  }
644  if (PassName == "amdgpu-lower-kernel-attributes") {
646  return true;
647  }
648  if (PassName == "amdgpu-propagate-attributes-early") {
650  return true;
651  }
652  return false;
653  });
654 
656  FAM.registerPass([&] { return AMDGPUAA(); });
657  });
658 
659  PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
660  if (AAName == "amdgpu-aa") {
662  return true;
663  }
664  return false;
665  });
666 
675  });
676 
680  return;
681 
684 
685  if (InternalizeSymbols) {
687  }
689  if (InternalizeSymbols) {
690  PM.addPass(GlobalDCEPass());
691  }
694  });
695 
699  return;
700 
702 
703  // Add infer address spaces pass to the opt pipeline after inlining
704  // but before SROA to increase SROA opportunities.
706 
707  // This should run after inlining to have any chance of doing
708  // anything, and before other cleanup optimizations.
710 
711  if (Level != OptimizationLevel::O0) {
712  // Promote alloca to vector before SROA and loop unroll. If we
713  // manage to eliminate allocas before unroll we may choose to unroll
714  // less.
716  }
717 
719  });
720 }
721 
722 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
723  return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
724  AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
725  AddrSpace == AMDGPUAS::REGION_ADDRESS)
726  ? -1
727  : 0;
728 }
729 
731  unsigned DestAS) const {
732  return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
734 }
735 
737  const auto *LD = dyn_cast<LoadInst>(V);
738  if (!LD)
740 
741  // It must be a generic pointer loaded.
742  assert(V->getType()->isPointerTy() &&
744 
745  const auto *Ptr = LD->getPointerOperand();
746  if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
748  // For a generic pointer loaded from the constant memory, it could be assumed
749  // as a global pointer since the constant memory is only populated on the
750  // host side. As implied by the offload programming model, only global
751  // pointers could be referenced on the host side.
753 }
754 
755 //===----------------------------------------------------------------------===//
756 // GCN Target Machine (SI+)
757 //===----------------------------------------------------------------------===//
758 
760  StringRef CPU, StringRef FS,
764  CodeGenOpt::Level OL, bool JIT)
765  : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
766 
767 const TargetSubtargetInfo *
769  StringRef GPU = getGPUName(F);
771 
772  SmallString<128> SubtargetKey(GPU);
773  SubtargetKey.append(FS);
774 
775  auto &I = SubtargetMap[SubtargetKey];
776  if (!I) {
777  // This needs to be done before we create a new subtarget since any
778  // creation will depend on the TM and the code generation flags on the
779  // function that reside in TargetOptions.
781  I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
782  }
783 
784  I->setScalarizeGlobalBehavior(ScalarizeGlobal);
785 
786  return I.get();
787 }
788 
791  return TargetTransformInfo(GCNTTIImpl(this, F));
792 }
793 
794 //===----------------------------------------------------------------------===//
795 // AMDGPU Pass Setup
796 //===----------------------------------------------------------------------===//
797 
798 std::unique_ptr<CSEConfigBase> llvm::AMDGPUPassConfig::getCSEConfig() const {
799  return getStandardCSEConfigForOpt(TM->getOptLevel());
800 }
801 
802 namespace {
803 
804 class GCNPassConfig final : public AMDGPUPassConfig {
805 public:
806  GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
807  : AMDGPUPassConfig(TM, PM) {
808  // It is necessary to know the register usage of the entire call graph. We
809  // allow calls without EnableAMDGPUFunctionCalls if they are marked
810  // noinline, so this is always required.
811  setRequiresCodeGenSCCOrder(true);
812  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
813  }
814 
815  GCNTargetMachine &getGCNTargetMachine() const {
816  return getTM<GCNTargetMachine>();
817  }
818 
820  createMachineScheduler(MachineSchedContext *C) const override;
821 
823  createPostMachineScheduler(MachineSchedContext *C) const override {
825  const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
826  DAG->addMutation(ST.createFillMFMAShadowMutation(DAG->TII));
827  return DAG;
828  }
829 
830  bool addPreISel() override;
831  void addMachineSSAOptimization() override;
832  bool addILPOpts() override;
833  bool addInstSelector() override;
834  bool addIRTranslator() override;
835  void addPreLegalizeMachineIR() override;
836  bool addLegalizeMachineIR() override;
837  void addPreRegBankSelect() override;
838  bool addRegBankSelect() override;
839  void addPreGlobalInstructionSelect() override;
840  bool addGlobalInstructionSelect() override;
841  void addFastRegAlloc() override;
842  void addOptimizedRegAlloc() override;
843 
844  FunctionPass *createSGPRAllocPass(bool Optimized);
845  FunctionPass *createVGPRAllocPass(bool Optimized);
846  FunctionPass *createRegAllocPass(bool Optimized) override;
847 
848  bool addRegAssignAndRewriteFast() override;
849  bool addRegAssignAndRewriteOptimized() override;
850 
851  void addPreRegAlloc() override;
852  bool addPreRewrite() override;
853  void addPostRegAlloc() override;
854  void addPreSched2() override;
855  void addPreEmitPass() override;
856 };
857 
858 } // end anonymous namespace
859 
861  : TargetPassConfig(TM, PM) {
862  // Exceptions and StackMaps are not supported, so these passes will never do
863  // anything.
866  // Garbage collection is not supported.
869 }
870 
874  else
876 }
877 
882  // ReassociateGEPs exposes more opportunites for SLSR. See
883  // the example in reassociate-geps-and-slsr.ll.
885  // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
886  // EarlyCSE can reuse.
888  // Run NaryReassociate after EarlyCSE/GVN to be more effective.
890  // NaryReassociate on GEPs creates redundant common expressions, so run
891  // EarlyCSE after it.
893 }
894 
897 
898  // There is no reason to run these.
902 
905 
906  // This must occur before inlining, as the inliner will not look through
907  // bitcast calls.
909 
910  // A call to propagate attributes pass in the backend in case opt was not run.
912 
914 
915  // Function calls are not supported, so make sure we inline everything.
918  // We need to add the barrier noop pass, otherwise adding the function
919  // inlining pass will cause all of the PassConfigs passes to be run
920  // one function at a time, which means if we have a nodule with two
921  // functions, then we will generate code for the first function
922  // without ever running any passes on the second.
924 
925  // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
928 
929  // Replace OpenCL enqueued block function pointers with global variables.
931 
932  // Can increase LDS used by kernel so runs before PromoteAlloca
933  if (EnableLowerModuleLDS) {
934  // The pass "amdgpu-replace-lds-use-with-pointer" need to be run before the
935  // pass "amdgpu-lower-module-lds", and also it required to be run only if
936  // "amdgpu-lower-module-lds" pass is enabled.
939 
941  }
942 
945 
947 
948  if (TM.getOptLevel() > CodeGenOpt::None) {
950 
951  if (EnableSROA)
955 
959  AAResults &AAR) {
960  if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
961  AAR.addAAResult(WrapperPass->getResult());
962  }));
963  }
964 
966  // TODO: May want to move later or split into an early and late one.
968  }
969  }
970 
972 
973  // EarlyCSE is not always strong enough to clean up what LSR produces. For
974  // example, GVN can combine
975  //
976  // %0 = add %a, %b
977  // %1 = add %b, %a
978  //
979  // and
980  //
981  // %0 = shl nsw %a, 2
982  // %1 = shl %a, 2
983  //
984  // but EarlyCSE can do neither of them.
987 }
988 
992 
993  // FIXME: This pass adds 2 hacky attributes that can be replaced with an
994  // analysis, and should be removed.
996  }
997 
1001 
1003 
1006 
1007  // LowerSwitch pass may introduce unreachable blocks that can
1008  // cause unexpected behavior for subsequent passes. Placing it
1009  // here seems better that these blocks would get cleaned up by
1010  // UnreachableBlockElim inserted next in the pass flow.
1012 }
1013 
1015  if (TM->getOptLevel() > CodeGenOpt::None)
1017  return false;
1018 }
1019 
1021  // Defer the verifier until FinalizeISel.
1023  return false;
1024 }
1025 
1027  // Do nothing. GC is not supported.
1028  return false;
1029 }
1030 
1034  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1035  return DAG;
1036 }
1037 
1038 //===----------------------------------------------------------------------===//
1039 // GCN Pass Setup
1040 //===----------------------------------------------------------------------===//
1041 
1042 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1043  MachineSchedContext *C) const {
1044  const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1045  if (ST.enableSIScheduler())
1046  return createSIMachineScheduler(C);
1048 }
1049 
1050 bool GCNPassConfig::addPreISel() {
1052 
1053  if (TM->getOptLevel() > CodeGenOpt::None)
1055 
1056  if (isPassEnabled(EnableAtomicOptimizations, CodeGenOpt::Less)) {
1058  }
1059 
1060  if (TM->getOptLevel() > CodeGenOpt::None)
1061  addPass(createSinkingPass());
1062 
1063  // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1064  // regions formed by them.
1066  if (!LateCFGStructurize) {
1068  addPass(createFixIrreduciblePass());
1069  addPass(createUnifyLoopExitsPass());
1070  }
1071  addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1072  }
1074  if (!LateCFGStructurize) {
1076  }
1077  addPass(createLCSSAPass());
1078 
1079  if (TM->getOptLevel() > CodeGenOpt::Less)
1080  addPass(&AMDGPUPerfHintAnalysisID);
1081 
1082  return false;
1083 }
1084 
1085 void GCNPassConfig::addMachineSSAOptimization() {
1087 
1088  // We want to fold operands after PeepholeOptimizer has run (or as part of
1089  // it), because it will eliminate extra copies making it easier to fold the
1090  // real source operand. We want to eliminate dead instructions after, so that
1091  // we see fewer uses of the copies. We then need to clean up the dead
1092  // instructions leftover after the operands are folded as well.
1093  //
1094  // XXX - Can we get away without running DeadMachineInstructionElim again?
1095  addPass(&SIFoldOperandsID);
1096  if (EnableDPPCombine)
1097  addPass(&GCNDPPCombineID);
1098  addPass(&SILoadStoreOptimizerID);
1099  if (isPassEnabled(EnableSDWAPeephole)) {
1100  addPass(&SIPeepholeSDWAID);
1101  addPass(&EarlyMachineLICMID);
1102  addPass(&MachineCSEID);
1103  addPass(&SIFoldOperandsID);
1104  }
1105  addPass(&DeadMachineInstructionElimID);
1106  addPass(createSIShrinkInstructionsPass());
1107 }
1108 
1109 bool GCNPassConfig::addILPOpts() {
1111  addPass(&EarlyIfConverterID);
1112 
1114  return false;
1115 }
1116 
1117 bool GCNPassConfig::addInstSelector() {
1119  addPass(&SIFixSGPRCopiesID);
1120  addPass(createSILowerI1CopiesPass());
1121  return false;
1122 }
1123 
1124 bool GCNPassConfig::addIRTranslator() {
1125  addPass(new IRTranslator(getOptLevel()));
1126  return false;
1127 }
1128 
1129 void GCNPassConfig::addPreLegalizeMachineIR() {
1130  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1131  addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1132  addPass(new Localizer());
1133 }
1134 
1135 bool GCNPassConfig::addLegalizeMachineIR() {
1136  addPass(new Legalizer());
1137  return false;
1138 }
1139 
1140 void GCNPassConfig::addPreRegBankSelect() {
1141  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1142  addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1143 }
1144 
1145 bool GCNPassConfig::addRegBankSelect() {
1146  addPass(new RegBankSelect());
1147  return false;
1148 }
1149 
1150 void GCNPassConfig::addPreGlobalInstructionSelect() {
1151  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1152  addPass(createAMDGPURegBankCombiner(IsOptNone));
1153 }
1154 
1155 bool GCNPassConfig::addGlobalInstructionSelect() {
1156  addPass(new InstructionSelect(getOptLevel()));
1157  return false;
1158 }
1159 
1160 void GCNPassConfig::addPreRegAlloc() {
1161  if (LateCFGStructurize) {
1163  }
1164 }
1165 
1166 void GCNPassConfig::addFastRegAlloc() {
1167  // FIXME: We have to disable the verifier here because of PHIElimination +
1168  // TwoAddressInstructions disabling it.
1169 
1170  // This must be run immediately after phi elimination and before
1171  // TwoAddressInstructions, otherwise the processing of the tied operand of
1172  // SI_ELSE will introduce a copy of the tied operand source after the else.
1173  insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1174 
1177 
1179 }
1180 
1181 void GCNPassConfig::addOptimizedRegAlloc() {
1182  // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1183  // instructions that cause scheduling barriers.
1184  insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1186 
1187  if (OptExecMaskPreRA)
1189 
1190  if (isPassEnabled(EnablePreRAOptimizations))
1192 
1193  // This is not an essential optimization and it has a noticeable impact on
1194  // compilation time, so we only enable it from O2.
1195  if (TM->getOptLevel() > CodeGenOpt::Less)
1197 
1198  // FIXME: when an instruction has a Killed operand, and the instruction is
1199  // inside a bundle, seems only the BUNDLE instruction appears as the Kills of
1200  // the register in LiveVariables, this would trigger a failure in verifier,
1201  // we should fix it and enable the verifier.
1202  if (OptVGPRLiveRange)
1203  insertPass(&LiveVariablesID, &SIOptimizeVGPRLiveRangeID, false);
1204  // This must be run immediately after phi elimination and before
1205  // TwoAddressInstructions, otherwise the processing of the tied operand of
1206  // SI_ELSE will introduce a copy of the tied operand source after the else.
1207  insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1208 
1209  if (EnableDCEInRA)
1211 
1213 }
1214 
1215 bool GCNPassConfig::addPreRewrite() {
1216  if (EnableRegReassign)
1217  addPass(&GCNNSAReassignID);
1218  return true;
1219 }
1220 
1221 FunctionPass *GCNPassConfig::createSGPRAllocPass(bool Optimized) {
1222  // Initialize the global default.
1223  llvm::call_once(InitializeDefaultSGPRRegisterAllocatorFlag,
1224  initializeDefaultSGPRRegisterAllocatorOnce);
1225 
1226  RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
1227  if (Ctor != useDefaultRegisterAllocator)
1228  return Ctor();
1229 
1230  if (Optimized)
1231  return createGreedyRegisterAllocator(onlyAllocateSGPRs);
1232 
1233  return createFastRegisterAllocator(onlyAllocateSGPRs, false);
1234 }
1235 
1236 FunctionPass *GCNPassConfig::createVGPRAllocPass(bool Optimized) {
1237  // Initialize the global default.
1238  llvm::call_once(InitializeDefaultVGPRRegisterAllocatorFlag,
1239  initializeDefaultVGPRRegisterAllocatorOnce);
1240 
1241  RegisterRegAlloc::FunctionPassCtor Ctor = VGPRRegisterRegAlloc::getDefault();
1242  if (Ctor != useDefaultRegisterAllocator)
1243  return Ctor();
1244 
1245  if (Optimized)
1246  return createGreedyVGPRRegisterAllocator();
1247 
1248  return createFastVGPRRegisterAllocator();
1249 }
1250 
1251 FunctionPass *GCNPassConfig::createRegAllocPass(bool Optimized) {
1252  llvm_unreachable("should not be used");
1253 }
1254 
1255 static const char RegAllocOptNotSupportedMessage[] =
1256  "-regalloc not supported with amdgcn. Use -sgpr-regalloc and -vgpr-regalloc";
1257 
1258 bool GCNPassConfig::addRegAssignAndRewriteFast() {
1259  if (!usingDefaultRegAlloc())
1261 
1262  addPass(createSGPRAllocPass(false));
1263 
1264  // Equivalent of PEI for SGPRs.
1265  addPass(&SILowerSGPRSpillsID);
1266 
1267  addPass(createVGPRAllocPass(false));
1268  return true;
1269 }
1270 
1271 bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
1272  if (!usingDefaultRegAlloc())
1274 
1275  addPass(createSGPRAllocPass(true));
1276 
1277  // Commit allocated register changes. This is mostly necessary because too
1278  // many things rely on the use lists of the physical registers, such as the
1279  // verifier. This is only necessary with allocators which use LiveIntervals,
1280  // since FastRegAlloc does the replacments itself.
1281  addPass(createVirtRegRewriter(false));
1282 
1283  // Equivalent of PEI for SGPRs.
1284  addPass(&SILowerSGPRSpillsID);
1285 
1286  addPass(createVGPRAllocPass(true));
1287 
1288  addPreRewrite();
1289  addPass(&VirtRegRewriterID);
1290 
1291  return true;
1292 }
1293 
1294 void GCNPassConfig::addPostRegAlloc() {
1295  addPass(&SIFixVGPRCopiesID);
1296  if (getOptLevel() > CodeGenOpt::None)
1297  addPass(&SIOptimizeExecMaskingID);
1299 }
1300 
1301 void GCNPassConfig::addPreSched2() {
1302  addPass(&SIPostRABundlerID);
1303 }
1304 
1305 void GCNPassConfig::addPreEmitPass() {
1306  addPass(createSIMemoryLegalizerPass());
1307  addPass(createSIInsertWaitcntsPass());
1308 
1309  if (TM->getOptLevel() > CodeGenOpt::None)
1310  addPass(createSIShrinkInstructionsPass());
1311 
1312  addPass(createSIModeRegisterPass());
1313 
1314  if (getOptLevel() > CodeGenOpt::None)
1315  addPass(&SIInsertHardClausesID);
1316 
1317  addPass(&SILateBranchLoweringPassID);
1318  if (getOptLevel() > CodeGenOpt::None)
1319  addPass(&SIPreEmitPeepholeID);
1320  // The hazard recognizer that runs as part of the post-ra scheduler does not
1321  // guarantee to be able handle all hazards correctly. This is because if there
1322  // are multiple scheduling regions in a basic block, the regions are scheduled
1323  // bottom up, so when we begin to schedule a region we don't know what
1324  // instructions were emitted directly before it.
1325  //
1326  // Here we add a stand-alone hazard recognizer pass which can handle all
1327  // cases.
1328  addPass(&PostRAHazardRecognizerID);
1329  addPass(&BranchRelaxationPassID);
1330 }
1331 
1333  return new GCNPassConfig(*this, PM);
1334 }
1335 
1337  return new yaml::SIMachineFunctionInfo();
1338 }
1339 
1343  return new yaml::SIMachineFunctionInfo(
1344  *MFI, *MF.getSubtarget().getRegisterInfo(), MF);
1345 }
1346 
1349  SMDiagnostic &Error, SMRange &SourceRange) const {
1350  const yaml::SIMachineFunctionInfo &YamlMFI =
1351  reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1352  MachineFunction &MF = PFS.MF;
1354 
1355  if (MFI->initializeBaseYamlFields(YamlMFI, MF, PFS, Error, SourceRange))
1356  return true;
1357 
1358  if (MFI->Occupancy == 0) {
1359  // Fixup the subtarget dependent default value.
1360  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1361  MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1362  }
1363 
1364  auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1365  Register TempReg;
1366  if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1367  SourceRange = RegName.SourceRange;
1368  return true;
1369  }
1370  RegVal = TempReg;
1371 
1372  return false;
1373  };
1374 
1375  auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1376  // Create a diagnostic for a the register string literal.
1377  const MemoryBuffer &Buffer =
1378  *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1379  Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1380  RegName.Value.size(), SourceMgr::DK_Error,
1381  "incorrect register class for field", RegName.Value,
1382  None, None);
1383  SourceRange = RegName.SourceRange;
1384  return true;
1385  };
1386 
1387  if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1388  parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1389  parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1390  return true;
1391 
1392  if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1393  !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1394  return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1395  }
1396 
1397  if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1398  !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1399  return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1400  }
1401 
1402  if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1403  !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1404  return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1405  }
1406 
1407  auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1408  const TargetRegisterClass &RC,
1409  ArgDescriptor &Arg, unsigned UserSGPRs,
1410  unsigned SystemSGPRs) {
1411  // Skip parsing if it's not present.
1412  if (!A)
1413  return false;
1414 
1415  if (A->IsRegister) {
1416  Register Reg;
1417  if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1418  SourceRange = A->RegisterName.SourceRange;
1419  return true;
1420  }
1421  if (!RC.contains(Reg))
1422  return diagnoseRegisterClass(A->RegisterName);
1424  } else
1425  Arg = ArgDescriptor::createStack(A->StackOffset);
1426  // Check and apply the optional mask.
1427  if (A->Mask)
1428  Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1429 
1430  MFI->NumUserSGPRs += UserSGPRs;
1431  MFI->NumSystemSGPRs += SystemSGPRs;
1432  return false;
1433  };
1434 
1435  if (YamlMFI.ArgInfo &&
1436  (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1437  AMDGPU::SGPR_128RegClass,
1438  MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1439  parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1440  AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1441  2, 0) ||
1442  parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1443  MFI->ArgInfo.QueuePtr, 2, 0) ||
1444  parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1445  AMDGPU::SReg_64RegClass,
1446  MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1447  parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1448  AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1449  2, 0) ||
1450  parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1451  AMDGPU::SReg_64RegClass,
1452  MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1453  parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1454  AMDGPU::SGPR_32RegClass,
1455  MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1456  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1457  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1458  0, 1) ||
1459  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1460  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1461  0, 1) ||
1462  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1463  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1464  0, 1) ||
1465  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1466  AMDGPU::SGPR_32RegClass,
1467  MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1468  parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1469  AMDGPU::SGPR_32RegClass,
1470  MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1471  parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1472  AMDGPU::SReg_64RegClass,
1473  MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1474  parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1475  AMDGPU::SReg_64RegClass,
1476  MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1477  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1478  AMDGPU::VGPR_32RegClass,
1479  MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1480  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1481  AMDGPU::VGPR_32RegClass,
1482  MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1483  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1484  AMDGPU::VGPR_32RegClass,
1485  MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1486  return true;
1487 
1488  MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1489  MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1494 
1495  return false;
1496 }
llvm::AAResults::addAAResult
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Register a specific AA result.
Definition: AliasAnalysis.h:465
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Definition: TargetPassConfig.h:419
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Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:185
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FastRegisterAllocation Pass - This pass register allocates as fast as possible.
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Definition: AliasAnalysis.h:1233
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Definition: AMDGPUBaseInfo.h:925
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::initializeAMDGPUAlwaysInlinePass
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
llvm::yaml::MachineFunctionInfo
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Definition: MIRYamlMapping.h:673
llvm::PHIEliminationID
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
Definition: PHIElimination.cpp:129
llvm::initializeSIInsertHardClausesPass
void initializeSIInsertHardClausesPass(PassRegistry &)
llvm::initializeAMDGPUOpenCLEnqueuedBlockLoweringPass
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
llvm::initializeSIPreAllocateWWMRegsPass
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::initializeAMDGPUPropagateAttributesLatePass
void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &)
InferAddressSpaces.h
llvm::AMDGPU::SIModeRegisterDefaults::IEEE
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
Definition: AMDGPUBaseInfo.h:916
llvm::createAlwaysInlinerLegacyPass
Pass * createAlwaysInlinerLegacyPass(bool InsertLifetime=true)
Create a legacy pass manager instance of a pass to inline and remove functions marked as "always_inli...
Definition: AlwaysInliner.cpp:169
getGPUOrDefault
static LLVM_READNONE StringRef getGPUOrDefault(const Triple &TT, StringRef GPU)
Definition: AMDGPUTargetMachine.cpp:462
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::AMDGPUPromoteAllocaToVectorPass
Definition: AMDGPU.h:227
llvm::initializeAMDGPULateCodeGenPreparePass
void initializeAMDGPULateCodeGenPreparePass(PassRegistry &)
llvm::createFixIrreduciblePass
FunctionPass * createFixIrreduciblePass()
Definition: FixIrreducible.cpp:103
llvm::MachineSchedRegistry
MachineSchedRegistry provides a selection of available machine instruction schedulers.
Definition: MachineScheduler.h:136
llvm::createVirtRegRewriter
FunctionPass * createVirtRegRewriter(bool ClearVirtRegs=true)
Definition: VirtRegMap.cpp:653
llvm::Triple::amdgcn
@ amdgcn
Definition: Triple.h:72
GCNSchedStrategy.h
llvm::GCNIterativeScheduler::SCHEDULE_ILP
@ SCHEDULE_ILP
Definition: GCNIterativeScheduler.h:37
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:734
llvm::createAMDGPULateCodeGenPreparePass
FunctionPass * createAMDGPULateCodeGenPreparePass()
Definition: AMDGPULateCodeGenPrepare.cpp:195
llvm::createSILowerI1CopiesPass
FunctionPass * createSILowerI1CopiesPass()
Definition: SILowerI1Copies.cpp:413
llvm::initializeR600ClauseMergePassPass
void initializeR600ClauseMergePassPass(PassRegistry &)
llvm::GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY
@ SCHEDULE_LEGACYMAXOCCUPANCY
Definition: GCNIterativeScheduler.h:36
llvm::createFlattenCFGPass
FunctionPass * createFlattenCFGPass()
Definition: FlattenCFGPass.cpp:52
llvm::InternalizePass
A pass that internalizes all functions and variables other than those that must be preserved accordin...
Definition: Internalize.h:36
llvm::initializeSIOptimizeExecMaskingPreRAPass
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
llvm::AMDGPUFunctionArgInfo::FlatScratchInit
ArgDescriptor FlatScratchInit
Definition: AMDGPUArgumentUsageInfo.h:129
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
FAM
FunctionAnalysisManager FAM
Definition: PassBuilderBindings.cpp:59
llvm::createEarlyCSEPass
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1729
llvm::Wave64
@ Wave64
Definition: AMDGPUMCTargetDesc.h:31
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::initializeSILowerI1CopiesPass
void initializeSILowerI1CopiesPass(PassRegistry &)
llvm::SIPreEmitPeepholeID
char & SIPreEmitPeepholeID
llvm::createAMDGPUPostLegalizeCombiner
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPostLegalizerCombiner.cpp:400
llvm::initializeAMDGPUDAGToDAGISelPass
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
llvm::initializeSIPeepholeSDWAPass
void initializeSIPeepholeSDWAPass(PassRegistry &)
llvm::ShadowStackGCLoweringID
char & ShadowStackGCLoweringID
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC.
Definition: ShadowStackGCLowering.cpp:92
llvm::SILowerControlFlowID
char & SILowerControlFlowID
Definition: SILowerControlFlow.cpp:165
llvm::yaml::SIMachineFunctionInfo
Definition: SIMachineFunctionInfo.h:270
llvm::AMDGPUMachineFunction::getLDSSize
unsigned getLDSSize() const
Definition: AMDGPUMachineFunction.h:70
llvm::SIOptimizeVGPRLiveRangeID
char & SIOptimizeVGPRLiveRangeID
Definition: SIOptimizeVGPRLiveRange.cpp:572
llvm::createAMDGPUUnifyMetadataPass
ModulePass * createAMDGPUUnifyMetadataPass()
InstructionSelect.h
EnableStructurizerWorkarounds
static cl::opt< bool > EnableStructurizerWorkarounds("amdgpu-enable-structurizer-workarounds", cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true), cl::Hidden)
llvm::AMDGPUPassConfig
Definition: AMDGPUTargetMachine.h:105
llvm::AMDGPUAAWrapperPass
Legacy wrapper pass to provide the AMDGPUAAResult object.
Definition: AMDGPUAliasAnalysis.h:63
EnableAtomicOptimizations
static cl::opt< bool > EnableAtomicOptimizations("amdgpu-atomic-optimizations", cl::desc("Enable atomic optimizations"), cl::init(false), cl::Hidden)
createGCNMaxOccupancyMachineScheduler
static ScheduleDAGInstrs * createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:391
llvm::Optional< Reloc::Model >
llvm::GCNScheduleDAGMILive
Definition: GCNSchedStrategy.h:73
llvm::initializeSIFoldOperandsPass
void initializeSIFoldOperandsPass(PassRegistry &)
llvm::createBarrierNoopPass
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
Definition: BarrierNoopPass.cpp:43
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::createAMDGPUISelDag
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
Definition: AMDGPUISelDAGToDAG.cpp:387
InternalizeSymbols
static cl::opt< bool > InternalizeSymbols("amdgpu-internalize-symbols", cl::desc("Enable elimination of non-kernel functions and unused globals"), cl::init(false), cl::Hidden)
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
llvm::AMDGPU::SIModeRegisterDefaults::FP32InputDenormals
bool FP32InputDenormals
If this is set, neither input or output denormals are flushed for most f32 instructions.
Definition: AMDGPUBaseInfo.h:924
llvm::PassBuilder::registerAnalysisRegistrationCallback
void registerAnalysisRegistrationCallback(const std::function< void(CGSCCAnalysisManager &)> &C)
{{@ Register callbacks for analysis registration with this PassBuilder instance.
Definition: PassBuilder.h:475
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
SIMachineScheduler.h
llvm::yaml::SIMode::FP32OutputDenormals
bool FP32OutputDenormals
Definition: SIMachineFunctionInfo.h:234
llvm::createGVNPass
FunctionPass * createGVNPass(bool NoMemDepAnalysis=false)
Create a legacy GVN pass.
Definition: GVN.cpp:3115
llvm::AMDGPUFunctionArgInfo::PrivateSegmentSize
ArgDescriptor PrivateSegmentSize
Definition: AMDGPUArgumentUsageInfo.h:130
llvm::createR600OpenCLImageTypeLoweringPass
ModulePass * createR600OpenCLImageTypeLoweringPass()
Definition: R600OpenCLImageTypeLoweringPass.cpp:372
llvm::AMDGPUUseNativeCallsPass
Definition: AMDGPU.h:68
llvm::AMDGPUFunctionArgInfo::DispatchPtr
ArgDescriptor DispatchPtr
Definition: AMDGPUArgumentUsageInfo.h:125
llvm::initializeAMDGPUPropagateAttributesEarlyPass
void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &)
llvm::SIPreAllocateWWMRegsID
char & SIPreAllocateWWMRegsID
Definition: SIPreAllocateWWMRegs.cpp:81
llvm::SIPostRABundlerID
char & SIPostRABundlerID
Definition: SIPostRABundler.cpp:69
llvm::OptimizationLevel::O0
static const OptimizationLevel O0
Disable as many optimizations as possible.
Definition: OptimizationLevel.h:41
llvm::initializeSIShrinkInstructionsPass
void initializeSIShrinkInstructionsPass(PassRegistry &)
LegacyPassManager.h
llvm::TwoAddressInstructionPassID
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Definition: TwoAddressInstructionPass.cpp:192
PassManagerBuilder.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::cl::ReallyHidden
@ ReallyHidden
Definition: CommandLine.h:144
llvm::GCNTargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: AMDGPUTargetMachine.cpp:1347
llvm::initializeAMDGPUSimplifyLibCallsPass
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
Internalize.h
createSIMachineScheduler
static ScheduleDAGInstrs * createSIMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:386
llvm::MemoryBuffer
This interface provides simple read-only access to a block of memory, and provides simple methods for...
Definition: MemoryBuffer.h:50
llvm::AMDGPUMachineFunction::Mode
AMDGPU::SIModeRegisterDefaults Mode
Definition: AMDGPUMachineFunction.h:44
llvm::AMDGPUPassConfig::addGCPasses
bool addGCPasses() override
addGCPasses - Add late codegen passes that analyze code for garbage collection.
Definition: AMDGPUTargetMachine.cpp:1026
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::createAMDGPUExternalAAWrapperPass
ImmutablePass * createAMDGPUExternalAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:36
llvm::AMDGPUFunctionArgInfo::DispatchID
ArgDescriptor DispatchID
Definition: AMDGPUArgumentUsageInfo.h:128
llvm::initializeAMDGPULowerIntrinsicsPass
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
llvm::initializeGCNDPPCombinePass
void initializeGCNDPPCombinePass(PassRegistry &)
llvm::AMDGPUUnifyMetadataPass
Definition: AMDGPU.h:268
llvm::AMDGPUFunctionArgInfo::ImplicitArgPtr
ArgDescriptor ImplicitArgPtr
Definition: AMDGPUArgumentUsageInfo.h:141
EnableSDWAPeephole
static cl::opt< bool > EnableSDWAPeephole("amdgpu-sdwa-peephole", cl::desc("Enable SDWA peepholer"), cl::init(true))
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
FunctionPassCtor
llvm::SIOptimizeExecMaskingID
char & SIOptimizeExecMaskingID
Definition: SIOptimizeExecMasking.cpp:52
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::initializeAMDGPUUnifyMetadataPass
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
llvm::yaml::SIMachineFunctionInfo::FrameOffsetReg
StringValue FrameOffsetReg
Definition: SIMachineFunctionInfo.h:287
llvm::initializeAMDGPUArgumentUsageInfoPass
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
R600.h
llvm::AMDGPUPassConfig::addIRPasses
void addIRPasses() override
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: AMDGPUTargetMachine.cpp:895
SISchedRegistry
static MachineSchedRegistry SISchedRegistry("si", "Run SI's custom scheduler", createSIMachineScheduler)
GCNIterativeScheduler.h
llvm::AMDGPUFunctionArgInfo::WorkGroupIDX
ArgDescriptor WorkGroupIDX
Definition: AMDGPUArgumentUsageInfo.h:133
llvm::GCNTargetMachine::GCNTargetMachine
GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AMDGPUTargetMachine.cpp:759
llvm::createInferAddressSpacesPass
FunctionPass * createInferAddressSpacesPass(unsigned AddressSpace=~0u)
Definition: InferAddressSpaces.cpp:1208
llvm::initializeSILateBranchLoweringPass
void initializeSILateBranchLoweringPass(PassRegistry &)
llvm::TargetPassConfig::TM
LLVMTargetMachine * TM
Definition: TargetPassConfig.h:122
AMDGPUAliasAnalysis.h
llvm::AMDGPUTargetMachine
Definition: AMDGPUTargetMachine.h:29
llvm::createAMDGPUUseNativeCallsPass
FunctionPass * createAMDGPUUseNativeCallsPass()
Definition: AMDGPULibCalls.cpp:1703
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
AlwaysInliner.h
llvm::AAResults
Definition: AliasAnalysis.h:456
llvm::yaml::SIMode::FP32InputDenormals
bool FP32InputDenormals
Definition: SIMachineFunctionInfo.h:233
llvm::PassBuilder::registerParseAACallback
void registerParseAACallback(const std::function< bool(StringRef Name, AAManager &AA)> &C)
Register a callback for parsing an AliasAnalysis Name to populate the given AAManager AA.
Definition: PassBuilder.h:467
ScalarizeGlobal
static cl::opt< bool > ScalarizeGlobal("amdgpu-scalarize-global-loads", cl::desc("Enable global load scalarization"), cl::init(true), cl::Hidden)
llvm::createNaryReassociatePass
FunctionPass * createNaryReassociatePass()
Definition: NaryReassociate.cpp:165
llvm::PostRAHazardRecognizerID
char & PostRAHazardRecognizerID
PostRAHazardRecognizer - This pass runs the post-ra hazard recognizer.
Definition: PostRAHazardRecognizer.cpp:64
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:724
llvm::initializeAMDGPULowerKernelArgumentsPass
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
llvm::initializeSIWholeQuadModePass
void initializeSIWholeQuadModePass(PassRegistry &)
llvm::initializeAMDGPUAtomicOptimizerPass
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
llvm::getTheAMDGPUTarget
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
Definition: AMDGPUTargetInfo.cpp:20
llvm::Legalizer
Definition: Legalizer.h:31
llvm::AMDGPUFunctionArgInfo::WorkItemIDX
ArgDescriptor WorkItemIDX
Definition: AMDGPUArgumentUsageInfo.h:148
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
EnableAMDGPUAliasAnalysis
static cl::opt< bool > EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden, cl::desc("Enable AMDGPU Alias Analysis"), cl::init(true))
EnableLowerKernelArguments
static cl::opt< bool > EnableLowerKernelArguments("amdgpu-ir-lower-kernel-arguments", cl::desc("Lower kernel argument loads in IR pass"), cl::init(true), cl::Hidden)
EnableLoadStoreVectorizer
static cl::opt< bool > EnableLoadStoreVectorizer("amdgpu-load-store-vectorizer", cl::desc("Enable load store vectorizer"), cl::init(true), cl::Hidden)
AMDGPUTargetInfo.h
llvm::createAMDGPULowerModuleLDSPass
ModulePass * createAMDGPULowerModuleLDSPass()
R600TargetMachine.h
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
AMDGPUMacroFusion.h
llvm::initializeAMDGPUUseNativeCallsPass
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
llvm::createSIInsertWaitcntsPass
FunctionPass * createSIInsertWaitcntsPass()
Definition: SIInsertWaitcnts.cpp:802
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
EnableLDSReplaceWithPointer
static cl::opt< bool > EnableLDSReplaceWithPointer("amdgpu-enable-lds-replace-with-pointer", cl::desc("Enable LDS replace with pointer pass"), cl::init(false), cl::Hidden)
llvm::PassBuilder
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:84
EnableRegReassign
static cl::opt< bool > EnableRegReassign("amdgpu-reassign-regs", cl::desc("Enable register reassign optimizations on gfx10+"), cl::init(true), cl::Hidden)
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:251
llvm::yaml::SIMode::FP64FP16InputDenormals
bool FP64FP16InputDenormals
Definition: SIMachineFunctionInfo.h:235
llvm::createAMDGPUAnnotateUniformValues
FunctionPass * createAMDGPUAnnotateUniformValues()
Definition: AMDGPUAnnotateUniformValues.cpp:150
llvm::initializeAMDGPUUnifyDivergentExitNodesPass
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:784
useDefaultRegisterAllocator
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Definition: TargetPassConfig.cpp:1109
llvm::AMDGPUPromoteAllocaPass
Definition: AMDGPU.h:219
llvm::createGenericSchedPostRA
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Definition: MachineScheduler.cpp:3646
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createModuleToFunctionPassAdaptor
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:1221
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:31
llvm::AMDGPUTargetMachine::getNullPointerValue
static int64_t getNullPointerValue(unsigned AddrSpace)
Get the integer value of a null pointer in the given address space.
Definition: AMDGPUTargetMachine.cpp:722
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1275
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:318
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::Triple::r600
@ r600
Definition: Triple.h:71
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createUnifyLoopExitsPass
FunctionPass * createUnifyLoopExitsPass()
Definition: UnifyLoopExits.cpp:53
llvm::GCNIterativeScheduler
Definition: GCNIterativeScheduler.h:29
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: AMDGPUTargetMachine.cpp:382
llvm::SourceMgr::getMainFileID
unsigned getMainFileID() const
Definition: SourceMgr.h:129
AMDGPUTargetObjectFile.h
llvm::AMDGPULowerKernelAttributesPass
Definition: AMDGPU.h:109
GVN.h
llvm::createAMDGPUPropagateAttributesLatePass
ModulePass * createAMDGPUPropagateAttributesLatePass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:410
llvm::initializeSIMemoryLegalizerPass
void initializeSIMemoryLegalizerPass(PassRegistry &)
llvm::createLoadStoreVectorizerPass
Pass * createLoadStoreVectorizerPass()
Create a legacy pass manager instance of the LoadStoreVectorizer pass.
llvm::initializeAMDGPUResourceUsageAnalysisPass
void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &)
EnableDPPCombine
static cl::opt< bool > EnableDPPCombine("amdgpu-dpp-combine", cl::desc("Enable DPP combiner"), cl::init(true))
llvm::createAMDGPULowerIntrinsicsPass
ModulePass * createAMDGPULowerIntrinsicsPass()
Definition: AMDGPULowerIntrinsics.cpp:180
llvm::AMDGPUPassConfig::addCodeGenPrepare
void addCodeGenPrepare() override
Add pass to prepare the LLVM IR for code generation.
Definition: AMDGPUTargetMachine.cpp:989
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:28
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
llvm::createAMDGPUAnnotateKernelFeaturesPass
Pass * createAMDGPUAnnotateKernelFeaturesPass()
Definition: AMDGPUAnnotateKernelFeatures.cpp:137
llvm::initializeAMDGPUReplaceLDSUseWithPointerPass
void initializeAMDGPUReplaceLDSUseWithPointerPass(PassRegistry &)
llvm::AMDGPUTargetMachine::~AMDGPUTargetMachine
~AMDGPUTargetMachine() override
llvm::AMDGPUTargetMachine::getSubtargetImpl
const TargetSubtargetInfo * getSubtargetImpl() const
llvm::createSinkingPass
FunctionPass * createSinkingPass()
Definition: Sink.cpp:284
llvm::Triple::getArch
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:307
llvm::createSpeculativeExecutionPass
FunctionPass * createSpeculativeExecutionPass()
Definition: SpeculativeExecution.cpp:325
Utils.h
llvm::SILoadStoreOptimizerID
char & SILoadStoreOptimizerID
Definition: SILoadStoreOptimizer.cpp:575
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:301
llvm::RegisterPassParser
RegisterPassParser class - Handle the addition of new machine passes.
Definition: MachinePassRegistry.h:135
llvm::None
const NoneType None
Definition: None.h:23
llvm::Value::use_empty
bool use_empty() const
Definition: Value.h:345
llvm::createAMDGPUExportClusteringDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAMDGPUExportClusteringDAGMutation()
Definition: AMDGPUExportClustering.cpp:144
llvm::initializeSIOptimizeVGPRLiveRangePass
void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &)
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1381
llvm::SmallString< 128 >
llvm::SourceMgr::getMemoryBuffer
const MemoryBuffer * getMemoryBuffer(unsigned i) const
Definition: SourceMgr.h:122
llvm::createFunctionInliningPass
Pass * createFunctionInliningPass()
createFunctionInliningPass - Return a new pass object that uses a heuristic to inline direct function...
Definition: InlineSimple.cpp:97
llvm::legacy::PassManagerBase::add
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
llvm::MemoryBuffer::getBufferIdentifier
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
Definition: MemoryBuffer.h:75
llvm::createAMDGPUAAWrapperPass
ImmutablePass * createAMDGPUAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:32
llvm::PassManagerBuilder
PassManagerBuilder - This class is used to set up a standard optimization sequence for languages like...
Definition: PassManagerBuilder.h:59
llvm::createLowerSwitchPass
FunctionPass * createLowerSwitchPass()
Definition: LowerSwitch.cpp:580
llvm::createAMDGPUPrintfRuntimeBinding
ModulePass * createAMDGPUPrintfRuntimeBinding()
Definition: AMDGPUPrintfRuntimeBinding.cpp:92
AMDGPUTargetTransformInfo.h
llvm::AMDGPUPassConfig::addInstSelector
bool addInstSelector() override
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
Definition: AMDGPUTargetMachine.cpp:1020
PB
PassBuilder PB(Machine, PassOpts->PTO, None, &PIC)
Passes.h
llvm::Triple::AMDHSA
@ AMDHSA
Definition: Triple.h:190
llvm::VirtRegRewriterID
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:227
llvm::createAMDGPUAlwaysInlinePass
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPUAlwaysInlinePass.cpp:158
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::SmallString::append
void append(StringRef RHS)
Append from a StringRef.
Definition: SmallString.h:67
llvm::initializeSILowerSGPRSpillsPass
void initializeSILowerSGPRSpillsPass(PassRegistry &)
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::PassBuilder::registerPipelineEarlySimplificationEPCallback
void registerPipelineEarlySimplificationEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:451
llvm::AMDGPUTargetMachine::getFeatureString
StringRef getFeatureString(const Function &F) const
Definition: AMDGPUTargetMachine.cpp:510
OptVGPRLiveRange
static cl::opt< bool > OptVGPRLiveRange("amdgpu-opt-vgpr-liverange", cl::desc("Enable VGPR liverange optimizations for if-else structure"), cl::init(true), cl::Hidden)
llvm::cl::opt
Definition: CommandLine.h:1434
llvm::createLCSSAPass
Pass * createLCSSAPass()
Definition: LCSSA.cpp:484
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:98
OptExecMaskPreRA
static cl::opt< bool > OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden, cl::desc("Run pre-RA exec mask optimizations"), cl::init(true))
llvm::GCLoweringID
char & GCLoweringID
GCLowering Pass - Used by gc.root to perform its default lowering operations.
Definition: GCRootLowering.cpp:88
llvm::yaml::SIMachineFunctionInfo::ScratchRSrcReg
StringValue ScratchRSrcReg
Definition: SIMachineFunctionInfo.h:286
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::AMDGPUUnifyDivergentExitNodesID
char & AMDGPUUnifyDivergentExitNodesID
Definition: AMDGPUUnifyDivergentExitNodes.cpp:79
llvm::initializeSIInsertWaitcntsPass
void initializeSIInsertWaitcntsPass(PassRegistry &)
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::initializeSIAnnotateControlFlowPass
void initializeSIAnnotateControlFlowPass(PassRegistry &)
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3489
llvm::AMDGPUFunctionArgInfo::WorkGroupIDZ
ArgDescriptor WorkGroupIDZ
Definition: AMDGPUArgumentUsageInfo.h:135
llvm::RegisterRegAllocBase< RegisterRegAlloc >::FunctionPassCtor
FunctionPass *(*)() FunctionPassCtor
Definition: RegAllocRegistry.h:32
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::DetectDeadLanesID
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
Definition: DetectDeadLanes.cpp:128
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::TargetMachine::getMCSubtargetInfo
const MCSubtargetInfo * getMCSubtargetInfo() const
Definition: TargetMachine.h:211
llvm::AMDGPUFunctionArgInfo::PrivateSegmentBuffer
ArgDescriptor PrivateSegmentBuffer
Definition: AMDGPUArgumentUsageInfo.h:124
llvm::createAMDGPUAtomicOptimizerPass
FunctionPass * createAMDGPUAtomicOptimizerPass()
Definition: AMDGPUAtomicOptimizer.cpp:707
llvm::initializeR600VectorRegMergerPass
void initializeR600VectorRegMergerPass(PassRegistry &)
IPO.h
llvm::SIPeepholeSDWAID
char & SIPeepholeSDWAID
Definition: SIPeepholeSDWA.cpp:191
llvm::SIMachineFunctionInfo::initializeBaseYamlFields
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
Definition: SIMachineFunctionInfo.cpp:595
llvm::createGlobalDCEPass
ModulePass * createGlobalDCEPass()
createGlobalDCEPass - This transform is designed to eliminate unreachable internal globals (functions...
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::GCNTTIImpl
Definition: AMDGPUTargetTransformInfo.h:59
llvm::SIFixVGPRCopiesID
char & SIFixVGPRCopiesID
Definition: SIFixVGPRCopies.cpp:45
llvm::initializeAMDGPURewriteOutArgumentsPass
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
CGSCCPassManager.h
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:120
llvm::GCNIterativeScheduler::SCHEDULE_MINREGFORCED
@ SCHEDULE_MINREGFORCED
Definition: GCNIterativeScheduler.h:35
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::AMDGPUSimplifyLibCallsPass
Definition: AMDGPU.h:60
llvm::AMDGPUPassConfig::createMachineScheduler
ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override
Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...
Definition: AMDGPUTargetMachine.cpp:1032
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:850
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::TargetPassConfig::addOptimizedRegAlloc
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: TargetPassConfig.cpp:1433
llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset
ArgDescriptor PrivateSegmentWaveByteOffset
Definition: AMDGPUArgumentUsageInfo.h:137
llvm::SIFormMemoryClausesID
char & SIFormMemoryClausesID
Definition: SIFormMemoryClauses.cpp:91
llvm::LiveVariablesID
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
Definition: LiveVariables.cpp:45
LateCFGStructurize
static cl::opt< bool, true > LateCFGStructurize("amdgpu-late-structurize", cl::desc("Enable late CFG structurization"), cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG), cl::Hidden)
TargetPassConfig.h
llvm::createExternalAAWrapperPass
ImmutablePass * createExternalAAWrapperPass(std::function< void(Pass &, Function &, AAResults &)> Callback)
A wrapper pass around a callback which can be used to populate the AAResults in the AAResultsWrapperP...
llvm::SIFixSGPRCopiesID
char & SIFixSGPRCopiesID
Definition: SIFixSGPRCopies.cpp:121
llvm::AMDGPUFunctionArgInfo::WorkGroupIDY
ArgDescriptor WorkGroupIDY
Definition: AMDGPUArgumentUsageInfo.h:134
Localizer.h
llvm::MachineCSEID
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:153
llvm::GCNDPPCombineID
char & GCNDPPCombineID
Definition: GCNDPPCombine.cpp:111
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:354
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:979
llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:920
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SIInsertHardClausesID
char & SIInsertHardClausesID
Definition: SIInsertHardClauses.cpp:209
GCNMinRegSchedRegistry
static MachineSchedRegistry GCNMinRegSchedRegistry("gcn-minreg", "Run GCN iterative scheduler for minimal register usage (experimental)", createMinRegScheduler)
llvm::AMDGPUPassConfig::addStraightLineScalarOptimizationPasses
void addStraightLineScalarOptimizationPasses()
Definition: AMDGPUTargetMachine.cpp:878
llvm::AMDGPU::isFlatGlobalAddrSpace
bool isFlatGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:397
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
Definition: AMDGPUBaseInfo.h:929
llvm::getTheGCNTarget
Target & getTheGCNTarget()
The target for GCN GPUs.
Definition: AMDGPUTargetInfo.cpp:25
llvm::AMDGPUPassConfig::getAMDGPUTargetMachine
AMDGPUTargetMachine & getAMDGPUTargetMachine() const
Definition: AMDGPUTargetMachine.h:109
llvm::initializeSIOptimizeExecMaskingPass
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
llvm::initializeSIPostRABundlerPass
void initializeSIPostRABundlerPass(PassRegistry &)
llvm::SIScheduleDAGMI
Definition: SIMachineScheduler.h:425
llvm::PassBuilder::registerPipelineParsingCallback
void registerPipelineParsingCallback(const std::function< bool(StringRef Name, CGSCCPassManager &, ArrayRef< PipelineElement >)> &C)
{{@ Register pipeline parsing callbacks with this pass builder instance.
Definition: PassBuilder.h:497
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::initializeAMDGPUAAWrapperPassPass
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:266
llvm::initializeAMDGPUCodeGenPreparePass
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
llvm::AMDGPUPassConfig::AMDGPUPassConfig
AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
Definition: AMDGPUTargetMachine.cpp:860
llvm::createAMDGPUOpenCLEnqueuedBlockLoweringPass
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
llvm::initializeGCNNSAReassignPass
void initializeGCNNSAReassignPass(PassRegistry &)
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::AMDGPUTargetMachine::EnableLowerModuleLDS
static bool EnableLowerModuleLDS
Definition: AMDGPUTargetMachine.h:40
llvm::yaml::StringValue
A wrapper around std::string which contains a source range that's being set during parsing.
Definition: MIRYamlMapping.h:34
llvm::GlobalDCEPass
Pass to remove unused function declarations.
Definition: GlobalDCE.h:29
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:650
IterativeGCNMaxOccupancySchedRegistry
static MachineSchedRegistry IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental", "Run GCN scheduler to maximize occupancy (experimental)", createIterativeGCNMaxOccupancyMachineScheduler)
AMDGPUExportClustering.h
llvm::AMDGPUFunctionArgInfo::WorkItemIDZ
ArgDescriptor WorkItemIDZ
Definition: AMDGPUArgumentUsageInfo.h:150
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::AMDGPUAS::REGION_ADDRESS
@ REGION_ADDRESS
Address space for region memory. (GDS)
Definition: AMDGPU.h:351
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::createSIShrinkInstructionsPass
FunctionPass * createSIShrinkInstructionsPass()
llvm::createAMDGPUMachineCFGStructurizerPass
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
Definition: AMDGPUMachineCFGStructurizer.cpp:2886
llvm::GCNTargetMachine
Definition: AMDGPUTargetMachine.h:72
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:472
llvm::ScheduleDAG::TRI
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:559
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::Constant::removeDeadConstantUsers
void removeDeadConstantUsers() const
If there are any dead constant users dangling off of this constant, remove them.
Definition: Constants.cpp:741
llvm::initializeSIFormMemoryClausesPass
void initializeSIFormMemoryClausesPass(PassRegistry &)
computeDataLayout
static StringRef computeDataLayout(const Triple &TT)
Definition: AMDGPUTargetMachine.cpp:446
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::initializeAMDGPUExternalAAWrapperPass
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
AMDGPU.h
llvm::GCNTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: AMDGPUTargetMachine.cpp:790
llvm::yaml::SIMachineFunctionInfo::StackPtrOffsetReg
StringValue StackPtrOffsetReg
Definition: SIMachineFunctionInfo.h:288
SimplifyLibCalls.h
llvm::AMDGPUPassConfig::addPreISel
bool addPreISel() override
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Definition: AMDGPUTargetMachine.cpp:1014
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
GlobalDCE.h
llvm::yaml::SIMachineFunctionInfo::Mode
SIMode Mode
Definition: SIMachineFunctionInfo.h:291
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:353
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:74
llvm::createAMDGPURegBankCombiner
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
Definition: AMDGPURegBankCombiner.cpp:272
EnablePreRAOptimizations
static cl::opt< bool > EnablePreRAOptimizations("amdgpu-enable-pre-ra-optimizations", cl::desc("Enable Pre-RA optimizations pass"), cl::init(true), cl::Hidden)
IRTranslator.h
llvm::TargetMachine::getTargetFeatureString
StringRef getTargetFeatureString() const
Definition: TargetMachine.h:130
EarlyInlineAll
static cl::opt< bool > EarlyInlineAll("amdgpu-early-inline-all", cl::desc("Inline all functions early"), cl::init(false), cl::Hidden)
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::once_flag
std::once_flag once_flag
Definition: Threading.h:60
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::AMDGPUFunctionArgInfo::ImplicitBufferPtr
ArgDescriptor ImplicitBufferPtr
Definition: AMDGPUArgumentUsageInfo.h:144
llvm::SIWholeQuadModeID
char & SIWholeQuadModeID
Definition: SIWholeQuadMode.cpp:265
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
EnableSROA
static cl::opt< bool > EnableSROA("amdgpu-sroa", cl::desc("Run SROA after promote alloca pass"), cl::ReallyHidden, cl::init(true))
llvm::initializeAMDGPULowerKernelAttributesPass
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:481
llvm::AMDGPUPassConfig::getCSEConfig
std::unique_ptr< CSEConfigBase > getCSEConfig() const override
Returns the CSEConfig object to use for the current optimization level.
Definition: AMDGPUTargetMachine.cpp:798
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
llvm::initializeAMDGPUAnnotateUniformValuesPass
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
llvm::RenameIndependentSubregsID
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
Definition: RenameIndependentSubregs.cpp:113
llvm::AMDGPUPrintfRuntimeBindingPass
Definition: AMDGPU.h:259
llvm::AMDGPUReplaceLDSUseWithPointerPass
Definition: AMDGPU.h:141
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::createStructurizeCFGPass
Pass * createStructurizeCFGPass(bool SkipUniformRegions=false)
When SkipUniformRegions is true the structizer will not structurize regions that only contain uniform...
Definition: StructurizeCFG.cpp:1086
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: AMDGPUBaseInfo.h:930
llvm::GCNTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: AMDGPUTargetMachine.cpp:1332
llvm::PassManager< Module >
llvm::AMDGPUAS::FLAT_ADDRESS
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:349
llvm::createAMDGPULowerKernelAttributesPass
ModulePass * createAMDGPULowerKernelAttributesPass()
Definition: AMDGPULowerKernelAttributes.cpp:258
llvm::initializeSIFixSGPRCopiesPass
void initializeSIFixSGPRCopiesPass(PassRegistry &)
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::AMDGPUFunctionArgInfo::WorkGroupInfo
ArgDescriptor WorkGroupInfo
Definition: AMDGPUArgumentUsageInfo.h:136
llvm::createAMDGPUPromoteAllocaToVector
FunctionPass * createAMDGPUPromoteAllocaToVector()
Definition: AMDGPUPromoteAlloca.cpp:1155
llvm::initializeAMDGPULowerModuleLDSPass
void initializeAMDGPULowerModuleLDSPass(PassRegistry &)
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:205
createIterativeILPMachineScheduler
static ScheduleDAGInstrs * createIterativeILPMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:414
llvm::parseNamedRegisterReference
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
Definition: MIParser.cpp:3426
EnableEarlyIfConversion
static cl::opt< bool > EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(false))
llvm::initializeSIFixVGPRCopiesPass
void initializeSIFixVGPRCopiesPass(PassRegistry &)
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:355
llvm::TargetPassConfig::addPass
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true)
Utilities for targets to add passes to the pass manager.
Definition: TargetPassConfig.cpp:776
llvm::yaml::SIMode::DX10Clamp
bool DX10Clamp
Definition: SIMachineFunctionInfo.h:232
llvm::initializeAMDGPUPromoteAllocaToVectorPass
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)
EnableScalarIRPasses
static cl::opt< bool > EnableScalarIRPasses("amdgpu-scalar-ir-passes", cl::desc("Enable scalar IR passes"), cl::init(true), cl::Hidden)
llvm::initializeSIPreEmitPeepholePass
void initializeSIPreEmitPeepholePass(PassRegistry &)
createIterativeGCNMaxOccupancyMachineScheduler
static ScheduleDAGInstrs * createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:401
llvm::call_once
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:90
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
llvm::AMDGPUTargetMachine::registerPassBuilderCallbacks
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline with New Pass Manager (similar to adjustPassManager for ...
Definition: AMDGPUTargetMachine.cpp:595
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1287
llvm::AMDGPUPassConfig::addEarlyCSEOrGVNPass
void addEarlyCSEOrGVNPass()
Definition: AMDGPUTargetMachine.cpp:871
llvm::createAMDGPUPropagateAttributesEarlyPass
FunctionPass * createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:405
llvm::AMDGPUPropagateAttributesEarlyPass
Definition: AMDGPU.h:117
llvm::initializeSIModeRegisterPass
void initializeSIModeRegisterPass(PassRegistry &)
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::createLoadClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1573
RegBankSelect.h
llvm::ScheduleDAG::TII
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
GCNMaxOccupancySchedRegistry
static MachineSchedRegistry GCNMaxOccupancySchedRegistry("gcn-max-occupancy", "Run GCN scheduler to maximize occupancy", createGCNMaxOccupancyMachineScheduler)
llvm::createAMDGPULowerKernelArgumentsPass
FunctionPass * createAMDGPULowerKernelArgumentsPass()
Definition: AMDGPULowerKernelArguments.cpp:248
llvm::AMDGPUTargetMachine::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: AMDGPUTargetMachine.cpp:730
llvm::PassManagerBuilder::EP_ModuleOptimizerEarly
@ EP_ModuleOptimizerEarly
EP_ModuleOptimizerEarly - This extension point allows adding passes just before the main module-level...
Definition: PassManagerBuilder.h:76
llvm::createSIModeRegisterPass
FunctionPass * createSIModeRegisterPass()
Definition: SIModeRegister.cpp:157
llvm::OptimizationLevel
Definition: OptimizationLevel.h:22
llvm::ArgDescriptor::createRegister
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
PassManager.h
llvm::createInternalizePass
ModulePass * createInternalizePass(std::function< bool(const GlobalValue &)> MustPreserveGV)
createInternalizePass - This pass loops over all of the functions in the input module,...
Definition: Internalize.cpp:315
llvm::SourceMgr::DK_Error
@ DK_Error
Definition: SourceMgr.h:34
llvm::AMDGPUAS::UNKNOWN_ADDRESS_SPACE
@ UNKNOWN_ADDRESS_SPACE
Definition: AMDGPU.h:390
llvm::createAMDGPUReplaceLDSUseWithPointerPass
ModulePass * createAMDGPUReplaceLDSUseWithPointerPass()
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:451
llvm::AMDGPUTargetMachine::adjustPassManager
void adjustPassManager(PassManagerBuilder &) override
Allow the target to modify the pass manager, e.g.
Definition: AMDGPUTargetMachine.cpp:526
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:393
llvm::TargetPassConfig::disablePass
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
Definition: TargetPassConfig.h:197
llvm::DeadMachineInstructionElimID
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Definition: DeadMachineInstructionElim.cpp:57
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:164
GCNILPSchedRegistry
static MachineSchedRegistry GCNILPSchedRegistry("gcn-ilp", "Run GCN iterative scheduler for ILP scheduling (experimental)", createIterativeILPMachineScheduler)
llvm::AnalysisManager::registerPass
bool registerPass(PassBuilderT &&PassBuilder)
Register an analysis pass with the manager.
Definition: PassManager.h:841
llvm::AMDGPUFunctionArgInfo::KernargSegmentPtr
ArgDescriptor KernargSegmentPtr
Definition: AMDGPUArgumentUsageInfo.h:127
llvm::createAMDGPUPromoteAlloca
FunctionPass * createAMDGPUPromoteAlloca()
Definition: AMDGPUPromoteAlloca.cpp:1151
llvm::initializeAMDGPUPrintfRuntimeBindingPass
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
llvm::AAManager::registerFunctionAnalysis
void registerFunctionAnalysis()
Register a specific AA result.
Definition: AliasAnalysis.h:1238
llvm::AMDGPUPassConfig::isPassEnabled
bool isPassEnabled(const cl::opt< bool > &Opt, CodeGenOpt::Level Level=CodeGenOpt::Default) const
Check if a pass is enabled given Opt option.
Definition: AMDGPUTargetMachine.h:130
llvm::BranchRelaxationPassID
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Definition: BranchRelaxation.cpp:119
llvm::initializeAMDGPUPreLegalizerCombinerPass
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)
llvm::createAMDGPUCodeGenPreparePass
FunctionPass * createAMDGPUCodeGenPreparePass()
Definition: AMDGPUCodeGenPrepare.cpp:1445
llvm::RegisterRegAllocBase
RegisterRegAllocBase class - Track the registration of register allocators.
Definition: RegAllocRegistry.h:30
llvm::MachineSchedulerID
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
Definition: MachineScheduler.cpp:210
llvm::AMDGPUTargetMachine::EnableFunctionCalls
static bool EnableFunctionCalls
Definition: AMDGPUTargetMachine.h:38
llvm::initializeAMDGPUAttributorPass
void initializeAMDGPUAttributorPass(PassRegistry &)
Legalizer.h
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::createLICMPass
Pass * createLICMPass()
Definition: LICM.cpp:327
llvm::createAMDGPUFixFunctionBitcastsPass
ModulePass * createAMDGPUFixFunctionBitcastsPass()
llvm::GCNNSAReassignID
char & GCNNSAReassignID
Definition: GCNNSAReassign.cpp:104
llvm::TargetMachine::getTargetCPU
StringRef getTargetCPU() const
Definition: TargetMachine.h:129
llvm::PassManagerBuilder::EP_EarlyAsPossible
@ EP_EarlyAsPossible
EP_EarlyAsPossible - This extension point allows adding passes before any other transformations,...
Definition: PassManagerBuilder.h:72
llvm::initializeAMDGPUAnnotateKernelFeaturesPass
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:199
llvm::AMDGPUFunctionArgInfo::WorkItemIDY
ArgDescriptor WorkItemIDY
Definition: AMDGPUArgumentUsageInfo.h:149
llvm::createAMDGPUPreLegalizeCombiner
FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPreLegalizerCombiner.cpp:296
llvm::AMDGPUTargetMachine::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const override
If the specified generic pointer could be assumed as a pointer to a specific address space,...
Definition: AMDGPUTargetMachine.cpp:736
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
N
#define N
llvm::createStraightLineStrengthReducePass
FunctionPass * createStraightLineStrengthReducePass()
Definition: StraightLineStrengthReduce.cpp:269
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:335
llvm::initializeAMDGPUFixFunctionBitcastsPass
void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &)
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:128
llvm::GCNPreRAOptimizationsID
char & GCNPreRAOptimizationsID
Definition: GCNPreRAOptimizations.cpp:78
llvm::initializeSILoadStoreOptimizerPass
void initializeSILoadStoreOptimizerPass(PassRegistry &)
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::IRTranslator
Definition: IRTranslator.h:62
llvm::PassBuilder::registerCGSCCOptimizerLateEPCallback
void registerCGSCCOptimizerLateEPCallback(const std::function< void(CGSCCPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:421
llvm::initializeAMDGPURegBankCombinerPass
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
RegName
#define RegName(no)
llvm::createSIAnnotateControlFlowPass
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
Definition: SIAnnotateControlFlow.cpp:375
Vectorize.h
llvm::yaml::SIMode::IEEE
bool IEEE
Definition: SIMachineFunctionInfo.h:231
llvm::initializeAMDGPUCtorDtorLoweringPass
void initializeAMDGPUCtorDtorLoweringPass(PassRegistry &)
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:44
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SIFoldOperandsID
char & SIFoldOperandsID
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::createBasicRegisterAllocator
FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
Definition: RegAllocBasic.cpp:337
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::EarlyMachineLICMID
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
Definition: MachineLICM.cpp:298
llvm::AMDGPUAS::GLOBAL_ADDRESS
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:350
llvm::AMDGPUTargetMachine::getGPUName
StringRef getGPUName(const Function &F) const
Definition: AMDGPUTargetMachine.cpp:505
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:241
llvm::cl::desc
Definition: CommandLine.h:414
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:385
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::PassManagerBuilder::EP_CGSCCOptimizerLate
@ EP_CGSCCOptimizerLate
EP_CGSCCOptimizerLate - This extension point allows adding CallGraphSCC passes at the end of the main...
Definition: PassManagerBuilder.h:117
llvm::PassManager::addPass
std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT &&Pass)
Definition: PassManager.h:552
llvm::CodeGenOpt::Less
@ Less
Definition: CodeGen.h:54
llvm::AMDGPUTargetMachine::AMDGPUTargetMachine
AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL)
Definition: AMDGPUTargetMachine.cpp:479
llvm::TargetPassConfig::addFastRegAlloc
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: TargetPassConfig.cpp:1423
llvm::AMDGPUPerfHintAnalysisID
char & AMDGPUPerfHintAnalysisID
Definition: AMDGPUPerfHintAnalysis.cpp:58
TargetRegistry.h
llvm::createSROAPass
FunctionPass * createSROAPass()
Definition: SROA.cpp:4875
llvm::AMDGPUPropagateAttributesLatePass
Definition: AMDGPU.h:129
EnableLibCallSimplify
static cl::opt< bool > EnableLibCallSimplify("amdgpu-simplify-libcall", cl::desc("Enable amdgpu library simplifications"), cl::init(true), cl::Hidden)
InitializePasses.h
llvm::yaml::SIMode::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: SIMachineFunctionInfo.h:236
llvm::SIOptimizeExecMaskingPreRAID
char & SIOptimizeExecMaskingPreRAID
Definition: SIOptimizeExecMaskingPreRA.cpp:75
llvm::createGCNMCRegisterInfo
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)
Definition: AMDGPUMCTargetDesc.cpp:68
llvm::TargetMachine::MRI
std::unique_ptr< const MCRegisterInfo > MRI
Definition: TargetMachine.h:108
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
EnableAMDGPUFixedFunctionABIOpt
static cl::opt< bool, true > EnableAMDGPUFixedFunctionABIOpt("amdgpu-fixed-function-abi", cl::desc("Enable all implicit function arguments"), cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI), cl::init(false), cl::Hidden)
llvm::AMDGPUTargetMachine::EnableLateStructurizeCFG
static bool EnableLateStructurizeCFG
Definition: AMDGPUTargetMachine.h:37
llvm::TargetPassConfig::addILPOpts
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
Definition: TargetPassConfig.h:373
llvm::TargetPassConfig::getOptLevel
CodeGenOpt::Level getOptLevel() const
Definition: TargetPassConfig.cpp:638
AMDGPUTargetMachine.h
llvm::GCNTargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: AMDGPUTargetMachine.cpp:1336
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:669
llvm::initializeSILowerControlFlowPass
void initializeSILowerControlFlowPass(PassRegistry &)
llvm::SILateBranchLoweringPassID
char & SILateBranchLoweringPassID
Definition: SILateBranchLowering.cpp:66
RegAllocRegistry.h
llvm::createAMDGPUSimplifyLibCallsPass
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetMachine *)
Definition: AMDGPULibCalls.cpp:1699
MIParser.h
llvm::Localizer
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:40
llvm::createAMDGPUMacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAMDGPUMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAMDGPUMacroFusionDAGMutation()); to AMDGPUPassConfig...
Definition: AMDGPUMacroFusion.cpp:62