LLVM  13.0.0git
AMDGPUTargetMachine.cpp
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1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// The AMDGPU target machine contains all of the hardware specific
11 /// information needed to emit code for R600 and SI GPUs.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUTargetMachine.h"
16 #include "AMDGPU.h"
17 #include "AMDGPUAliasAnalysis.h"
18 #include "AMDGPUExportClustering.h"
19 #include "AMDGPUMacroFusion.h"
20 #include "AMDGPUTargetObjectFile.h"
22 #include "GCNIterativeScheduler.h"
23 #include "GCNSchedStrategy.h"
24 #include "R600MachineScheduler.h"
25 #include "SIMachineFunctionInfo.h"
26 #include "SIMachineScheduler.h"
37 #include "llvm/IR/PassManager.h"
38 #include "llvm/InitializePasses.h"
41 #include "llvm/Transforms/IPO.h"
46 #include "llvm/Transforms/Scalar.h"
49 #include "llvm/Transforms/Utils.h"
52 
53 using namespace llvm;
54 
56  "r600-ir-structurize",
57  cl::desc("Use StructurizeCFG IR pass"),
58  cl::init(true));
59 
61  "amdgpu-sroa",
62  cl::desc("Run SROA after promote alloca pass"),
64  cl::init(true));
65 
66 static cl::opt<bool>
67 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
68  cl::desc("Run early if-conversion"),
69  cl::init(false));
70 
71 static cl::opt<bool>
72 OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden,
73  cl::desc("Run pre-RA exec mask optimizations"),
74  cl::init(true));
75 
77  "r600-if-convert",
78  cl::desc("Use if conversion pass"),
80  cl::init(true));
81 
82 // Option to disable vectorizer for tests.
84  "amdgpu-load-store-vectorizer",
85  cl::desc("Enable load store vectorizer"),
86  cl::init(true),
87  cl::Hidden);
88 
89 // Option to control global loads scalarization
91  "amdgpu-scalarize-global-loads",
92  cl::desc("Enable global load scalarization"),
93  cl::init(true),
94  cl::Hidden);
95 
96 // Option to run internalize pass.
98  "amdgpu-internalize-symbols",
99  cl::desc("Enable elimination of non-kernel functions and unused globals"),
100  cl::init(false),
101  cl::Hidden);
102 
103 // Option to inline all early.
105  "amdgpu-early-inline-all",
106  cl::desc("Inline all functions early"),
107  cl::init(false),
108  cl::Hidden);
109 
111  "amdgpu-sdwa-peephole",
112  cl::desc("Enable SDWA peepholer"),
113  cl::init(true));
114 
116  "amdgpu-dpp-combine",
117  cl::desc("Enable DPP combiner"),
118  cl::init(true));
119 
120 // Enable address space based alias analysis
121 static cl::opt<bool> EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden,
122  cl::desc("Enable AMDGPU Alias Analysis"),
123  cl::init(true));
124 
125 // Option to run late CFG structurizer
127  "amdgpu-late-structurize",
128  cl::desc("Enable late CFG structurization"),
130  cl::Hidden);
131 
133  "amdgpu-function-calls",
134  cl::desc("Enable AMDGPU function call support"),
136  cl::init(true),
137  cl::Hidden);
138 
140  "amdgpu-fixed-function-abi",
141  cl::desc("Enable all implicit function arguments"),
143  cl::init(false),
144  cl::Hidden);
145 
146 // Enable lib calls simplifications
148  "amdgpu-simplify-libcall",
149  cl::desc("Enable amdgpu library simplifications"),
150  cl::init(true),
151  cl::Hidden);
152 
154  "amdgpu-ir-lower-kernel-arguments",
155  cl::desc("Lower kernel argument loads in IR pass"),
156  cl::init(true),
157  cl::Hidden);
158 
160  "amdgpu-reassign-regs",
161  cl::desc("Enable register reassign optimizations on gfx10+"),
162  cl::init(true),
163  cl::Hidden);
164 
165 // Enable atomic optimization
167  "amdgpu-atomic-optimizations",
168  cl::desc("Enable atomic optimizations"),
169  cl::init(false),
170  cl::Hidden);
171 
172 // Enable Mode register optimization
174  "amdgpu-mode-register",
175  cl::desc("Enable mode register pass"),
176  cl::init(true),
177  cl::Hidden);
178 
179 // Option is used in lit tests to prevent deadcoding of patterns inspected.
180 static cl::opt<bool>
181 EnableDCEInRA("amdgpu-dce-in-ra",
182  cl::init(true), cl::Hidden,
183  cl::desc("Enable machine DCE inside regalloc"));
184 
186  "amdgpu-scalar-ir-passes",
187  cl::desc("Enable scalar IR passes"),
188  cl::init(true),
189  cl::Hidden);
190 
192  "amdgpu-enable-structurizer-workarounds",
193  cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true),
194  cl::Hidden);
195 
196 static cl::opt<bool>
197  DisableLowerModuleLDS("amdgpu-disable-lower-module-lds", cl::Hidden,
198  cl::desc("Disable lower module lds pass"),
199  cl::init(false));
200 
202  // Register the target
205 
267 }
268 
269 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
270  return std::make_unique<AMDGPUTargetObjectFile>();
271 }
272 
274  return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
275 }
276 
278  return new SIScheduleDAGMI(C);
279 }
280 
281 static ScheduleDAGInstrs *
283  ScheduleDAGMILive *DAG =
284  new GCNScheduleDAGMILive(C, std::make_unique<GCNMaxOccupancySchedStrategy>(C));
288  return DAG;
289 }
290 
291 static ScheduleDAGInstrs *
293  auto DAG = new GCNIterativeScheduler(C,
295  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
296  return DAG;
297 }
298 
300  return new GCNIterativeScheduler(C,
302 }
303 
304 static ScheduleDAGInstrs *
306  auto DAG = new GCNIterativeScheduler(C,
308  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
309  DAG->addMutation(createAMDGPUMacroFusionDAGMutation());
310  return DAG;
311 }
312 
314 R600SchedRegistry("r600", "Run R600's custom scheduler",
316 
318 SISchedRegistry("si", "Run SI's custom scheduler",
320 
322 GCNMaxOccupancySchedRegistry("gcn-max-occupancy",
323  "Run GCN scheduler to maximize occupancy",
325 
327 IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental",
328  "Run GCN scheduler to maximize occupancy (experimental)",
330 
332 GCNMinRegSchedRegistry("gcn-minreg",
333  "Run GCN iterative scheduler for minimal register usage (experimental)",
335 
337 GCNILPSchedRegistry("gcn-ilp",
338  "Run GCN iterative scheduler for ILP scheduling (experimental)",
340 
341 static StringRef computeDataLayout(const Triple &TT) {
342  if (TT.getArch() == Triple::r600) {
343  // 32-bit pointers.
344  return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
345  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
346  }
347 
348  // 32-bit private, local, and region pointers. 64-bit global, constant and
349  // flat, non-integral buffer fat pointers.
350  return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
351  "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
352  "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
353  "-ni:7";
354 }
355 
357 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
358  if (!GPU.empty())
359  return GPU;
360 
361  // Need to default to a target with flat support for HSA.
362  if (TT.getArch() == Triple::amdgcn)
363  return TT.getOS() == Triple::AMDHSA ? "generic-hsa" : "generic";
364 
365  return "r600";
366 }
367 
369  // The AMDGPU toolchain only supports generating shared objects, so we
370  // must always use PIC.
371  return Reloc::PIC_;
372 }
373 
375  StringRef CPU, StringRef FS,
376  TargetOptions Options,
379  CodeGenOpt::Level OptLevel)
381  FS, Options, getEffectiveRelocModel(RM),
382  getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
383  TLOF(createTLOF(getTargetTriple())) {
384  initAsmInfo();
385  if (TT.getArch() == Triple::amdgcn) {
386  if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))
388  else if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize32"))
390  }
391 }
392 
396 
398 
400  Attribute GPUAttr = F.getFnAttribute("target-cpu");
401  return GPUAttr.isValid() ? GPUAttr.getValueAsString() : getTargetCPU();
402 }
403 
405  Attribute FSAttr = F.getFnAttribute("target-features");
406 
407  return FSAttr.isValid() ? FSAttr.getValueAsString()
409 }
410 
411 /// Predicate for Internalize pass.
412 static bool mustPreserveGV(const GlobalValue &GV) {
413  if (const Function *F = dyn_cast<Function>(&GV))
414  return F->isDeclaration() || AMDGPU::isEntryFunctionCC(F->getCallingConv());
415 
416  return !GV.use_empty();
417 }
418 
420  Builder.DivergentTarget = true;
421 
422  bool EnableOpt = getOptLevel() > CodeGenOpt::None;
423  bool Internalize = InternalizeSymbols;
424  bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls;
425  bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt;
426  bool LibCallSimplify = EnableLibCallSimplify && EnableOpt;
427 
428  if (EnableFunctionCalls) {
429  delete Builder.Inliner;
431  }
432 
433  Builder.addExtension(
435  [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &,
437  if (AMDGPUAA) {
440  }
443  if (Internalize)
446  if (Internalize)
447  PM.add(createGlobalDCEPass());
448  if (EarlyInline)
450  });
451 
452  Builder.addExtension(
454  [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &,
456  if (AMDGPUAA) {
459  }
462  if (LibCallSimplify)
464  });
465 
466  Builder.addExtension(
468  [EnableOpt](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
469  // Add infer address spaces pass to the opt pipeline after inlining
470  // but before SROA to increase SROA opportunities.
472 
473  // This should run after inlining to have any chance of doing anything,
474  // and before other cleanup optimizations.
476 
477  // Promote alloca to vector before SROA and loop unroll. If we manage
478  // to eliminate allocas before unroll we may choose to unroll less.
479  if (EnableOpt)
481  });
482 }
483 
486 }
487 
489  bool DebugPassManager) {
493  if (PassName == "amdgpu-propagate-attributes-late") {
495  return true;
496  }
497  if (PassName == "amdgpu-unify-metadata") {
499  return true;
500  }
501  if (PassName == "amdgpu-printf-runtime-binding") {
503  return true;
504  }
505  if (PassName == "amdgpu-always-inline") {
507  return true;
508  }
509  if (PassName == "amdgpu-lower-module-lds") {
511  return true;
512  }
513  return false;
514  });
518  if (PassName == "amdgpu-simplifylib") {
520  return true;
521  }
522  if (PassName == "amdgpu-usenative") {
524  return true;
525  }
526  if (PassName == "amdgpu-promote-alloca") {
527  PM.addPass(AMDGPUPromoteAllocaPass(*this));
528  return true;
529  }
530  if (PassName == "amdgpu-promote-alloca-to-vector") {
532  return true;
533  }
534  if (PassName == "amdgpu-lower-kernel-attributes") {
536  return true;
537  }
538  if (PassName == "amdgpu-propagate-attributes-early") {
540  return true;
541  }
542  return false;
543  });
544 
546  FAM.registerPass([&] { return AMDGPUAA(); });
547  });
548 
549  PB.registerParseAACallback([](StringRef AAName, AAManager &AAM) {
550  if (AAName == "amdgpu-aa") {
552  return true;
553  }
554  return false;
555  });
556 
557  PB.registerPipelineStartEPCallback([this, DebugPassManager](
558  ModulePassManager &PM,
560  FunctionPassManager FPM(DebugPassManager);
566  });
567 
571  return;
572 
575 
576  if (InternalizeSymbols) {
578  }
580  if (InternalizeSymbols) {
581  PM.addPass(GlobalDCEPass());
582  }
585  });
586 
588  [this, DebugPassManager](CGSCCPassManager &PM,
591  return;
592 
593  FunctionPassManager FPM(DebugPassManager);
594 
595  // Add infer address spaces pass to the opt pipeline after inlining
596  // but before SROA to increase SROA opportunities.
598 
599  // This should run after inlining to have any chance of doing
600  // anything, and before other cleanup optimizations.
602 
604  // Promote alloca to vector before SROA and loop unroll. If we
605  // manage to eliminate allocas before unroll we may choose to unroll
606  // less.
608  }
609 
611  });
612 }
613 
614 //===----------------------------------------------------------------------===//
615 // R600 Target Machine (R600 -> Cayman)
616 //===----------------------------------------------------------------------===//
617 
619  StringRef CPU, StringRef FS,
620  TargetOptions Options,
623  CodeGenOpt::Level OL, bool JIT)
624  : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
626 
627  // Override the default since calls aren't supported for r600.
628  if (EnableFunctionCalls &&
629  EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
630  EnableFunctionCalls = false;
631 }
632 
634  const Function &F) const {
635  StringRef GPU = getGPUName(F);
637 
638  SmallString<128> SubtargetKey(GPU);
639  SubtargetKey.append(FS);
640 
641  auto &I = SubtargetMap[SubtargetKey];
642  if (!I) {
643  // This needs to be done before we create a new subtarget since any
644  // creation will depend on the TM and the code generation flags on the
645  // function that reside in TargetOptions.
647  I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
648  }
649 
650  return I.get();
651 }
652 
653 int64_t AMDGPUTargetMachine::getNullPointerValue(unsigned AddrSpace) {
654  return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
655  AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
656  AddrSpace == AMDGPUAS::REGION_ADDRESS)
657  ? -1
658  : 0;
659 }
660 
662  unsigned DestAS) const {
663  return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
665 }
666 
668  const auto *LD = dyn_cast<LoadInst>(V);
669  if (!LD)
671 
672  // It must be a generic pointer loaded.
673  assert(V->getType()->isPointerTy() &&
675 
676  const auto *Ptr = LD->getPointerOperand();
677  if (Ptr->getType()->getPointerAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
679  // For a generic pointer loaded from the constant memory, it could be assumed
680  // as a global pointer since the constant memory is only populated on the
681  // host side. As implied by the offload programming model, only global
682  // pointers could be referenced on the host side.
684 }
685 
688  return TargetTransformInfo(R600TTIImpl(this, F));
689 }
690 
691 //===----------------------------------------------------------------------===//
692 // GCN Target Machine (SI+)
693 //===----------------------------------------------------------------------===//
694 
696  StringRef CPU, StringRef FS,
697  TargetOptions Options,
700  CodeGenOpt::Level OL, bool JIT)
701  : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
702 
704  StringRef GPU = getGPUName(F);
706 
707  SmallString<128> SubtargetKey(GPU);
708  SubtargetKey.append(FS);
709 
710  auto &I = SubtargetMap[SubtargetKey];
711  if (!I) {
712  // This needs to be done before we create a new subtarget since any
713  // creation will depend on the TM and the code generation flags on the
714  // function that reside in TargetOptions.
716  I = std::make_unique<GCNSubtarget>(TargetTriple, GPU, FS, *this);
717  }
718 
719  I->setScalarizeGlobalBehavior(ScalarizeGlobal);
720 
721  return I.get();
722 }
723 
726  return TargetTransformInfo(GCNTTIImpl(this, F));
727 }
728 
729 //===----------------------------------------------------------------------===//
730 // AMDGPU Pass Setup
731 //===----------------------------------------------------------------------===//
732 
733 namespace {
734 
735 class AMDGPUPassConfig : public TargetPassConfig {
736 public:
737  AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
738  : TargetPassConfig(TM, PM) {
739  // Exceptions and StackMaps are not supported, so these passes will never do
740  // anything.
741  disablePass(&StackMapLivenessID);
742  disablePass(&FuncletLayoutID);
743  }
744 
745  AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
746  return getTM<AMDGPUTargetMachine>();
747  }
748 
750  createMachineScheduler(MachineSchedContext *C) const override {
753  return DAG;
754  }
755 
756  void addEarlyCSEOrGVNPass();
757  void addStraightLineScalarOptimizationPasses();
758  void addIRPasses() override;
759  void addCodeGenPrepare() override;
760  bool addPreISel() override;
761  bool addInstSelector() override;
762  bool addGCPasses() override;
763 
764  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
765 };
766 
767 std::unique_ptr<CSEConfigBase> AMDGPUPassConfig::getCSEConfig() const {
768  return getStandardCSEConfigForOpt(TM->getOptLevel());
769 }
770 
771 class R600PassConfig final : public AMDGPUPassConfig {
772 public:
773  R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
774  : AMDGPUPassConfig(TM, PM) {}
775 
776  ScheduleDAGInstrs *createMachineScheduler(
777  MachineSchedContext *C) const override {
779  }
780 
781  bool addPreISel() override;
782  bool addInstSelector() override;
783  void addPreRegAlloc() override;
784  void addPreSched2() override;
785  void addPreEmitPass() override;
786 };
787 
788 class GCNPassConfig final : public AMDGPUPassConfig {
789 public:
790  GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
791  : AMDGPUPassConfig(TM, PM) {
792  // It is necessary to know the register usage of the entire call graph. We
793  // allow calls without EnableAMDGPUFunctionCalls if they are marked
794  // noinline, so this is always required.
795  setRequiresCodeGenSCCOrder(true);
796  }
797 
798  GCNTargetMachine &getGCNTargetMachine() const {
799  return getTM<GCNTargetMachine>();
800  }
801 
803  createMachineScheduler(MachineSchedContext *C) const override;
804 
805  bool addPreISel() override;
806  void addMachineSSAOptimization() override;
807  bool addILPOpts() override;
808  bool addInstSelector() override;
809  bool addIRTranslator() override;
810  void addPreLegalizeMachineIR() override;
811  bool addLegalizeMachineIR() override;
812  void addPreRegBankSelect() override;
813  bool addRegBankSelect() override;
814  void addPreGlobalInstructionSelect() override;
815  bool addGlobalInstructionSelect() override;
816  void addFastRegAlloc() override;
817  void addOptimizedRegAlloc() override;
818  void addPreRegAlloc() override;
819  bool addPreRewrite() override;
820  void addPostRegAlloc() override;
821  void addPreSched2() override;
822  void addPreEmitPass() override;
823 };
824 
825 } // end anonymous namespace
826 
827 void AMDGPUPassConfig::addEarlyCSEOrGVNPass() {
828  if (getOptLevel() == CodeGenOpt::Aggressive)
829  addPass(createGVNPass());
830  else
831  addPass(createEarlyCSEPass());
832 }
833 
834 void AMDGPUPassConfig::addStraightLineScalarOptimizationPasses() {
835  addPass(createLICMPass());
838  // ReassociateGEPs exposes more opportunites for SLSR. See
839  // the example in reassociate-geps-and-slsr.ll.
841  // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
842  // EarlyCSE can reuse.
843  addEarlyCSEOrGVNPass();
844  // Run NaryReassociate after EarlyCSE/GVN to be more effective.
845  addPass(createNaryReassociatePass());
846  // NaryReassociate on GEPs creates redundant common expressions, so run
847  // EarlyCSE after it.
848  addPass(createEarlyCSEPass());
849 }
850 
851 void AMDGPUPassConfig::addIRPasses() {
852  const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
853 
854  // There is no reason to run these.
855  disablePass(&StackMapLivenessID);
856  disablePass(&FuncletLayoutID);
857  disablePass(&PatchableFunctionID);
858 
860 
861  // This must occur before inlining, as the inliner will not look through
862  // bitcast calls.
864 
865  // A call to propagate attributes pass in the backend in case opt was not run.
867 
868  addPass(createAtomicExpandPass());
869 
870 
872 
873  // Function calls are not supported, so make sure we inline everything.
874  addPass(createAMDGPUAlwaysInlinePass());
876  // We need to add the barrier noop pass, otherwise adding the function
877  // inlining pass will cause all of the PassConfigs passes to be run
878  // one function at a time, which means if we have a nodule with two
879  // functions, then we will generate code for the first function
880  // without ever running any passes on the second.
881  addPass(createBarrierNoopPass());
882 
883  // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
884  if (TM.getTargetTriple().getArch() == Triple::r600)
886 
887  // Replace OpenCL enqueued block function pointers with global variables.
889 
890  // Can increase LDS used by kernel so runs before PromoteAlloca
893 
894  if (TM.getOptLevel() > CodeGenOpt::None) {
895  addPass(createInferAddressSpacesPass());
896  addPass(createAMDGPUPromoteAlloca());
897 
898  if (EnableSROA)
899  addPass(createSROAPass());
900 
902  addStraightLineScalarOptimizationPasses();
903 
905  addPass(createAMDGPUAAWrapperPass());
907  AAResults &AAR) {
908  if (auto *WrapperPass = P.getAnalysisIfAvailable<AMDGPUAAWrapperPass>())
909  AAR.addAAResult(WrapperPass->getResult());
910  }));
911  }
912  }
913 
914  if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
915  // TODO: May want to move later or split into an early and late one.
917  }
918 
920 
921  // EarlyCSE is not always strong enough to clean up what LSR produces. For
922  // example, GVN can combine
923  //
924  // %0 = add %a, %b
925  // %1 = add %b, %a
926  //
927  // and
928  //
929  // %0 = shl nsw %a, 2
930  // %1 = shl %a, 2
931  //
932  // but EarlyCSE can do neither of them.
933  if (getOptLevel() != CodeGenOpt::None && EnableScalarIRPasses)
934  addEarlyCSEOrGVNPass();
935 }
936 
937 void AMDGPUPassConfig::addCodeGenPrepare() {
938  if (TM->getTargetTriple().getArch() == Triple::amdgcn)
940 
941  if (TM->getTargetTriple().getArch() == Triple::amdgcn &&
944 
945  addPass(&AMDGPUPerfHintAnalysisID);
946 
948 
951 
952  // LowerSwitch pass may introduce unreachable blocks that can
953  // cause unexpected behavior for subsequent passes. Placing it
954  // here seems better that these blocks would get cleaned up by
955  // UnreachableBlockElim inserted next in the pass flow.
956  addPass(createLowerSwitchPass());
957 }
958 
959 bool AMDGPUPassConfig::addPreISel() {
960  addPass(createFlattenCFGPass());
961  return false;
962 }
963 
964 bool AMDGPUPassConfig::addInstSelector() {
965  // Defer the verifier until FinalizeISel.
966  addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false);
967  return false;
968 }
969 
970 bool AMDGPUPassConfig::addGCPasses() {
971  // Do nothing. GC is not supported.
972  return false;
973 }
974 
975 //===----------------------------------------------------------------------===//
976 // R600 Pass Setup
977 //===----------------------------------------------------------------------===//
978 
979 bool R600PassConfig::addPreISel() {
980  AMDGPUPassConfig::addPreISel();
981 
983  addPass(createStructurizeCFGPass());
984  return false;
985 }
986 
987 bool R600PassConfig::addInstSelector() {
988  addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
989  return false;
990 }
991 
992 void R600PassConfig::addPreRegAlloc() {
993  addPass(createR600VectorRegMerger());
994 }
995 
996 void R600PassConfig::addPreSched2() {
997  addPass(createR600EmitClauseMarkers(), false);
999  addPass(&IfConverterID, false);
1000  addPass(createR600ClauseMergePass(), false);
1001 }
1002 
1003 void R600PassConfig::addPreEmitPass() {
1004  addPass(createAMDGPUCFGStructurizerPass(), false);
1005  addPass(createR600ExpandSpecialInstrsPass(), false);
1006  addPass(&FinalizeMachineBundlesID, false);
1007  addPass(createR600Packetizer(), false);
1008  addPass(createR600ControlFlowFinalizer(), false);
1009 }
1010 
1012  return new R600PassConfig(*this, PM);
1013 }
1014 
1015 //===----------------------------------------------------------------------===//
1016 // GCN Pass Setup
1017 //===----------------------------------------------------------------------===//
1018 
1019 ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
1020  MachineSchedContext *C) const {
1021  const GCNSubtarget &ST = C->MF->getSubtarget<GCNSubtarget>();
1022  if (ST.enableSIScheduler())
1023  return createSIMachineScheduler(C);
1025 }
1026 
1027 bool GCNPassConfig::addPreISel() {
1028  AMDGPUPassConfig::addPreISel();
1029 
1033  }
1034 
1035  // FIXME: We need to run a pass to propagate the attributes when calls are
1036  // supported.
1037 
1038  // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
1039  // regions formed by them.
1041  if (!LateCFGStructurize) {
1043  addPass(createFixIrreduciblePass());
1044  addPass(createUnifyLoopExitsPass());
1045  }
1046  addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions
1047  }
1048  addPass(createSinkingPass());
1050  if (!LateCFGStructurize) {
1052  }
1053  addPass(createLCSSAPass());
1054 
1055  return false;
1056 }
1057 
1058 void GCNPassConfig::addMachineSSAOptimization() {
1060 
1061  // We want to fold operands after PeepholeOptimizer has run (or as part of
1062  // it), because it will eliminate extra copies making it easier to fold the
1063  // real source operand. We want to eliminate dead instructions after, so that
1064  // we see fewer uses of the copies. We then need to clean up the dead
1065  // instructions leftover after the operands are folded as well.
1066  //
1067  // XXX - Can we get away without running DeadMachineInstructionElim again?
1068  addPass(&SIFoldOperandsID);
1069  if (EnableDPPCombine)
1070  addPass(&GCNDPPCombineID);
1071  addPass(&DeadMachineInstructionElimID);
1072  addPass(&SILoadStoreOptimizerID);
1073  if (EnableSDWAPeephole) {
1074  addPass(&SIPeepholeSDWAID);
1075  addPass(&EarlyMachineLICMID);
1076  addPass(&MachineCSEID);
1077  addPass(&SIFoldOperandsID);
1078  addPass(&DeadMachineInstructionElimID);
1079  }
1080  addPass(createSIShrinkInstructionsPass());
1081 }
1082 
1083 bool GCNPassConfig::addILPOpts() {
1085  addPass(&EarlyIfConverterID);
1086 
1088  return false;
1089 }
1090 
1091 bool GCNPassConfig::addInstSelector() {
1092  AMDGPUPassConfig::addInstSelector();
1093  addPass(&SIFixSGPRCopiesID);
1094  addPass(createSILowerI1CopiesPass());
1095  return false;
1096 }
1097 
1098 bool GCNPassConfig::addIRTranslator() {
1099  addPass(new IRTranslator(getOptLevel()));
1100  return false;
1101 }
1102 
1103 void GCNPassConfig::addPreLegalizeMachineIR() {
1104  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1105  addPass(createAMDGPUPreLegalizeCombiner(IsOptNone));
1106  addPass(new Localizer());
1107 }
1108 
1109 bool GCNPassConfig::addLegalizeMachineIR() {
1110  addPass(new Legalizer());
1111  return false;
1112 }
1113 
1114 void GCNPassConfig::addPreRegBankSelect() {
1115  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1116  addPass(createAMDGPUPostLegalizeCombiner(IsOptNone));
1117 }
1118 
1119 bool GCNPassConfig::addRegBankSelect() {
1120  addPass(new RegBankSelect());
1121  return false;
1122 }
1123 
1124 void GCNPassConfig::addPreGlobalInstructionSelect() {
1125  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
1126  addPass(createAMDGPURegBankCombiner(IsOptNone));
1127 }
1128 
1129 bool GCNPassConfig::addGlobalInstructionSelect() {
1130  addPass(new InstructionSelect(getOptLevel()));
1131  return false;
1132 }
1133 
1134 void GCNPassConfig::addPreRegAlloc() {
1135  if (LateCFGStructurize) {
1137  }
1138 }
1139 
1140 void GCNPassConfig::addFastRegAlloc() {
1141  // FIXME: We have to disable the verifier here because of PHIElimination +
1142  // TwoAddressInstructions disabling it.
1143 
1144  // This must be run immediately after phi elimination and before
1145  // TwoAddressInstructions, otherwise the processing of the tied operand of
1146  // SI_ELSE will introduce a copy of the tied operand source after the else.
1147  insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1148 
1151 
1153 }
1154 
1155 void GCNPassConfig::addOptimizedRegAlloc() {
1156  // Allow the scheduler to run before SIWholeQuadMode inserts exec manipulation
1157  // instructions that cause scheduling barriers.
1158  insertPass(&MachineSchedulerID, &SIWholeQuadModeID);
1160 
1161  if (OptExecMaskPreRA)
1164 
1165  // This must be run immediately after phi elimination and before
1166  // TwoAddressInstructions, otherwise the processing of the tied operand of
1167  // SI_ELSE will introduce a copy of the tied operand source after the else.
1168  insertPass(&PHIEliminationID, &SILowerControlFlowID, false);
1169 
1170  if (EnableDCEInRA)
1172 
1174 }
1175 
1176 bool GCNPassConfig::addPreRewrite() {
1177  if (EnableRegReassign) {
1178  addPass(&GCNNSAReassignID);
1180  }
1181  return true;
1182 }
1183 
1184 void GCNPassConfig::addPostRegAlloc() {
1185  addPass(&SIFixVGPRCopiesID);
1186  if (getOptLevel() > CodeGenOpt::None)
1187  addPass(&SIOptimizeExecMaskingID);
1189 
1190  // Equivalent of PEI for SGPRs.
1191  addPass(&SILowerSGPRSpillsID);
1192 }
1193 
1194 void GCNPassConfig::addPreSched2() {
1195  addPass(&SIPostRABundlerID);
1196 }
1197 
1198 void GCNPassConfig::addPreEmitPass() {
1199  addPass(createSIMemoryLegalizerPass());
1200  addPass(createSIInsertWaitcntsPass());
1201  addPass(createSIShrinkInstructionsPass());
1202  addPass(createSIModeRegisterPass());
1203 
1204  if (getOptLevel() > CodeGenOpt::None)
1205  addPass(&SIInsertHardClausesID);
1206 
1207  addPass(&SILateBranchLoweringPassID);
1208  if (getOptLevel() > CodeGenOpt::None)
1209  addPass(&SIPreEmitPeepholeID);
1210  // The hazard recognizer that runs as part of the post-ra scheduler does not
1211  // guarantee to be able handle all hazards correctly. This is because if there
1212  // are multiple scheduling regions in a basic block, the regions are scheduled
1213  // bottom up, so when we begin to schedule a region we don't know what
1214  // instructions were emitted directly before it.
1215  //
1216  // Here we add a stand-alone hazard recognizer pass which can handle all
1217  // cases.
1218  addPass(&PostRAHazardRecognizerID);
1219  addPass(&BranchRelaxationPassID);
1220 }
1221 
1223  return new GCNPassConfig(*this, PM);
1224 }
1225 
1227  return new yaml::SIMachineFunctionInfo();
1228 }
1229 
1233  return new yaml::SIMachineFunctionInfo(*MFI,
1234  *MF.getSubtarget().getRegisterInfo());
1235 }
1236 
1239  SMDiagnostic &Error, SMRange &SourceRange) const {
1240  const yaml::SIMachineFunctionInfo &YamlMFI =
1241  reinterpret_cast<const yaml::SIMachineFunctionInfo &>(MFI_);
1242  MachineFunction &MF = PFS.MF;
1244 
1245  MFI->initializeBaseYamlFields(YamlMFI);
1246 
1247  if (MFI->Occupancy == 0) {
1248  // Fixup the subtarget dependent default value.
1249  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1250  MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize());
1251  }
1252 
1253  auto parseRegister = [&](const yaml::StringValue &RegName, Register &RegVal) {
1254  Register TempReg;
1255  if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) {
1256  SourceRange = RegName.SourceRange;
1257  return true;
1258  }
1259  RegVal = TempReg;
1260 
1261  return false;
1262  };
1263 
1264  auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
1265  // Create a diagnostic for a the register string literal.
1266  const MemoryBuffer &Buffer =
1267  *PFS.SM->getMemoryBuffer(PFS.SM->getMainFileID());
1268  Error = SMDiagnostic(*PFS.SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
1269  RegName.Value.size(), SourceMgr::DK_Error,
1270  "incorrect register class for field", RegName.Value,
1271  None, None);
1272  SourceRange = RegName.SourceRange;
1273  return true;
1274  };
1275 
1276  if (parseRegister(YamlMFI.ScratchRSrcReg, MFI->ScratchRSrcReg) ||
1277  parseRegister(YamlMFI.FrameOffsetReg, MFI->FrameOffsetReg) ||
1278  parseRegister(YamlMFI.StackPtrOffsetReg, MFI->StackPtrOffsetReg))
1279  return true;
1280 
1281  if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
1282  !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1283  return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
1284  }
1285 
1286  if (MFI->FrameOffsetReg != AMDGPU::FP_REG &&
1287  !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1288  return diagnoseRegisterClass(YamlMFI.FrameOffsetReg);
1289  }
1290 
1291  if (MFI->StackPtrOffsetReg != AMDGPU::SP_REG &&
1292  !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1293  return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg);
1294  }
1295 
1296  auto parseAndCheckArgument = [&](const Optional<yaml::SIArgument> &A,
1297  const TargetRegisterClass &RC,
1298  ArgDescriptor &Arg, unsigned UserSGPRs,
1299  unsigned SystemSGPRs) {
1300  // Skip parsing if it's not present.
1301  if (!A)
1302  return false;
1303 
1304  if (A->IsRegister) {
1305  Register Reg;
1306  if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, Error)) {
1307  SourceRange = A->RegisterName.SourceRange;
1308  return true;
1309  }
1310  if (!RC.contains(Reg))
1311  return diagnoseRegisterClass(A->RegisterName);
1313  } else
1314  Arg = ArgDescriptor::createStack(A->StackOffset);
1315  // Check and apply the optional mask.
1316  if (A->Mask)
1317  Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue());
1318 
1319  MFI->NumUserSGPRs += UserSGPRs;
1320  MFI->NumSystemSGPRs += SystemSGPRs;
1321  return false;
1322  };
1323 
1324  if (YamlMFI.ArgInfo &&
1325  (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
1326  AMDGPU::SGPR_128RegClass,
1327  MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
1328  parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
1329  AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
1330  2, 0) ||
1331  parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass,
1332  MFI->ArgInfo.QueuePtr, 2, 0) ||
1333  parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr,
1334  AMDGPU::SReg_64RegClass,
1335  MFI->ArgInfo.KernargSegmentPtr, 2, 0) ||
1336  parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID,
1337  AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchID,
1338  2, 0) ||
1339  parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit,
1340  AMDGPU::SReg_64RegClass,
1341  MFI->ArgInfo.FlatScratchInit, 2, 0) ||
1342  parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize,
1343  AMDGPU::SGPR_32RegClass,
1344  MFI->ArgInfo.PrivateSegmentSize, 0, 0) ||
1345  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX,
1346  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDX,
1347  0, 1) ||
1348  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY,
1349  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDY,
1350  0, 1) ||
1351  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ,
1352  AMDGPU::SGPR_32RegClass, MFI->ArgInfo.WorkGroupIDZ,
1353  0, 1) ||
1354  parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo,
1355  AMDGPU::SGPR_32RegClass,
1356  MFI->ArgInfo.WorkGroupInfo, 0, 1) ||
1357  parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset,
1358  AMDGPU::SGPR_32RegClass,
1359  MFI->ArgInfo.PrivateSegmentWaveByteOffset, 0, 1) ||
1360  parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr,
1361  AMDGPU::SReg_64RegClass,
1362  MFI->ArgInfo.ImplicitArgPtr, 0, 0) ||
1363  parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr,
1364  AMDGPU::SReg_64RegClass,
1365  MFI->ArgInfo.ImplicitBufferPtr, 2, 0) ||
1366  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX,
1367  AMDGPU::VGPR_32RegClass,
1368  MFI->ArgInfo.WorkItemIDX, 0, 0) ||
1369  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY,
1370  AMDGPU::VGPR_32RegClass,
1371  MFI->ArgInfo.WorkItemIDY, 0, 0) ||
1372  parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ,
1373  AMDGPU::VGPR_32RegClass,
1374  MFI->ArgInfo.WorkItemIDZ, 0, 0)))
1375  return true;
1376 
1377  MFI->Mode.IEEE = YamlMFI.Mode.IEEE;
1378  MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp;
1383 
1384  return false;
1385 }
llvm::AAResults::addAAResult
void addAAResult(AAResultT &AAResult)
Register a specific AA result.
Definition: AliasAnalysis.h:465
llvm::initializeR600ControlFlowFinalizerPass
void initializeR600ControlFlowFinalizerPass(PassRegistry &)
llvm::TargetPassConfig::addPostRegAlloc
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Definition: TargetPassConfig.h:415
llvm::createR600ExpandSpecialInstrsPass
FunctionPass * createR600ExpandSpecialInstrsPass()
Definition: R600ExpandSpecialInstrs.cpp:57
EnableDCEInRA
static cl::opt< bool > EnableDCEInRA("amdgpu-dce-in-ra", cl::init(true), cl::Hidden, cl::desc("Enable machine DCE inside regalloc"))
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:198
llvm::AAManager
A manager for alias analyses.
Definition: AliasAnalysis.h:1221
llvm::AMDGPUAA
Analysis pass providing a never-invalidated alias analysis result.
Definition: AMDGPUAliasAnalysis.h:50
llvm::ArgDescriptor::createStack
static constexpr ArgDescriptor createStack(unsigned Offset, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:49
llvm::AMDGPUFunctionArgInfo::QueuePtr
ArgDescriptor QueuePtr
Definition: AMDGPUArgumentUsageInfo.h:126
llvm::AMDGPUTargetMachine::EnableFixedFunctionABI
static bool EnableFixedFunctionABI
Definition: AMDGPUTargetMachine.h:37
llvm::initializeR600PacketizerPass
void initializeR600PacketizerPass(PassRegistry &)
LLVMInitializeAMDGPUTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget()
Definition: AMDGPUTargetMachine.cpp:201
llvm::AMDGPUAS::UNKNOWN_ADDRESS_SPACE
@ UNKNOWN_ADDRESS_SPACE
Definition: AMDGPU.h:413
llvm::InferAddressSpacesPass
Definition: InferAddressSpaces.h:16
EnableSIModeRegisterPass
static cl::opt< bool > EnableSIModeRegisterPass("amdgpu-mode-register", cl::desc("Enable mode register pass"), cl::init(true), cl::Hidden)
llvm::PerFunctionMIParsingState::SM
SourceMgr * SM
Definition: MIParser.h:163
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:155
llvm::AMDGPUTargetMachine::registerDefaultAliasAnalyses
void registerDefaultAliasAnalyses(AAManager &) override
Allow the target to register alias analyses with the AAManager for use with the new pass manager.
Definition: AMDGPUTargetMachine.cpp:484
mustPreserveGV
static bool mustPreserveGV(const GlobalValue &GV)
Predicate for Internalize pass.
Definition: AMDGPUTargetMachine.cpp:412
llvm::createSeparateConstOffsetFromGEPPass
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Definition: SeparateConstOffsetFromGEP.cpp:499
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:156
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::GCNTargetMachine::convertFuncInfoToYAML
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
Definition: AMDGPUTargetMachine.cpp:1231
llvm::AMDGPULowerModuleLDSPass
Definition: AMDGPU.h:162
llvm::initializeR600ExpandSpecialInstrsPassPass
void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &)
llvm::initializeAMDGPUPostLegalizerCombinerPass
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
llvm::initializeAMDGPUPromoteAllocaPass
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
llvm::createSIMemoryLegalizerPass
FunctionPass * createSIMemoryLegalizerPass()
Definition: SIMemoryLegalizer.cpp:1791
llvm::SILowerSGPRSpillsID
char & SILowerSGPRSpillsID
Definition: SILowerSGPRSpills.cpp:78
llvm::Wave32
@ Wave32
Definition: AMDGPUMCTargetDesc.h:34
llvm::PassBuilder::registerPipelineStartEPCallback
void registerPipelineStartEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:608
llvm::Type::isPointerTy
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:229
llvm::TargetOptions
Definition: TargetOptions.h:123
llvm::AMDGPUAlwaysInlinePass
Definition: AMDGPU.h:270
llvm::yaml::SIMachineFunctionInfo::ArgInfo
Optional< SIArgumentInfo > ArgInfo
Definition: SIMachineFunctionInfo.h:289
SIMachineFunctionInfo.h
Scalar.h
llvm::ArgDescriptor::createArg
static constexpr ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask)
Definition: AMDGPUArgumentUsageInfo.h:54
createMinRegScheduler
static ScheduleDAGInstrs * createMinRegScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:299
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::Function
Definition: Function.h:61
llvm::cl::location
LocationClass< Ty > location(Ty &L)
Definition: CommandLine.h:456
llvm::Attribute
Definition: Attributes.h:52
llvm::AMDGPU::SIModeRegisterDefaults::FP32OutputDenormals
bool FP32OutputDenormals
Definition: AMDGPUBaseInfo.h:899
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::initializeAMDGPUAlwaysInlinePass
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
llvm::yaml::MachineFunctionInfo
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Definition: MIRYamlMapping.h:626
llvm::PHIEliminationID
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
Definition: PHIElimination.cpp:129
llvm::initializeSIInsertHardClausesPass
void initializeSIInsertHardClausesPass(PassRegistry &)
llvm::initializeAMDGPUOpenCLEnqueuedBlockLoweringPass
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
llvm::initializeSIPreAllocateWWMRegsPass
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::initializeAMDGPUPropagateAttributesLatePass
void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &)
InferAddressSpaces.h
llvm::AMDGPU::SIModeRegisterDefaults::IEEE
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
Definition: AMDGPUBaseInfo.h:890
llvm::createAlwaysInlinerLegacyPass
Pass * createAlwaysInlinerLegacyPass(bool InsertLifetime=true)
Create a legacy pass manager instance of a pass to inline and remove functions marked as "always_inli...
Definition: AlwaysInliner.cpp:169
getGPUOrDefault
static LLVM_READNONE StringRef getGPUOrDefault(const Triple &TT, StringRef GPU)
Definition: AMDGPUTargetMachine.cpp:357
R600MachineScheduler.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:124
llvm::AMDGPUPromoteAllocaToVectorPass
Definition: AMDGPU.h:255
llvm::initializeAMDGPULateCodeGenPreparePass
void initializeAMDGPULateCodeGenPreparePass(PassRegistry &)
llvm::createFixIrreduciblePass
FunctionPass * createFixIrreduciblePass()
Definition: FixIrreducible.cpp:103
llvm::MachineSchedRegistry
MachineSchedRegistry provides a selection of available machine instruction schedulers.
Definition: MachineScheduler.h:135
llvm::Triple::amdgcn
@ amdgcn
Definition: Triple.h:72
GCNSchedStrategy.h
llvm::GCNIterativeScheduler::SCHEDULE_ILP
@ SCHEDULE_ILP
Definition: GCNIterativeScheduler.h:37
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:693
llvm::createAMDGPULateCodeGenPreparePass
FunctionPass * createAMDGPULateCodeGenPreparePass()
Definition: AMDGPULateCodeGenPrepare.cpp:193
llvm::createSILowerI1CopiesPass
FunctionPass * createSILowerI1CopiesPass()
Definition: SILowerI1Copies.cpp:413
llvm::initializeR600ClauseMergePassPass
void initializeR600ClauseMergePassPass(PassRegistry &)
llvm::GCNIterativeScheduler::SCHEDULE_LEGACYMAXOCCUPANCY
@ SCHEDULE_LEGACYMAXOCCUPANCY
Definition: GCNIterativeScheduler.h:36
llvm::AMDGPU::RM_BOTH
@ RM_BOTH
Definition: AMDGPU.h:81
llvm::createFlattenCFGPass
FunctionPass * createFlattenCFGPass()
Definition: FlattenCFGPass.cpp:52
llvm::InternalizePass
A pass that internalizes all functions and variables other than those that must be preserved accordin...
Definition: Internalize.h:36
llvm::initializeSIOptimizeExecMaskingPreRAPass
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
llvm::AMDGPUFunctionArgInfo::FlatScratchInit
ArgDescriptor FlatScratchInit
Definition: AMDGPUArgumentUsageInfo.h:129
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::createEarlyCSEPass
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1699
llvm::Wave64
@ Wave64
Definition: AMDGPUMCTargetDesc.h:34
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::initializeSILowerI1CopiesPass
void initializeSILowerI1CopiesPass(PassRegistry &)
llvm::SIPreEmitPeepholeID
char & SIPreEmitPeepholeID
llvm::createAMDGPUPostLegalizeCombiner
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPostLegalizerCombiner.cpp:390
llvm::initializeAMDGPUDAGToDAGISelPass
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
llvm::initializeSIPeepholeSDWAPass
void initializeSIPeepholeSDWAPass(PassRegistry &)
llvm::SILowerControlFlowID
char & SILowerControlFlowID
Definition: SILowerControlFlow.cpp:165
llvm::yaml::SIMachineFunctionInfo
Definition: SIMachineFunctionInfo.h:269
llvm::AMDGPUMachineFunction::getLDSSize
unsigned getLDSSize() const
Definition: AMDGPUMachineFunction.h:70
llvm::createAMDGPUUnifyMetadataPass
ModulePass * createAMDGPUUnifyMetadataPass()
InstructionSelect.h
EnableStructurizerWorkarounds
static cl::opt< bool > EnableStructurizerWorkarounds("amdgpu-enable-structurizer-workarounds", cl::desc("Enable workarounds for the StructurizeCFG pass"), cl::init(true), cl::Hidden)
llvm::AMDGPUAAWrapperPass
Legacy wrapper pass to provide the AMDGPUAAResult object.
Definition: AMDGPUAliasAnalysis.h:64
llvm::createCGSCCToFunctionPassAdaptor
CGSCCToFunctionPassAdaptor createCGSCCToFunctionPassAdaptor(FunctionPassT Pass)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: CGSCCPassManager.h:494
EnableAtomicOptimizations
static cl::opt< bool > EnableAtomicOptimizations("amdgpu-atomic-optimizations", cl::desc("Enable atomic optimizations"), cl::init(false), cl::Hidden)
createGCNMaxOccupancyMachineScheduler
static ScheduleDAGInstrs * createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:282
llvm::Optional< Reloc::Model >
llvm::GCNScheduleDAGMILive
Definition: GCNSchedStrategy.h:73
llvm::initializeSIFoldOperandsPass
void initializeSIFoldOperandsPass(PassRegistry &)
llvm::createBarrierNoopPass
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
Definition: BarrierNoopPass.cpp:43
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::createAMDGPUISelDag
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
Definition: AMDGPUISelDAGToDAG.cpp:380
InternalizeSymbols
static cl::opt< bool > InternalizeSymbols("amdgpu-internalize-symbols", cl::desc("Enable elimination of non-kernel functions and unused globals"), cl::init(false), cl::Hidden)
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
llvm::AMDGPU::SIModeRegisterDefaults::FP32InputDenormals
bool FP32InputDenormals
If this is set, neither input or output denormals are flushed for most f32 instructions.
Definition: AMDGPUBaseInfo.h:898
llvm::PassBuilder::registerAnalysisRegistrationCallback
void registerAnalysisRegistrationCallback(const std::function< void(CGSCCAnalysisManager &)> &C)
{{@ Register callbacks for analysis registration with this PassBuilder instance.
Definition: PassBuilder.h:641
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
SIMachineScheduler.h
llvm::yaml::SIMode::FP32OutputDenormals
bool FP32OutputDenormals
Definition: SIMachineFunctionInfo.h:233
llvm::createGVNPass
FunctionPass * createGVNPass(bool NoMemDepAnalysis=false)
Create a legacy GVN pass.
Definition: GVN.cpp:2967
llvm::AMDGPUFunctionArgInfo::PrivateSegmentSize
ArgDescriptor PrivateSegmentSize
Definition: AMDGPUArgumentUsageInfo.h:130
llvm::createR600OpenCLImageTypeLoweringPass
ModulePass * createR600OpenCLImageTypeLoweringPass()
Definition: R600OpenCLImageTypeLoweringPass.cpp:372
llvm::createR600ClauseMergePass
FunctionPass * createR600ClauseMergePass()
Definition: R600ClauseMergePass.cpp:209
llvm::AMDGPUUseNativeCallsPass
Definition: AMDGPU.h:95
llvm::AMDGPUFunctionArgInfo::DispatchPtr
ArgDescriptor DispatchPtr
Definition: AMDGPUArgumentUsageInfo.h:125
llvm::initializeAMDGPUPropagateAttributesEarlyPass
void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &)
llvm::SIPreAllocateWWMRegsID
char & SIPreAllocateWWMRegsID
Definition: SIPreAllocateWWMRegs.cpp:81
llvm::SIPostRABundlerID
char & SIPostRABundlerID
Definition: SIPostRABundler.cpp:69
llvm::initializeSIShrinkInstructionsPass
void initializeSIShrinkInstructionsPass(PassRegistry &)
LegacyPassManager.h
llvm::TwoAddressInstructionPassID
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Definition: TwoAddressInstructionPass.cpp:192
PassManagerBuilder.h
llvm::cl::ReallyHidden
@ ReallyHidden
Definition: CommandLine.h:141
llvm::GCNTargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: AMDGPUTargetMachine.cpp:1237
llvm::initializeAMDGPUSimplifyLibCallsPass
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
Internalize.h
createSIMachineScheduler
static ScheduleDAGInstrs * createSIMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:277
llvm::MemoryBuffer
This interface provides simple read-only access to a block of memory, and provides simple methods for...
Definition: MemoryBuffer.h:50
llvm::AMDGPUMachineFunction::Mode
AMDGPU::SIModeRegisterDefaults Mode
Definition: AMDGPUMachineFunction.h:44
DisableLowerModuleLDS
static cl::opt< bool > DisableLowerModuleLDS("amdgpu-disable-lower-module-lds", cl::Hidden, cl::desc("Disable lower module lds pass"), cl::init(false))
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::createAMDGPUExternalAAWrapperPass
ImmutablePass * createAMDGPUExternalAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:36
llvm::AMDGPUFunctionArgInfo::DispatchID
ArgDescriptor DispatchID
Definition: AMDGPUArgumentUsageInfo.h:128
llvm::initializeAMDGPULowerIntrinsicsPass
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
llvm::initializeGCNDPPCombinePass
void initializeGCNDPPCombinePass(PassRegistry &)
llvm::AMDGPUUnifyMetadataPass
Definition: AMDGPU.h:294
llvm::PassBuilder::OptimizationLevel::O0
static const OptimizationLevel O0
Disable as many optimizations as possible.
Definition: PassBuilder.h:183
llvm::AMDGPUFunctionArgInfo::ImplicitArgPtr
ArgDescriptor ImplicitArgPtr
Definition: AMDGPUArgumentUsageInfo.h:141
EnableSDWAPeephole
static cl::opt< bool > EnableSDWAPeephole("amdgpu-sdwa-peephole", cl::desc("Enable SDWA peepholer"), cl::init(true))
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::SIOptimizeExecMaskingID
char & SIOptimizeExecMaskingID
Definition: SIOptimizeExecMasking.cpp:52
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::initializeAMDGPUUnifyMetadataPass
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
llvm::yaml::SIMachineFunctionInfo::FrameOffsetReg
StringValue FrameOffsetReg
Definition: SIMachineFunctionInfo.h:286
llvm::initializeAMDGPUArgumentUsageInfoPass
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
SISchedRegistry
static MachineSchedRegistry SISchedRegistry("si", "Run SI's custom scheduler", createSIMachineScheduler)
GCNIterativeScheduler.h
llvm::AMDGPUFunctionArgInfo::WorkGroupIDX
ArgDescriptor WorkGroupIDX
Definition: AMDGPUArgumentUsageInfo.h:133
llvm::GCNTargetMachine::GCNTargetMachine
GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AMDGPUTargetMachine.cpp:695
llvm::createInferAddressSpacesPass
FunctionPass * createInferAddressSpacesPass(unsigned AddressSpace=~0u)
Definition: InferAddressSpaces.cpp:1199
llvm::initializeSILateBranchLoweringPass
void initializeSILateBranchLoweringPass(PassRegistry &)
AMDGPUAliasAnalysis.h
llvm::AMDGPUTargetMachine
Definition: AMDGPUTargetMachine.h:27
llvm::createAMDGPUUseNativeCallsPass
FunctionPass * createAMDGPUUseNativeCallsPass()
Definition: AMDGPULibCalls.cpp:1702
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::createR600Packetizer
FunctionPass * createR600Packetizer()
Definition: R600Packetizer.cpp:411
AlwaysInliner.h
llvm::R600TargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: AMDGPUTargetMachine.cpp:687
llvm::AAResults
Definition: AliasAnalysis.h:456
llvm::yaml::SIMode::FP32InputDenormals
bool FP32InputDenormals
Definition: SIMachineFunctionInfo.h:232
llvm::PassBuilder::registerParseAACallback
void registerParseAACallback(const std::function< bool(StringRef Name, AAManager &AA)> &C)
Register a callback for parsing an AliasAnalysis Name to populate the given AAManager AA.
Definition: PassBuilder.h:633
llvm::X86AS::FS
@ FS
Definition: X86.h:183
ScalarizeGlobal
static cl::opt< bool > ScalarizeGlobal("amdgpu-scalarize-global-loads", cl::desc("Enable global load scalarization"), cl::init(true), cl::Hidden)
llvm::createNaryReassociatePass
FunctionPass * createNaryReassociatePass()
Definition: NaryReassociate.cpp:165
llvm::PostRAHazardRecognizerID
char & PostRAHazardRecognizerID
PostRAHazardRecognizer - This pass runs the post-ra hazard recognizer.
Definition: PostRAHazardRecognizer.cpp:64
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
llvm::initializeAMDGPULowerKernelArgumentsPass
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
llvm::initializeSIWholeQuadModePass
void initializeSIWholeQuadModePass(PassRegistry &)
llvm::initializeAMDGPUAtomicOptimizerPass
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
llvm::getTheAMDGPUTarget
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
Definition: AMDGPUTargetInfo.cpp:20
llvm::Legalizer
Definition: Legalizer.h:31
llvm::AMDGPUFunctionArgInfo::WorkItemIDX
ArgDescriptor WorkItemIDX
Definition: AMDGPUArgumentUsageInfo.h:148
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
EnableAMDGPUAliasAnalysis
static cl::opt< bool > EnableAMDGPUAliasAnalysis("enable-amdgpu-aa", cl::Hidden, cl::desc("Enable AMDGPU Alias Analysis"), cl::init(true))
EnableLowerKernelArguments
static cl::opt< bool > EnableLowerKernelArguments("amdgpu-ir-lower-kernel-arguments", cl::desc("Lower kernel argument loads in IR pass"), cl::init(true), cl::Hidden)
EnableLoadStoreVectorizer
static cl::opt< bool > EnableLoadStoreVectorizer("amdgpu-load-store-vectorizer", cl::desc("Enable load store vectorizer"), cl::init(true), cl::Hidden)
AMDGPUTargetInfo.h
llvm::createAMDGPULowerModuleLDSPass
ModulePass * createAMDGPULowerModuleLDSPass()
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
AMDGPUMacroFusion.h
llvm::initializeAMDGPUUseNativeCallsPass
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
llvm::createSIInsertWaitcntsPass
FunctionPass * createSIInsertWaitcntsPass()
Definition: SIInsertWaitcnts.cpp:797
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::PassBuilder
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:139
EnableRegReassign
static cl::opt< bool > EnableRegReassign("amdgpu-reassign-regs", cl::desc("Enable register reassign optimizations on gfx10+"), cl::init(true), cl::Hidden)
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:251
llvm::yaml::SIMode::FP64FP16InputDenormals
bool FP64FP16InputDenormals
Definition: SIMachineFunctionInfo.h:234
llvm::createAMDGPUAnnotateUniformValues
FunctionPass * createAMDGPUAnnotateUniformValues()
Definition: AMDGPUAnnotateUniformValues.cpp:186
llvm::AMDGPUAS::GLOBAL_ADDRESS
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:373
llvm::createR600EmitClauseMarkers
FunctionPass * createR600EmitClauseMarkers()
Definition: R600EmitClauseMarkers.cpp:336
llvm::initializeAMDGPUUnifyDivergentExitNodesPass
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:730
llvm::AMDGPUPromoteAllocaPass
Definition: AMDGPU.h:247
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:31
llvm::initializeGCNRegBankReassignPass
void initializeGCNRegBankReassignPass(PassRegistry &)
llvm::AMDGPUTargetMachine::getNullPointerValue
static int64_t getNullPointerValue(unsigned AddrSpace)
Get the integer value of a null pointer in the given address space.
Definition: AMDGPUTargetMachine.cpp:653
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1118
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:317
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::Triple::r600
@ r600
Definition: Triple.h:71
llvm::createUnifyLoopExitsPass
FunctionPass * createUnifyLoopExitsPass()
Definition: UnifyLoopExits.cpp:53
llvm::GCNIterativeScheduler
Definition: GCNIterativeScheduler.h:29
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: AMDGPUTargetMachine.cpp:269
llvm::SourceMgr::getMainFileID
unsigned getMainFileID() const
Definition: SourceMgr.h:129
AMDGPUTargetObjectFile.h
llvm::AMDGPULowerKernelAttributesPass
Definition: AMDGPU.h:130
GVN.h
llvm::createAMDGPUPropagateAttributesLatePass
ModulePass * createAMDGPUPropagateAttributesLatePass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:406
llvm::initializeSIMemoryLegalizerPass
void initializeSIMemoryLegalizerPass(PassRegistry &)
EnableDPPCombine
static cl::opt< bool > EnableDPPCombine("amdgpu-dpp-combine", cl::desc("Enable DPP combiner"), cl::init(true))
llvm::createAMDGPULowerIntrinsicsPass
ModulePass * createAMDGPULowerIntrinsicsPass()
Definition: AMDGPULowerIntrinsics.cpp:180
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
llvm::createAMDGPUAnnotateKernelFeaturesPass
Pass * createAMDGPUAnnotateKernelFeaturesPass()
Definition: AMDGPUAnnotateKernelFeatures.cpp:424
llvm::AMDGPUTargetMachine::~AMDGPUTargetMachine
~AMDGPUTargetMachine() override
llvm::AMDGPUTargetMachine::getSubtargetImpl
const TargetSubtargetInfo * getSubtargetImpl() const
llvm::createSinkingPass
FunctionPass * createSinkingPass()
Definition: Sink.cpp:284
llvm::AMDGPUAS::REGION_ADDRESS
@ REGION_ADDRESS
Address space for region memory. (GDS)
Definition: AMDGPU.h:374
llvm::createSpeculativeExecutionPass
FunctionPass * createSpeculativeExecutionPass()
Definition: SpeculativeExecution.cpp:325
Utils.h
llvm::SILoadStoreOptimizerID
char & SILoadStoreOptimizerID
Definition: SILoadStoreOptimizer.cpp:576
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:297
llvm::None
const NoneType None
Definition: None.h:23
llvm::Value::use_empty
bool use_empty() const
Definition: Value.h:357
llvm::createAMDGPUExportClusteringDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAMDGPUExportClusteringDAGMutation()
Definition: AMDGPUExportClustering.cpp:144
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1336
llvm::SmallString< 128 >
llvm::SourceMgr::getMemoryBuffer
const MemoryBuffer * getMemoryBuffer(unsigned i) const
Definition: SourceMgr.h:122
llvm::createFunctionInliningPass
Pass * createFunctionInliningPass()
createFunctionInliningPass - Return a new pass object that uses a heuristic to inline direct function...
Definition: InlineSimple.cpp:97
llvm::legacy::PassManagerBase::add
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
llvm::R600TTIImpl
Definition: AMDGPUTargetTransformInfo.h:223
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:378
llvm::MemoryBuffer::getBufferIdentifier
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
Definition: MemoryBuffer.h:75
llvm::createAMDGPUAAWrapperPass
ImmutablePass * createAMDGPUAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:32
llvm::PassManagerBuilder
PassManagerBuilder - This class is used to set up a standard optimization sequence for languages like...
Definition: PassManagerBuilder.h:59
llvm::createLowerSwitchPass
FunctionPass * createLowerSwitchPass()
Definition: LowerSwitch.cpp:582
llvm::createAMDGPUPrintfRuntimeBinding
ModulePass * createAMDGPUPrintfRuntimeBinding()
Definition: AMDGPUPrintfRuntimeBinding.cpp:92
AMDGPUTargetTransformInfo.h
llvm::Triple::AMDHSA
@ AMDHSA
Definition: Triple.h:190
llvm::createAMDGPUAlwaysInlinePass
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPUAlwaysInlinePass.cpp:158
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::SmallString::append
void append(StringRef RHS)
Append from a StringRef.
Definition: SmallString.h:67
llvm::initializeSILowerSGPRSpillsPass
void initializeSILowerSGPRSpillsPass(PassRegistry &)
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::PassBuilder::registerPipelineEarlySimplificationEPCallback
void registerPipelineEarlySimplificationEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:617
llvm::AMDGPUTargetMachine::getFeatureString
StringRef getFeatureString(const Function &F) const
Definition: AMDGPUTargetMachine.cpp:404
R600SchedRegistry
static MachineSchedRegistry R600SchedRegistry("r600", "Run R600's custom scheduler", createR600MachineScheduler)
llvm::cl::opt< bool >
llvm::createLCSSAPass
Pass * createLCSSAPass()
Definition: LCSSA.cpp:484
EnableR600StructurizeCFG
static cl::opt< bool > EnableR600StructurizeCFG("r600-ir-structurize", cl::desc("Use StructurizeCFG IR pass"), cl::init(true))
llvm::createModuleToFunctionPassAdaptor
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT Pass)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:1252
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
OptExecMaskPreRA
static cl::opt< bool > OptExecMaskPreRA("amdgpu-opt-exec-mask-pre-ra", cl::Hidden, cl::desc("Run pre-RA exec mask optimizations"), cl::init(true))
llvm::R600Subtarget
Definition: R600Subtarget.h:36
llvm::yaml::SIMachineFunctionInfo::ScratchRSrcReg
StringValue ScratchRSrcReg
Definition: SIMachineFunctionInfo.h:285
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::AMDGPUUnifyDivergentExitNodesID
char & AMDGPUUnifyDivergentExitNodesID
Definition: AMDGPUUnifyDivergentExitNodes.cpp:73
llvm::R600TargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: AMDGPUTargetMachine.cpp:1011
llvm::initializeSIInsertWaitcntsPass
void initializeSIInsertWaitcntsPass(PassRegistry &)
llvm::TargetMachine::setRequiresStructuredCFG
void setRequiresStructuredCFG(bool Value)
Definition: TargetMachine.h:214
llvm::initializeSIAnnotateControlFlowPass
void initializeSIAnnotateControlFlowPass(PassRegistry &)
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3445
llvm::AMDGPUFunctionArgInfo::WorkGroupIDZ
ArgDescriptor WorkGroupIDZ
Definition: AMDGPUArgumentUsageInfo.h:135
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:525
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::DetectDeadLanesID
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
Definition: DetectDeadLanes.cpp:128
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::TargetMachine::getMCSubtargetInfo
const MCSubtargetInfo * getMCSubtargetInfo() const
Definition: TargetMachine.h:206
llvm::AMDGPUFunctionArgInfo::PrivateSegmentBuffer
ArgDescriptor PrivateSegmentBuffer
Definition: AMDGPUArgumentUsageInfo.h:124
llvm::createAMDGPUAtomicOptimizerPass
FunctionPass * createAMDGPUAtomicOptimizerPass()
Definition: AMDGPUAtomicOptimizer.cpp:707
llvm::initializeR600VectorRegMergerPass
void initializeR600VectorRegMergerPass(PassRegistry &)
IPO.h
llvm::SIPeepholeSDWAID
char & SIPeepholeSDWAID
Definition: SIPeepholeSDWA.cpp:191
llvm::createGlobalDCEPass
ModulePass * createGlobalDCEPass()
createGlobalDCEPass - This transform is designed to eliminate unreachable internal globals (functions...
llvm::FinalizeMachineBundlesID
char & FinalizeMachineBundlesID
FinalizeMachineBundles - This pass finalize machine instruction bundles (created earlier,...
Definition: MachineInstrBundle.cpp:98
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::GCNTTIImpl
Definition: AMDGPUTargetTransformInfo.h:62
llvm::SIFixVGPRCopiesID
char & SIFixVGPRCopiesID
Definition: SIFixVGPRCopies.cpp:45
llvm::initializeAMDGPURewriteOutArgumentsPass
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
CGSCCPassManager.h
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:119
llvm::GCNIterativeScheduler::SCHEDULE_MINREGFORCED
@ SCHEDULE_MINREGFORCED
Definition: GCNIterativeScheduler.h:35
createR600MachineScheduler
static ScheduleDAGInstrs * createR600MachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:273
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::AMDGPUSimplifyLibCallsPass
Definition: AMDGPU.h:87
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:800
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
llvm::TargetPassConfig::addOptimizedRegAlloc
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: TargetPassConfig.cpp:1353
llvm::AMDGPUFunctionArgInfo::PrivateSegmentWaveByteOffset
ArgDescriptor PrivateSegmentWaveByteOffset
Definition: AMDGPUArgumentUsageInfo.h:137
llvm::SIFormMemoryClausesID
char & SIFormMemoryClausesID
Definition: SIFormMemoryClauses.cpp:92
LateCFGStructurize
static cl::opt< bool, true > LateCFGStructurize("amdgpu-late-structurize", cl::desc("Enable late CFG structurization"), cl::location(AMDGPUTargetMachine::EnableLateStructurizeCFG), cl::Hidden)
TargetPassConfig.h
llvm::createExternalAAWrapperPass
ImmutablePass * createExternalAAWrapperPass(std::function< void(Pass &, Function &, AAResults &)> Callback)
A wrapper pass around a callback which can be used to populate the AAResults in the AAResultsWrapperP...
llvm::SIFixSGPRCopiesID
char & SIFixSGPRCopiesID
Definition: SIFixSGPRCopies.cpp:121
llvm::AMDGPUFunctionArgInfo::WorkGroupIDY
ArgDescriptor WorkGroupIDY
Definition: AMDGPUArgumentUsageInfo.h:134
Localizer.h
llvm::MachineCSEID
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:153
llvm::GCNDPPCombineID
char & GCNDPPCombineID
Definition: GCNDPPCombine.cpp:111
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:924
llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:894
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::SIInsertHardClausesID
char & SIInsertHardClausesID
Definition: SIInsertHardClauses.cpp:201
GCNMinRegSchedRegistry
static MachineSchedRegistry GCNMinRegSchedRegistry("gcn-minreg", "Run GCN iterative scheduler for minimal register usage (experimental)", createMinRegScheduler)
llvm::AMDGPU::isFlatGlobalAddrSpace
bool isFlatGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:420
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
Definition: AMDGPUBaseInfo.h:903
llvm::getTheGCNTarget
Target & getTheGCNTarget()
The target for GCN GPUs.
Definition: AMDGPUTargetInfo.cpp:25
llvm::initializeSIOptimizeExecMaskingPass
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
llvm::initializeSIPostRABundlerPass
void initializeSIPostRABundlerPass(PassRegistry &)
llvm::SIScheduleDAGMI
Definition: SIMachineScheduler.h:426
llvm::PassBuilder::registerPipelineParsingCallback
void registerPipelineParsingCallback(const std::function< bool(StringRef Name, CGSCCPassManager &, ArrayRef< PipelineElement >)> &C)
{{@ Register pipeline parsing callbacks with this pass builder instance.
Definition: PassBuilder.h:663
llvm::initializeAMDGPUAAWrapperPassPass
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
llvm::initializeAMDGPUCodeGenPreparePass
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
llvm::createAMDGPUOpenCLEnqueuedBlockLoweringPass
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
llvm::initializeGCNNSAReassignPass
void initializeGCNNSAReassignPass(PassRegistry &)
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::yaml::StringValue
A wrapper around std::string which contains a source range that's being set during parsing.
Definition: MIRYamlMapping.h:34
llvm::GlobalDCEPass
Pass to remove unused function declarations.
Definition: GlobalDCE.h:29
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:649
IterativeGCNMaxOccupancySchedRegistry
static MachineSchedRegistry IterativeGCNMaxOccupancySchedRegistry("gcn-max-occupancy-experimental", "Run GCN scheduler to maximize occupancy (experimental)", createIterativeGCNMaxOccupancyMachineScheduler)
AMDGPUExportClustering.h
llvm::AMDGPUFunctionArgInfo::WorkItemIDZ
ArgDescriptor WorkItemIDZ
Definition: AMDGPUArgumentUsageInfo.h:150
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::createSIShrinkInstructionsPass
FunctionPass * createSIShrinkInstructionsPass()
llvm::createAMDGPUMachineCFGStructurizerPass
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
Definition: AMDGPUMachineCFGStructurizer.cpp:2886
llvm::GCNTargetMachine
Definition: AMDGPUTargetMachine.h:95
EnableAMDGPUFunctionCallsOpt
static cl::opt< bool, true > EnableAMDGPUFunctionCallsOpt("amdgpu-function-calls", cl::desc("Enable AMDGPU function call support"), cl::location(AMDGPUTargetMachine::EnableFunctionCalls), cl::init(true), cl::Hidden)
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:467
llvm::ScheduleDAG::TRI
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:559
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::initializeSIFormMemoryClausesPass
void initializeSIFormMemoryClausesPass(PassRegistry &)
computeDataLayout
static StringRef computeDataLayout(const Triple &TT)
Definition: AMDGPUTargetMachine.cpp:341
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::initializeAMDGPUExternalAAWrapperPass
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
AMDGPU.h
llvm::GCNTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: AMDGPUTargetMachine.cpp:725
llvm::yaml::SIMachineFunctionInfo::StackPtrOffsetReg
StringValue StackPtrOffsetReg
Definition: SIMachineFunctionInfo.h:287
SimplifyLibCalls.h
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
GlobalDCE.h
llvm::yaml::SIMachineFunctionInfo::Mode
SIMode Mode
Definition: SIMachineFunctionInfo.h:290
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:73
llvm::createAMDGPURegBankCombiner
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
Definition: AMDGPURegBankCombiner.cpp:149
llvm::SIMachineFunctionInfo::initializeBaseYamlFields
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI)
Definition: SIMachineFunctionInfo.cpp:570
IRTranslator.h
llvm::TargetMachine::getTargetFeatureString
StringRef getTargetFeatureString() const
Definition: TargetMachine.h:125
EarlyInlineAll
static cl::opt< bool > EarlyInlineAll("amdgpu-early-inline-all", cl::desc("Inline all functions early"), cl::init(false), cl::Hidden)
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::AMDGPUFunctionArgInfo::ImplicitBufferPtr
ArgDescriptor ImplicitBufferPtr
Definition: AMDGPUArgumentUsageInfo.h:144
llvm::SIWholeQuadModeID
char & SIWholeQuadModeID
Definition: SIWholeQuadMode.cpp:265
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:39
EnableSROA
static cl::opt< bool > EnableSROA("amdgpu-sroa", cl::desc("Run SROA after promote alloca pass"), cl::ReallyHidden, cl::init(true))
llvm::initializeAMDGPULowerKernelAttributesPass
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:474
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
llvm::initializeAMDGPUAnnotateUniformValuesPass
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
llvm::AMDGPUPrintfRuntimeBindingPass
Definition: AMDGPU.h:285
llvm::createLoadStoreVectorizerPass
Pass * createLoadStoreVectorizerPass()
Create a legacy pass manager instance of the LoadStoreVectorizer pass.
Definition: LoadStoreVectorizer.cpp:229
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::createStructurizeCFGPass
Pass * createStructurizeCFGPass(bool SkipUniformRegions=false)
When SkipUniformRegions is true the structizer will not structurize regions that only contain uniform...
Definition: StructurizeCFG.cpp:1086
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: AMDGPUBaseInfo.h:904
llvm::GCNTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: AMDGPUTargetMachine.cpp:1222
llvm::PassManager< Module >
llvm::createAMDGPULowerKernelAttributesPass
ModulePass * createAMDGPULowerKernelAttributesPass()
Definition: AMDGPULowerKernelAttributes.cpp:258
llvm::initializeSIFixSGPRCopiesPass
void initializeSIFixSGPRCopiesPass(PassRegistry &)
llvm::PerFunctionMIParsingState
Definition: MIParser.h:160
llvm::AMDGPUFunctionArgInfo::WorkGroupInfo
ArgDescriptor WorkGroupInfo
Definition: AMDGPUArgumentUsageInfo.h:136
llvm::createAMDGPUPromoteAllocaToVector
FunctionPass * createAMDGPUPromoteAllocaToVector()
Definition: AMDGPUPromoteAlloca.cpp:1144
llvm::R600TargetMachine::R600TargetMachine
R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AMDGPUTargetMachine.cpp:618
llvm::createR600VectorRegMerger
FunctionPass * createR600VectorRegMerger()
Definition: R600OptimizeVectorRegisters.cpp:385
llvm::initializeAMDGPULowerModuleLDSPass
void initializeAMDGPULowerModuleLDSPass(PassRegistry &)
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:205
createIterativeILPMachineScheduler
static ScheduleDAGInstrs * createIterativeILPMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:305
llvm::parseNamedRegisterReference
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
Definition: MIParser.cpp:3238
EnableEarlyIfConversion
static cl::opt< bool > EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(false))
llvm::initializeSIFixVGPRCopiesPass
void initializeSIFixVGPRCopiesPass(PassRegistry &)
llvm::yaml::SIMode::DX10Clamp
bool DX10Clamp
Definition: SIMachineFunctionInfo.h:231
llvm::initializeAMDGPUPromoteAllocaToVectorPass
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)
EnableScalarIRPasses
static cl::opt< bool > EnableScalarIRPasses("amdgpu-scalar-ir-passes", cl::desc("Enable scalar IR passes"), cl::init(true), cl::Hidden)
EnableR600IfConvert
static cl::opt< bool > EnableR600IfConvert("r600-if-convert", cl::desc("Use if conversion pass"), cl::ReallyHidden, cl::init(true))
llvm::initializeSIPreEmitPeepholePass
void initializeSIPreEmitPeepholePass(PassRegistry &)
createIterativeGCNMaxOccupancyMachineScheduler
static ScheduleDAGInstrs * createIterativeGCNMaxOccupancyMachineScheduler(MachineSchedContext *C)
Definition: AMDGPUTargetMachine.cpp:292
llvm::PassBuilder::OptimizationLevel
LLVM-provided high-level optimization levels.
Definition: PassBuilder.h:164
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::createR600ControlFlowFinalizer
FunctionPass * createR600ControlFlowFinalizer()
Definition: R600ControlFlowFinalizer.cpp:689
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1211
llvm::createAMDGPUPropagateAttributesEarlyPass
FunctionPass * createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:401
llvm::AMDGPUPropagateAttributesEarlyPass
Definition: AMDGPU.h:138
llvm::initializeSIModeRegisterPass
void initializeSIModeRegisterPass(PassRegistry &)
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:377
llvm::createLoadClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1573
RegBankSelect.h
llvm::ScheduleDAG::TII
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
GCNMaxOccupancySchedRegistry
static MachineSchedRegistry GCNMaxOccupancySchedRegistry("gcn-max-occupancy", "Run GCN scheduler to maximize occupancy", createGCNMaxOccupancyMachineScheduler)
llvm::createAMDGPULowerKernelArgumentsPass
FunctionPass * createAMDGPULowerKernelArgumentsPass()
Definition: AMDGPULowerKernelArguments.cpp:248
llvm::AMDGPUTargetMachine::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: AMDGPUTargetMachine.cpp:661
llvm::PassManagerBuilder::EP_ModuleOptimizerEarly
@ EP_ModuleOptimizerEarly
EP_ModuleOptimizerEarly - This extension point allows adding passes just before the main module-level...
Definition: PassManagerBuilder.h:76
llvm::createSIModeRegisterPass
FunctionPass * createSIModeRegisterPass()
Definition: SIModeRegister.cpp:157
llvm::ArgDescriptor::createRegister
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Definition: AMDGPUArgumentUsageInfo.h:44
PassManager.h
llvm::createInternalizePass
ModulePass * createInternalizePass(std::function< bool(const GlobalValue &)> MustPreserveGV)
createInternalizePass - This pass loops over all of the functions in the input module,...
Definition: Internalize.cpp:288
llvm::SourceMgr::DK_Error
@ DK_Error
Definition: SourceMgr.h:34
llvm::AMDGPUTargetMachine::adjustPassManager
void adjustPassManager(PassManagerBuilder &) override
Allow the target to modify the pass manager, e.g.
Definition: AMDGPUTargetMachine.cpp:419
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:386
llvm::DeadMachineInstructionElimID
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Definition: DeadMachineInstructionElim.cpp:57
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:162
GCNILPSchedRegistry
static MachineSchedRegistry GCNILPSchedRegistry("gcn-ilp", "Run GCN iterative scheduler for ILP scheduling (experimental)", createIterativeILPMachineScheduler)
llvm::AnalysisManager::registerPass
bool registerPass(PassBuilderT &&PassBuilder)
Register an analysis pass with the manager.
Definition: PassManager.h:847
llvm::AMDGPUFunctionArgInfo::KernargSegmentPtr
ArgDescriptor KernargSegmentPtr
Definition: AMDGPUArgumentUsageInfo.h:127
llvm::createAMDGPUPromoteAlloca
FunctionPass * createAMDGPUPromoteAlloca()
Definition: AMDGPUPromoteAlloca.cpp:1140
llvm::initializeAMDGPUPrintfRuntimeBindingPass
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
llvm::AAManager::registerFunctionAnalysis
void registerFunctionAnalysis()
Register a specific AA result.
Definition: AliasAnalysis.h:1226
llvm::BranchRelaxationPassID
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Definition: BranchRelaxation.cpp:119
llvm::initializeAMDGPUPreLegalizerCombinerPass
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)
llvm::createAMDGPUCodeGenPreparePass
FunctionPass * createAMDGPUCodeGenPreparePass()
Definition: AMDGPUCodeGenPrepare.cpp:1418
llvm::MachineSchedulerID
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
Definition: MachineScheduler.cpp:210
llvm::AMDGPUTargetMachine::EnableFunctionCalls
static bool EnableFunctionCalls
Definition: AMDGPUTargetMachine.h:36
Legalizer.h
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::createLICMPass
Pass * createLICMPass()
Definition: LICM.cpp:310
llvm::createAMDGPUFixFunctionBitcastsPass
ModulePass * createAMDGPUFixFunctionBitcastsPass()
llvm::GCNNSAReassignID
char & GCNNSAReassignID
Definition: GCNNSAReassign.cpp:104
llvm::TargetMachine::getTargetCPU
StringRef getTargetCPU() const
Definition: TargetMachine.h:124
llvm::PassManagerBuilder::EP_EarlyAsPossible
@ EP_EarlyAsPossible
EP_EarlyAsPossible - This extension point allows adding passes before any other transformations,...
Definition: PassManagerBuilder.h:72
llvm::initializeAMDGPUAnnotateKernelFeaturesPass
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
llvm::AMDGPUFunctionArgInfo::WorkItemIDY
ArgDescriptor WorkItemIDY
Definition: AMDGPUArgumentUsageInfo.h:149
llvm::createAMDGPUPreLegalizeCombiner
FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPreLegalizerCombiner.cpp:296
llvm::AMDGPUTargetMachine::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const override
If the specified generic pointer could be assumed as a pointer to a specific address space,...
Definition: AMDGPUTargetMachine.cpp:667
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::createStraightLineStrengthReducePass
FunctionPass * createStraightLineStrengthReducePass()
Definition: StraightLineStrengthReduce.cpp:269
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:331
llvm::initializeAMDGPUFixFunctionBitcastsPass
void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &)
llvm::initializeSILoadStoreOptimizerPass
void initializeSILoadStoreOptimizerPass(PassRegistry &)
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::IRTranslator
Definition: IRTranslator.h:62
llvm::PassBuilder::registerCGSCCOptimizerLateEPCallback
void registerCGSCCOptimizerLateEPCallback(const std::function< void(CGSCCPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:587
llvm::initializeAMDGPURegBankCombinerPass
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
RegName
#define RegName(no)
llvm::createSIAnnotateControlFlowPass
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
Definition: SIAnnotateControlFlow.cpp:374
Vectorize.h
llvm::yaml::SIMode::IEEE
bool IEEE
Definition: SIMachineFunctionInfo.h:230
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:43
llvm::SIFoldOperandsID
char & SIFoldOperandsID
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::AMDGPUAS::FLAT_ADDRESS
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:372
llvm::EarlyMachineLICMID
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
Definition: MachineLICM.cpp:295
llvm::AMDGPUTargetMachine::getGPUName
StringRef getGPUName(const Function &F) const
Definition: AMDGPUTargetMachine.cpp:399
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:376
llvm::cl::desc
Definition: CommandLine.h:411
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:384
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::PassManagerBuilder::EP_CGSCCOptimizerLate
@ EP_CGSCCOptimizerLate
EP_CGSCCOptimizerLate - This extension point allows adding CallGraphSCC passes at the end of the main...
Definition: PassManagerBuilder.h:117
llvm::createAMDGPUCFGStructurizerPass
FunctionPass * createAMDGPUCFGStructurizerPass()
Definition: AMDILCFGStructurizer.cpp:1654
llvm::createR600ISelDag
FunctionPass * createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a R600-specific.
Definition: AMDGPUISelDAGToDAG.cpp:387
llvm::IfConverterID
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
Definition: IfConversion.cpp:436
llvm::AMDGPUTargetMachine::AMDGPUTargetMachine
AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, TargetOptions Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL)
Definition: AMDGPUTargetMachine.cpp:374
llvm::TargetPassConfig::addFastRegAlloc
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
Definition: TargetPassConfig.cpp:1343
llvm::AMDGPUPerfHintAnalysisID
char & AMDGPUPerfHintAnalysisID
Definition: AMDGPUPerfHintAnalysis.cpp:57
TargetRegistry.h
llvm::createSROAPass
FunctionPass * createSROAPass()
Definition: SROA.cpp:4829
llvm::AMDGPUPropagateAttributesLatePass
Definition: AMDGPU.h:150
EnableLibCallSimplify
static cl::opt< bool > EnableLibCallSimplify("amdgpu-simplify-libcall", cl::desc("Enable amdgpu library simplifications"), cl::init(true), cl::Hidden)
InitializePasses.h
llvm::yaml::SIMode::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: SIMachineFunctionInfo.h:235
llvm::SIOptimizeExecMaskingPreRAID
char & SIOptimizeExecMaskingPreRAID
Definition: SIOptimizeExecMaskingPreRA.cpp:75
llvm::createGCNMCRegisterInfo
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)
Definition: AMDGPUMCTargetDesc.cpp:68
llvm::TargetMachine::MRI
std::unique_ptr< const MCRegisterInfo > MRI
Definition: TargetMachine.h:106
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
EnableAMDGPUFixedFunctionABIOpt
static cl::opt< bool, true > EnableAMDGPUFixedFunctionABIOpt("amdgpu-fixed-function-abi", cl::desc("Enable all implicit function arguments"), cl::location(AMDGPUTargetMachine::EnableFixedFunctionABI), cl::init(false), cl::Hidden)
llvm::createGCNRegBankReassignPass
MachineFunctionPass * createGCNRegBankReassignPass(AMDGPU::RegBankReassignMode Mode)
Definition: GCNRegBankReassign.cpp:898
llvm::AMDGPUTargetMachine::EnableLateStructurizeCFG
static bool EnableLateStructurizeCFG
Definition: AMDGPUTargetMachine.h:35
llvm::AMDGPUTargetMachine::registerPassBuilderCallbacks
void registerPassBuilderCallbacks(PassBuilder &PB, bool DebugPassManager) override
Allow the target to modify the pass pipeline with New Pass Manager (similar to adjustPassManager for ...
Definition: AMDGPUTargetMachine.cpp:488
llvm::TargetPassConfig::addILPOpts
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
Definition: TargetPassConfig.h:373
AMDGPUTargetMachine.h
llvm::GCNTargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: AMDGPUTargetMachine.cpp:1226
PassBuilder.h
llvm::PassManager::addPass
std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT Pass)
Definition: PassManager.h:553
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:666
llvm::initializeSILowerControlFlowPass
void initializeSILowerControlFlowPass(PassRegistry &)
llvm::SILateBranchLoweringPassID
char & SILateBranchLoweringPassID
Definition: SILateBranchLowering.cpp:66
llvm::createAMDGPUSimplifyLibCallsPass
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetMachine *)
Definition: AMDGPULibCalls.cpp:1698
MIParser.h
llvm::Localizer
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:40
llvm::createAMDGPUMacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAMDGPUMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAMDGPUMacroFusionDAGMutation()); to AMDGPUPassConfig...
Definition: AMDGPUMacroFusion.cpp:62