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42 #define DEBUG_TYPE "rename-independent-subregs"
52 return "Rename Disconnected Subregister Components";
94 void computeMainRangesFixFlags(
const IntEqClasses &Classes,
116 "Rename Independent Subregisters",
false,
false)
122 bool RenameIndependentSubregs::renameComponents(
LiveInterval &LI)
const {
124 if (LI.valnos.size() < 2)
129 if (!findComponents(Classes, SubRangeInfos, LI))
133 unsigned Reg = LI.reg();
136 Intervals.push_back(&LI);
138 <<
" equivalence classes.\n");
140 for (
unsigned I = 1, NumClasses = Classes.
getNumClasses();
I < NumClasses;
143 LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg);
144 Intervals.push_back(&NewLI);
149 rewriteOperands(Classes, SubRangeInfos, Intervals);
150 distribute(Classes, SubRangeInfos, Intervals);
151 computeMainRangesFixFlags(Classes, SubRangeInfos, Intervals);
155 bool RenameIndependentSubregs::findComponents(
IntEqClasses &Classes,
160 unsigned NumComponents = 0;
162 SubRangeInfos.push_back(SubRangeInfo(*LIS, SR, NumComponents));
165 unsigned NumSubComponents = ConEQ.
Classify(SR);
166 NumComponents += NumSubComponents;
171 if (SubRangeInfos.size() < 2)
177 Classes.
grow(NumComponents);
180 if (!MO.isDef() && !MO.readsReg())
182 unsigned SubRegIdx = MO.getSubReg();
184 unsigned MergedID = ~0u;
185 for (RenameIndependentSubregs::SubRangeInfo &SRInfo : SubRangeInfos) {
187 if ((SR.
LaneMask & LaneMask).none())
189 SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent());
190 Pos = MO.isDef() ? Pos.
getRegSlot(MO.isEarlyClobber())
197 unsigned LocalID = SRInfo.ConEQ.getEqClass(VNI);
199 unsigned ID = LocalID + SRInfo.Index;
201 MergedID = MergedID == ~0u ?
ID : Classes.
join(MergedID,
ID);
208 return NumClasses > 1;
211 void RenameIndependentSubregs::rewriteOperands(
const IntEqClasses &Classes,
215 unsigned Reg = Intervals[0]->reg();
230 for (
const SubRangeInfo &SRInfo : SubRangeInfos) {
232 if ((SR.
LaneMask & LaneMask).none())
239 unsigned LocalID = SRInfo.ConEQ.getEqClass(VNI);
241 ID = Classes[LocalID + SRInfo.Index];
245 unsigned VReg = Intervals[
ID]->reg();
252 unsigned OperandNo =
MI->getOperandNo(&MO);
253 unsigned TiedIdx =
MI->findTiedOperandIdx(OperandNo);
254 MI->getOperand(TiedIdx).setReg(VReg);
272 for (
const SubRangeInfo &SRInfo : SubRangeInfos) {
274 unsigned NumValNos = SR.
valnos.size();
278 SubRanges.
resize(NumClasses-1,
nullptr);
279 for (
unsigned I = 0;
I < NumValNos; ++
I) {
281 unsigned LocalID = SRInfo.ConEQ.getEqClass(&VNI);
282 unsigned ID = Classes[LocalID + SRInfo.Index];
283 VNIMapping.push_back(
ID);
284 if (
ID > 0 && SubRanges[
ID-1] ==
nullptr)
299 void RenameIndependentSubregs::computeMainRangesFixFlags(
304 const SlotIndexes &Indexes = *LIS->getSlotIndexes();
305 for (
size_t I = 0,
E = Intervals.size();
I <
E; ++
I) {
318 for (
unsigned I = 0;
I < SR.
valnos.size(); ++
I) {
335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef);
368 LIS->constructMainRangeFromSubranges(LI);
373 LIS->shrinkToUses(&LI);
377 bool RenameIndependentSubregs::runOnMachineFunction(
MachineFunction &MF) {
383 LLVM_DEBUG(
dbgs() <<
"Renaming independent subregister live ranges in "
386 LIS = &getAnalysis<LiveIntervals>();
392 bool Changed =
false;
395 if (!LIS->hasInterval(
Reg))
401 Changed |= renameComponents(LI);
Rename Independent Subregisters
This is an optimization pass for GlobalISel generic memory operations.
bool subRegLivenessEnabled() const
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual const TargetInstrInfo * getInstrInfo() const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Reg
All possible values of the reg field in the ModR/M byte.
const TargetRegisterInfo * getTargetRegisterInfo() const
This represents a simple continuous liveness interval for a value.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
IdxPair distribute(unsigned Nodes, unsigned Elements, unsigned Capacity, const unsigned *CurSize, unsigned NewSize[], unsigned Position, bool Grow)
IntervalMapImpl::distribute - Compute a new distribution of node elements after an overflow or underf...
SlotIndex def
The index of the defining instruction.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
unsigned const TargetRegisterInfo * TRI
unsigned join(unsigned a, unsigned b)
Join the equivalence classes of a and b.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static void DistributeRange(LiveRangeT &LR, LiveRangeT *SplitLRs[], EqClassesT VNIClasses)
Helper function that distributes live range value numbers and the corresponding segments of a primary...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
bool liveAt(SlotIndex index) const
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
Represent the analysis usage information of a pass.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
LiveInterval - This class represents the liveness of a register, or stack slot.
SlotIndex - An opaque wrapper around machine indexes.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static reg_nodbg_iterator reg_nodbg_end()
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
void setIsDead(bool Val=true)
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
Allocate memory in an ever growing pool, as if by bump-pointer.
void compress()
compress - Compress equivalence classes by numbering them 0 .
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
unsigned Classify(const LiveRange &LR)
Classify the values in LR into connected components.
bool isEarlyClobber() const
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
iterator_range< pred_iterator > predecessors()
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
StringRef - Represent a constant reference to a string, i.e.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setIsUndef(bool Val=true)
INITIALIZE_PASS_BEGIN(RenameIndependentSubregs, DEBUG_TYPE, "Rename Independent Subregisters", false, false) INITIALIZE_PASS_END(RenameIndependentSubregs
MachineBasicBlock::iterator findPHICopyInsertPoint(MachineBasicBlock *MBB, MachineBasicBlock *SuccMBB, unsigned SrcReg)
findPHICopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg when following the CFG...
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
A live range for subregisters.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
void grow(unsigned N)
grow - Increase capacity to hold 0 .
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
VNInfo - Value Number Information.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
static bool subRangeLiveAt(const LiveInterval &LI, SlotIndex Pos)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void setReg(Register Reg)
Change the register this operand corresponds to.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
unsigned getNumClasses() const
getNumClasses - Return the number of equivalence classes after compress() was called.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isUnused() const
Returns true if this value is unused.
AnalysisUsage & addRequired()
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void reserve(size_type N)
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
iterator_range< subrange_iterator > subranges()