224#ifndef LLVM_CODEGEN_RDFGRAPH_H
225#define LLVM_CODEGEN_RDFGRAPH_H
239#include <unordered_map>
246static_assert(
sizeof(
uint32_t) ==
sizeof(
unsigned),
"Those should be equal");
327 return KB ==
Phi || KB ==
Stmt;
350 template <
typename S>
416 : NodesPerBlock(NPB), BitsPerIndex(
Log2_32(NPB)),
417 IndexMask((1 << BitsPerIndex) - 1) {
423 uint32_t BlockN = N1 >> BitsPerIndex;
433 void startNewBlock();
438 return ((
Block << BitsPerIndex) | Index) + 1;
444 char *ActiveEnd =
nullptr;
445 std::vector<char *> Blocks;
483 return LM.
all() ? 0 :
find(LM);
505 void init() { memset(
this, 0,
sizeof *
this); }
548 "NodeBase must be at most NodeAllocator::NodeMemSize bytes");
582 template <
typename Predicate>
625 template <
typename Predicate>
675 :
TrackRegs(Track.begin(), Track.end()) {}
684 return static_cast<T>(
ptr(
N));
708 using value_type =
Def;
710 using value_type = DefStack::value_type;
713 Pos = DS.nextUp(Pos);
717 Pos = DS.nextDown(Pos);
723 return DS.Stack[Pos - 1];
725 const value_type *operator->()
const {
727 return &DS.Stack[Pos - 1];
729 bool operator==(
const Iterator &It)
const {
return Pos == It.Pos; }
730 bool operator!=(
const Iterator &It)
const {
return Pos != It.Pos; }
733 friend struct DefStack;
735 Iterator(
const DefStack &S,
bool Top);
748 unsigned size()
const;
756 friend struct Iterator;
758 using StorageType = std::vector<value_type>;
760 bool isDelimiter(
const StorageType::value_type &
P,
NodeId N = 0)
const {
761 return (
P.Addr ==
nullptr) && (
N == 0 ||
P.Id ==
N);
764 unsigned nextUp(
unsigned P)
const;
765 unsigned nextDown(
unsigned P)
const;
782 return {RR.
Reg, LMI.getIndexForLaneMask(RR.
Mask)};
785 return {RR.
Reg, LMI.getIndexForLaneMask(RR.
Mask)};
817 template <u
int16_t Kind>
static bool IsRef(
const Node BA) {
841 uint16_t Flags = DA.Addr->getFlags();
862 template <
typename Predicate>
868 void recordDefsForDF(BlockRefsMap &PhiM, BlockRefsMap &PhiClobberM,
Block BA);
869 void buildPhis(BlockRefsMap &PhiM,
Block BA,
871 void removeUnusedPhis();
875 template <
typename T>
void linkRefUp(
Instr IA,
NodeAddr<T> TA, DefStack &DS);
876 template <
typename Predicate>
880 void unlinkUseDF(
Use UA);
881 void unlinkDefDF(
Def DA);
883 void removeFromOwner(
Ref RA) {
884 Instr IA =
RA.Addr->getOwner(*
this);
885 IA.Addr->removeMember(
RA, *
this);
889 std::unique_ptr<TargetOperandInfo> DefaultTOI;
894 const PhysicalRegisterInfo PRI;
897 const TargetOperandInfo &TOI;
899 RegisterAggr LiveIns;
903 std::map<MachineBasicBlock *, Block> BlockNodes;
908 std::set<unsigned> TrackedUnits;
912template <
typename Predicate>
919 while (NA.Addr !=
this) {
922 if (
G.getPRI().equal_to(
RA.Addr->getRegRef(
G), RR) &&
P(NA))
926 NA =
G.addr<
NodeBase *>(NA.Addr->getNext());
946template <
typename Predicate>
953 while (M.Addr !=
this) {
956 M =
G.addr<
NodeBase *>(M.Addr->getNext());
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file defines the BumpPtrAllocator interface.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static RegisterPass< DebugifyModulePass > DM("debugify", "Attach debug info to everything")
const HexagonInstrInfo * TII
A common definition of LaneBitmask for use in TableGen and CodeGen.
Register const TargetRegisterInfo * TRI
SI optimize exec mask operations pre RA
This file defines the SmallVector class.
INLINE void g(uint32_t *state, size_t a, size_t b, size_t c, size_t d, uint32_t x, uint32_t y)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Allocate memory in an ever growing pool, as if by bump-pointer.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
This class provides various memory handling functions that manipulate MemoryBlock instances.
@ C
The default llvm calling convention, compatible with C.
NodeAddr< DefNode * > Def
NodeAddr< InstrNode * > Instr
NodeAddr< BlockNode * > Block
std::set< RegisterRef > RegisterSet
NodeAddr< PhiNode * > Phi
Print(const T &, const DataFlowGraph &) -> Print< T >
NodeAddr< PhiUseNode * > PhiUse
NodeAddr< StmtNode * > Stmt
NodeAddr< UseNode * > Use
NodeAddr< NodeBase * > Node
raw_ostream & operator<<(raw_ostream &OS, const Print< RegisterRef > &P)
std::set< NodeId > NodeSet
SmallVector< Node, 4 > NodeList
NodeAddr< CodeNode * > Code
NodeAddr< FuncNode * > Func
NodeAddr< RefNode * > Ref
This is an optimization pass for GlobalISel generic memory operations.
APInt operator*(APInt a, uint64_t RHS)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
@ Sub
Subtraction of integers.
DWARFExpression::Operation Op
static constexpr LaneBitmask getAll()
constexpr bool any() const
constexpr bool all() const
MachineBasicBlock * getCode() const
void addPhi(Phi PA, const DataFlowGraph &G)
NodeList members_if(Predicate P, const DataFlowGraph &G) const
void removeMember(Node NA, const DataFlowGraph &G)
NodeList members(const DataFlowGraph &G) const
void addMember(Node NA, const DataFlowGraph &G)
Node getFirstMember(const DataFlowGraph &G) const
void addMemberAfter(Node MA, Node NA, const DataFlowGraph &G)
Node getLastMember(const DataFlowGraph &G) const
Config(ArrayRef< const TargetRegisterClass * > RCs)
SmallVector< const TargetRegisterClass * > Classes
std::set< RegisterId > TrackRegs
Config(ArrayRef< RegisterId > Track)
Config(ArrayRef< MCPhysReg > Track)
void clear_block(NodeId N)
void start_block(NodeId N)
NodeId id(const NodeBase *P) const
void unlinkUse(Use UA, bool RemoveFromOwner)
const RegisterAggr & getLiveIns() const
void releaseBlock(NodeId B, DefStackMap &DefM)
PackedRegisterRef pack(RegisterRef RR)
Ref getNextRelated(Instr IA, Ref RA) const
bool isTracked(RegisterRef RR) const
RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const
RegisterRef unpack(PackedRegisterRef PR) const
static bool IsDef(const Node BA)
DataFlowGraph(MachineFunction &mf, const TargetInstrInfo &tii, const TargetRegisterInfo &tri, const MachineDominatorTree &mdt, const MachineDominanceFrontier &mdf)
Ref getNextShadow(Instr IA, Ref RA, bool Create)
static bool IsPhi(const Node BA)
const MachineDominanceFrontier & getDF() const
static bool IsPreservingDef(const Def DA)
const MachineDominatorTree & getDT() const
NodeList getRelatedRefs(Instr IA, Ref RA) const
void unlinkDef(Def DA, bool RemoveFromOwner)
MachineFunction & getMF() const
const TargetInstrInfo & getTII() const
static bool IsRef(const Node BA)
PackedRegisterRef pack(RegisterRef RR) const
static bool IsUse(const Node BA)
const PhysicalRegisterInfo & getPRI() const
static bool IsCode(const Node BA)
void markBlock(NodeId B, DefStackMap &DefM)
NodeBase * ptr(NodeId N) const
Block findBlock(MachineBasicBlock *BB) const
bool hasUntrackedRef(Stmt S, bool IgnoreReserved=true) const
std::unordered_map< RegisterId, DefStack > DefStackMap
const TargetRegisterInfo & getTRI() const
void pushAllDefs(Instr IA, DefStackMap &DM)
NodeAddr< T > addr(NodeId N) const
NodeId getReachedUse() const
void setReachedUse(NodeId U)
void setReachedDef(NodeId D)
NodeId getReachedDef() const
void linkToDef(NodeId Self, Def DA)
MachineFunction * getCode() const
Block findBlock(const MachineBasicBlock *BB, const DataFlowGraph &G) const
Block getEntryBlock(const DataFlowGraph &G)
LaneBitmask get(uint32_t Idx) const
uint32_t insert(LaneBitmask Val)
uint32_t find(LaneBitmask Val) const
Node getOwner(const DataFlowGraph &G)
uint32_t getIndexForLaneMask(LaneBitmask LM) const
LaneBitmask getLaneMaskForIndex(uint32_t K) const
uint32_t getIndexForLaneMask(LaneBitmask LM)
NodeAddr(const NodeAddr< S > &NA)
bool operator==(const NodeAddr< T > &NA) const
bool operator!=(const NodeAddr< T > &NA) const
NodeBase * ptr(NodeId N) const
NodeId id(const NodeBase *P) const
NodeAllocator(uint32_t NPB=4096)
static uint16_t set_kind(uint16_t A, uint16_t K)
static uint16_t flags(uint16_t T)
static uint16_t kind(uint16_t T)
static uint16_t set_type(uint16_t A, uint16_t T)
static bool contains(uint16_t A, uint16_t B)
static uint16_t set_flags(uint16_t A, uint16_t F)
static uint16_t type(uint16_t T)
void setFlags(uint16_t F)
uint16_t getAttrs() const
void setAttrs(uint16_t A)
uint16_t getFlags() const
MachineInstr * getCode() const
NodeId getPredecessor() const
void setPredecessor(NodeId B)
PrintNode(const NodeAddr< T > &x, const DataFlowGraph &g)
Print(const T &x, const DataFlowGraph &g)
NodeId getReachingDef() const
NodeId getSibling() const
Ref getNextRef(RegisterRef RR, Predicate P, bool NextOnly, const DataFlowGraph &G)
void setRegRef(RegisterRef RR, DataFlowGraph &G)
RegisterRef getRegRef(const DataFlowGraph &G) const
void setSibling(NodeId Sib)
void setReachingDef(NodeId RD)
Node getOwner(const DataFlowGraph &G)
MachineInstr * getCode() const
virtual bool isFixedReg(const MachineInstr &In, unsigned OpNum) const
const TargetInstrInfo & TII
virtual ~TargetOperandInfo()=default
virtual bool isPreserving(const MachineInstr &In, unsigned OpNum) const
virtual bool isClobbering(const MachineInstr &In, unsigned OpNum) const
TargetOperandInfo(const TargetInstrInfo &tii)
void linkToDef(NodeId Self, Def DA)