224#ifndef LLVM_CODEGEN_RDFGRAPH_H
225#define LLVM_CODEGEN_RDFGRAPH_H
238#include <unordered_map>
245static_assert(
sizeof(
uint32_t) ==
sizeof(
unsigned),
"Those should be equal");
249class MachineBasicBlock;
250class MachineDominanceFrontier;
251class MachineDominatorTree;
252class MachineFunction;
256class TargetInstrInfo;
257class TargetRegisterInfo;
319 return KB ==
Phi || KB ==
Stmt;
379 : NodesPerBlock(NPB), BitsPerIndex(
Log2_32(NPB)),
380 IndexMask((1 << BitsPerIndex)-1) {
386 uint32_t BlockN = N1 >> BitsPerIndex;
396 void startNewBlock();
407 char *ActiveEnd =
nullptr;
408 std::vector<char*> Blocks;
446 return LM.
all() ? 0 :
find(LM);
468 void init() { memset(
this, 0,
sizeof *
this); }
511 "NodeBase must be at most NodeAllocator::NodeMemSize bytes");
553 template <
typename Predicate>
593 return static_cast<T>(
Code.
CP);
607 template <
typename Predicate>
623 return CodeNode::getCode<MachineInstr*>();
629 return CodeNode::getCode<MachineBasicBlock*>();
637 return CodeNode::getCode<MachineFunction*>();
655 return static_cast<T>(
ptr(
N));
661 return { ptr<T>(
N),
N };
683 Iterator &up() { Pos = DS.nextUp(Pos);
return *
this; }
684 Iterator &down() { Pos = DS.nextDown(Pos);
return *
this; }
688 return DS.Stack[Pos-1];
690 const value_type *operator->()
const {
692 return &DS.Stack[Pos-1];
694 bool operator==(
const Iterator &It)
const {
return Pos == It.Pos; }
695 bool operator!=(
const Iterator &It)
const {
return Pos != It.Pos; }
698 friend struct DefStack;
700 Iterator(
const DefStack &S,
bool Top);
713 unsigned size()
const;
723 using StorageType = std::vector<value_type>;
725 bool isDelimiter(
const StorageType::value_type &
P,
NodeId N = 0)
const {
726 return (
P.Addr ==
nullptr) && (
N == 0 ||
P.Id ==
N);
729 unsigned nextUp(
unsigned P)
const;
730 unsigned nextDown(
unsigned P)
const;
768 return BlockNodes.at(BB);
784 template <u
int16_t Kind>
787 BA.
Addr->getKind() == Kind;
790 template <u
int16_t Kind>
793 BA.
Addr->getKind() == Kind;
839 template <
typename Predicate>
844 using BlockRefsMap = std::map<NodeId, RegisterSet>;
848 void buildPhis(BlockRefsMap &PhiM,
RegisterSet &AllRefs,
850 void removeUnusedPhis();
856 template <
typename Predicate>
void linkStmtRefs(
DefStackMap &DefM,
865 IA.Addr->removeMember(
RA, *
this);
869 std::unique_ptr<TargetOperandInfo> DefaultTOI;
874 const PhysicalRegisterInfo PRI;
877 const TargetOperandInfo &TOI;
879 RegisterAggr LiveIns;
880 NodeAddr<FuncNode*> Func;
883 std::map<MachineBasicBlock*,NodeAddr<BlockNode*>> BlockNodes;
888 template <
typename Predicate>
895 while (NA.Addr !=
this) {
898 if (
RA.Addr->getRegRef(
G) == RR &&
P(NA))
902 NA =
G.addr<
NodeBase*>(NA.Addr->getNext());
907 NA = CA.
Addr->getFirstMember(
G);
914 template <
typename Predicate>
921 while (M.Addr !=
this) {
924 M =
G.addr<
NodeBase*>(M.Addr->getNext());
929 template <
typename T>
939 template <
typename T>
950 const Print<NodeAddr<PhiUseNode *>> &
P);
956 const Print<NodeAddr<StmtNode *>> &
P);
958 const Print<NodeAddr<InstrNode *>> &
P);
960 const Print<NodeAddr<BlockNode *>> &
P);
962 const Print<NodeAddr<FuncNode *>> &
P);
966 const Print<DataFlowGraph::DefStack> &
P);
This file defines the BumpPtrAllocator interface.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static RegisterPass< DebugifyModulePass > DM("debugify", "Attach debug info to everything")
const HexagonInstrInfo * TII
A common definition of LaneBitmask for use in TableGen and CodeGen.
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
This file defines the SmallVector class.
INLINE void g(uint32_t *state, size_t a, size_t b, size_t c, size_t d, uint32_t x, uint32_t y)
Allocate memory in an ever growing pool, as if by bump-pointer.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A Use represents the edge between a Value definition and its users.
This class implements an extremely fast bulk output stream that can only output to a stream.
This class provides various memory handling functions that manipulate MemoryBlock instances.
@ C
The default llvm calling convention, compatible with C.
std::set< RegisterRef > RegisterSet
raw_ostream & operator<<(raw_ostream &OS, const Print< RegisterRef > &P)
std::set< NodeId > NodeSet
This is an optimization pass for GlobalISel generic memory operations.
APInt operator*(APInt a, uint64_t RHS)
bool operator!=(uint64_t V1, const APInt &V2)
bool operator==(const AddressRangeValuePair &LHS, const AddressRangeValuePair &RHS)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
static constexpr LaneBitmask getAll()
constexpr bool any() const
constexpr bool all() const
MachineBasicBlock * getCode() const
void addPhi(NodeAddr< PhiNode * > PA, const DataFlowGraph &G)
NodeList members_if(Predicate P, const DataFlowGraph &G) const
void removeMember(NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
void addMemberAfter(NodeAddr< NodeBase * > MA, NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
NodeAddr< NodeBase * > getLastMember(const DataFlowGraph &G) const
NodeAddr< NodeBase * > getFirstMember(const DataFlowGraph &G) const
NodeList members(const DataFlowGraph &G) const
void addMember(NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
void push(NodeAddr< DefNode * > DA)
void clear_block(NodeId N)
void start_block(NodeId N)
const RegisterAggr & getLiveIns() const
PackedRegisterRef pack(RegisterRef RR)
NodeAddr< FuncNode * > getFunc() const
NodeAddr< BlockNode * > findBlock(MachineBasicBlock *BB) const
void releaseBlock(NodeId B, DefStackMap &DefM)
RegisterRef unpack(PackedRegisterRef PR) const
void markBlock(NodeId B, DefStackMap &DefM)
NodeAddr< RefNode * > getNextShadow(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA, bool Create)
static bool IsPreservingDef(const NodeAddr< DefNode * > DA)
const MachineDominanceFrontier & getDF() const
static bool IsRef(const NodeAddr< NodeBase * > BA)
const MachineDominatorTree & getDT() const
MachineFunction & getMF() const
const TargetInstrInfo & getTII() const
void unlinkUse(NodeAddr< UseNode * > UA, bool RemoveFromOwner)
static bool IsPhi(const NodeAddr< NodeBase * > BA)
NodeId id(const NodeBase *P) const
PackedRegisterRef pack(RegisterRef RR) const
static bool IsUse(const NodeAddr< NodeBase * > BA)
RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const
static bool IsDef(const NodeAddr< NodeBase * > BA)
const PhysicalRegisterInfo & getPRI() const
static bool IsCode(const NodeAddr< NodeBase * > BA)
void unlinkDef(NodeAddr< DefNode * > DA, bool RemoveFromOwner)
void build(unsigned Options=BuildOptions::None)
NodeBase * ptr(NodeId N) const
void pushAllDefs(NodeAddr< InstrNode * > IA, DefStackMap &DM)
NodeList getRelatedRefs(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA) const
NodeAddr< RefNode * > getNextRelated(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA) const
std::unordered_map< RegisterId, DefStack > DefStackMap
const TargetRegisterInfo & getTRI() const
NodeAddr< T > addr(NodeId N) const
NodeId getReachedUse() const
void linkToDef(NodeId Self, NodeAddr< DefNode * > DA)
void setReachedUse(NodeId U)
void setReachedDef(NodeId D)
NodeId getReachedDef() const
MachineFunction * getCode() const
NodeAddr< BlockNode * > getEntryBlock(const DataFlowGraph &G)
NodeAddr< BlockNode * > findBlock(const MachineBasicBlock *BB, const DataFlowGraph &G) const
LaneBitmask get(uint32_t Idx) const
uint32_t insert(LaneBitmask Val)
uint32_t find(LaneBitmask Val) const
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)
uint32_t getIndexForLaneMask(LaneBitmask LM) const
LaneBitmask getLaneMaskForIndex(uint32_t K) const
uint32_t getIndexForLaneMask(LaneBitmask LM)
NodeAddr(const NodeAddr< S > &NA)
bool operator==(const NodeAddr< T > &NA) const
bool operator!=(const NodeAddr< T > &NA) const
NodeBase * ptr(NodeId N) const
NodeId id(const NodeBase *P) const
NodeAddr< NodeBase * > New()
NodeAllocator(uint32_t NPB=4096)
static uint16_t set_kind(uint16_t A, uint16_t K)
static uint16_t flags(uint16_t T)
static uint16_t kind(uint16_t T)
static uint16_t set_type(uint16_t A, uint16_t T)
static bool contains(uint16_t A, uint16_t B)
static uint16_t set_flags(uint16_t A, uint16_t F)
static uint16_t type(uint16_t T)
void setFlags(uint16_t F)
uint16_t getAttrs() const
void setAttrs(uint16_t A)
uint16_t getFlags() const
void append(NodeAddr< NodeBase * > NA)
MachineInstr * getCode() const
NodeId getPredecessor() const
void setPredecessor(NodeId B)
PrintNode(const NodeAddr< T > &x, const DataFlowGraph &g)
Print(const T &x, const DataFlowGraph &g)
NodeId getReachingDef() const
NodeId getSibling() const
void setRegRef(RegisterRef RR, DataFlowGraph &G)
void setSibling(NodeId Sib)
void setReachingDef(NodeId RD)
NodeAddr< RefNode * > getNextRef(RegisterRef RR, Predicate P, bool NextOnly, const DataFlowGraph &G)
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)
RegisterRef getRegRef(const DataFlowGraph &G) const
MachineInstr * getCode() const
virtual bool isPreserving(const MachineInstr &In, unsigned OpNum) const
const TargetInstrInfo & TII
virtual ~TargetOperandInfo()=default
TargetOperandInfo(const TargetInstrInfo &tii)
virtual bool isFixedReg(const MachineInstr &In, unsigned OpNum) const
virtual bool isClobbering(const MachineInstr &In, unsigned OpNum) const
void linkToDef(NodeId Self, NodeAddr< DefNode * > DA)