Go to the documentation of this file.
9 #ifndef LLVM_CODEGEN_RDFREGISTERS_H
10 #define LLVM_CODEGEN_RDFREGISTERS_H
24 class MachineFunction;
35 template <
typename T,
unsigned N = 32>
41 assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size());
49 return F - Map.begin() + 1;
57 return F - Map.begin() + 1;
79 operator bool()
const {
96 return std::hash<RegisterId>{}(
Reg) ^
135 return AliasInfos[U].Regs;
156 const TargetRegisterInfo &TRI;
157 IndexedSet<const uint32_t*> RegMasks;
158 std::vector<RegInfo> RegInfos;
159 std::vector<UnitInfo> UnitInfos;
160 std::vector<MaskInfo> MaskInfos;
161 std::vector<AliasInfo> AliasInfos;
163 bool aliasRR(RegisterRef RA, RegisterRef RB)
const;
164 bool aliasRM(RegisterRef RR, RegisterRef
RM)
const;
165 bool aliasMM(RegisterRef
RM, RegisterRef
RN)
const;
170 : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
205 using MapType = std::map<RegisterId, LaneBitmask>;
209 MapType::iterator Pos;
229 return Index ==
I.Index;
233 return !(*
this ==
I);
262 template <>
struct hash<
llvm::rdf::RegisterRef> {
267 template <>
struct hash<
llvm::rdf::RegisterAggr> {
272 template <>
struct equal_to<
llvm::rdf::RegisterAggr> {
279 #endif // LLVM_CODEGEN_RDFREGISTERS_H
rr_iterator rr_end() const
This is an optimization pass for GlobalISel generic memory operations.
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
RegisterRef makeRegRef() const
RegisterAggr & insert(RegisterRef RR)
RegisterAggr & clear(RegisterRef RR)
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
bool none() const
none - Returns true if none of the bits are set.
Reg
All possible values of the reg field in the ModR/M byte.
T get(uint32_t Idx) const
static int stackSlot2Index(Register Reg)
Compute the frame index from a register value representing a stack slot.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
rr_iterator & operator++()
RegisterId getRegMaskId(const uint32_t *RM) const
size_t operator()(const llvm::rdf::RegisterAggr &A) const
bool operator!=(const rr_iterator &I) const
const BitVector & getMaskUnits(RegisterId MaskId) const
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
PhysicalRegisterInfo(const TargetRegisterInfo &tri, const MachineFunction &mf)
RegisterAggr(const PhysicalRegisterInfo &pri)
bool operator==(const rr_iterator &I) const
An information struct used to provide DenseMap with the various necessary components for a given valu...
static Register index2StackSlot(int FI)
Convert a non-negative frame index to a stack slot register value.
bool operator<(const RegisterRef &RR) const
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
static bool isRegMaskId(RegisterId R)
size_type count() const
count - Returns the number of bits which are set.
RegisterRef(RegisterId R, LaneBitmask M=LaneBitmask::getAll())
static constexpr LaneBitmask getNone()
bool alias(RegisterRef RA, RegisterRef RB) const
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const_iterator begin() const
This class implements an extremely fast bulk output stream that can only output to a stream.
typename std::vector< const uint32_t * >::const_iterator const_iterator
bool operator!=(const RegisterRef &RR) const
static bool isCoverOf(RegisterRef RA, RegisterRef RB, const PhysicalRegisterInfo &PRI)
size_t operator()(llvm::rdf::RegisterRef A) const
bool operator()(const llvm::rdf::RegisterAggr &A, const llvm::rdf::RegisterAggr &B) const
const BitVector & getUnitAliases(uint32_t U) const
bool hasCoverOf(RegisterRef RR) const
bool hasAliasOf(RegisterRef RR) const
rr_iterator(const RegisterAggr &RG, bool End)
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
RegisterAggr & intersect(RegisterRef RR)
constexpr bool any() const
raw_ostream & operator<<(raw_ostream &OS, const Print< RegisterRef > &P)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::set< RegisterId > getAliasSet(RegisterId Reg) const
uint32_t find(T Val) const
SI optimize exec mask operations pre RA
rr_iterator rr_begin() const
PrintLaneMaskOpt(LaneBitmask M)
bool operator==(const RegisterAggr &A) const
constexpr Type getAsInteger() const
RegisterRef intersectWith(RegisterRef RR) const
const_iterator end() const
std::map< RegisterId, LaneBitmask > MapType
RegisterRef operator*() const
static bool isEqual(const Function &Caller, const Function &Callee)
RegisterRef clearIn(RegisterRef RR) const
const uint32_t * getRegMaskBits(RegisterId R) const
void print(raw_ostream &OS) const
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR RN
bool operator==(const RegisterRef &RR) const
static constexpr LaneBitmask getAll()
RegisterRef getRefForUnit(uint32_t U) const
RegisterRef mapTo(RegisterRef RR, unsigned R) const
const TargetRegisterInfo & getTRI() const