9#ifndef LLVM_CODEGEN_RDFREGISTERS_H
10#define LLVM_CODEGEN_RDFREGISTERS_H
35 template <
typename T,
unsigned N = 32>
49 return F - Map.begin() + 1;
57 return F - Map.begin() + 1;
96 return std::hash<RegisterId>{}(
Reg) ^
135 return AliasInfos[U].Regs;
156 const TargetRegisterInfo &TRI;
157 IndexedSet<const uint32_t*> RegMasks;
158 std::vector<RegInfo> RegInfos;
159 std::vector<UnitInfo> UnitInfos;
160 std::vector<MaskInfo> MaskInfos;
161 std::vector<AliasInfo> AliasInfos;
163 bool aliasRR(RegisterRef
RA, RegisterRef RB)
const;
164 bool aliasRM(RegisterRef RR, RegisterRef RM)
const;
165 bool aliasMM(RegisterRef RM, RegisterRef RN)
const;
170 : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
205 using MapType = std::map<RegisterId, LaneBitmask>;
209 MapType::iterator Pos;
233 return !(*
this ==
I);
262 template <>
struct hash<
llvm::rdf::RegisterRef> {
267 template <>
struct hash<
llvm::rdf::RegisterAggr> {
272 template <>
struct equal_to<
llvm::rdf::RegisterAggr> {
This file implements the BitVector class.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
A common definition of LaneBitmask for use in TableGen and CodeGen.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
size_type count() const
count - Returns the number of bits which are set.
bool none() const
none - Returns true if none of the bits are set.
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
static int stackSlot2Index(Register Reg)
Compute the frame index from a register value representing a stack slot.
static Register index2StackSlot(int FI)
Convert a non-negative frame index to a stack slot register value.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & operator<<(raw_ostream &OS, const Print< RegisterRef > &P)
This is an optimization pass for GlobalISel generic memory operations.
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
An information struct used to provide DenseMap with the various necessary components for a given valu...
static constexpr LaneBitmask getAll()
constexpr bool any() const
static constexpr LaneBitmask getNone()
constexpr Type getAsInteger() const
const_iterator end() const
typename std::vector< T >::const_iterator const_iterator
T get(uint32_t Idx) const
const_iterator begin() const
uint32_t find(T Val) const
const BitVector & getMaskUnits(RegisterId MaskId) const
RegisterId getRegMaskId(const uint32_t *RM) const
const TargetRegisterInfo & getTRI() const
static bool isRegMaskId(RegisterId R)
const uint32_t * getRegMaskBits(RegisterId R) const
const BitVector & getUnitAliases(uint32_t U) const
bool alias(RegisterRef RA, RegisterRef RB) const
std::set< RegisterId > getAliasSet(RegisterId Reg) const
RegisterRef mapTo(RegisterRef RR, unsigned R) const
RegisterRef getRefForUnit(uint32_t U) const
PrintLaneMaskOpt(LaneBitmask M)
RegisterRef operator*() const
rr_iterator & operator++()
bool operator!=(const rr_iterator &I) const
bool operator==(const rr_iterator &I) const
std::map< RegisterId, LaneBitmask > MapType
rr_iterator rr_end() const
RegisterAggr & insert(RegisterRef RR)
bool hasAliasOf(RegisterRef RR) const
bool hasCoverOf(RegisterRef RR) const
RegisterAggr(const PhysicalRegisterInfo &pri)
RegisterAggr(const RegisterAggr &RG)=default
RegisterRef clearIn(RegisterRef RR) const
void print(raw_ostream &OS) const
bool operator==(const RegisterAggr &A) const
RegisterRef makeRegRef() const
RegisterRef intersectWith(RegisterRef RR) const
rr_iterator rr_begin() const
RegisterAggr & intersect(RegisterRef RR)
RegisterAggr & clear(RegisterRef RR)
static bool isCoverOf(RegisterRef RA, RegisterRef RB, const PhysicalRegisterInfo &PRI)
bool operator<(const RegisterRef &RR) const
bool operator==(const RegisterRef &RR) const
bool operator!=(const RegisterRef &RR) const
RegisterRef(RegisterId R, LaneBitmask M=LaneBitmask::getAll())
bool operator()(const llvm::rdf::RegisterAggr &A, const llvm::rdf::RegisterAggr &B) const
size_t operator()(const llvm::rdf::RegisterAggr &A) const
size_t operator()(llvm::rdf::RegisterRef A) const