LLVM
20.0.0git
- r -
R2 :
MathExtras.h
r2FromEVEX2of4 :
X86DisassemblerDecoder.h
r2FromREX2 :
X86DisassemblerDecoder.h
R4 :
MathExtras.h
R6 :
MathExtras.h
R_00B028_SPI_SHADER_PGM_RSRC1_PS :
SIDefines.h
R_00B02C_SPI_SHADER_PGM_RSRC2_PS :
SIDefines.h
R_00B128_SPI_SHADER_PGM_RSRC1_VS :
SIDefines.h
R_00B228_SPI_SHADER_PGM_RSRC1_GS :
SIDefines.h
R_00B328_SPI_SHADER_PGM_RSRC1_ES :
SIDefines.h
R_00B428_SPI_SHADER_PGM_RSRC1_HS :
SIDefines.h
R_00B528_SPI_SHADER_PGM_RSRC1_LS :
SIDefines.h
R_00B800_COMPUTE_DISPATCH_INITIATOR :
SIDefines.h
R_00B848_COMPUTE_PGM_RSRC1 :
SIDefines.h
R_00B84C_COMPUTE_PGM_RSRC2 :
SIDefines.h
R_00B860_COMPUTE_TMPRING_SIZE :
SIDefines.h
R_0286CC_SPI_PS_INPUT_ENA :
SIDefines.h
R_0286D0_SPI_PS_INPUT_ADDR :
SIDefines.h
R_0286D8_SPI_PS_IN_CONTROL :
SIDefines.h
R_0286E8_SPI_TMPRING_SIZE :
SIDefines.h
R_02880C_DB_SHADER_CONTROL :
R600Defines.h
R_028844_SQ_PGM_RESOURCES_PS :
R600Defines.h
R_028850_SQ_PGM_RESOURCES_PS :
R600Defines.h
R_028860_SQ_PGM_RESOURCES_VS :
R600Defines.h
R_028868_SQ_PGM_RESOURCES_VS :
R600Defines.h
R_028878_SQ_PGM_RESOURCES_GS :
R600Defines.h
R_0288D4_SQ_PGM_RESOURCES_LS :
R600Defines.h
R_0288E8_SQ_LDS_ALLOC :
R600Defines.h
R_028B54_VGT_SHADER_STAGES_EN :
SIDefines.h
R_CLS :
AArch64ELFObjectWriter.cpp
R_SPILLED_SGPRS :
SIDefines.h
R_SPILLED_VGPRS :
SIDefines.h
R_SSYM_MASK :
MCELFObjectWriter.h
R_SSYM_SHIFT :
MCELFObjectWriter.h
R_TYPE2_MASK :
MCELFObjectWriter.h
R_TYPE2_SHIFT :
MCELFObjectWriter.h
R_TYPE3_MASK :
MCELFObjectWriter.h
R_TYPE3_SHIFT :
MCELFObjectWriter.h
R_TYPE_MASK :
MCELFObjectWriter.h
R_TYPE_SHIFT :
MCELFObjectWriter.h
RA_EVICT_FEATURES_LIST :
MLRegAllocEvictAdvisor.cpp
RA_EVICT_FIRST_DEVELOPMENT_FEATURE :
MLRegAllocEvictAdvisor.cpp
RA_EVICT_REST_DEVELOPMENT_FEATURES :
MLRegAllocEvictAdvisor.cpp
RA_PRIORITY_FEATURES_LIST :
MLRegAllocPriorityAdvisor.cpp
RAW_ID_METHOD_DUMP :
DIARawSymbol.cpp
RAW_METHOD_DUMP :
DIARawSymbol.cpp
RAW_METHOD_DUMP_AS :
DIARawSymbol.cpp
rc :
HexagonBitTracker.cpp
READ_NUM :
InstrProfReader.cpp
RECORD :
AMDKernelCodeTUtils.cpp
REG_ASSERT :
regex_impl.h
REG_ATOI :
regex_impl.h
REG_BACKR :
regex_impl.h
REG_BADBR :
regex_impl.h
REG_BADPAT :
regex_impl.h
REG_BADRPT :
regex_impl.h
REG_BASIC :
regex_impl.h
REG_DUMP :
regex_impl.h
REG_EBRACE :
regex_impl.h
REG_EBRACK :
regex_impl.h
REG_ECOLLATE :
regex_impl.h
REG_ECTYPE :
regex_impl.h
REG_EESCAPE :
regex_impl.h
REG_EMPTY :
regex_impl.h
REG_EPAREN :
regex_impl.h
REG_ERANGE :
regex_impl.h
REG_ESPACE :
regex_impl.h
REG_ESUBREG :
regex_impl.h
REG_EXTENDED :
regex_impl.h
REG_ICASE :
regex_impl.h
REG_INVARG :
regex_impl.h
REG_ITOA :
regex_impl.h
REG_LARGE :
regex_impl.h
REG_NEWLINE :
regex_impl.h
REG_NOMATCH :
regex_impl.h
REG_NOSPEC :
regex_impl.h
REG_NOSUB :
regex_impl.h
REG_NOTBOL :
regex_impl.h
REG_NOTEOL :
regex_impl.h
REG_PEND :
regex_impl.h
REG_STARTEND :
regex_impl.h
REG_TRACE :
regex_impl.h
REGEX_BAD :
regex2.h
regFromModRM :
X86DisassemblerDecoder.h
REGINFINITY :
regcomp.c
REGION_PASS :
SandboxVectorizerPassBuilder.cpp
RegionGraphTraits :
RegionIterator.h
RegionNodeGraphTraits :
RegionIterator.h
REGISTER_PACKED :
VECustomDAG.cpp
RegName :
LVLGen.cpp
REGS_16BIT :
X86DisassemblerDecoder.h
REGS_32BIT :
X86DisassemblerDecoder.h
REGS_64BIT :
X86DisassemblerDecoder.h
REGS_8BIT :
X86DisassemblerDecoder.h
REGS_CONTROL :
X86DisassemblerDecoder.h
REGS_DEBUG :
X86DisassemblerDecoder.h
REGS_MASK_PAIRS :
X86DisassemblerDecoder.h
REGS_MASKS :
X86DisassemblerDecoder.h
REGS_MMX :
X86DisassemblerDecoder.h
REGS_SEGMENT :
X86DisassemblerDecoder.h
REGS_TMM :
X86DisassemblerDecoder.h
REGS_TMM_PAIRS :
X86DisassemblerDecoder.h
REGS_XMM :
X86DisassemblerDecoder.h
REGS_YMM :
X86DisassemblerDecoder.h
REGS_ZMM :
X86DisassemblerDecoder.h
RELOC_CASE :
XCOFF.cpp
REMARK_PASS :
AnnotationRemarks.cpp
REMARKS_API_VERSION :
Remarks.h
REP :
regcomp.c
REPORT_OPTION :
LVOptions.h
REQUIRE :
regcomp.c
REQUIRE_FIELD :
LLParser.cpp
RESET_OPTION :
TargetMachine.cpp
RESOURCE_FLAG :
DXContainer.h
,
DXContainerYAML.cpp
RESOURCE_KIND :
DXContainer.h
,
DXContainer.cpp
RESOURCE_TYPE :
DXContainer.h
,
DXContainer.cpp
RET_ON_ERR :
PGOCtxProfReader.cpp
RETURN_CASE :
FormatUtil.h
,
LVCodeViewReader.cpp
RETURN_IF_ERROR :
COFFObjectFile.cpp
,
WindowsResource.cpp
rFromEVEX2of4 :
X86DisassemblerDecoder.h
rFromREX :
X86DisassemblerDecoder.h
rFromREX2 :
X86DisassemblerDecoder.h
rFromVEX2of2 :
X86DisassemblerDecoder.h
rFromVEX2of3 :
X86DisassemblerDecoder.h
rFromXOP2of3 :
X86DisassemblerDecoder.h
RISCV_COMPRESS_INSTRS_NAME :
RISCVMakeCompressible.cpp
RISCV_DEAD_REG_DEF_NAME :
RISCVDeadRegisterDefinitions.cpp
RISCV_DYNAMIC_TAG :
ELF.cpp
,
ELFYAML.cpp
,
ELF.cpp
RISCV_EXPAND_ATOMIC_PSEUDO_NAME :
RISCVExpandAtomicPseudoInsts.cpp
RISCV_EXPAND_PSEUDO_NAME :
RISCVExpandPseudoInsts.cpp
RISCV_INSERT_READ_WRITE_CSR_NAME :
RISCVInsertReadWriteCSR.cpp
RISCV_INSERT_VSETVLI_NAME :
RISCVInsertVSETVLI.cpp
RISCV_INSERT_WRITE_VXRM_NAME :
RISCVInsertWriteVXRM.cpp
RISCV_MERGE_BASE_OFFSET_NAME :
RISCVMergeBaseOffset.cpp
RISCV_MOVE_MERGE_NAME :
RISCVMoveMerger.cpp
RISCV_OPT_W_INSTRS_NAME :
RISCVOptWInstrs.cpp
RISCV_POST_RA_EXPAND_PSEUDO_NAME :
RISCVPostRAExpandPseudoInsts.cpp
RISCV_PRERA_EXPAND_PSEUDO_NAME :
RISCVExpandPseudoInsts.cpp
RISCV_PUSH_POP_OPT_NAME :
RISCVPushPopOptimizer.cpp
rmFromModRM :
X86DisassemblerDecoder.h
ROTL :
SipHash.cpp
ROTR :
SHA256.cpp
RPMALLOC_ALLOCATOR :
rpmalloc.h
rpmalloc_assert :
rpmalloc.c
rpmalloc_assume :
rpmalloc.c
RPMALLOC_ATTRIB_ALLOC_SIZE :
rpmalloc.h
RPMALLOC_ATTRIB_ALLOC_SIZE2 :
rpmalloc.h
RPMALLOC_ATTRIB_MALLOC :
rpmalloc.h
RPMALLOC_CDECL :
rpmalloc.h
RPMALLOC_CONFIGURABLE :
rpmalloc.h
RPMALLOC_EXPORT :
rpmalloc.h
RPMALLOC_FIRST_CLASS_HEAPS :
rpmalloc.h
RPMALLOC_GROW_OR_FAIL :
rpmalloc.h
RPMALLOC_NO_PRESERVE :
rpmalloc.h
RPMALLOC_RESTRICT :
malloc.c
RRCAS_multi_cases :
VERegisterInfo.cpp
RTDYLD_INVALID_SECTION_ID :
RuntimeDyldImpl.h
RTLIBCASE :
LegalizerHelper.cpp
RTLIBCASE_CMP :
LegalizerHelper.cpp
RTLIBCASE_INT :
LegalizerHelper.cpp
RUIP_NAME :
RegUsageInfoPropagate.cpp
RuleST2 :
AArch64SIMDInstrOpt.cpp
RuleST4 :
AArch64SIMDInstrOpt.cpp
RVV_OPC_LMUL_CASE :
RISCVInstrInfo.cpp
RVV_OPC_LMUL_MASK_CASE :
RISCVInstrInfo.cpp
Generated on Mon Jan 20 2025 11:47:28 for LLVM by
1.9.6