#include "AArch64InstrInfo.h"#include "llvm/ADT/SmallVector.h"#include "llvm/ADT/Statistic.h"#include "llvm/ADT/StringRef.h"#include "llvm/CodeGen/MachineBasicBlock.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineFunctionPass.h"#include "llvm/CodeGen/MachineInstr.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineOperand.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/TargetInstrInfo.h"#include "llvm/CodeGen/TargetSchedule.h"#include "llvm/CodeGen/TargetSubtargetInfo.h"#include "llvm/MC/MCInstrDesc.h"#include "llvm/MC/MCSchedule.h"#include "llvm/Pass.h"#include <unordered_map>
Include dependency graph for AArch64SIMDInstrOpt.cpp:
Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "aarch64-simdinstr-opt" |
| #define | AARCH64_VECTOR_BY_ELEMENT_OPT_NAME "AArch64 SIMD instructions optimization pass" |
| #define | RuleST2(OpcOrg, OpcR0, OpcR1, OpcR2, RC) {OpcOrg, {OpcR0, OpcR1, OpcR2}, RC} |
| #define | RuleST4(OpcOrg, OpcR0, OpcR1, OpcR2, OpcR3, OpcR4, OpcR5, OpcR6, OpcR7, OpcR8, OpcR9, RC) |
Functions | |
| STATISTIC (NumModifiedInstr, "Number of SIMD instructions modified") | |
| INITIALIZE_PASS (AArch64SIMDInstrOpt, "aarch64-simdinstr-opt", AARCH64_VECTOR_BY_ELEMENT_OPT_NAME, false, false) bool AArch64SIMDInstrOpt | |
| Based only on latency of instructions, determine if it is cost efficient to replace the instruction InstDesc by the instructions stored in the array InstDescRepl. | |
Macro Definition Documentation
◆ AARCH64_VECTOR_BY_ELEMENT_OPT_NAME
| #define AARCH64_VECTOR_BY_ELEMENT_OPT_NAME "AArch64 SIMD instructions optimization pass" |
Definition at line 61 of file AArch64SIMDInstrOpt.cpp.
◆ DEBUG_TYPE
| #define DEBUG_TYPE "aarch64-simdinstr-opt" |
Definition at line 56 of file AArch64SIMDInstrOpt.cpp.
◆ RuleST2
| #define RuleST2 | ( | OpcOrg, | |
| OpcR0, | |||
| OpcR1, | |||
| OpcR2, | |||
| RC | |||
| ) | {OpcOrg, {OpcR0, OpcR1, OpcR2}, RC} |
Definition at line 93 of file AArch64SIMDInstrOpt.cpp.
◆ RuleST4
| #define RuleST4 | ( | OpcOrg, | |
| OpcR0, | |||
| OpcR1, | |||
| OpcR2, | |||
| OpcR3, | |||
| OpcR4, | |||
| OpcR5, | |||
| OpcR6, | |||
| OpcR7, | |||
| OpcR8, | |||
| OpcR9, | |||
| RC | |||
| ) |
Value:
{OpcOrg, \
{OpcR0, OpcR1, OpcR2, OpcR3, OpcR4, OpcR5, OpcR6, OpcR7, OpcR8, OpcR9}, RC}
Definition at line 95 of file AArch64SIMDInstrOpt.cpp.
Function Documentation
◆ INITIALIZE_PASS()
| INITIALIZE_PASS | ( | AArch64SIMDInstrOpt | , |
| "aarch64-simdinstr-opt" | , | ||
| AARCH64_VECTOR_BY_ELEMENT_OPT_NAME | , | ||
| false | , | ||
| false | |||
| ) |
Based only on latency of instructions, determine if it is cost efficient to replace the instruction InstDesc by the instructions stored in the array InstDescRepl.
Return true if replacement is expected to be faster.
Definition at line 210 of file AArch64SIMDInstrOpt.cpp.
References llvm::MCSchedClassDesc::isValid(), and llvm::MCSchedClassDesc::isVariant().
◆ STATISTIC()
| STATISTIC | ( | NumModifiedInstr | , |
| "Number of SIMD instructions modified" | |||
| ) |
