LLVM 19.0.0git
MachineInstr.h
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1//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineInstr class, which is the
10// basic representation for all target dependent machine instructions used by
11// the back end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H
17
20#include "llvm/ADT/ilist.h"
21#include "llvm/ADT/ilist_node.h"
27#include "llvm/IR/DebugLoc.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/MC/MCInstrDesc.h"
30#include "llvm/MC/MCSymbol.h"
34#include <algorithm>
35#include <cassert>
36#include <cstdint>
37#include <utility>
38
39namespace llvm {
40
41class DILabel;
42class Instruction;
43class MDNode;
44class AAResults;
45template <typename T> class ArrayRef;
46class DIExpression;
47class DILocalVariable;
48class MachineBasicBlock;
49class MachineFunction;
50class MachineRegisterInfo;
51class ModuleSlotTracker;
52class raw_ostream;
53template <typename T> class SmallVectorImpl;
54class SmallBitVector;
55class StringRef;
56class TargetInstrInfo;
57class TargetRegisterClass;
58class TargetRegisterInfo;
59
60//===----------------------------------------------------------------------===//
61/// Representation of each machine instruction.
62///
63/// This class isn't a POD type, but it must have a trivial destructor. When a
64/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
65/// without having their destructor called.
66///
68 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
69 ilist_sentinel_tracking<true>> {
70public:
72
73 /// Flags to specify different kinds of comments to output in
74 /// assembly code. These flags carry semantic information not
75 /// otherwise easily derivable from the IR text.
76 ///
78 ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
80 TAsmComments = 0x4 // Target Asm comments should start from this value.
81 };
82
83 enum MIFlag {
85 FrameSetup = 1 << 0, // Instruction is used as a part of
86 // function frame setup code.
87 FrameDestroy = 1 << 1, // Instruction is used as a part of
88 // function frame destruction code.
89 BundledPred = 1 << 2, // Instruction has bundled predecessors.
90 BundledSucc = 1 << 3, // Instruction has bundled successors.
91 FmNoNans = 1 << 4, // Instruction does not support Fast
92 // math nan values.
93 FmNoInfs = 1 << 5, // Instruction does not support Fast
94 // math infinity values.
95 FmNsz = 1 << 6, // Instruction is not required to retain
96 // signed zero values.
97 FmArcp = 1 << 7, // Instruction supports Fast math
98 // reciprocal approximations.
99 FmContract = 1 << 8, // Instruction supports Fast math
100 // contraction operations like fma.
101 FmAfn = 1 << 9, // Instruction may map to Fast math
102 // intrinsic approximation.
103 FmReassoc = 1 << 10, // Instruction supports Fast math
104 // reassociation of operand order.
105 NoUWrap = 1 << 11, // Instruction supports binary operator
106 // no unsigned wrap.
107 NoSWrap = 1 << 12, // Instruction supports binary operator
108 // no signed wrap.
109 IsExact = 1 << 13, // Instruction supports division is
110 // known to be exact.
111 NoFPExcept = 1 << 14, // Instruction does not raise
112 // floatint-point exceptions.
113 NoMerge = 1 << 15, // Passes that drop source location info
114 // (e.g. branch folding) should skip
115 // this instruction.
116 Unpredictable = 1 << 16, // Instruction with unpredictable condition.
117 NoConvergent = 1 << 17, // Call does not require convergence guarantees.
118 NonNeg = 1 << 18, // The operand is non-negative.
119 Disjoint = 1 << 19, // Each bit is zero in at least one of the inputs.
120 };
121
122private:
123 const MCInstrDesc *MCID; // Instruction descriptor.
124 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
125
126 // Operands are allocated by an ArrayRecycler.
127 MachineOperand *Operands = nullptr; // Pointer to the first operand.
128
129#define LLVM_MI_NUMOPERANDS_BITS 24
130#define LLVM_MI_FLAGS_BITS 24
131#define LLVM_MI_ASMPRINTERFLAGS_BITS 8
132
133 /// Number of operands on instruction.
135
136 // OperandCapacity has uint8_t size, so it should be next to NumOperands
137 // to properly pack.
138 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
139 OperandCapacity CapOperands; // Capacity of the Operands array.
140
141 /// Various bits of additional information about the machine instruction.
143
144 /// Various bits of information used by the AsmPrinter to emit helpful
145 /// comments. This is *not* semantic information. Do not use this for
146 /// anything other than to convey comment information to AsmPrinter.
147 uint8_t AsmPrinterFlags : LLVM_MI_ASMPRINTERFLAGS_BITS;
148
149 /// Internal implementation detail class that provides out-of-line storage for
150 /// extra info used by the machine instruction when this info cannot be stored
151 /// in-line within the instruction itself.
152 ///
153 /// This has to be defined eagerly due to the implementation constraints of
154 /// `PointerSumType` where it is used.
155 class ExtraInfo final : TrailingObjects<ExtraInfo, MachineMemOperand *,
156 MCSymbol *, MDNode *, uint32_t> {
157 public:
158 static ExtraInfo *create(BumpPtrAllocator &Allocator,
159 ArrayRef<MachineMemOperand *> MMOs,
160 MCSymbol *PreInstrSymbol = nullptr,
161 MCSymbol *PostInstrSymbol = nullptr,
162 MDNode *HeapAllocMarker = nullptr,
163 MDNode *PCSections = nullptr, uint32_t CFIType = 0,
164 MDNode *MMRAs = nullptr) {
165 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
166 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
167 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
168 bool HasMMRAs = MMRAs != nullptr;
169 bool HasCFIType = CFIType != 0;
170 bool HasPCSections = PCSections != nullptr;
171 auto *Result = new (Allocator.Allocate(
172 totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *, uint32_t>(
173 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
174 HasHeapAllocMarker + HasPCSections + HasMMRAs, HasCFIType),
175 alignof(ExtraInfo)))
176 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
177 HasHeapAllocMarker, HasPCSections, HasCFIType, HasMMRAs);
178
179 // Copy the actual data into the trailing objects.
180 std::copy(MMOs.begin(), MMOs.end(),
181 Result->getTrailingObjects<MachineMemOperand *>());
182
183 unsigned MDNodeIdx = 0;
184
185 if (HasPreInstrSymbol)
186 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
187 if (HasPostInstrSymbol)
188 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
189 PostInstrSymbol;
190 if (HasHeapAllocMarker)
191 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = HeapAllocMarker;
192 if (HasPCSections)
193 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = PCSections;
194 if (HasCFIType)
195 Result->getTrailingObjects<uint32_t>()[0] = CFIType;
196 if (HasMMRAs)
197 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = MMRAs;
198
199 return Result;
200 }
201
202 ArrayRef<MachineMemOperand *> getMMOs() const {
203 return ArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
204 }
205
206 MCSymbol *getPreInstrSymbol() const {
207 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
208 }
209
210 MCSymbol *getPostInstrSymbol() const {
211 return HasPostInstrSymbol
212 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
213 : nullptr;
214 }
215
216 MDNode *getHeapAllocMarker() const {
217 return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
218 }
219
220 MDNode *getPCSections() const {
221 return HasPCSections
222 ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker]
223 : nullptr;
224 }
225
226 uint32_t getCFIType() const {
227 return HasCFIType ? getTrailingObjects<uint32_t>()[0] : 0;
228 }
229
230 MDNode *getMMRAMetadata() const {
231 return HasMMRAs ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker +
232 HasPCSections]
233 : nullptr;
234 }
235
236 private:
237 friend TrailingObjects;
238
239 // Description of the extra info, used to interpret the actual optional
240 // data appended.
241 //
242 // Note that this is not terribly space optimized. This leaves a great deal
243 // of flexibility to fit more in here later.
244 const int NumMMOs;
245 const bool HasPreInstrSymbol;
246 const bool HasPostInstrSymbol;
247 const bool HasHeapAllocMarker;
248 const bool HasPCSections;
249 const bool HasCFIType;
250 const bool HasMMRAs;
251
252 // Implement the `TrailingObjects` internal API.
253 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
254 return NumMMOs;
255 }
256 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
257 return HasPreInstrSymbol + HasPostInstrSymbol;
258 }
259 size_t numTrailingObjects(OverloadToken<MDNode *>) const {
260 return HasHeapAllocMarker + HasPCSections;
261 }
262 size_t numTrailingObjects(OverloadToken<uint32_t>) const {
263 return HasCFIType;
264 }
265
266 // Just a boring constructor to allow us to initialize the sizes. Always use
267 // the `create` routine above.
268 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
269 bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType,
270 bool HasMMRAs)
271 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
272 HasPostInstrSymbol(HasPostInstrSymbol),
273 HasHeapAllocMarker(HasHeapAllocMarker), HasPCSections(HasPCSections),
274 HasCFIType(HasCFIType), HasMMRAs(HasMMRAs) {}
275 };
276
277 /// Enumeration of the kinds of inline extra info available. It is important
278 /// that the `MachineMemOperand` inline kind has a tag value of zero to make
279 /// it accessible as an `ArrayRef`.
280 enum ExtraInfoInlineKinds {
281 EIIK_MMO = 0,
282 EIIK_PreInstrSymbol,
283 EIIK_PostInstrSymbol,
284 EIIK_OutOfLine
285 };
286
287 // We store extra information about the instruction here. The common case is
288 // expected to be nothing or a single pointer (typically a MMO or a symbol).
289 // We work to optimize this common case by storing it inline here rather than
290 // requiring a separate allocation, but we fall back to an allocation when
291 // multiple pointers are needed.
292 PointerSumType<ExtraInfoInlineKinds,
293 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
294 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
295 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
296 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
297 Info;
298
299 DebugLoc DbgLoc; // Source line information.
300
301 /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
302 /// defined by this instruction.
303 unsigned DebugInstrNum;
304
305 // Intrusive list support
306 friend struct ilist_traits<MachineInstr>;
308 void setParent(MachineBasicBlock *P) { Parent = P; }
309
310 /// This constructor creates a copy of the given
311 /// MachineInstr in the given MachineFunction.
313
314 /// This constructor create a MachineInstr and add the implicit operands.
315 /// It reserves space for number of operands specified by
316 /// MCInstrDesc. An explicit DebugLoc is supplied.
318 bool NoImp = false);
319
320 // MachineInstrs are pool-allocated and owned by MachineFunction.
321 friend class MachineFunction;
322
323 void
324 dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
325 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
326
327 static bool opIsRegDef(const MachineOperand &Op) {
328 return Op.isReg() && Op.isDef();
329 }
330
331 static bool opIsRegUse(const MachineOperand &Op) {
332 return Op.isReg() && Op.isUse();
333 }
334
335public:
336 MachineInstr(const MachineInstr &) = delete;
338 // Use MachineFunction::DeleteMachineInstr() instead.
339 ~MachineInstr() = delete;
340
341 const MachineBasicBlock* getParent() const { return Parent; }
342 MachineBasicBlock* getParent() { return Parent; }
343
344 /// Move the instruction before \p MovePos.
345 void moveBefore(MachineInstr *MovePos);
346
347 /// Return the function that contains the basic block that this instruction
348 /// belongs to.
349 ///
350 /// Note: this is undefined behaviour if the instruction does not have a
351 /// parent.
352 const MachineFunction *getMF() const;
354 return const_cast<MachineFunction *>(
355 static_cast<const MachineInstr *>(this)->getMF());
356 }
357
358 /// Return the asm printer flags bitvector.
359 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
360
361 /// Clear the AsmPrinter bitvector.
362 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
363
364 /// Return whether an AsmPrinter flag is set.
366 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
367 "Flag is out of range for the AsmPrinterFlags field");
368 return AsmPrinterFlags & Flag;
369 }
370
371 /// Set a flag for the AsmPrinter.
372 void setAsmPrinterFlag(uint8_t Flag) {
373 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
374 "Flag is out of range for the AsmPrinterFlags field");
375 AsmPrinterFlags |= Flag;
376 }
377
378 /// Clear specific AsmPrinter flags.
380 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
381 "Flag is out of range for the AsmPrinterFlags field");
382 AsmPrinterFlags &= ~Flag;
383 }
384
385 /// Return the MI flags bitvector.
387 return Flags;
388 }
389
390 /// Return whether an MI flag is set.
391 bool getFlag(MIFlag Flag) const {
392 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
393 "Flag is out of range for the Flags field");
394 return Flags & Flag;
395 }
396
397 /// Set a MI flag.
398 void setFlag(MIFlag Flag) {
399 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
400 "Flag is out of range for the Flags field");
401 Flags |= (uint32_t)Flag;
402 }
403
404 void setFlags(unsigned flags) {
405 assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
406 "flags to be set are out of range for the Flags field");
407 // Filter out the automatically maintained flags.
408 unsigned Mask = BundledPred | BundledSucc;
409 Flags = (Flags & Mask) | (flags & ~Mask);
410 }
411
412 /// clearFlag - Clear a MI flag.
413 void clearFlag(MIFlag Flag) {
414 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
415 "Flag to clear is out of range for the Flags field");
416 Flags &= ~((uint32_t)Flag);
417 }
418
419 void clearFlags(unsigned flags) {
420 assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
421 "flags to be cleared are out of range for the Flags field");
422 Flags &= ~flags;
423 }
424
425 /// Return true if MI is in a bundle (but not the first MI in a bundle).
426 ///
427 /// A bundle looks like this before it's finalized:
428 /// ----------------
429 /// | MI |
430 /// ----------------
431 /// |
432 /// ----------------
433 /// | MI * |
434 /// ----------------
435 /// |
436 /// ----------------
437 /// | MI * |
438 /// ----------------
439 /// In this case, the first MI starts a bundle but is not inside a bundle, the
440 /// next 2 MIs are considered "inside" the bundle.
441 ///
442 /// After a bundle is finalized, it looks like this:
443 /// ----------------
444 /// | Bundle |
445 /// ----------------
446 /// |
447 /// ----------------
448 /// | MI * |
449 /// ----------------
450 /// |
451 /// ----------------
452 /// | MI * |
453 /// ----------------
454 /// |
455 /// ----------------
456 /// | MI * |
457 /// ----------------
458 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
459 /// a bundle, but the next three MIs are.
460 bool isInsideBundle() const {
461 return getFlag(BundledPred);
462 }
463
464 /// Return true if this instruction part of a bundle. This is true
465 /// if either itself or its following instruction is marked "InsideBundle".
466 bool isBundled() const {
468 }
469
470 /// Return true if this instruction is part of a bundle, and it is not the
471 /// first instruction in the bundle.
472 bool isBundledWithPred() const { return getFlag(BundledPred); }
473
474 /// Return true if this instruction is part of a bundle, and it is not the
475 /// last instruction in the bundle.
476 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
477
478 /// Bundle this instruction with its predecessor. This can be an unbundled
479 /// instruction, or it can be the first instruction in a bundle.
480 void bundleWithPred();
481
482 /// Bundle this instruction with its successor. This can be an unbundled
483 /// instruction, or it can be the last instruction in a bundle.
484 void bundleWithSucc();
485
486 /// Break bundle above this instruction.
487 void unbundleFromPred();
488
489 /// Break bundle below this instruction.
490 void unbundleFromSucc();
491
492 /// Returns the debug location id of this MachineInstr.
493 const DebugLoc &getDebugLoc() const { return DbgLoc; }
494
495 /// Return the operand containing the offset to be used if this DBG_VALUE
496 /// instruction is indirect; will be an invalid register if this value is
497 /// not indirect, and an immediate with value 0 otherwise.
499 assert(isNonListDebugValue() && "not a DBG_VALUE");
500 return getOperand(1);
501 }
503 assert(isNonListDebugValue() && "not a DBG_VALUE");
504 return getOperand(1);
505 }
506
507 /// Return the operand for the debug variable referenced by
508 /// this DBG_VALUE instruction.
509 const MachineOperand &getDebugVariableOp() const;
511
512 /// Return the debug variable referenced by
513 /// this DBG_VALUE instruction.
514 const DILocalVariable *getDebugVariable() const;
515
516 /// Return the operand for the complex address expression referenced by
517 /// this DBG_VALUE instruction.
520
521 /// Return the complex address expression referenced by
522 /// this DBG_VALUE instruction.
523 const DIExpression *getDebugExpression() const;
524
525 /// Return the debug label referenced by
526 /// this DBG_LABEL instruction.
527 const DILabel *getDebugLabel() const;
528
529 /// Fetch the instruction number of this MachineInstr. If it does not have
530 /// one already, a new and unique number will be assigned.
531 unsigned getDebugInstrNum();
532
533 /// Fetch instruction number of this MachineInstr -- but before it's inserted
534 /// into \p MF. Needed for transformations that create an instruction but
535 /// don't immediately insert them.
536 unsigned getDebugInstrNum(MachineFunction &MF);
537
538 /// Examine the instruction number of this MachineInstr. May be zero if
539 /// it hasn't been assigned a number yet.
540 unsigned peekDebugInstrNum() const { return DebugInstrNum; }
541
542 /// Set instruction number of this MachineInstr. Avoid using unless you're
543 /// deserializing this information.
544 void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
545
546 /// Drop any variable location debugging information associated with this
547 /// instruction. Use when an instruction is modified in such a way that it no
548 /// longer defines the value it used to. Variable locations using that value
549 /// will be dropped.
550 void dropDebugNumber() { DebugInstrNum = 0; }
551
552 /// Emit an error referring to the source location of this instruction.
553 /// This should only be used for inline assembly that is somehow
554 /// impossible to compile. Other errors should have been handled much
555 /// earlier.
556 ///
557 /// If this method returns, the caller should try to recover from the error.
558 void emitError(StringRef Msg) const;
559
560 /// Returns the target instruction descriptor of this MachineInstr.
561 const MCInstrDesc &getDesc() const { return *MCID; }
562
563 /// Returns the opcode of this MachineInstr.
564 unsigned getOpcode() const { return MCID->Opcode; }
565
566 /// Retuns the total number of operands.
567 unsigned getNumOperands() const { return NumOperands; }
568
569 /// Returns the total number of operands which are debug locations.
570 unsigned getNumDebugOperands() const {
571 return std::distance(debug_operands().begin(), debug_operands().end());
572 }
573
574 const MachineOperand& getOperand(unsigned i) const {
575 assert(i < getNumOperands() && "getOperand() out of range!");
576 return Operands[i];
577 }
579 assert(i < getNumOperands() && "getOperand() out of range!");
580 return Operands[i];
581 }
582
584 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
585 return *(debug_operands().begin() + Index);
586 }
587 const MachineOperand &getDebugOperand(unsigned Index) const {
588 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
589 return *(debug_operands().begin() + Index);
590 }
591
592 /// Returns whether this debug value has at least one debug operand with the
593 /// register \p Reg.
595 return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
596 return Op.isReg() && Op.getReg() == Reg;
597 });
598 }
599
600 /// Returns a range of all of the operands that correspond to a debug use of
601 /// \p Reg.
602 template <typename Operand, typename Instruction>
603 static iterator_range<
604 filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
606 std::function<bool(Operand & Op)> OpUsesReg(
607 [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
608 return make_filter_range(MI->debug_operands(), OpUsesReg);
609 }
611 std::function<bool(const MachineOperand &Op)>>>
614 const MachineInstr>(this, Reg);
615 }
617 std::function<bool(MachineOperand &Op)>>>
619 return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
620 this, Reg);
621 }
622
623 bool isDebugOperand(const MachineOperand *Op) const {
624 return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
625 }
626
627 unsigned getDebugOperandIndex(const MachineOperand *Op) const {
628 assert(isDebugOperand(Op) && "Expected a debug operand.");
629 return std::distance(adl_begin(debug_operands()), Op);
630 }
631
632 /// Returns the total number of definitions.
633 unsigned getNumDefs() const {
634 return getNumExplicitDefs() + MCID->implicit_defs().size();
635 }
636
637 /// Returns true if the instruction has implicit definition.
638 bool hasImplicitDef() const {
639 for (const MachineOperand &MO : implicit_operands())
640 if (MO.isDef() && MO.isImplicit())
641 return true;
642 return false;
643 }
644
645 /// Returns the implicit operands number.
646 unsigned getNumImplicitOperands() const {
648 }
649
650 /// Return true if operand \p OpIdx is a subregister index.
651 bool isOperandSubregIdx(unsigned OpIdx) const {
652 assert(getOperand(OpIdx).isImm() && "Expected MO_Immediate operand type.");
653 if (isExtractSubreg() && OpIdx == 2)
654 return true;
655 if (isInsertSubreg() && OpIdx == 3)
656 return true;
657 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
658 return true;
659 if (isSubregToReg() && OpIdx == 3)
660 return true;
661 return false;
662 }
663
664 /// Returns the number of non-implicit operands.
665 unsigned getNumExplicitOperands() const;
666
667 /// Returns the number of non-implicit definitions.
668 unsigned getNumExplicitDefs() const;
669
670 /// iterator/begin/end - Iterate over all operands of a machine instruction.
673
675 mop_iterator operands_end() { return Operands + NumOperands; }
676
678 const_mop_iterator operands_end() const { return Operands + NumOperands; }
679
682 }
685 }
687 return make_range(operands_begin(),
689 }
691 return make_range(operands_begin(),
693 }
695 return make_range(explicit_operands().end(), operands_end());
696 }
698 return make_range(explicit_operands().end(), operands_end());
699 }
700 /// Returns a range over all operands that are used to determine the variable
701 /// location for this DBG_VALUE instruction.
703 assert((isDebugValueLike()) && "Must be a debug value instruction.");
704 return isNonListDebugValue()
707 }
708 /// \copydoc debug_operands()
710 assert((isDebugValueLike()) && "Must be a debug value instruction.");
711 return isNonListDebugValue()
714 }
715 /// Returns a range over all explicit operands that are register definitions.
716 /// Implicit definition are not included!
718 return make_range(operands_begin(),
720 }
721 /// \copydoc defs()
723 return make_range(operands_begin(),
725 }
726 /// Returns a range that includes all operands that are register uses.
727 /// This may include unrelated operands which are not register uses.
730 }
731 /// \copydoc uses()
734 }
738 }
742 }
743
748
749 /// Returns an iterator range over all operands that are (explicit or
750 /// implicit) register defs.
752 return make_filter_range(operands(), opIsRegDef);
753 }
754 /// \copydoc all_defs()
756 return make_filter_range(operands(), opIsRegDef);
757 }
758
759 /// Returns an iterator range over all operands that are (explicit or
760 /// implicit) register uses.
762 return make_filter_range(uses(), opIsRegUse);
763 }
764 /// \copydoc all_uses()
766 return make_filter_range(uses(), opIsRegUse);
767 }
768
769 /// Returns the number of the operand iterator \p I points to.
771 return I - operands_begin();
772 }
773
774 /// Access to memory operands of the instruction. If there are none, that does
775 /// not imply anything about whether the function accesses memory. Instead,
776 /// the caller must behave conservatively.
778 if (!Info)
779 return {};
780
781 if (Info.is<EIIK_MMO>())
782 return ArrayRef(Info.getAddrOfZeroTagPointer(), 1);
783
784 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
785 return EI->getMMOs();
786
787 return {};
788 }
789
790 /// Access to memory operands of the instruction.
791 ///
792 /// If `memoperands_begin() == memoperands_end()`, that does not imply
793 /// anything about whether the function accesses memory. Instead, the caller
794 /// must behave conservatively.
795 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
796
797 /// Access to memory operands of the instruction.
798 ///
799 /// If `memoperands_begin() == memoperands_end()`, that does not imply
800 /// anything about whether the function accesses memory. Instead, the caller
801 /// must behave conservatively.
802 mmo_iterator memoperands_end() const { return memoperands().end(); }
803
804 /// Return true if we don't have any memory operands which described the
805 /// memory access done by this instruction. If this is true, calling code
806 /// must be conservative.
807 bool memoperands_empty() const { return memoperands().empty(); }
808
809 /// Return true if this instruction has exactly one MachineMemOperand.
810 bool hasOneMemOperand() const { return memoperands().size() == 1; }
811
812 /// Return the number of memory operands.
813 unsigned getNumMemOperands() const { return memoperands().size(); }
814
815 /// Helper to extract a pre-instruction symbol if one has been added.
817 if (!Info)
818 return nullptr;
819 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
820 return S;
821 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
822 return EI->getPreInstrSymbol();
823
824 return nullptr;
825 }
826
827 /// Helper to extract a post-instruction symbol if one has been added.
829 if (!Info)
830 return nullptr;
831 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
832 return S;
833 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
834 return EI->getPostInstrSymbol();
835
836 return nullptr;
837 }
838
839 /// Helper to extract a heap alloc marker if one has been added.
841 if (!Info)
842 return nullptr;
843 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
844 return EI->getHeapAllocMarker();
845
846 return nullptr;
847 }
848
849 /// Helper to extract PCSections metadata target sections.
851 if (!Info)
852 return nullptr;
853 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
854 return EI->getPCSections();
855
856 return nullptr;
857 }
858
859 /// Helper to extract mmra.op metadata.
861 if (!Info)
862 return nullptr;
863 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
864 return EI->getMMRAMetadata();
865 return nullptr;
866 }
867
868 /// Helper to extract a CFI type hash if one has been added.
870 if (!Info)
871 return 0;
872 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
873 return EI->getCFIType();
874
875 return 0;
876 }
877
878 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
879 /// queries but they are bundle aware.
880
882 IgnoreBundle, // Ignore bundles
883 AnyInBundle, // Return true if any instruction in bundle has property
884 AllInBundle // Return true if all instructions in bundle have property
885 };
886
887 /// Return true if the instruction (or in the case of a bundle,
888 /// the instructions inside the bundle) has the specified property.
889 /// The first argument is the property being queried.
890 /// The second argument indicates whether the query should look inside
891 /// instruction bundles.
892 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
893 assert(MCFlag < 64 &&
894 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
895 // Inline the fast path for unbundled or bundle-internal instructions.
897 return getDesc().getFlags() & (1ULL << MCFlag);
898
899 // If this is the first instruction in a bundle, take the slow path.
900 return hasPropertyInBundle(1ULL << MCFlag, Type);
901 }
902
903 /// Return true if this is an instruction that should go through the usual
904 /// legalization steps.
907 }
908
909 /// Return true if this instruction can have a variable number of operands.
910 /// In this case, the variable operands will be after the normal
911 /// operands but before the implicit definitions and uses (if any are
912 /// present).
915 }
916
917 /// Set if this instruction has an optional definition, e.g.
918 /// ARM instructions which can set condition code if 's' bit is set.
921 }
922
923 /// Return true if this is a pseudo instruction that doesn't
924 /// correspond to a real machine instruction.
927 }
928
929 /// Return true if this instruction doesn't produce any output in the form of
930 /// executable instructions.
932 return hasProperty(MCID::Meta, Type);
933 }
934
937 }
938
939 /// Return true if this is an instruction that marks the end of an EH scope,
940 /// i.e., a catchpad or a cleanuppad instruction.
943 }
944
946 return hasProperty(MCID::Call, Type);
947 }
948
949 /// Return true if this is a call instruction that may have an associated
950 /// call site entry in the debug info.
952 /// Return true if copying, moving, or erasing this instruction requires
953 /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
954 /// \ref eraseCallSiteInfo).
955 bool shouldUpdateCallSiteInfo() const;
956
957 /// Returns true if the specified instruction stops control flow
958 /// from executing the instruction immediately following it. Examples include
959 /// unconditional branches and return instructions.
962 }
963
964 /// Returns true if this instruction part of the terminator for a basic block.
965 /// Typically this is things like return and branch instructions.
966 ///
967 /// Various passes use this to insert code into the bottom of a basic block,
968 /// but before control flow occurs.
971 }
972
973 /// Returns true if this is a conditional, unconditional, or indirect branch.
974 /// Predicates below can be used to discriminate between
975 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
976 /// get more information.
979 }
980
981 /// Return true if this is an indirect branch, such as a
982 /// branch through a register.
985 }
986
987 /// Return true if this is a branch which may fall
988 /// through to the next instruction or may transfer control flow to some other
989 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
990 /// information about this branch.
993 }
994
995 /// Return true if this is a branch which always
996 /// transfers control flow to some other block. The
997 /// TargetInstrInfo::analyzeBranch method can be used to get more information
998 /// about this branch.
1001 }
1002
1003 /// Return true if this instruction has a predicate operand that
1004 /// controls execution. It may be set to 'always', or may be set to other
1005 /// values. There are various methods in TargetInstrInfo that can be used to
1006 /// control and modify the predicate in this instruction.
1008 // If it's a bundle than all bundled instructions must be predicable for this
1009 // to return true.
1011 }
1012
1013 /// Return true if this instruction is a comparison.
1016 }
1017
1018 /// Return true if this instruction is a move immediate
1019 /// (including conditional moves) instruction.
1022 }
1023
1024 /// Return true if this instruction is a register move.
1025 /// (including moving values from subreg to reg)
1028 }
1029
1030 /// Return true if this instruction is a bitcast instruction.
1033 }
1034
1035 /// Return true if this instruction is a select instruction.
1037 return hasProperty(MCID::Select, Type);
1038 }
1039
1040 /// Return true if this instruction cannot be safely duplicated.
1041 /// For example, if the instruction has a unique labels attached
1042 /// to it, duplicating it would cause multiple definition errors.
1045 return true;
1047 }
1048
1049 /// Return true if this instruction is convergent.
1050 /// Convergent instructions can not be made control-dependent on any
1051 /// additional values.
1053 if (isInlineAsm()) {
1054 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1055 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1056 return true;
1057 }
1058 if (getFlag(NoConvergent))
1059 return false;
1061 }
1062
1063 /// Returns true if the specified instruction has a delay slot
1064 /// which must be filled by the code generator.
1067 }
1068
1069 /// Return true for instructions that can be folded as
1070 /// memory operands in other instructions. The most common use for this
1071 /// is instructions that are simple loads from memory that don't modify
1072 /// the loaded value in any way, but it can also be used for instructions
1073 /// that can be expressed as constant-pool loads, such as V_SETALLONES
1074 /// on x86, to allow them to be folded when it is beneficial.
1075 /// This should only be set on instructions that return a value in their
1076 /// only virtual register definition.
1079 }
1080
1081 /// Return true if this instruction behaves
1082 /// the same way as the generic REG_SEQUENCE instructions.
1083 /// E.g., on ARM,
1084 /// dX VMOVDRR rY, rZ
1085 /// is equivalent to
1086 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
1087 ///
1088 /// Note that for the optimizers to be able to take advantage of
1089 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
1090 /// override accordingly.
1093 }
1094
1095 /// Return true if this instruction behaves
1096 /// the same way as the generic EXTRACT_SUBREG instructions.
1097 /// E.g., on ARM,
1098 /// rX, rY VMOVRRD dZ
1099 /// is equivalent to two EXTRACT_SUBREG:
1100 /// rX = EXTRACT_SUBREG dZ, ssub_0
1101 /// rY = EXTRACT_SUBREG dZ, ssub_1
1102 ///
1103 /// Note that for the optimizers to be able to take advantage of
1104 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
1105 /// override accordingly.
1108 }
1109
1110 /// Return true if this instruction behaves
1111 /// the same way as the generic INSERT_SUBREG instructions.
1112 /// E.g., on ARM,
1113 /// dX = VSETLNi32 dY, rZ, Imm
1114 /// is equivalent to a INSERT_SUBREG:
1115 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
1116 ///
1117 /// Note that for the optimizers to be able to take advantage of
1118 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
1119 /// override accordingly.
1122 }
1123
1124 //===--------------------------------------------------------------------===//
1125 // Side Effect Analysis
1126 //===--------------------------------------------------------------------===//
1127
1128 /// Return true if this instruction could possibly read memory.
1129 /// Instructions with this flag set are not necessarily simple load
1130 /// instructions, they may load a value and modify it, for example.
1132 if (isInlineAsm()) {
1133 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1134 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1135 return true;
1136 }
1138 }
1139
1140 /// Return true if this instruction could possibly modify memory.
1141 /// Instructions with this flag set are not necessarily simple store
1142 /// instructions, they may store a modified value based on their operands, or
1143 /// may not actually modify anything, for example.
1145 if (isInlineAsm()) {
1146 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1147 if (ExtraInfo & InlineAsm::Extra_MayStore)
1148 return true;
1149 }
1151 }
1152
1153 /// Return true if this instruction could possibly read or modify memory.
1155 return mayLoad(Type) || mayStore(Type);
1156 }
1157
1158 /// Return true if this instruction could possibly raise a floating-point
1159 /// exception. This is the case if the instruction is a floating-point
1160 /// instruction that can in principle raise an exception, as indicated
1161 /// by the MCID::MayRaiseFPException property, *and* at the same time,
1162 /// the instruction is used in a context where we expect floating-point
1163 /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
1164 bool mayRaiseFPException() const {
1167 }
1168
1169 //===--------------------------------------------------------------------===//
1170 // Flags that indicate whether an instruction can be modified by a method.
1171 //===--------------------------------------------------------------------===//
1172
1173 /// Return true if this may be a 2- or 3-address
1174 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
1175 /// result if Y and Z are exchanged. If this flag is set, then the
1176 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
1177 /// instruction.
1178 ///
1179 /// Note that this flag may be set on instructions that are only commutable
1180 /// sometimes. In these cases, the call to commuteInstruction will fail.
1181 /// Also note that some instructions require non-trivial modification to
1182 /// commute them.
1185 }
1186
1187 /// Return true if this is a 2-address instruction
1188 /// which can be changed into a 3-address instruction if needed. Doing this
1189 /// transformation can be profitable in the register allocator, because it
1190 /// means that the instruction can use a 2-address form if possible, but
1191 /// degrade into a less efficient form if the source and dest register cannot
1192 /// be assigned to the same register. For example, this allows the x86
1193 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1194 /// is the same speed as the shift but has bigger code size.
1195 ///
1196 /// If this returns true, then the target must implement the
1197 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1198 /// is allowed to fail if the transformation isn't valid for this specific
1199 /// instruction (e.g. shl reg, 4 on x86).
1200 ///
1203 }
1204
1205 /// Return true if this instruction requires
1206 /// custom insertion support when the DAG scheduler is inserting it into a
1207 /// machine basic block. If this is true for the instruction, it basically
1208 /// means that it is a pseudo instruction used at SelectionDAG time that is
1209 /// expanded out into magic code by the target when MachineInstrs are formed.
1210 ///
1211 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1212 /// is used to insert this into the MachineBasicBlock.
1215 }
1216
1217 /// Return true if this instruction requires *adjustment*
1218 /// after instruction selection by calling a target hook. For example, this
1219 /// can be used to fill in ARM 's' optional operand depending on whether
1220 /// the conditional flag register is used.
1223 }
1224
1225 /// Returns true if this instruction is a candidate for remat.
1226 /// This flag is deprecated, please don't use it anymore. If this
1227 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
1228 /// verify the instruction is really rematerializable.
1230 // It's only possible to re-mat a bundle if all bundled instructions are
1231 // re-materializable.
1233 }
1234
1235 /// Returns true if this instruction has the same cost (or less) than a move
1236 /// instruction. This is useful during certain types of optimizations
1237 /// (e.g., remat during two-address conversion or machine licm)
1238 /// where we would like to remat or hoist the instruction, but not if it costs
1239 /// more than moving the instruction into the appropriate register. Note, we
1240 /// are not marking copies from and to the same register class with this flag.
1242 // Only returns true for a bundle if all bundled instructions are cheap.
1244 }
1245
1246 /// Returns true if this instruction source operands
1247 /// have special register allocation requirements that are not captured by the
1248 /// operand register classes. e.g. ARM::STRD's two source registers must be an
1249 /// even / odd pair, ARM::STM registers have to be in ascending order.
1250 /// Post-register allocation passes should not attempt to change allocations
1251 /// for sources of instructions with this flag.
1254 }
1255
1256 /// Returns true if this instruction def operands
1257 /// have special register allocation requirements that are not captured by the
1258 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
1259 /// even / odd pair, ARM::LDM registers have to be in ascending order.
1260 /// Post-register allocation passes should not attempt to change allocations
1261 /// for definitions of instructions with this flag.
1264 }
1265
1267 CheckDefs, // Check all operands for equality
1268 CheckKillDead, // Check all operands including kill / dead markers
1269 IgnoreDefs, // Ignore all definitions
1270 IgnoreVRegDefs // Ignore virtual register definitions
1272
1273 /// Return true if this instruction is identical to \p Other.
1274 /// Two instructions are identical if they have the same opcode and all their
1275 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1276 /// Note that this means liveness related flags (dead, undef, kill) do not
1277 /// affect the notion of identical.
1278 bool isIdenticalTo(const MachineInstr &Other,
1279 MICheckType Check = CheckDefs) const;
1280
1281 /// Returns true if this instruction is a debug instruction that represents an
1282 /// identical debug value to \p Other.
1283 /// This function considers these debug instructions equivalent if they have
1284 /// identical variables, debug locations, and debug operands, and if the
1285 /// DIExpressions combined with the directness flags are equivalent.
1286 bool isEquivalentDbgInstr(const MachineInstr &Other) const;
1287
1288 /// Unlink 'this' from the containing basic block, and return it without
1289 /// deleting it.
1290 ///
1291 /// This function can not be used on bundled instructions, use
1292 /// removeFromBundle() to remove individual instructions from a bundle.
1294
1295 /// Unlink this instruction from its basic block and return it without
1296 /// deleting it.
1297 ///
1298 /// If the instruction is part of a bundle, the other instructions in the
1299 /// bundle remain bundled.
1301
1302 /// Unlink 'this' from the containing basic block and delete it.
1303 ///
1304 /// If this instruction is the header of a bundle, the whole bundle is erased.
1305 /// This function can not be used for instructions inside a bundle, use
1306 /// eraseFromBundle() to erase individual bundled instructions.
1307 void eraseFromParent();
1308
1309 /// Unlink 'this' from its basic block and delete it.
1310 ///
1311 /// If the instruction is part of a bundle, the other instructions in the
1312 /// bundle remain bundled.
1313 void eraseFromBundle();
1314
1315 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1316 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1317 bool isAnnotationLabel() const {
1318 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1319 }
1320
1321 /// Returns true if the MachineInstr represents a label.
1322 bool isLabel() const {
1323 return isEHLabel() || isGCLabel() || isAnnotationLabel();
1324 }
1325
1326 bool isCFIInstruction() const {
1327 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1328 }
1329
1330 bool isPseudoProbe() const {
1331 return getOpcode() == TargetOpcode::PSEUDO_PROBE;
1332 }
1333
1334 // True if the instruction represents a position in the function.
1335 bool isPosition() const { return isLabel() || isCFIInstruction(); }
1336
1337 bool isNonListDebugValue() const {
1338 return getOpcode() == TargetOpcode::DBG_VALUE;
1339 }
1340 bool isDebugValueList() const {
1341 return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1342 }
1343 bool isDebugValue() const {
1345 }
1346 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1347 bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1348 bool isDebugValueLike() const { return isDebugValue() || isDebugRef(); }
1349 bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
1350 bool isDebugInstr() const {
1351 return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
1352 }
1354 return isDebugInstr() || isPseudoProbe();
1355 }
1356
1357 bool isDebugOffsetImm() const {
1359 }
1360
1361 /// A DBG_VALUE is indirect iff the location operand is a register and
1362 /// the offset operand is an immediate.
1364 return isDebugOffsetImm() && getDebugOperand(0).isReg();
1365 }
1366
1367 /// A DBG_VALUE is an entry value iff its debug expression contains the
1368 /// DW_OP_LLVM_entry_value operation.
1369 bool isDebugEntryValue() const;
1370
1371 /// Return true if the instruction is a debug value which describes a part of
1372 /// a variable as unavailable.
1373 bool isUndefDebugValue() const {
1374 if (!isDebugValue())
1375 return false;
1376 // If any $noreg locations are given, this DV is undef.
1377 for (const MachineOperand &Op : debug_operands())
1378 if (Op.isReg() && !Op.getReg().isValid())
1379 return true;
1380 return false;
1381 }
1382
1384 return getOpcode() == TargetOpcode::JUMP_TABLE_DEBUG_INFO;
1385 }
1386
1387 bool isPHI() const {
1388 return getOpcode() == TargetOpcode::PHI ||
1389 getOpcode() == TargetOpcode::G_PHI;
1390 }
1391 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1392 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1393 bool isInlineAsm() const {
1394 return getOpcode() == TargetOpcode::INLINEASM ||
1395 getOpcode() == TargetOpcode::INLINEASM_BR;
1396 }
1397 /// Returns true if the register operand can be folded with a load or store
1398 /// into a frame index. Does so by checking the InlineAsm::Flag immediate
1399 /// operand at OpId - 1.
1400 bool mayFoldInlineAsmRegOp(unsigned OpId) const;
1401
1402 bool isStackAligningInlineAsm() const;
1404
1405 bool isInsertSubreg() const {
1406 return getOpcode() == TargetOpcode::INSERT_SUBREG;
1407 }
1408
1409 bool isSubregToReg() const {
1410 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1411 }
1412
1413 bool isRegSequence() const {
1414 return getOpcode() == TargetOpcode::REG_SEQUENCE;
1415 }
1416
1417 bool isBundle() const {
1418 return getOpcode() == TargetOpcode::BUNDLE;
1419 }
1420
1421 bool isCopy() const {
1422 return getOpcode() == TargetOpcode::COPY;
1423 }
1424
1425 bool isFullCopy() const {
1426 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1427 }
1428
1429 bool isExtractSubreg() const {
1430 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1431 }
1432
1433 /// Return true if the instruction behaves like a copy.
1434 /// This does not include native copy instructions.
1435 bool isCopyLike() const {
1436 return isCopy() || isSubregToReg();
1437 }
1438
1439 /// Return true is the instruction is an identity copy.
1440 bool isIdentityCopy() const {
1441 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1443 }
1444
1445 /// Return true if this is a transient instruction that is either very likely
1446 /// to be eliminated during register allocation (such as copy-like
1447 /// instructions), or if this instruction doesn't have an execution-time cost.
1448 bool isTransient() const {
1449 switch (getOpcode()) {
1450 default:
1451 return isMetaInstruction();
1452 // Copy-like instructions are usually eliminated during register allocation.
1453 case TargetOpcode::PHI:
1454 case TargetOpcode::G_PHI:
1455 case TargetOpcode::COPY:
1456 case TargetOpcode::INSERT_SUBREG:
1457 case TargetOpcode::SUBREG_TO_REG:
1458 case TargetOpcode::REG_SEQUENCE:
1459 return true;
1460 }
1461 }
1462
1463 /// Return the number of instructions inside the MI bundle, excluding the
1464 /// bundle header.
1465 ///
1466 /// This is the number of instructions that MachineBasicBlock::iterator
1467 /// skips, 0 for unbundled instructions.
1468 unsigned getBundleSize() const;
1469
1470 /// Return true if the MachineInstr reads the specified register.
1471 /// If TargetRegisterInfo is non-null, then it also checks if there
1472 /// is a read of a super-register.
1473 /// This does not count partial redefines of virtual registers as reads:
1474 /// %reg1024:6 = OP.
1476 return findRegisterUseOperandIdx(Reg, TRI, false) != -1;
1477 }
1478
1479 /// Return true if the MachineInstr reads the specified virtual register.
1480 /// Take into account that a partial define is a
1481 /// read-modify-write operation.
1483 return readsWritesVirtualRegister(Reg).first;
1484 }
1485
1486 /// Return a pair of bools (reads, writes) indicating if this instruction
1487 /// reads or writes Reg. This also considers partial defines.
1488 /// If Ops is not null, all operand indices for Reg are added.
1489 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1490 SmallVectorImpl<unsigned> *Ops = nullptr) const;
1491
1492 /// Return true if the MachineInstr kills the specified register.
1493 /// If TargetRegisterInfo is non-null, then it also checks if there is
1494 /// a kill of a super-register.
1496 return findRegisterUseOperandIdx(Reg, TRI, true) != -1;
1497 }
1498
1499 /// Return true if the MachineInstr fully defines the specified register.
1500 /// If TargetRegisterInfo is non-null, then it also checks
1501 /// if there is a def of a super-register.
1502 /// NOTE: It's ignoring subreg indices on virtual registers.
1504 return findRegisterDefOperandIdx(Reg, TRI, false, false) != -1;
1505 }
1506
1507 /// Return true if the MachineInstr modifies (fully define or partially
1508 /// define) the specified register.
1509 /// NOTE: It's ignoring subreg indices on virtual registers.
1511 return findRegisterDefOperandIdx(Reg, TRI, false, true) != -1;
1512 }
1513
1514 /// Returns true if the register is dead in this machine instruction.
1515 /// If TargetRegisterInfo is non-null, then it also checks
1516 /// if there is a dead def of a super-register.
1518 return findRegisterDefOperandIdx(Reg, TRI, true, false) != -1;
1519 }
1520
1521 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1522 /// the given register (not considering sub/super-registers).
1524
1525 /// Returns the operand index that is a use of the specific register or -1
1526 /// if it is not found. It further tightens the search criteria to a use
1527 /// that kills the register if isKill is true.
1529 bool isKill = false) const;
1530
1531 /// Wrapper for findRegisterUseOperandIdx, it returns
1532 /// a pointer to the MachineOperand rather than an index.
1534 const TargetRegisterInfo *TRI,
1535 bool isKill = false) {
1537 return (Idx == -1) ? nullptr : &getOperand(Idx);
1538 }
1539
1541 const TargetRegisterInfo *TRI,
1542 bool isKill = false) const {
1543 return const_cast<MachineInstr *>(this)->findRegisterUseOperand(Reg, TRI,
1544 isKill);
1545 }
1546
1547 /// Returns the operand index that is a def of the specified register or
1548 /// -1 if it is not found. If isDead is true, defs that are not dead are
1549 /// skipped. If Overlap is true, then it also looks for defs that merely
1550 /// overlap the specified register. If TargetRegisterInfo is non-null,
1551 /// then it also checks if there is a def of a super-register.
1552 /// This may also return a register mask operand when Overlap is true.
1554 bool isDead = false,
1555 bool Overlap = false) const;
1556
1557 /// Wrapper for findRegisterDefOperandIdx, it returns
1558 /// a pointer to the MachineOperand rather than an index.
1560 const TargetRegisterInfo *TRI,
1561 bool isDead = false,
1562 bool Overlap = false) {
1563 int Idx = findRegisterDefOperandIdx(Reg, TRI, isDead, Overlap);
1564 return (Idx == -1) ? nullptr : &getOperand(Idx);
1565 }
1566
1568 const TargetRegisterInfo *TRI,
1569 bool isDead = false,
1570 bool Overlap = false) const {
1571 return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1572 Reg, TRI, isDead, Overlap);
1573 }
1574
1575 /// Find the index of the first operand in the
1576 /// operand list that is used to represent the predicate. It returns -1 if
1577 /// none is found.
1578 int findFirstPredOperandIdx() const;
1579
1580 /// Find the index of the flag word operand that
1581 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1582 /// getOperand(OpIdx) does not belong to an inline asm operand group.
1583 ///
1584 /// If GroupNo is not NULL, it will receive the number of the operand group
1585 /// containing OpIdx.
1586 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1587
1588 /// Compute the static register class constraint for operand OpIdx.
1589 /// For normal instructions, this is derived from the MCInstrDesc.
1590 /// For inline assembly it is derived from the flag words.
1591 ///
1592 /// Returns NULL if the static register class constraint cannot be
1593 /// determined.
1594 const TargetRegisterClass*
1595 getRegClassConstraint(unsigned OpIdx,
1596 const TargetInstrInfo *TII,
1597 const TargetRegisterInfo *TRI) const;
1598
1599 /// Applies the constraints (def/use) implied by this MI on \p Reg to
1600 /// the given \p CurRC.
1601 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1602 /// instructions inside the bundle will be taken into account. In other words,
1603 /// this method accumulates all the constraints of the operand of this MI and
1604 /// the related bundle if MI is a bundle or inside a bundle.
1605 ///
1606 /// Returns the register class that satisfies both \p CurRC and the
1607 /// constraints set by MI. Returns NULL if such a register class does not
1608 /// exist.
1609 ///
1610 /// \pre CurRC must not be NULL.
1612 Register Reg, const TargetRegisterClass *CurRC,
1614 bool ExploreBundle = false) const;
1615
1616 /// Applies the constraints (def/use) implied by the \p OpIdx operand
1617 /// to the given \p CurRC.
1618 ///
1619 /// Returns the register class that satisfies both \p CurRC and the
1620 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1621 /// does not exist.
1622 ///
1623 /// \pre CurRC must not be NULL.
1624 /// \pre The operand at \p OpIdx must be a register.
1625 const TargetRegisterClass *
1626 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1627 const TargetInstrInfo *TII,
1628 const TargetRegisterInfo *TRI) const;
1629
1630 /// Add a tie between the register operands at DefIdx and UseIdx.
1631 /// The tie will cause the register allocator to ensure that the two
1632 /// operands are assigned the same physical register.
1633 ///
1634 /// Tied operands are managed automatically for explicit operands in the
1635 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1636 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1637
1638 /// Given the index of a tied register operand, find the
1639 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1640 /// index of the tied operand which must exist.
1641 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1642
1643 /// Given the index of a register def operand,
1644 /// check if the register def is tied to a source operand, due to either
1645 /// two-address elimination or inline assembly constraints. Returns the
1646 /// first tied use operand index by reference if UseOpIdx is not null.
1647 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1648 unsigned *UseOpIdx = nullptr) const {
1649 const MachineOperand &MO = getOperand(DefOpIdx);
1650 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1651 return false;
1652 if (UseOpIdx)
1653 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1654 return true;
1655 }
1656
1657 /// Return true if the use operand of the specified index is tied to a def
1658 /// operand. It also returns the def operand index by reference if DefOpIdx
1659 /// is not null.
1660 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1661 unsigned *DefOpIdx = nullptr) const {
1662 const MachineOperand &MO = getOperand(UseOpIdx);
1663 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1664 return false;
1665 if (DefOpIdx)
1666 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1667 return true;
1668 }
1669
1670 /// Clears kill flags on all operands.
1671 void clearKillInfo();
1672
1673 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1674 /// properly composing subreg indices where necessary.
1675 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1677
1678 /// We have determined MI kills a register. Look for the
1679 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1680 /// add a implicit operand if it's not found. Returns true if the operand
1681 /// exists / is added.
1682 bool addRegisterKilled(Register IncomingReg,
1684 bool AddIfNotFound = false);
1685
1686 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1687 /// all aliasing registers.
1689
1690 /// We have determined MI defined a register without a use.
1691 /// Look for the operand that defines it and mark it as IsDead. If
1692 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1693 /// true if the operand exists / is added.
1695 bool AddIfNotFound = false);
1696
1697 /// Clear all dead flags on operands defining register @p Reg.
1699
1700 /// Mark all subregister defs of register @p Reg with the undef flag.
1701 /// This function is used when we determined to have a subregister def in an
1702 /// otherwise undefined super register.
1703 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1704
1705 /// We have determined MI defines a register. Make sure there is an operand
1706 /// defining Reg.
1708 const TargetRegisterInfo *RegInfo = nullptr);
1709
1710 /// Mark every physreg used by this instruction as
1711 /// dead except those in the UsedRegs list.
1712 ///
1713 /// On instructions with register mask operands, also add implicit-def
1714 /// operands for all registers in UsedRegs.
1716 const TargetRegisterInfo &TRI);
1717
1718 /// Return true if it is safe to move this instruction. If
1719 /// SawStore is set to true, it means that there is a store (or call) between
1720 /// the instruction's location and its intended destination.
1721 bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1722
1723 /// Returns true if this instruction's memory access aliases the memory
1724 /// access of Other.
1725 //
1726 /// Assumes any physical registers used to compute addresses
1727 /// have the same value for both instructions. Returns false if neither
1728 /// instruction writes to memory.
1729 ///
1730 /// @param AA Optional alias analysis, used to compare memory operands.
1731 /// @param Other MachineInstr to check aliasing against.
1732 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1733 bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1734
1735 /// Return true if this instruction may have an ordered
1736 /// or volatile memory reference, or if the information describing the memory
1737 /// reference is not available. Return false if it is known to have no
1738 /// ordered or volatile memory references.
1739 bool hasOrderedMemoryRef() const;
1740
1741 /// Return true if this load instruction never traps and points to a memory
1742 /// location whose value doesn't change during the execution of this function.
1743 ///
1744 /// Examples include loading a value from the constant pool or from the
1745 /// argument area of a function (if it does not change). If the instruction
1746 /// does multiple loads, this returns true only if all of the loads are
1747 /// dereferenceable and invariant.
1748 bool isDereferenceableInvariantLoad() const;
1749
1750 /// If the specified instruction is a PHI that always merges together the
1751 /// same virtual register, return the register, otherwise return 0.
1752 unsigned isConstantValuePHI() const;
1753
1754 /// Return true if this instruction has side effects that are not modeled
1755 /// by mayLoad / mayStore, etc.
1756 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1757 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1758 /// INLINEASM instruction, in which case the side effect property is encoded
1759 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1760 ///
1761 bool hasUnmodeledSideEffects() const;
1762
1763 /// Returns true if it is illegal to fold a load across this instruction.
1764 bool isLoadFoldBarrier() const;
1765
1766 /// Return true if all the defs of this instruction are dead.
1767 bool allDefsAreDead() const;
1768
1769 /// Return true if all the implicit defs of this instruction are dead.
1770 bool allImplicitDefsAreDead() const;
1771
1772 /// Return a valid size if the instruction is a spill instruction.
1773 std::optional<LocationSize> getSpillSize(const TargetInstrInfo *TII) const;
1774
1775 /// Return a valid size if the instruction is a folded spill instruction.
1776 std::optional<LocationSize>
1778
1779 /// Return a valid size if the instruction is a restore instruction.
1780 std::optional<LocationSize> getRestoreSize(const TargetInstrInfo *TII) const;
1781
1782 /// Return a valid size if the instruction is a folded restore instruction.
1783 std::optional<LocationSize>
1785
1786 /// Copy implicit register operands from specified
1787 /// instruction to this instruction.
1789
1790 /// Debugging support
1791 /// @{
1792 /// Determine the generic type to be printed (if needed) on uses and defs.
1793 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1794 const MachineRegisterInfo &MRI) const;
1795
1796 /// Return true when an instruction has tied register that can't be determined
1797 /// by the instruction's descriptor. This is useful for MIR printing, to
1798 /// determine whether we need to print the ties or not.
1799 bool hasComplexRegisterTies() const;
1800
1801 /// Print this MI to \p OS.
1802 /// Don't print information that can be inferred from other instructions if
1803 /// \p IsStandalone is false. It is usually true when only a fragment of the
1804 /// function is printed.
1805 /// Only print the defs and the opcode if \p SkipOpers is true.
1806 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1807 /// Otherwise, also print the debug loc, with a terminating newline.
1808 /// \p TII is used to print the opcode name. If it's not present, but the
1809 /// MI is in a function, the opcode will be printed using the function's TII.
1810 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1811 bool SkipDebugLoc = false, bool AddNewLine = true,
1812 const TargetInstrInfo *TII = nullptr) const;
1813 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1814 bool SkipOpers = false, bool SkipDebugLoc = false,
1815 bool AddNewLine = true,
1816 const TargetInstrInfo *TII = nullptr) const;
1817 void dump() const;
1818 /// Print on dbgs() the current instruction and the instructions defining its
1819 /// operands and so on until we reach \p MaxDepth.
1820 void dumpr(const MachineRegisterInfo &MRI,
1821 unsigned MaxDepth = UINT_MAX) const;
1822 /// @}
1823
1824 //===--------------------------------------------------------------------===//
1825 // Accessors used to build up machine instructions.
1826
1827 /// Add the specified operand to the instruction. If it is an implicit
1828 /// operand, it is added to the end of the operand list. If it is an
1829 /// explicit operand it is added at the end of the explicit operand list
1830 /// (before the first implicit operand).
1831 ///
1832 /// MF must be the machine function that was used to allocate this
1833 /// instruction.
1834 ///
1835 /// MachineInstrBuilder provides a more convenient interface for creating
1836 /// instructions and adding operands.
1837 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1838
1839 /// Add an operand without providing an MF reference. This only works for
1840 /// instructions that are inserted in a basic block.
1841 ///
1842 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1843 /// preferred.
1844 void addOperand(const MachineOperand &Op);
1845
1846 /// Inserts Ops BEFORE It. Can untie/retie tied operands.
1847 void insert(mop_iterator InsertBefore, ArrayRef<MachineOperand> Ops);
1848
1849 /// Replace the instruction descriptor (thus opcode) of
1850 /// the current instruction with a new one.
1851 void setDesc(const MCInstrDesc &TID);
1852
1853 /// Replace current source information with new such.
1854 /// Avoid using this, the constructor argument is preferable.
1856 DbgLoc = std::move(DL);
1857 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
1858 }
1859
1860 /// Erase an operand from an instruction, leaving it with one
1861 /// fewer operand than it started with.
1862 void removeOperand(unsigned OpNo);
1863
1864 /// Clear this MachineInstr's memory reference descriptor list. This resets
1865 /// the memrefs to their most conservative state. This should be used only
1866 /// as a last resort since it greatly pessimizes our knowledge of the memory
1867 /// access performed by the instruction.
1868 void dropMemRefs(MachineFunction &MF);
1869
1870 /// Assign this MachineInstr's memory reference descriptor list.
1871 ///
1872 /// Unlike other methods, this *will* allocate them into a new array
1873 /// associated with the provided `MachineFunction`.
1875
1876 /// Add a MachineMemOperand to the machine instruction.
1877 /// This function should be used only occasionally. The setMemRefs function
1878 /// is the primary method for setting up a MachineInstr's MemRefs list.
1880
1881 /// Clone another MachineInstr's memory reference descriptor list and replace
1882 /// ours with it.
1883 ///
1884 /// Note that `*this` may be the incoming MI!
1885 ///
1886 /// Prefer this API whenever possible as it can avoid allocations in common
1887 /// cases.
1888 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1889
1890 /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1891 /// list and replace ours with it.
1892 ///
1893 /// Note that `*this` may be one of the incoming MIs!
1894 ///
1895 /// Prefer this API whenever possible as it can avoid allocations in common
1896 /// cases.
1899
1900 /// Set a symbol that will be emitted just prior to the instruction itself.
1901 ///
1902 /// Setting this to a null pointer will remove any such symbol.
1903 ///
1904 /// FIXME: This is not fully implemented yet.
1905 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1906
1907 /// Set a symbol that will be emitted just after the instruction itself.
1908 ///
1909 /// Setting this to a null pointer will remove any such symbol.
1910 ///
1911 /// FIXME: This is not fully implemented yet.
1912 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1913
1914 /// Clone another MachineInstr's pre- and post- instruction symbols and
1915 /// replace ours with it.
1917
1918 /// Set a marker on instructions that denotes where we should create and emit
1919 /// heap alloc site labels. This waits until after instruction selection and
1920 /// optimizations to create the label, so it should still work if the
1921 /// instruction is removed or duplicated.
1923
1924 // Set metadata on instructions that say which sections to emit instruction
1925 // addresses into.
1926 void setPCSections(MachineFunction &MF, MDNode *MD);
1927
1928 void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs);
1929
1930 /// Set the CFI type for the instruction.
1932
1933 /// Return the MIFlags which represent both MachineInstrs. This
1934 /// should be used when merging two MachineInstrs into one. This routine does
1935 /// not modify the MIFlags of this MachineInstr.
1937
1939
1940 /// Copy all flags to MachineInst MIFlags
1941 void copyIRFlags(const Instruction &I);
1942
1943 /// Break any tie involving OpIdx.
1944 void untieRegOperand(unsigned OpIdx) {
1945 MachineOperand &MO = getOperand(OpIdx);
1946 if (MO.isReg() && MO.isTied()) {
1947 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1948 MO.TiedTo = 0;
1949 }
1950 }
1951
1952 /// Add all implicit def and use operands to this instruction.
1954
1955 /// Scan instructions immediately following MI and collect any matching
1956 /// DBG_VALUEs.
1958
1959 /// Find all DBG_VALUEs that point to the register def in this instruction
1960 /// and point them to \p Reg instead.
1962
1963 /// Sets all register debug operands in this debug value instruction to be
1964 /// undef.
1966 assert(isDebugValue() && "Must be a debug value instruction.");
1967 for (MachineOperand &MO : debug_operands()) {
1968 if (MO.isReg()) {
1969 MO.setReg(0);
1970 MO.setSubReg(0);
1971 }
1972 }
1973 }
1974
1975 std::tuple<Register, Register> getFirst2Regs() const {
1976 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg());
1977 }
1978
1979 std::tuple<Register, Register, Register> getFirst3Regs() const {
1980 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
1981 getOperand(2).getReg());
1982 }
1983
1984 std::tuple<Register, Register, Register, Register> getFirst4Regs() const {
1985 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
1986 getOperand(2).getReg(), getOperand(3).getReg());
1987 }
1988
1989 std::tuple<Register, Register, Register, Register, Register>
1991 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
1993 getOperand(4).getReg());
1994 }
1995
1996 std::tuple<LLT, LLT> getFirst2LLTs() const;
1997 std::tuple<LLT, LLT, LLT> getFirst3LLTs() const;
1998 std::tuple<LLT, LLT, LLT, LLT> getFirst4LLTs() const;
1999 std::tuple<LLT, LLT, LLT, LLT, LLT> getFirst5LLTs() const;
2000
2001 std::tuple<Register, LLT, Register, LLT> getFirst2RegLLTs() const;
2002 std::tuple<Register, LLT, Register, LLT, Register, LLT>
2003 getFirst3RegLLTs() const;
2004 std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2005 getFirst4RegLLTs() const;
2006 std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT,
2007 Register, LLT>
2008 getFirst5RegLLTs() const;
2009
2010private:
2011 /// If this instruction is embedded into a MachineFunction, return the
2012 /// MachineRegisterInfo object for the current function, otherwise
2013 /// return null.
2014 MachineRegisterInfo *getRegInfo();
2015 const MachineRegisterInfo *getRegInfo() const;
2016
2017 /// Unlink all of the register operands in this instruction from their
2018 /// respective use lists. This requires that the operands already be on their
2019 /// use lists.
2020 void removeRegOperandsFromUseLists(MachineRegisterInfo&);
2021
2022 /// Add all of the register operands in this instruction from their
2023 /// respective use lists. This requires that the operands not be on their
2024 /// use lists yet.
2025 void addRegOperandsToUseLists(MachineRegisterInfo&);
2026
2027 /// Slow path for hasProperty when we're dealing with a bundle.
2028 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
2029
2030 /// Implements the logic of getRegClassConstraintEffectForVReg for the
2031 /// this MI and the given operand index \p OpIdx.
2032 /// If the related operand does not constrained Reg, this returns CurRC.
2033 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
2034 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
2035 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
2036
2037 /// Stores extra instruction information inline or allocates as ExtraInfo
2038 /// based on the number of pointers.
2039 void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
2040 MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
2041 MDNode *HeapAllocMarker, MDNode *PCSections,
2042 uint32_t CFIType, MDNode *MMRAs);
2043};
2044
2045/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
2046/// instruction rather than by pointer value.
2047/// The hashing and equality testing functions ignore definitions so this is
2048/// useful for CSE, etc.
2050 static inline MachineInstr *getEmptyKey() {
2051 return nullptr;
2052 }
2053
2055 return reinterpret_cast<MachineInstr*>(-1);
2056 }
2057
2058 static unsigned getHashValue(const MachineInstr* const &MI);
2059
2060 static bool isEqual(const MachineInstr* const &LHS,
2061 const MachineInstr* const &RHS) {
2062 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
2063 LHS == getEmptyKey() || LHS == getTombstoneKey())
2064 return LHS == RHS;
2065 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
2066 }
2067};
2068
2069//===----------------------------------------------------------------------===//
2070// Debugging Support
2071
2073 MI.print(OS);
2074 return OS;
2075}
2076
2077} // end namespace llvm
2078
2079#endif // LLVM_CODEGEN_MACHINEINSTR_H
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines DenseMapInfo traits for DenseMap.
#define Check(C,...)
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static const unsigned MaxDepth
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
#define LLVM_MI_ASMPRINTERFLAGS_BITS
Definition: MachineInstr.h:131
#define LLVM_MI_FLAGS_BITS
Definition: MachineInstr.h:130
#define LLVM_MI_NUMOPERANDS_BITS
Definition: MachineInstr.h:129
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Promote Memory to Register
Definition: Mem2Reg.cpp:110
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
#define P(N)
Basic Register Allocator
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
raw_pwrite_stream & OS
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
This header defines support for implementing classes that have some trailing object (or arrays of obj...
Value * RHS
Value * LHS
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
DWARF expression.
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:251
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:579
unsigned short Opcode
Definition: MCInstrDesc.h:205
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
Metadata node.
Definition: Metadata.h:1067
Representation of each machine instruction.
Definition: MachineInstr.h:69
mop_iterator operands_begin()
Definition: MachineInstr.h:674
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
std::tuple< Register, Register, Register, Register, Register > getFirst5Regs() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:564
unsigned getNumImplicitOperands() const
Returns the implicit operands number.
Definition: MachineInstr.h:646
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:935
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:605
bool hasDebugOperandForReg(Register Reg) const
Returns whether this debug value has at least one debug operand with the register Reg.
Definition: MachineInstr.h:594
bool isDebugValueList() const
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:735
void bundleWithPred()
Bundle this instruction with its predecessor.
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:77
bool isPosition() const
void setDebugValueUndef()
Sets all register debug operands in this debug value instruction to be undef.
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:969
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
std::tuple< Register, Register, Register, Register > getFirst4Regs() const
bool isImplicitDef() const
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:732
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
bool isCopy() const
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:362
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:702
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:341
bool isCopyLike() const
Return true if the instruction behaves like a copy.
void dropDebugNumber()
Drop any variable location debugging information associated with this instruction.
Definition: MachineInstr.h:550
MDNode * getMMRAMetadata() const
Helper to extract mmra.op metadata.
Definition: MachineInstr.h:860
void bundleWithSucc()
Bundle this instruction with its successor.
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
Definition: MachineInstr.h:869
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr reads the specified register.
bool isDebugLabel() const
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool isDebugOffsetImm() const
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:892
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void setFlags(unsigned flags)
Definition: MachineInstr.h:404
MachineFunction * getMF()
Definition: MachineInstr.h:353
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:881
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:960
std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const
MachineBasicBlock * getParent()
Definition: MachineInstr.h:342
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:945
std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:391
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:379
uint32_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:728
bool allImplicitDefsAreDead() const
Return true if all the implicit defs of this instruction are dead.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:739
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
iterator_range< filtered_mop_iterator > all_uses()
Returns an iterator range over all operands that are (explicit or implicit) register uses.
Definition: MachineInstr.h:761
bool isBundle() const
bool isDebugInstr() const
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
Definition: MachineInstr.h:570
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:567
void setDebugInstrNum(unsigned Num)
Set instruction number of this MachineInstr.
Definition: MachineInstr.h:544
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:690
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
const MachineOperand * const_mop_iterator
Definition: MachineInstr.h:672
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:365
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
bool isDebugValueLike() const
bool isInlineAsm() const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:807
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:802
bool isDebugRef() const
bool isAnnotationLabel() const
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
MachineOperand & getDebugOffset()
Definition: MachineInstr.h:502
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:686
unsigned peekDebugInstrNum() const
Examine the instruction number of this MachineInstr.
Definition: MachineInstr.h:540
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:722
std::optional< LocationSize > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:770
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isSubregToReg() const
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
bool hasImplicitDef() const
Returns true if the instruction has implicit definition.
Definition: MachineInstr.h:638
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:977
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:472
bool isDebugPHI() const
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:578
std::tuple< LLT, LLT > getFirst2LLTs() const
std::optional< LocationSize > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
const_mop_iterator operands_end() const
Definition: MachineInstr.h:678
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
void unbundleFromPred()
Break bundle above this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:372
bool isDebugOrPseudoInstr() const
bool isStackAligningInlineAsm() const
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand,...
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
mop_iterator operands_end()
Definition: MachineInstr.h:675
bool isFullCopy() const
int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
Definition: MachineInstr.h:850
bool isCFIInstruction() const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:561
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
void clearFlags(unsigned flags)
Definition: MachineInstr.h:419
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
iterator_range< filtered_const_mop_iterator > all_uses() const
Returns an iterator range over all operands that are (explicit or implicit) register uses.
Definition: MachineInstr.h:765
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
MachineInstr & operator=(const MachineInstr &)=delete
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:991
iterator_range< const_mop_iterator > debug_operands() const
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:709
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr kills the specified register.
std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:813
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:413
bool isGCLabel() const
std::optional< LocationSize > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:359
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:651
InlineAsm::AsmDialect getInlineAsmDialect() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isEquivalentDbgInstr(const MachineInstr &Other) const
Returns true if this instruction is a debug instruction that represents an identical debug value to O...
bool isRegSequence() const
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const
Returns true if the register is dead in this machine instruction.
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:677
static uint32_t copyFlagsFromInstruction(const Instruction &I)
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr fully defines the specified register.
void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)
Inserts Ops BEFORE It. Can untie/retie tied operands.
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
Definition: MachineInstr.h:999
const MachineOperand * findRegisterUseOperand(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const
bool isJumpTableDebugInfo() const
std::tuple< Register, Register, Register > getFirst3Regs() const
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' from its basic block and delete it.
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:810
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:680
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
bool isInsertSubreg() const
iterator_range< filtered_const_mop_iterator > all_defs() const
Returns an iterator range over all operands that are (explicit or implicit) register defs.
Definition: MachineInstr.h:755
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
iterator_range< filter_iterator< MachineOperand *, std::function< bool(MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg)
Definition: MachineInstr.h:618
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:717
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:795
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:460
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:683
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:777
bool isLabel() const
Returns true if the MachineInstr represents a label.
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool isExtractSubreg() const
bool isNonListDebugValue() const
MachineOperand * mop_iterator
iterator/begin/end - Iterate over all operands of a machine instruction.
Definition: MachineInstr.h:671
MachineOperand * findRegisterUseOperand(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:398
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:493
std::tuple< LLT, LLT, LLT > getFirst3LLTs() const
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction.
bool isPreISelOpcode(QueryType Type=IgnoreBundle) const
Return true if this is an instruction that should go through the usual legalization steps.
Definition: MachineInstr.h:905
bool isEHScopeReturn(QueryType Type=AnyInBundle) const
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanu...
Definition: MachineInstr.h:941
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MachineInstr.h:925
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:697
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:816
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool readsVirtualRegister(Register Reg) const
Return true if the MachineInstr reads the specified virtual register.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:919
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
bool isDebugValue() const
unsigned getDebugOperandIndex(const MachineOperand *Op) const
Definition: MachineInstr.h:627
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:498
MachineOperand & getDebugOperand(unsigned Index)
Definition: MachineInstr.h:583
std::optional< LocationSize > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:694
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:476
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:840
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
bool isDebugOperand(const MachineOperand *Op) const
Definition: MachineInstr.h:623
std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const
bool isPHI() const
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:574
uint32_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:386
bool isEHLabel() const
bool isPseudoProbe() const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
bool isUndefDebugValue() const
Return true if the instruction is a debug value which describes a part of a variable as unavailable.
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:828
void unbundleFromSucc()
Break bundle below this instruction.
iterator_range< filtered_mop_iterator > all_defs()
Returns an iterator range over all operands that are (explicit or implicit) register defs.
Definition: MachineInstr.h:751
const MachineOperand & getDebugOperand(unsigned Index) const
Definition: MachineInstr.h:587
void clearKillInfo()
Clears kill flags on all operands.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:633
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
void setPCSections(MachineFunction &MF, MDNode *MD)
MachineInstr(const MachineInstr &)=delete
bool isKill() const
const MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const
int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool isMetaInstruction(QueryType Type=IgnoreBundle) const
Return true if this instruction doesn't produce any output in the form of executable instructions.
Definition: MachineInstr.h:931
iterator_range< filter_iterator< const MachineOperand *, std::function< bool(const MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg) const
Definition: MachineInstr.h:612
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
void setDebugLoc(DebugLoc DL)
Replace current source information with new such.
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:983
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:913
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs)
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:466
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool mayFoldInlineAsmRegOp(unsigned OpId) const
Returns true if the register operand can be folded with a load or store into a frame index.
std::tuple< Register, Register > getFirst2Regs() const
~MachineInstr()=delete
A description of a memory reference used in the backend.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
int64_t getImm() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Manage lifetime of a slot tracker for printing IR.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:321
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
Specialization of filter_iterator_base for forward iteration only.
Definition: STLExtras.h:497
An ilist node that can access its parent list.
Definition: ilist_node.h:284
A range adaptor for a pair of iterators.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This file defines classes to implement an intrusive doubly linked list class (i.e.
This file defines the ilist_node class template, which is a convenient base class for creating classe...
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
@ ExtraDefRegAllocReq
Definition: MCInstrDesc.h:181
@ ConvertibleTo3Addr
Definition: MCInstrDesc.h:175
@ MayRaiseFPException
Definition: MCInstrDesc.h:170
@ Rematerializable
Definition: MCInstrDesc.h:178
@ ExtraSrcRegAllocReq
Definition: MCInstrDesc.h:180
@ UsesCustomInserter
Definition: MCInstrDesc.h:176
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
constexpr auto adl_begin(RangeT &&range) -> decltype(adl_detail::begin_impl(std::forward< RangeT >(range)))
Returns the begin iterator to range using std::begin and function found through Argument-Dependent Lo...
Definition: ADL.h:78
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
constexpr auto adl_end(RangeT &&range) -> decltype(adl_detail::end_impl(std::forward< RangeT >(range)))
Returns the end iterator to range using std::end and functions found through Argument-Dependent Looku...
Definition: ADL.h:86
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1729
iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)
Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...
Definition: STLExtras.h:572
BumpPtrAllocatorImpl BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template parameters.
Definition: Allocator.h:380
@ Other
Any other memory.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:293
ArrayRef(const T &OneElt) -> ArrayRef< T >
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition: DenseMapInfo.h:50
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
static MachineInstr * getEmptyKey()
static unsigned getHashValue(const MachineInstr *const &MI)
static MachineInstr * getTombstoneKey()
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:65
Template traits for intrusive list.
Definition: ilist.h:90