LLVM 20.0.0git
MachineInstr.h
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1//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineInstr class, which is the
10// basic representation for all target dependent machine instructions used by
11// the back end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H
17
20#include "llvm/ADT/ilist.h"
21#include "llvm/ADT/ilist_node.h"
27#include "llvm/IR/DebugLoc.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/MC/MCInstrDesc.h"
30#include "llvm/MC/MCSymbol.h"
34#include <algorithm>
35#include <cassert>
36#include <cstdint>
37#include <utility>
38
39namespace llvm {
40
41class DILabel;
42class Instruction;
43class MDNode;
44class AAResults;
45template <typename T> class ArrayRef;
46class DIExpression;
47class DILocalVariable;
48class MachineBasicBlock;
49class MachineFunction;
50class MachineRegisterInfo;
51class ModuleSlotTracker;
52class raw_ostream;
53template <typename T> class SmallVectorImpl;
54class SmallBitVector;
55class StringRef;
56class TargetInstrInfo;
57class TargetRegisterClass;
58class TargetRegisterInfo;
59
60//===----------------------------------------------------------------------===//
61/// Representation of each machine instruction.
62///
63/// This class isn't a POD type, but it must have a trivial destructor. When a
64/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
65/// without having their destructor called.
66///
68 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
69 ilist_sentinel_tracking<true>> {
70public:
72
73 /// Flags to specify different kinds of comments to output in
74 /// assembly code. These flags carry semantic information not
75 /// otherwise easily derivable from the IR text.
76 ///
78 ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
80 TAsmComments = 0x4 // Target Asm comments should start from this value.
81 };
82
83 enum MIFlag {
85 FrameSetup = 1 << 0, // Instruction is used as a part of
86 // function frame setup code.
87 FrameDestroy = 1 << 1, // Instruction is used as a part of
88 // function frame destruction code.
89 BundledPred = 1 << 2, // Instruction has bundled predecessors.
90 BundledSucc = 1 << 3, // Instruction has bundled successors.
91 FmNoNans = 1 << 4, // Instruction does not support Fast
92 // math nan values.
93 FmNoInfs = 1 << 5, // Instruction does not support Fast
94 // math infinity values.
95 FmNsz = 1 << 6, // Instruction is not required to retain
96 // signed zero values.
97 FmArcp = 1 << 7, // Instruction supports Fast math
98 // reciprocal approximations.
99 FmContract = 1 << 8, // Instruction supports Fast math
100 // contraction operations like fma.
101 FmAfn = 1 << 9, // Instruction may map to Fast math
102 // intrinsic approximation.
103 FmReassoc = 1 << 10, // Instruction supports Fast math
104 // reassociation of operand order.
105 NoUWrap = 1 << 11, // Instruction supports binary operator
106 // no unsigned wrap.
107 NoSWrap = 1 << 12, // Instruction supports binary operator
108 // no signed wrap.
109 IsExact = 1 << 13, // Instruction supports division is
110 // known to be exact.
111 NoFPExcept = 1 << 14, // Instruction does not raise
112 // floatint-point exceptions.
113 NoMerge = 1 << 15, // Passes that drop source location info
114 // (e.g. branch folding) should skip
115 // this instruction.
116 Unpredictable = 1 << 16, // Instruction with unpredictable condition.
117 NoConvergent = 1 << 17, // Call does not require convergence guarantees.
118 NonNeg = 1 << 18, // The operand is non-negative.
119 Disjoint = 1 << 19, // Each bit is zero in at least one of the inputs.
120 NoUSWrap = 1 << 20, // Instruction supports geps
121 // no unsigned signed wrap.
122 SameSign = 1 << 21 // Both operands have the same sign.
123 };
124
125private:
126 const MCInstrDesc *MCID; // Instruction descriptor.
127 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
128
129 // Operands are allocated by an ArrayRecycler.
130 MachineOperand *Operands = nullptr; // Pointer to the first operand.
131
132#define LLVM_MI_NUMOPERANDS_BITS 24
133#define LLVM_MI_FLAGS_BITS 24
134#define LLVM_MI_ASMPRINTERFLAGS_BITS 8
135
136 /// Number of operands on instruction.
138
139 // OperandCapacity has uint8_t size, so it should be next to NumOperands
140 // to properly pack.
141 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
142 OperandCapacity CapOperands; // Capacity of the Operands array.
143
144 /// Various bits of additional information about the machine instruction.
146
147 /// Various bits of information used by the AsmPrinter to emit helpful
148 /// comments. This is *not* semantic information. Do not use this for
149 /// anything other than to convey comment information to AsmPrinter.
150 uint8_t AsmPrinterFlags : LLVM_MI_ASMPRINTERFLAGS_BITS;
151
152 /// Internal implementation detail class that provides out-of-line storage for
153 /// extra info used by the machine instruction when this info cannot be stored
154 /// in-line within the instruction itself.
155 ///
156 /// This has to be defined eagerly due to the implementation constraints of
157 /// `PointerSumType` where it is used.
158 class ExtraInfo final : TrailingObjects<ExtraInfo, MachineMemOperand *,
159 MCSymbol *, MDNode *, uint32_t> {
160 public:
161 static ExtraInfo *create(BumpPtrAllocator &Allocator,
162 ArrayRef<MachineMemOperand *> MMOs,
163 MCSymbol *PreInstrSymbol = nullptr,
164 MCSymbol *PostInstrSymbol = nullptr,
165 MDNode *HeapAllocMarker = nullptr,
166 MDNode *PCSections = nullptr, uint32_t CFIType = 0,
167 MDNode *MMRAs = nullptr) {
168 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
169 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
170 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
171 bool HasMMRAs = MMRAs != nullptr;
172 bool HasCFIType = CFIType != 0;
173 bool HasPCSections = PCSections != nullptr;
174 auto *Result = new (Allocator.Allocate(
175 totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *, uint32_t>(
176 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
177 HasHeapAllocMarker + HasPCSections + HasMMRAs, HasCFIType),
178 alignof(ExtraInfo)))
179 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
180 HasHeapAllocMarker, HasPCSections, HasCFIType, HasMMRAs);
181
182 // Copy the actual data into the trailing objects.
183 std::copy(MMOs.begin(), MMOs.end(),
184 Result->getTrailingObjects<MachineMemOperand *>());
185
186 unsigned MDNodeIdx = 0;
187
188 if (HasPreInstrSymbol)
189 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
190 if (HasPostInstrSymbol)
191 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
192 PostInstrSymbol;
193 if (HasHeapAllocMarker)
194 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = HeapAllocMarker;
195 if (HasPCSections)
196 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = PCSections;
197 if (HasCFIType)
198 Result->getTrailingObjects<uint32_t>()[0] = CFIType;
199 if (HasMMRAs)
200 Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = MMRAs;
201
202 return Result;
203 }
204
205 ArrayRef<MachineMemOperand *> getMMOs() const {
206 return ArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
207 }
208
209 MCSymbol *getPreInstrSymbol() const {
210 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
211 }
212
213 MCSymbol *getPostInstrSymbol() const {
214 return HasPostInstrSymbol
215 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
216 : nullptr;
217 }
218
219 MDNode *getHeapAllocMarker() const {
220 return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
221 }
222
223 MDNode *getPCSections() const {
224 return HasPCSections
225 ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker]
226 : nullptr;
227 }
228
229 uint32_t getCFIType() const {
230 return HasCFIType ? getTrailingObjects<uint32_t>()[0] : 0;
231 }
232
233 MDNode *getMMRAMetadata() const {
234 return HasMMRAs ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker +
235 HasPCSections]
236 : nullptr;
237 }
238
239 private:
240 friend TrailingObjects;
241
242 // Description of the extra info, used to interpret the actual optional
243 // data appended.
244 //
245 // Note that this is not terribly space optimized. This leaves a great deal
246 // of flexibility to fit more in here later.
247 const int NumMMOs;
248 const bool HasPreInstrSymbol;
249 const bool HasPostInstrSymbol;
250 const bool HasHeapAllocMarker;
251 const bool HasPCSections;
252 const bool HasCFIType;
253 const bool HasMMRAs;
254
255 // Implement the `TrailingObjects` internal API.
256 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
257 return NumMMOs;
258 }
259 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
260 return HasPreInstrSymbol + HasPostInstrSymbol;
261 }
262 size_t numTrailingObjects(OverloadToken<MDNode *>) const {
263 return HasHeapAllocMarker + HasPCSections;
264 }
265 size_t numTrailingObjects(OverloadToken<uint32_t>) const {
266 return HasCFIType;
267 }
268
269 // Just a boring constructor to allow us to initialize the sizes. Always use
270 // the `create` routine above.
271 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
272 bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType,
273 bool HasMMRAs)
274 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
275 HasPostInstrSymbol(HasPostInstrSymbol),
276 HasHeapAllocMarker(HasHeapAllocMarker), HasPCSections(HasPCSections),
277 HasCFIType(HasCFIType), HasMMRAs(HasMMRAs) {}
278 };
279
280 /// Enumeration of the kinds of inline extra info available. It is important
281 /// that the `MachineMemOperand` inline kind has a tag value of zero to make
282 /// it accessible as an `ArrayRef`.
283 enum ExtraInfoInlineKinds {
284 EIIK_MMO = 0,
285 EIIK_PreInstrSymbol,
286 EIIK_PostInstrSymbol,
287 EIIK_OutOfLine
288 };
289
290 // We store extra information about the instruction here. The common case is
291 // expected to be nothing or a single pointer (typically a MMO or a symbol).
292 // We work to optimize this common case by storing it inline here rather than
293 // requiring a separate allocation, but we fall back to an allocation when
294 // multiple pointers are needed.
295 PointerSumType<ExtraInfoInlineKinds,
296 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
297 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
298 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
299 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
300 Info;
301
302 DebugLoc DbgLoc; // Source line information.
303
304 /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
305 /// defined by this instruction.
306 unsigned DebugInstrNum;
307
308 /// Cached opcode from MCID.
309 uint16_t Opcode;
310
311 // Intrusive list support
312 friend struct ilist_traits<MachineInstr>;
314 void setParent(MachineBasicBlock *P) { Parent = P; }
315
316 /// This constructor creates a copy of the given
317 /// MachineInstr in the given MachineFunction.
319
320 /// This constructor create a MachineInstr and add the implicit operands.
321 /// It reserves space for number of operands specified by
322 /// MCInstrDesc. An explicit DebugLoc is supplied.
324 bool NoImp = false);
325
326 // MachineInstrs are pool-allocated and owned by MachineFunction.
327 friend class MachineFunction;
328
329 void
330 dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
331 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
332
333 static bool opIsRegDef(const MachineOperand &Op) {
334 return Op.isReg() && Op.isDef();
335 }
336
337 static bool opIsRegUse(const MachineOperand &Op) {
338 return Op.isReg() && Op.isUse();
339 }
340
341public:
342 MachineInstr(const MachineInstr &) = delete;
344 // Use MachineFunction::DeleteMachineInstr() instead.
345 ~MachineInstr() = delete;
346
347 const MachineBasicBlock* getParent() const { return Parent; }
348 MachineBasicBlock* getParent() { return Parent; }
349
350 /// Move the instruction before \p MovePos.
351 void moveBefore(MachineInstr *MovePos);
352
353 /// Return the function that contains the basic block that this instruction
354 /// belongs to.
355 ///
356 /// Note: this is undefined behaviour if the instruction does not have a
357 /// parent.
358 const MachineFunction *getMF() const;
360 return const_cast<MachineFunction *>(
361 static_cast<const MachineInstr *>(this)->getMF());
362 }
363
364 /// Return the asm printer flags bitvector.
365 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
366
367 /// Clear the AsmPrinter bitvector.
368 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
369
370 /// Return whether an AsmPrinter flag is set.
372 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
373 "Flag is out of range for the AsmPrinterFlags field");
374 return AsmPrinterFlags & Flag;
375 }
376
377 /// Set a flag for the AsmPrinter.
379 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
380 "Flag is out of range for the AsmPrinterFlags field");
381 AsmPrinterFlags |= Flag;
382 }
383
384 /// Clear specific AsmPrinter flags.
386 assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
387 "Flag is out of range for the AsmPrinterFlags field");
388 AsmPrinterFlags &= ~Flag;
389 }
390
391 /// Return the MI flags bitvector.
393 return Flags;
394 }
395
396 /// Return whether an MI flag is set.
397 bool getFlag(MIFlag Flag) const {
398 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
399 "Flag is out of range for the Flags field");
400 return Flags & Flag;
401 }
402
403 /// Set a MI flag.
404 void setFlag(MIFlag Flag) {
405 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
406 "Flag is out of range for the Flags field");
407 Flags |= (uint32_t)Flag;
408 }
409
410 void setFlags(unsigned flags) {
411 assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
412 "flags to be set are out of range for the Flags field");
413 // Filter out the automatically maintained flags.
414 unsigned Mask = BundledPred | BundledSucc;
415 Flags = (Flags & Mask) | (flags & ~Mask);
416 }
417
418 /// clearFlag - Clear a MI flag.
419 void clearFlag(MIFlag Flag) {
420 assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
421 "Flag to clear is out of range for the Flags field");
422 Flags &= ~((uint32_t)Flag);
423 }
424
425 void clearFlags(unsigned flags) {
426 assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
427 "flags to be cleared are out of range for the Flags field");
428 Flags &= ~flags;
429 }
430
431 /// Return true if MI is in a bundle (but not the first MI in a bundle).
432 ///
433 /// A bundle looks like this before it's finalized:
434 /// ----------------
435 /// | MI |
436 /// ----------------
437 /// |
438 /// ----------------
439 /// | MI * |
440 /// ----------------
441 /// |
442 /// ----------------
443 /// | MI * |
444 /// ----------------
445 /// In this case, the first MI starts a bundle but is not inside a bundle, the
446 /// next 2 MIs are considered "inside" the bundle.
447 ///
448 /// After a bundle is finalized, it looks like this:
449 /// ----------------
450 /// | Bundle |
451 /// ----------------
452 /// |
453 /// ----------------
454 /// | MI * |
455 /// ----------------
456 /// |
457 /// ----------------
458 /// | MI * |
459 /// ----------------
460 /// |
461 /// ----------------
462 /// | MI * |
463 /// ----------------
464 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
465 /// a bundle, but the next three MIs are.
466 bool isInsideBundle() const {
467 return getFlag(BundledPred);
468 }
469
470 /// Return true if this instruction part of a bundle. This is true
471 /// if either itself or its following instruction is marked "InsideBundle".
472 bool isBundled() const {
474 }
475
476 /// Return true if this instruction is part of a bundle, and it is not the
477 /// first instruction in the bundle.
478 bool isBundledWithPred() const { return getFlag(BundledPred); }
479
480 /// Return true if this instruction is part of a bundle, and it is not the
481 /// last instruction in the bundle.
482 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
483
484 /// Bundle this instruction with its predecessor. This can be an unbundled
485 /// instruction, or it can be the first instruction in a bundle.
486 void bundleWithPred();
487
488 /// Bundle this instruction with its successor. This can be an unbundled
489 /// instruction, or it can be the last instruction in a bundle.
490 void bundleWithSucc();
491
492 /// Break bundle above this instruction.
493 void unbundleFromPred();
494
495 /// Break bundle below this instruction.
496 void unbundleFromSucc();
497
498 /// Returns the debug location id of this MachineInstr.
499 const DebugLoc &getDebugLoc() const { return DbgLoc; }
500
501 /// Return the operand containing the offset to be used if this DBG_VALUE
502 /// instruction is indirect; will be an invalid register if this value is
503 /// not indirect, and an immediate with value 0 otherwise.
505 assert(isNonListDebugValue() && "not a DBG_VALUE");
506 return getOperand(1);
507 }
509 assert(isNonListDebugValue() && "not a DBG_VALUE");
510 return getOperand(1);
511 }
512
513 /// Return the operand for the debug variable referenced by
514 /// this DBG_VALUE instruction.
515 const MachineOperand &getDebugVariableOp() const;
517
518 /// Return the debug variable referenced by
519 /// this DBG_VALUE instruction.
520 const DILocalVariable *getDebugVariable() const;
521
522 /// Return the operand for the complex address expression referenced by
523 /// this DBG_VALUE instruction.
526
527 /// Return the complex address expression referenced by
528 /// this DBG_VALUE instruction.
529 const DIExpression *getDebugExpression() const;
530
531 /// Return the debug label referenced by
532 /// this DBG_LABEL instruction.
533 const DILabel *getDebugLabel() const;
534
535 /// Fetch the instruction number of this MachineInstr. If it does not have
536 /// one already, a new and unique number will be assigned.
537 unsigned getDebugInstrNum();
538
539 /// Fetch instruction number of this MachineInstr -- but before it's inserted
540 /// into \p MF. Needed for transformations that create an instruction but
541 /// don't immediately insert them.
542 unsigned getDebugInstrNum(MachineFunction &MF);
543
544 /// Examine the instruction number of this MachineInstr. May be zero if
545 /// it hasn't been assigned a number yet.
546 unsigned peekDebugInstrNum() const { return DebugInstrNum; }
547
548 /// Set instruction number of this MachineInstr. Avoid using unless you're
549 /// deserializing this information.
550 void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
551
552 /// Drop any variable location debugging information associated with this
553 /// instruction. Use when an instruction is modified in such a way that it no
554 /// longer defines the value it used to. Variable locations using that value
555 /// will be dropped.
556 void dropDebugNumber() { DebugInstrNum = 0; }
557
558 /// For inline asm, get the !srcloc metadata node if we have it, and decode
559 /// the loc cookie from it.
560 const MDNode *getLocCookieMD() const;
561
562 /// Emit an error referring to the source location of this instruction. This
563 /// should only be used for inline assembly that is somehow impossible to
564 /// compile. Other errors should have been handled much earlier.
565 void emitInlineAsmError(const Twine &ErrMsg) const;
566
567 // Emit an error in the LLVMContext referring to the source location of this
568 // instruction, if available.
569 void emitGenericError(const Twine &ErrMsg) const;
570
571 /// Returns the target instruction descriptor of this MachineInstr.
572 const MCInstrDesc &getDesc() const { return *MCID; }
573
574 /// Returns the opcode of this MachineInstr.
575 unsigned getOpcode() const { return Opcode; }
576
577 /// Retuns the total number of operands.
578 unsigned getNumOperands() const { return NumOperands; }
579
580 /// Returns the total number of operands which are debug locations.
581 unsigned getNumDebugOperands() const {
582 return std::distance(debug_operands().begin(), debug_operands().end());
583 }
584
585 const MachineOperand& getOperand(unsigned i) const {
586 assert(i < getNumOperands() && "getOperand() out of range!");
587 return Operands[i];
588 }
590 assert(i < getNumOperands() && "getOperand() out of range!");
591 return Operands[i];
592 }
593
595 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
596 return *(debug_operands().begin() + Index);
597 }
598 const MachineOperand &getDebugOperand(unsigned Index) const {
599 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
600 return *(debug_operands().begin() + Index);
601 }
602
603 /// Returns whether this debug value has at least one debug operand with the
604 /// register \p Reg.
606 return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
607 return Op.isReg() && Op.getReg() == Reg;
608 });
609 }
610
611 /// Returns a range of all of the operands that correspond to a debug use of
612 /// \p Reg.
613 template <typename Operand, typename Instruction>
614 static iterator_range<
615 filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
617 std::function<bool(Operand & Op)> OpUsesReg(
618 [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
619 return make_filter_range(MI->debug_operands(), OpUsesReg);
620 }
622 std::function<bool(const MachineOperand &Op)>>>
625 const MachineInstr>(this, Reg);
626 }
628 std::function<bool(MachineOperand &Op)>>>
630 return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
631 this, Reg);
632 }
633
634 bool isDebugOperand(const MachineOperand *Op) const {
635 return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
636 }
637
638 unsigned getDebugOperandIndex(const MachineOperand *Op) const {
639 assert(isDebugOperand(Op) && "Expected a debug operand.");
640 return std::distance(adl_begin(debug_operands()), Op);
641 }
642
643 /// Returns the total number of definitions.
644 unsigned getNumDefs() const {
645 return getNumExplicitDefs() + MCID->implicit_defs().size();
646 }
647
648 /// Returns true if the instruction has implicit definition.
649 bool hasImplicitDef() const {
650 for (const MachineOperand &MO : implicit_operands())
651 if (MO.isDef())
652 return true;
653 return false;
654 }
655
656 /// Returns the implicit operands number.
657 unsigned getNumImplicitOperands() const {
659 }
660
661 /// Return true if operand \p OpIdx is a subregister index.
662 bool isOperandSubregIdx(unsigned OpIdx) const {
663 assert(getOperand(OpIdx).isImm() && "Expected MO_Immediate operand type.");
664 if (isExtractSubreg() && OpIdx == 2)
665 return true;
666 if (isInsertSubreg() && OpIdx == 3)
667 return true;
668 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
669 return true;
670 if (isSubregToReg() && OpIdx == 3)
671 return true;
672 return false;
673 }
674
675 /// Returns the number of non-implicit operands.
676 unsigned getNumExplicitOperands() const;
677
678 /// Returns the number of non-implicit definitions.
679 unsigned getNumExplicitDefs() const;
680
681 /// iterator/begin/end - Iterate over all operands of a machine instruction.
684
686 mop_iterator operands_end() { return Operands + NumOperands; }
687
689 const_mop_iterator operands_end() const { return Operands + NumOperands; }
690
693 }
696 }
698 return make_range(operands_begin(),
700 }
702 return make_range(operands_begin(),
704 }
706 return make_range(explicit_operands().end(), operands_end());
707 }
709 return make_range(explicit_operands().end(), operands_end());
710 }
711 /// Returns a range over all operands that are used to determine the variable
712 /// location for this DBG_VALUE instruction.
714 assert((isDebugValueLike()) && "Must be a debug value instruction.");
715 return isNonListDebugValue()
718 }
719 /// \copydoc debug_operands()
721 assert((isDebugValueLike()) && "Must be a debug value instruction.");
722 return isNonListDebugValue()
725 }
726 /// Returns a range over all explicit operands that are register definitions.
727 /// Implicit definition are not included!
729 return make_range(operands_begin(),
731 }
732 /// \copydoc defs()
734 return make_range(operands_begin(),
736 }
737 /// Returns a range that includes all operands which may be register uses.
738 /// This may include unrelated operands which are not register uses.
741 }
742 /// \copydoc uses()
745 }
749 }
753 }
754
759
760 /// Returns an iterator range over all operands that are (explicit or
761 /// implicit) register defs.
763 return make_filter_range(operands(), opIsRegDef);
764 }
765 /// \copydoc all_defs()
767 return make_filter_range(operands(), opIsRegDef);
768 }
769
770 /// Returns an iterator range over all operands that are (explicit or
771 /// implicit) register uses.
773 return make_filter_range(uses(), opIsRegUse);
774 }
775 /// \copydoc all_uses()
777 return make_filter_range(uses(), opIsRegUse);
778 }
779
780 /// Returns the number of the operand iterator \p I points to.
782 return I - operands_begin();
783 }
784
785 /// Access to memory operands of the instruction. If there are none, that does
786 /// not imply anything about whether the function accesses memory. Instead,
787 /// the caller must behave conservatively.
789 if (!Info)
790 return {};
791
792 if (Info.is<EIIK_MMO>())
793 return ArrayRef(Info.getAddrOfZeroTagPointer(), 1);
794
795 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
796 return EI->getMMOs();
797
798 return {};
799 }
800
801 /// Access to memory operands of the instruction.
802 ///
803 /// If `memoperands_begin() == memoperands_end()`, that does not imply
804 /// anything about whether the function accesses memory. Instead, the caller
805 /// must behave conservatively.
806 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
807
808 /// Access to memory operands of the instruction.
809 ///
810 /// If `memoperands_begin() == memoperands_end()`, that does not imply
811 /// anything about whether the function accesses memory. Instead, the caller
812 /// must behave conservatively.
813 mmo_iterator memoperands_end() const { return memoperands().end(); }
814
815 /// Return true if we don't have any memory operands which described the
816 /// memory access done by this instruction. If this is true, calling code
817 /// must be conservative.
818 bool memoperands_empty() const { return memoperands().empty(); }
819
820 /// Return true if this instruction has exactly one MachineMemOperand.
821 bool hasOneMemOperand() const { return memoperands().size() == 1; }
822
823 /// Return the number of memory operands.
824 unsigned getNumMemOperands() const { return memoperands().size(); }
825
826 /// Helper to extract a pre-instruction symbol if one has been added.
828 if (!Info)
829 return nullptr;
830 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
831 return S;
832 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
833 return EI->getPreInstrSymbol();
834
835 return nullptr;
836 }
837
838 /// Helper to extract a post-instruction symbol if one has been added.
840 if (!Info)
841 return nullptr;
842 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
843 return S;
844 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
845 return EI->getPostInstrSymbol();
846
847 return nullptr;
848 }
849
850 /// Helper to extract a heap alloc marker if one has been added.
852 if (!Info)
853 return nullptr;
854 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
855 return EI->getHeapAllocMarker();
856
857 return nullptr;
858 }
859
860 /// Helper to extract PCSections metadata target sections.
862 if (!Info)
863 return nullptr;
864 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
865 return EI->getPCSections();
866
867 return nullptr;
868 }
869
870 /// Helper to extract mmra.op metadata.
872 if (!Info)
873 return nullptr;
874 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
875 return EI->getMMRAMetadata();
876 return nullptr;
877 }
878
879 /// Helper to extract a CFI type hash if one has been added.
881 if (!Info)
882 return 0;
883 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
884 return EI->getCFIType();
885
886 return 0;
887 }
888
889 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
890 /// queries but they are bundle aware.
891
893 IgnoreBundle, // Ignore bundles
894 AnyInBundle, // Return true if any instruction in bundle has property
895 AllInBundle // Return true if all instructions in bundle have property
896 };
897
898 /// Return true if the instruction (or in the case of a bundle,
899 /// the instructions inside the bundle) has the specified property.
900 /// The first argument is the property being queried.
901 /// The second argument indicates whether the query should look inside
902 /// instruction bundles.
903 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
904 assert(MCFlag < 64 &&
905 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
906 // Inline the fast path for unbundled or bundle-internal instructions.
908 return getDesc().getFlags() & (1ULL << MCFlag);
909
910 // If this is the first instruction in a bundle, take the slow path.
911 return hasPropertyInBundle(1ULL << MCFlag, Type);
912 }
913
914 /// Return true if this is an instruction that should go through the usual
915 /// legalization steps.
918 }
919
920 /// Return true if this instruction can have a variable number of operands.
921 /// In this case, the variable operands will be after the normal
922 /// operands but before the implicit definitions and uses (if any are
923 /// present).
926 }
927
928 /// Set if this instruction has an optional definition, e.g.
929 /// ARM instructions which can set condition code if 's' bit is set.
932 }
933
934 /// Return true if this is a pseudo instruction that doesn't
935 /// correspond to a real machine instruction.
938 }
939
940 /// Return true if this instruction doesn't produce any output in the form of
941 /// executable instructions.
943 return hasProperty(MCID::Meta, Type);
944 }
945
948 }
949
950 /// Return true if this is an instruction that marks the end of an EH scope,
951 /// i.e., a catchpad or a cleanuppad instruction.
954 }
955
957 return hasProperty(MCID::Call, Type);
958 }
959
960 /// Return true if this is a call instruction that may have an additional
961 /// information associated with it.
963
964 /// Return true if copying, moving, or erasing this instruction requires
965 /// updating additional call info (see \ref copyCallInfo, \ref moveCallInfo,
966 /// \ref eraseCallInfo).
968
969 /// Returns true if the specified instruction stops control flow
970 /// from executing the instruction immediately following it. Examples include
971 /// unconditional branches and return instructions.
974 }
975
976 /// Returns true if this instruction part of the terminator for a basic block.
977 /// Typically this is things like return and branch instructions.
978 ///
979 /// Various passes use this to insert code into the bottom of a basic block,
980 /// but before control flow occurs.
983 }
984
985 /// Returns true if this is a conditional, unconditional, or indirect branch.
986 /// Predicates below can be used to discriminate between
987 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
988 /// get more information.
991 }
992
993 /// Return true if this is an indirect branch, such as a
994 /// branch through a register.
997 }
998
999 /// Return true if this is a branch which may fall
1000 /// through to the next instruction or may transfer control flow to some other
1001 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
1002 /// information about this branch.
1004 return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
1005 }
1006
1007 /// Return true if this is a branch which always
1008 /// transfers control flow to some other block. The
1009 /// TargetInstrInfo::analyzeBranch method can be used to get more information
1010 /// about this branch.
1013 }
1014
1015 /// Return true if this instruction has a predicate operand that
1016 /// controls execution. It may be set to 'always', or may be set to other
1017 /// values. There are various methods in TargetInstrInfo that can be used to
1018 /// control and modify the predicate in this instruction.
1020 // If it's a bundle than all bundled instructions must be predicable for this
1021 // to return true.
1023 }
1024
1025 /// Return true if this instruction is a comparison.
1028 }
1029
1030 /// Return true if this instruction is a move immediate
1031 /// (including conditional moves) instruction.
1034 }
1035
1036 /// Return true if this instruction is a register move.
1037 /// (including moving values from subreg to reg)
1040 }
1041
1042 /// Return true if this instruction is a bitcast instruction.
1045 }
1046
1047 /// Return true if this instruction is a select instruction.
1049 return hasProperty(MCID::Select, Type);
1050 }
1051
1052 /// Return true if this instruction cannot be safely duplicated.
1053 /// For example, if the instruction has a unique labels attached
1054 /// to it, duplicating it would cause multiple definition errors.
1057 return true;
1059 }
1060
1061 /// Return true if this instruction is convergent.
1062 /// Convergent instructions can not be made control-dependent on any
1063 /// additional values.
1065 if (isInlineAsm()) {
1066 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1067 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1068 return true;
1069 }
1070 if (getFlag(NoConvergent))
1071 return false;
1073 }
1074
1075 /// Returns true if the specified instruction has a delay slot
1076 /// which must be filled by the code generator.
1079 }
1080
1081 /// Return true for instructions that can be folded as
1082 /// memory operands in other instructions. The most common use for this
1083 /// is instructions that are simple loads from memory that don't modify
1084 /// the loaded value in any way, but it can also be used for instructions
1085 /// that can be expressed as constant-pool loads, such as V_SETALLONES
1086 /// on x86, to allow them to be folded when it is beneficial.
1087 /// This should only be set on instructions that return a value in their
1088 /// only virtual register definition.
1091 }
1092
1093 /// Return true if this instruction behaves
1094 /// the same way as the generic REG_SEQUENCE instructions.
1095 /// E.g., on ARM,
1096 /// dX VMOVDRR rY, rZ
1097 /// is equivalent to
1098 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
1099 ///
1100 /// Note that for the optimizers to be able to take advantage of
1101 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
1102 /// override accordingly.
1105 }
1106
1107 /// Return true if this instruction behaves
1108 /// the same way as the generic EXTRACT_SUBREG instructions.
1109 /// E.g., on ARM,
1110 /// rX, rY VMOVRRD dZ
1111 /// is equivalent to two EXTRACT_SUBREG:
1112 /// rX = EXTRACT_SUBREG dZ, ssub_0
1113 /// rY = EXTRACT_SUBREG dZ, ssub_1
1114 ///
1115 /// Note that for the optimizers to be able to take advantage of
1116 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
1117 /// override accordingly.
1120 }
1121
1122 /// Return true if this instruction behaves
1123 /// the same way as the generic INSERT_SUBREG instructions.
1124 /// E.g., on ARM,
1125 /// dX = VSETLNi32 dY, rZ, Imm
1126 /// is equivalent to a INSERT_SUBREG:
1127 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
1128 ///
1129 /// Note that for the optimizers to be able to take advantage of
1130 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
1131 /// override accordingly.
1134 }
1135
1136 //===--------------------------------------------------------------------===//
1137 // Side Effect Analysis
1138 //===--------------------------------------------------------------------===//
1139
1140 /// Return true if this instruction could possibly read memory.
1141 /// Instructions with this flag set are not necessarily simple load
1142 /// instructions, they may load a value and modify it, for example.
1144 if (isInlineAsm()) {
1145 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1146 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1147 return true;
1148 }
1150 }
1151
1152 /// Return true if this instruction could possibly modify memory.
1153 /// Instructions with this flag set are not necessarily simple store
1154 /// instructions, they may store a modified value based on their operands, or
1155 /// may not actually modify anything, for example.
1157 if (isInlineAsm()) {
1158 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1159 if (ExtraInfo & InlineAsm::Extra_MayStore)
1160 return true;
1161 }
1163 }
1164
1165 /// Return true if this instruction could possibly read or modify memory.
1167 return mayLoad(Type) || mayStore(Type);
1168 }
1169
1170 /// Return true if this instruction could possibly raise a floating-point
1171 /// exception. This is the case if the instruction is a floating-point
1172 /// instruction that can in principle raise an exception, as indicated
1173 /// by the MCID::MayRaiseFPException property, *and* at the same time,
1174 /// the instruction is used in a context where we expect floating-point
1175 /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
1176 bool mayRaiseFPException() const {
1179 }
1180
1181 //===--------------------------------------------------------------------===//
1182 // Flags that indicate whether an instruction can be modified by a method.
1183 //===--------------------------------------------------------------------===//
1184
1185 /// Return true if this may be a 2- or 3-address
1186 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
1187 /// result if Y and Z are exchanged. If this flag is set, then the
1188 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
1189 /// instruction.
1190 ///
1191 /// Note that this flag may be set on instructions that are only commutable
1192 /// sometimes. In these cases, the call to commuteInstruction will fail.
1193 /// Also note that some instructions require non-trivial modification to
1194 /// commute them.
1197 }
1198
1199 /// Return true if this is a 2-address instruction
1200 /// which can be changed into a 3-address instruction if needed. Doing this
1201 /// transformation can be profitable in the register allocator, because it
1202 /// means that the instruction can use a 2-address form if possible, but
1203 /// degrade into a less efficient form if the source and dest register cannot
1204 /// be assigned to the same register. For example, this allows the x86
1205 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1206 /// is the same speed as the shift but has bigger code size.
1207 ///
1208 /// If this returns true, then the target must implement the
1209 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1210 /// is allowed to fail if the transformation isn't valid for this specific
1211 /// instruction (e.g. shl reg, 4 on x86).
1212 ///
1215 }
1216
1217 /// Return true if this instruction requires
1218 /// custom insertion support when the DAG scheduler is inserting it into a
1219 /// machine basic block. If this is true for the instruction, it basically
1220 /// means that it is a pseudo instruction used at SelectionDAG time that is
1221 /// expanded out into magic code by the target when MachineInstrs are formed.
1222 ///
1223 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1224 /// is used to insert this into the MachineBasicBlock.
1227 }
1228
1229 /// Return true if this instruction requires *adjustment*
1230 /// after instruction selection by calling a target hook. For example, this
1231 /// can be used to fill in ARM 's' optional operand depending on whether
1232 /// the conditional flag register is used.
1235 }
1236
1237 /// Returns true if this instruction is a candidate for remat.
1238 /// This flag is deprecated, please don't use it anymore. If this
1239 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
1240 /// verify the instruction is really rematerializable.
1242 // It's only possible to re-mat a bundle if all bundled instructions are
1243 // re-materializable.
1245 }
1246
1247 /// Returns true if this instruction has the same cost (or less) than a move
1248 /// instruction. This is useful during certain types of optimizations
1249 /// (e.g., remat during two-address conversion or machine licm)
1250 /// where we would like to remat or hoist the instruction, but not if it costs
1251 /// more than moving the instruction into the appropriate register. Note, we
1252 /// are not marking copies from and to the same register class with this flag.
1254 // Only returns true for a bundle if all bundled instructions are cheap.
1256 }
1257
1258 /// Returns true if this instruction source operands
1259 /// have special register allocation requirements that are not captured by the
1260 /// operand register classes. e.g. ARM::STRD's two source registers must be an
1261 /// even / odd pair, ARM::STM registers have to be in ascending order.
1262 /// Post-register allocation passes should not attempt to change allocations
1263 /// for sources of instructions with this flag.
1266 }
1267
1268 /// Returns true if this instruction def operands
1269 /// have special register allocation requirements that are not captured by the
1270 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
1271 /// even / odd pair, ARM::LDM registers have to be in ascending order.
1272 /// Post-register allocation passes should not attempt to change allocations
1273 /// for definitions of instructions with this flag.
1276 }
1277
1279 CheckDefs, // Check all operands for equality
1280 CheckKillDead, // Check all operands including kill / dead markers
1281 IgnoreDefs, // Ignore all definitions
1282 IgnoreVRegDefs // Ignore virtual register definitions
1284
1285 /// Return true if this instruction is identical to \p Other.
1286 /// Two instructions are identical if they have the same opcode and all their
1287 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1288 /// Note that this means liveness related flags (dead, undef, kill) do not
1289 /// affect the notion of identical.
1290 bool isIdenticalTo(const MachineInstr &Other,
1291 MICheckType Check = CheckDefs) const;
1292
1293 /// Returns true if this instruction is a debug instruction that represents an
1294 /// identical debug value to \p Other.
1295 /// This function considers these debug instructions equivalent if they have
1296 /// identical variables, debug locations, and debug operands, and if the
1297 /// DIExpressions combined with the directness flags are equivalent.
1298 bool isEquivalentDbgInstr(const MachineInstr &Other) const;
1299
1300 /// Unlink 'this' from the containing basic block, and return it without
1301 /// deleting it.
1302 ///
1303 /// This function can not be used on bundled instructions, use
1304 /// removeFromBundle() to remove individual instructions from a bundle.
1306
1307 /// Unlink this instruction from its basic block and return it without
1308 /// deleting it.
1309 ///
1310 /// If the instruction is part of a bundle, the other instructions in the
1311 /// bundle remain bundled.
1313
1314 /// Unlink 'this' from the containing basic block and delete it.
1315 ///
1316 /// If this instruction is the header of a bundle, the whole bundle is erased.
1317 /// This function can not be used for instructions inside a bundle, use
1318 /// eraseFromBundle() to erase individual bundled instructions.
1319 void eraseFromParent();
1320
1321 /// Unlink 'this' from its basic block and delete it.
1322 ///
1323 /// If the instruction is part of a bundle, the other instructions in the
1324 /// bundle remain bundled.
1325 void eraseFromBundle();
1326
1327 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1328 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1329 bool isAnnotationLabel() const {
1330 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1331 }
1332
1333 bool isLifetimeMarker() const {
1334 return getOpcode() == TargetOpcode::LIFETIME_START ||
1335 getOpcode() == TargetOpcode::LIFETIME_END;
1336 }
1337
1338 /// Returns true if the MachineInstr represents a label.
1339 bool isLabel() const {
1340 return isEHLabel() || isGCLabel() || isAnnotationLabel();
1341 }
1342
1343 bool isCFIInstruction() const {
1344 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1345 }
1346
1347 bool isPseudoProbe() const {
1348 return getOpcode() == TargetOpcode::PSEUDO_PROBE;
1349 }
1350
1351 // True if the instruction represents a position in the function.
1352 bool isPosition() const { return isLabel() || isCFIInstruction(); }
1353
1354 bool isNonListDebugValue() const {
1355 return getOpcode() == TargetOpcode::DBG_VALUE;
1356 }
1357 bool isDebugValueList() const {
1358 return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1359 }
1360 bool isDebugValue() const {
1362 }
1363 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1364 bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1365 bool isDebugValueLike() const { return isDebugValue() || isDebugRef(); }
1366 bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
1367 bool isDebugInstr() const {
1368 return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
1369 }
1371 return isDebugInstr() || isPseudoProbe();
1372 }
1373
1374 bool isDebugOffsetImm() const {
1376 }
1377
1378 /// A DBG_VALUE is indirect iff the location operand is a register and
1379 /// the offset operand is an immediate.
1381 return isDebugOffsetImm() && getDebugOperand(0).isReg();
1382 }
1383
1384 /// A DBG_VALUE is an entry value iff its debug expression contains the
1385 /// DW_OP_LLVM_entry_value operation.
1386 bool isDebugEntryValue() const;
1387
1388 /// Return true if the instruction is a debug value which describes a part of
1389 /// a variable as unavailable.
1390 bool isUndefDebugValue() const {
1391 if (!isDebugValue())
1392 return false;
1393 // If any $noreg locations are given, this DV is undef.
1394 for (const MachineOperand &Op : debug_operands())
1395 if (Op.isReg() && !Op.getReg().isValid())
1396 return true;
1397 return false;
1398 }
1399
1401 return getOpcode() == TargetOpcode::JUMP_TABLE_DEBUG_INFO;
1402 }
1403
1404 bool isPHI() const {
1405 return getOpcode() == TargetOpcode::PHI ||
1406 getOpcode() == TargetOpcode::G_PHI;
1407 }
1408 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1409 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1410 bool isInlineAsm() const {
1411 return getOpcode() == TargetOpcode::INLINEASM ||
1412 getOpcode() == TargetOpcode::INLINEASM_BR;
1413 }
1414 /// Returns true if the register operand can be folded with a load or store
1415 /// into a frame index. Does so by checking the InlineAsm::Flag immediate
1416 /// operand at OpId - 1.
1417 bool mayFoldInlineAsmRegOp(unsigned OpId) const;
1418
1419 bool isStackAligningInlineAsm() const;
1421
1422 bool isInsertSubreg() const {
1423 return getOpcode() == TargetOpcode::INSERT_SUBREG;
1424 }
1425
1426 bool isSubregToReg() const {
1427 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1428 }
1429
1430 bool isRegSequence() const {
1431 return getOpcode() == TargetOpcode::REG_SEQUENCE;
1432 }
1433
1434 bool isBundle() const {
1435 return getOpcode() == TargetOpcode::BUNDLE;
1436 }
1437
1438 bool isCopy() const {
1439 return getOpcode() == TargetOpcode::COPY;
1440 }
1441
1442 bool isFullCopy() const {
1443 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1444 }
1445
1446 bool isExtractSubreg() const {
1447 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1448 }
1449
1450 bool isFakeUse() const { return getOpcode() == TargetOpcode::FAKE_USE; }
1451
1452 /// Return true if the instruction behaves like a copy.
1453 /// This does not include native copy instructions.
1454 bool isCopyLike() const {
1455 return isCopy() || isSubregToReg();
1456 }
1457
1458 /// Return true is the instruction is an identity copy.
1459 bool isIdentityCopy() const {
1460 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1462 }
1463
1464 /// Return true if this is a transient instruction that is either very likely
1465 /// to be eliminated during register allocation (such as copy-like
1466 /// instructions), or if this instruction doesn't have an execution-time cost.
1467 bool isTransient() const {
1468 switch (getOpcode()) {
1469 default:
1470 return isMetaInstruction();
1471 // Copy-like instructions are usually eliminated during register allocation.
1472 case TargetOpcode::PHI:
1473 case TargetOpcode::G_PHI:
1474 case TargetOpcode::COPY:
1475 case TargetOpcode::INSERT_SUBREG:
1476 case TargetOpcode::SUBREG_TO_REG:
1477 case TargetOpcode::REG_SEQUENCE:
1478 return true;
1479 }
1480 }
1481
1482 /// Return the number of instructions inside the MI bundle, excluding the
1483 /// bundle header.
1484 ///
1485 /// This is the number of instructions that MachineBasicBlock::iterator
1486 /// skips, 0 for unbundled instructions.
1487 unsigned getBundleSize() const;
1488
1489 /// Return true if the MachineInstr reads the specified register.
1490 /// If TargetRegisterInfo is non-null, then it also checks if there
1491 /// is a read of a super-register.
1492 /// This does not count partial redefines of virtual registers as reads:
1493 /// %reg1024:6 = OP.
1495 return findRegisterUseOperandIdx(Reg, TRI, false) != -1;
1496 }
1497
1498 /// Return true if the MachineInstr reads the specified virtual register.
1499 /// Take into account that a partial define is a
1500 /// read-modify-write operation.
1502 return readsWritesVirtualRegister(Reg).first;
1503 }
1504
1505 /// Return a pair of bools (reads, writes) indicating if this instruction
1506 /// reads or writes Reg. This also considers partial defines.
1507 /// If Ops is not null, all operand indices for Reg are added.
1508 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1509 SmallVectorImpl<unsigned> *Ops = nullptr) const;
1510
1511 /// Return true if the MachineInstr kills the specified register.
1512 /// If TargetRegisterInfo is non-null, then it also checks if there is
1513 /// a kill of a super-register.
1515 return findRegisterUseOperandIdx(Reg, TRI, true) != -1;
1516 }
1517
1518 /// Return true if the MachineInstr fully defines the specified register.
1519 /// If TargetRegisterInfo is non-null, then it also checks
1520 /// if there is a def of a super-register.
1521 /// NOTE: It's ignoring subreg indices on virtual registers.
1523 return findRegisterDefOperandIdx(Reg, TRI, false, false) != -1;
1524 }
1525
1526 /// Return true if the MachineInstr modifies (fully define or partially
1527 /// define) the specified register.
1528 /// NOTE: It's ignoring subreg indices on virtual registers.
1530 return findRegisterDefOperandIdx(Reg, TRI, false, true) != -1;
1531 }
1532
1533 /// Returns true if the register is dead in this machine instruction.
1534 /// If TargetRegisterInfo is non-null, then it also checks
1535 /// if there is a dead def of a super-register.
1537 return findRegisterDefOperandIdx(Reg, TRI, true, false) != -1;
1538 }
1539
1540 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1541 /// the given register (not considering sub/super-registers).
1543
1544 /// Returns the operand index that is a use of the specific register or -1
1545 /// if it is not found. It further tightens the search criteria to a use
1546 /// that kills the register if isKill is true.
1548 bool isKill = false) const;
1549
1550 /// Wrapper for findRegisterUseOperandIdx, it returns
1551 /// a pointer to the MachineOperand rather than an index.
1553 const TargetRegisterInfo *TRI,
1554 bool isKill = false) {
1556 return (Idx == -1) ? nullptr : &getOperand(Idx);
1557 }
1558
1560 const TargetRegisterInfo *TRI,
1561 bool isKill = false) const {
1562 return const_cast<MachineInstr *>(this)->findRegisterUseOperand(Reg, TRI,
1563 isKill);
1564 }
1565
1566 /// Returns the operand index that is a def of the specified register or
1567 /// -1 if it is not found. If isDead is true, defs that are not dead are
1568 /// skipped. If Overlap is true, then it also looks for defs that merely
1569 /// overlap the specified register. If TargetRegisterInfo is non-null,
1570 /// then it also checks if there is a def of a super-register.
1571 /// This may also return a register mask operand when Overlap is true.
1573 bool isDead = false,
1574 bool Overlap = false) const;
1575
1576 /// Wrapper for findRegisterDefOperandIdx, it returns
1577 /// a pointer to the MachineOperand rather than an index.
1579 const TargetRegisterInfo *TRI,
1580 bool isDead = false,
1581 bool Overlap = false) {
1582 int Idx = findRegisterDefOperandIdx(Reg, TRI, isDead, Overlap);
1583 return (Idx == -1) ? nullptr : &getOperand(Idx);
1584 }
1585
1587 const TargetRegisterInfo *TRI,
1588 bool isDead = false,
1589 bool Overlap = false) const {
1590 return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1591 Reg, TRI, isDead, Overlap);
1592 }
1593
1594 /// Find the index of the first operand in the
1595 /// operand list that is used to represent the predicate. It returns -1 if
1596 /// none is found.
1597 int findFirstPredOperandIdx() const;
1598
1599 /// Find the index of the flag word operand that
1600 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1601 /// getOperand(OpIdx) does not belong to an inline asm operand group.
1602 ///
1603 /// If GroupNo is not NULL, it will receive the number of the operand group
1604 /// containing OpIdx.
1605 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1606
1607 /// Compute the static register class constraint for operand OpIdx.
1608 /// For normal instructions, this is derived from the MCInstrDesc.
1609 /// For inline assembly it is derived from the flag words.
1610 ///
1611 /// Returns NULL if the static register class constraint cannot be
1612 /// determined.
1613 const TargetRegisterClass*
1614 getRegClassConstraint(unsigned OpIdx,
1615 const TargetInstrInfo *TII,
1616 const TargetRegisterInfo *TRI) const;
1617
1618 /// Applies the constraints (def/use) implied by this MI on \p Reg to
1619 /// the given \p CurRC.
1620 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1621 /// instructions inside the bundle will be taken into account. In other words,
1622 /// this method accumulates all the constraints of the operand of this MI and
1623 /// the related bundle if MI is a bundle or inside a bundle.
1624 ///
1625 /// Returns the register class that satisfies both \p CurRC and the
1626 /// constraints set by MI. Returns NULL if such a register class does not
1627 /// exist.
1628 ///
1629 /// \pre CurRC must not be NULL.
1631 Register Reg, const TargetRegisterClass *CurRC,
1633 bool ExploreBundle = false) const;
1634
1635 /// Applies the constraints (def/use) implied by the \p OpIdx operand
1636 /// to the given \p CurRC.
1637 ///
1638 /// Returns the register class that satisfies both \p CurRC and the
1639 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1640 /// does not exist.
1641 ///
1642 /// \pre CurRC must not be NULL.
1643 /// \pre The operand at \p OpIdx must be a register.
1644 const TargetRegisterClass *
1645 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1646 const TargetInstrInfo *TII,
1647 const TargetRegisterInfo *TRI) const;
1648
1649 /// Add a tie between the register operands at DefIdx and UseIdx.
1650 /// The tie will cause the register allocator to ensure that the two
1651 /// operands are assigned the same physical register.
1652 ///
1653 /// Tied operands are managed automatically for explicit operands in the
1654 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1655 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1656
1657 /// Given the index of a tied register operand, find the
1658 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1659 /// index of the tied operand which must exist.
1660 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1661
1662 /// Given the index of a register def operand,
1663 /// check if the register def is tied to a source operand, due to either
1664 /// two-address elimination or inline assembly constraints. Returns the
1665 /// first tied use operand index by reference if UseOpIdx is not null.
1666 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1667 unsigned *UseOpIdx = nullptr) const {
1668 const MachineOperand &MO = getOperand(DefOpIdx);
1669 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1670 return false;
1671 if (UseOpIdx)
1672 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1673 return true;
1674 }
1675
1676 /// Return true if the use operand of the specified index is tied to a def
1677 /// operand. It also returns the def operand index by reference if DefOpIdx
1678 /// is not null.
1679 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1680 unsigned *DefOpIdx = nullptr) const {
1681 const MachineOperand &MO = getOperand(UseOpIdx);
1682 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1683 return false;
1684 if (DefOpIdx)
1685 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1686 return true;
1687 }
1688
1689 /// Clears kill flags on all operands.
1690 void clearKillInfo();
1691
1692 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1693 /// properly composing subreg indices where necessary.
1694 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1696
1697 /// We have determined MI kills a register. Look for the
1698 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1699 /// add a implicit operand if it's not found. Returns true if the operand
1700 /// exists / is added.
1701 bool addRegisterKilled(Register IncomingReg,
1703 bool AddIfNotFound = false);
1704
1705 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1706 /// all aliasing registers.
1708
1709 /// We have determined MI defined a register without a use.
1710 /// Look for the operand that defines it and mark it as IsDead. If
1711 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1712 /// true if the operand exists / is added.
1714 bool AddIfNotFound = false);
1715
1716 /// Clear all dead flags on operands defining register @p Reg.
1718
1719 /// Mark all subregister defs of register @p Reg with the undef flag.
1720 /// This function is used when we determined to have a subregister def in an
1721 /// otherwise undefined super register.
1722 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1723
1724 /// We have determined MI defines a register. Make sure there is an operand
1725 /// defining Reg.
1727 const TargetRegisterInfo *RegInfo = nullptr);
1728
1729 /// Mark every physreg used by this instruction as
1730 /// dead except those in the UsedRegs list.
1731 ///
1732 /// On instructions with register mask operands, also add implicit-def
1733 /// operands for all registers in UsedRegs.
1735 const TargetRegisterInfo &TRI);
1736
1737 /// Return true if it is safe to move this instruction. If
1738 /// SawStore is set to true, it means that there is a store (or call) between
1739 /// the instruction's location and its intended destination.
1740 bool isSafeToMove(bool &SawStore) const;
1741
1742 /// Return true if this instruction would be trivially dead if all of its
1743 /// defined registers were dead.
1744 bool wouldBeTriviallyDead() const;
1745
1746 /// Returns true if this instruction's memory access aliases the memory
1747 /// access of Other.
1748 //
1749 /// Assumes any physical registers used to compute addresses
1750 /// have the same value for both instructions. Returns false if neither
1751 /// instruction writes to memory.
1752 ///
1753 /// @param AA Optional alias analysis, used to compare memory operands.
1754 /// @param Other MachineInstr to check aliasing against.
1755 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1756 bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1757
1758 /// Return true if this instruction may have an ordered
1759 /// or volatile memory reference, or if the information describing the memory
1760 /// reference is not available. Return false if it is known to have no
1761 /// ordered or volatile memory references.
1762 bool hasOrderedMemoryRef() const;
1763
1764 /// Return true if this load instruction never traps and points to a memory
1765 /// location whose value doesn't change during the execution of this function.
1766 ///
1767 /// Examples include loading a value from the constant pool or from the
1768 /// argument area of a function (if it does not change). If the instruction
1769 /// does multiple loads, this returns true only if all of the loads are
1770 /// dereferenceable and invariant.
1771 bool isDereferenceableInvariantLoad() const;
1772
1773 /// If the specified instruction is a PHI that always merges together the
1774 /// same virtual register, return the register, otherwise return Register().
1776
1777 /// Return true if this instruction has side effects that are not modeled
1778 /// by mayLoad / mayStore, etc.
1779 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1780 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1781 /// INLINEASM instruction, in which case the side effect property is encoded
1782 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1783 ///
1784 bool hasUnmodeledSideEffects() const;
1785
1786 /// Returns true if it is illegal to fold a load across this instruction.
1787 bool isLoadFoldBarrier() const;
1788
1789 /// Return true if all the defs of this instruction are dead.
1790 bool allDefsAreDead() const;
1791
1792 /// Return true if all the implicit defs of this instruction are dead.
1793 bool allImplicitDefsAreDead() const;
1794
1795 /// Return a valid size if the instruction is a spill instruction.
1796 std::optional<LocationSize> getSpillSize(const TargetInstrInfo *TII) const;
1797
1798 /// Return a valid size if the instruction is a folded spill instruction.
1799 std::optional<LocationSize>
1801
1802 /// Return a valid size if the instruction is a restore instruction.
1803 std::optional<LocationSize> getRestoreSize(const TargetInstrInfo *TII) const;
1804
1805 /// Return a valid size if the instruction is a folded restore instruction.
1806 std::optional<LocationSize>
1808
1809 /// Copy implicit register operands from specified
1810 /// instruction to this instruction.
1812
1813 /// Debugging support
1814 /// @{
1815 /// Determine the generic type to be printed (if needed) on uses and defs.
1816 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1817 const MachineRegisterInfo &MRI) const;
1818
1819 /// Return true when an instruction has tied register that can't be determined
1820 /// by the instruction's descriptor. This is useful for MIR printing, to
1821 /// determine whether we need to print the ties or not.
1822 bool hasComplexRegisterTies() const;
1823
1824 /// Print this MI to \p OS.
1825 /// Don't print information that can be inferred from other instructions if
1826 /// \p IsStandalone is false. It is usually true when only a fragment of the
1827 /// function is printed.
1828 /// Only print the defs and the opcode if \p SkipOpers is true.
1829 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1830 /// Otherwise, also print the debug loc, with a terminating newline.
1831 /// \p TII is used to print the opcode name. If it's not present, but the
1832 /// MI is in a function, the opcode will be printed using the function's TII.
1833 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1834 bool SkipDebugLoc = false, bool AddNewLine = true,
1835 const TargetInstrInfo *TII = nullptr) const;
1836 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1837 bool SkipOpers = false, bool SkipDebugLoc = false,
1838 bool AddNewLine = true,
1839 const TargetInstrInfo *TII = nullptr) const;
1840 void dump() const;
1841 /// Print on dbgs() the current instruction and the instructions defining its
1842 /// operands and so on until we reach \p MaxDepth.
1843 void dumpr(const MachineRegisterInfo &MRI,
1844 unsigned MaxDepth = UINT_MAX) const;
1845 /// @}
1846
1847 //===--------------------------------------------------------------------===//
1848 // Accessors used to build up machine instructions.
1849
1850 /// Add the specified operand to the instruction. If it is an implicit
1851 /// operand, it is added to the end of the operand list. If it is an
1852 /// explicit operand it is added at the end of the explicit operand list
1853 /// (before the first implicit operand).
1854 ///
1855 /// MF must be the machine function that was used to allocate this
1856 /// instruction.
1857 ///
1858 /// MachineInstrBuilder provides a more convenient interface for creating
1859 /// instructions and adding operands.
1860 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1861
1862 /// Add an operand without providing an MF reference. This only works for
1863 /// instructions that are inserted in a basic block.
1864 ///
1865 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1866 /// preferred.
1867 void addOperand(const MachineOperand &Op);
1868
1869 /// Inserts Ops BEFORE It. Can untie/retie tied operands.
1870 void insert(mop_iterator InsertBefore, ArrayRef<MachineOperand> Ops);
1871
1872 /// Replace the instruction descriptor (thus opcode) of
1873 /// the current instruction with a new one.
1874 void setDesc(const MCInstrDesc &TID);
1875
1876 /// Replace current source information with new such.
1877 /// Avoid using this, the constructor argument is preferable.
1879 DbgLoc = std::move(DL);
1880 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
1881 }
1882
1883 /// Erase an operand from an instruction, leaving it with one
1884 /// fewer operand than it started with.
1885 void removeOperand(unsigned OpNo);
1886
1887 /// Clear this MachineInstr's memory reference descriptor list. This resets
1888 /// the memrefs to their most conservative state. This should be used only
1889 /// as a last resort since it greatly pessimizes our knowledge of the memory
1890 /// access performed by the instruction.
1891 void dropMemRefs(MachineFunction &MF);
1892
1893 /// Assign this MachineInstr's memory reference descriptor list.
1894 ///
1895 /// Unlike other methods, this *will* allocate them into a new array
1896 /// associated with the provided `MachineFunction`.
1898
1899 /// Add a MachineMemOperand to the machine instruction.
1900 /// This function should be used only occasionally. The setMemRefs function
1901 /// is the primary method for setting up a MachineInstr's MemRefs list.
1903
1904 /// Clone another MachineInstr's memory reference descriptor list and replace
1905 /// ours with it.
1906 ///
1907 /// Note that `*this` may be the incoming MI!
1908 ///
1909 /// Prefer this API whenever possible as it can avoid allocations in common
1910 /// cases.
1911 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1912
1913 /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1914 /// list and replace ours with it.
1915 ///
1916 /// Note that `*this` may be one of the incoming MIs!
1917 ///
1918 /// Prefer this API whenever possible as it can avoid allocations in common
1919 /// cases.
1922
1923 /// Set a symbol that will be emitted just prior to the instruction itself.
1924 ///
1925 /// Setting this to a null pointer will remove any such symbol.
1926 ///
1927 /// FIXME: This is not fully implemented yet.
1928 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1929
1930 /// Set a symbol that will be emitted just after the instruction itself.
1931 ///
1932 /// Setting this to a null pointer will remove any such symbol.
1933 ///
1934 /// FIXME: This is not fully implemented yet.
1935 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1936
1937 /// Clone another MachineInstr's pre- and post- instruction symbols and
1938 /// replace ours with it.
1940
1941 /// Set a marker on instructions that denotes where we should create and emit
1942 /// heap alloc site labels. This waits until after instruction selection and
1943 /// optimizations to create the label, so it should still work if the
1944 /// instruction is removed or duplicated.
1946
1947 // Set metadata on instructions that say which sections to emit instruction
1948 // addresses into.
1949 void setPCSections(MachineFunction &MF, MDNode *MD);
1950
1951 void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs);
1952
1953 /// Set the CFI type for the instruction.
1955
1956 /// Return the MIFlags which represent both MachineInstrs. This
1957 /// should be used when merging two MachineInstrs into one. This routine does
1958 /// not modify the MIFlags of this MachineInstr.
1960
1962
1963 /// Copy all flags to MachineInst MIFlags
1964 void copyIRFlags(const Instruction &I);
1965
1966 /// Break any tie involving OpIdx.
1967 void untieRegOperand(unsigned OpIdx) {
1968 MachineOperand &MO = getOperand(OpIdx);
1969 if (MO.isReg() && MO.isTied()) {
1970 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1971 MO.TiedTo = 0;
1972 }
1973 }
1974
1975 /// Add all implicit def and use operands to this instruction.
1977
1978 /// Scan instructions immediately following MI and collect any matching
1979 /// DBG_VALUEs.
1981
1982 /// Find all DBG_VALUEs that point to the register def in this instruction
1983 /// and point them to \p Reg instead.
1985
1986 /// Sets all register debug operands in this debug value instruction to be
1987 /// undef.
1989 assert(isDebugValue() && "Must be a debug value instruction.");
1990 for (MachineOperand &MO : debug_operands()) {
1991 if (MO.isReg()) {
1992 MO.setReg(0);
1993 MO.setSubReg(0);
1994 }
1995 }
1996 }
1997
1998 std::tuple<Register, Register> getFirst2Regs() const {
1999 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg());
2000 }
2001
2002 std::tuple<Register, Register, Register> getFirst3Regs() const {
2003 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
2004 getOperand(2).getReg());
2005 }
2006
2007 std::tuple<Register, Register, Register, Register> getFirst4Regs() const {
2008 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
2009 getOperand(2).getReg(), getOperand(3).getReg());
2010 }
2011
2012 std::tuple<Register, Register, Register, Register, Register>
2014 return std::tuple(getOperand(0).getReg(), getOperand(1).getReg(),
2016 getOperand(4).getReg());
2017 }
2018
2019 std::tuple<LLT, LLT> getFirst2LLTs() const;
2020 std::tuple<LLT, LLT, LLT> getFirst3LLTs() const;
2021 std::tuple<LLT, LLT, LLT, LLT> getFirst4LLTs() const;
2022 std::tuple<LLT, LLT, LLT, LLT, LLT> getFirst5LLTs() const;
2023
2024 std::tuple<Register, LLT, Register, LLT> getFirst2RegLLTs() const;
2025 std::tuple<Register, LLT, Register, LLT, Register, LLT>
2026 getFirst3RegLLTs() const;
2027 std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2028 getFirst4RegLLTs() const;
2029 std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT,
2030 Register, LLT>
2031 getFirst5RegLLTs() const;
2032
2033private:
2034 /// If this instruction is embedded into a MachineFunction, return the
2035 /// MachineRegisterInfo object for the current function, otherwise
2036 /// return null.
2037 MachineRegisterInfo *getRegInfo();
2038 const MachineRegisterInfo *getRegInfo() const;
2039
2040 /// Unlink all of the register operands in this instruction from their
2041 /// respective use lists. This requires that the operands already be on their
2042 /// use lists.
2043 void removeRegOperandsFromUseLists(MachineRegisterInfo&);
2044
2045 /// Add all of the register operands in this instruction from their
2046 /// respective use lists. This requires that the operands not be on their
2047 /// use lists yet.
2048 void addRegOperandsToUseLists(MachineRegisterInfo&);
2049
2050 /// Slow path for hasProperty when we're dealing with a bundle.
2051 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
2052
2053 /// Implements the logic of getRegClassConstraintEffectForVReg for the
2054 /// this MI and the given operand index \p OpIdx.
2055 /// If the related operand does not constrained Reg, this returns CurRC.
2056 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
2057 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
2058 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
2059
2060 /// Stores extra instruction information inline or allocates as ExtraInfo
2061 /// based on the number of pointers.
2062 void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
2063 MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
2064 MDNode *HeapAllocMarker, MDNode *PCSections,
2065 uint32_t CFIType, MDNode *MMRAs);
2066};
2067
2068/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
2069/// instruction rather than by pointer value.
2070/// The hashing and equality testing functions ignore definitions so this is
2071/// useful for CSE, etc.
2073 static inline MachineInstr *getEmptyKey() {
2074 return nullptr;
2075 }
2076
2078 return reinterpret_cast<MachineInstr*>(-1);
2079 }
2080
2081 static unsigned getHashValue(const MachineInstr* const &MI);
2082
2083 static bool isEqual(const MachineInstr* const &LHS,
2084 const MachineInstr* const &RHS) {
2085 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
2086 LHS == getEmptyKey() || LHS == getTombstoneKey())
2087 return LHS == RHS;
2088 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
2089 }
2090};
2091
2092//===----------------------------------------------------------------------===//
2093// Debugging Support
2094
2096 MI.print(OS);
2097 return OS;
2098}
2099
2100} // end namespace llvm
2101
2102#endif // LLVM_CODEGEN_MACHINEINSTR_H
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines DenseMapInfo traits for DenseMap.
uint32_t Index
#define Check(C,...)
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
#define LLVM_MI_ASMPRINTERFLAGS_BITS
Definition: MachineInstr.h:134
#define LLVM_MI_FLAGS_BITS
Definition: MachineInstr.h:133
#define LLVM_MI_NUMOPERANDS_BITS
Definition: MachineInstr.h:132
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Promote Memory to Register
Definition: Mem2Reg.cpp:110
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
#define P(N)
Basic Register Allocator
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
bool isDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
raw_pwrite_stream & OS
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
This header defines support for implementing classes that have some trailing object (or arrays of obj...
Value * RHS
Value * LHS
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
DWARF expression.
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:251
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:579
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
Metadata node.
Definition: Metadata.h:1069
Representation of each machine instruction.
Definition: MachineInstr.h:69
mop_iterator operands_begin()
Definition: MachineInstr.h:685
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
std::tuple< Register, Register, Register, Register, Register > getFirst5Regs() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:575
unsigned getNumImplicitOperands() const
Returns the implicit operands number.
Definition: MachineInstr.h:657
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:946
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:616
bool hasDebugOperandForReg(Register Reg) const
Returns whether this debug value has at least one debug operand with the register Reg.
Definition: MachineInstr.h:605
bool isDebugValueList() const
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:746
void bundleWithPred()
Bundle this instruction with its predecessor.
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:77
bool isPosition() const
void setDebugValueUndef()
Sets all register debug operands in this debug value instruction to be undef.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:981
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
std::tuple< Register, Register, Register, Register > getFirst4Regs() const
bool isImplicitDef() const
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands which may be register uses.
Definition: MachineInstr.h:743
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
bool isCopy() const
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:368
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:713
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:347
bool isCopyLike() const
Return true if the instruction behaves like a copy.
void dropDebugNumber()
Drop any variable location debugging information associated with this instruction.
Definition: MachineInstr.h:556
MDNode * getMMRAMetadata() const
Helper to extract mmra.op metadata.
Definition: MachineInstr.h:871
void bundleWithSucc()
Bundle this instruction with its successor.
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
Definition: MachineInstr.h:880
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr reads the specified register.
bool isDebugLabel() const
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool isDebugOffsetImm() const
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:903
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void setFlags(unsigned flags)
Definition: MachineInstr.h:410
MachineFunction * getMF()
Definition: MachineInstr.h:359
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:892
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:972
std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const
MachineBasicBlock * getParent()
Definition: MachineInstr.h:348
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:956
std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:397
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:385
uint32_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Register isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands which may be register uses.
Definition: MachineInstr.h:739
bool allImplicitDefsAreDead() const
Return true if all the implicit defs of this instruction are dead.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:750
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
bool isSafeToMove(bool &SawStore) const
Return true if it is safe to move this instruction.
iterator_range< filtered_mop_iterator > all_uses()
Returns an iterator range over all operands that are (explicit or implicit) register uses.
Definition: MachineInstr.h:772
bool isBundle() const
bool isDebugInstr() const
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
Definition: MachineInstr.h:581
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:578
void setDebugInstrNum(unsigned Num)
Set instruction number of this MachineInstr.
Definition: MachineInstr.h:550
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:701
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
const MachineOperand * const_mop_iterator
Definition: MachineInstr.h:683
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:371
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
bool isDebugValueLike() const
bool isInlineAsm() const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:818
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:813
bool isDebugRef() const
bool isAnnotationLabel() const
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
MachineOperand & getDebugOffset()
Definition: MachineInstr.h:508
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:697
unsigned peekDebugInstrNum() const
Examine the instruction number of this MachineInstr.
Definition: MachineInstr.h:546
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:733
std::optional< LocationSize > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:781
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isSubregToReg() const
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
bool hasImplicitDef() const
Returns true if the instruction has implicit definition.
Definition: MachineInstr.h:649
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:989
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
bool wouldBeTriviallyDead() const
Return true if this instruction would be trivially dead if all of its defined registers were dead.
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:478
bool isDebugPHI() const
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:589
std::tuple< LLT, LLT > getFirst2LLTs() const
std::optional< LocationSize > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
const_mop_iterator operands_end() const
Definition: MachineInstr.h:689
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
void unbundleFromPred()
Break bundle above this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:378
bool isDebugOrPseudoInstr() const
bool isStackAligningInlineAsm() const
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand,...
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
mop_iterator operands_end()
Definition: MachineInstr.h:686
bool isFullCopy() const
int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
Definition: MachineInstr.h:861
bool isCFIInstruction() const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:572
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
void clearFlags(unsigned flags)
Definition: MachineInstr.h:425
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
iterator_range< filtered_const_mop_iterator > all_uses() const
Returns an iterator range over all operands that are (explicit or implicit) register uses.
Definition: MachineInstr.h:776
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
MachineInstr & operator=(const MachineInstr &)=delete
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
iterator_range< const_mop_iterator > debug_operands() const
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:720
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
bool isCandidateForAdditionalCallInfo(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an additional information associated with it.
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr kills the specified register.
std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:824
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:419
bool isGCLabel() const
std::optional< LocationSize > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:365
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:662
InlineAsm::AsmDialect getInlineAsmDialect() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isEquivalentDbgInstr(const MachineInstr &Other) const
Returns true if this instruction is a debug instruction that represents an identical debug value to O...
bool isRegSequence() const
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const
Returns true if the register is dead in this machine instruction.
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:688
static uint32_t copyFlagsFromInstruction(const Instruction &I)
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr fully defines the specified register.
void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)
Inserts Ops BEFORE It. Can untie/retie tied operands.
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
const MachineOperand * findRegisterUseOperand(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const
bool isJumpTableDebugInfo() const
std::tuple< Register, Register, Register > getFirst3Regs() const
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' from its basic block and delete it.
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:821
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:691
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
bool isMoveReg(QueryType Type=IgnoreBundle) const
Return true if this instruction is a register move.
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
bool isInsertSubreg() const
iterator_range< filtered_const_mop_iterator > all_defs() const
Returns an iterator range over all operands that are (explicit or implicit) register defs.
Definition: MachineInstr.h:766
bool isLifetimeMarker() const
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
iterator_range< filter_iterator< MachineOperand *, std::function< bool(MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg)
Definition: MachineInstr.h:629
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:728
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:806
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:466
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
void emitGenericError(const Twine &ErrMsg) const
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:694
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:788
bool isLabel() const
Returns true if the MachineInstr represents a label.
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool isExtractSubreg() const
bool isNonListDebugValue() const
MachineOperand * mop_iterator
iterator/begin/end - Iterate over all operands of a machine instruction.
Definition: MachineInstr.h:682
MachineOperand * findRegisterUseOperand(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:404
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:499
std::tuple< LLT, LLT, LLT > getFirst3LLTs() const
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction.
bool isPreISelOpcode(QueryType Type=IgnoreBundle) const
Return true if this is an instruction that should go through the usual legalization steps.
Definition: MachineInstr.h:916
bool isEHScopeReturn(QueryType Type=AnyInBundle) const
Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanu...
Definition: MachineInstr.h:952
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition: MachineInstr.h:936
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:708
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:827
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool readsVirtualRegister(Register Reg) const
Return true if the MachineInstr reads the specified virtual register.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:930
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
bool isDebugValue() const
unsigned getDebugOperandIndex(const MachineOperand *Op) const
Definition: MachineInstr.h:638
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:504
MachineOperand & getDebugOperand(unsigned Index)
Definition: MachineInstr.h:594
std::optional< LocationSize > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:705
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:482
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:851
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
bool isDebugOperand(const MachineOperand *Op) const
Definition: MachineInstr.h:634
std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const
bool isPHI() const
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:585
void emitInlineAsmError(const Twine &ErrMsg) const
Emit an error referring to the source location of this instruction.
uint32_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:392
bool isEHLabel() const
bool isPseudoProbe() const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
bool shouldUpdateAdditionalCallInfo() const
Return true if copying, moving, or erasing this instruction requires updating additional call info (s...
bool isUndefDebugValue() const
Return true if the instruction is a debug value which describes a part of a variable as unavailable.
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:839
void unbundleFromSucc()
Break bundle below this instruction.
iterator_range< filtered_mop_iterator > all_defs()
Returns an iterator range over all operands that are (explicit or implicit) register defs.
Definition: MachineInstr.h:762
const MachineOperand & getDebugOperand(unsigned Index) const
Definition: MachineInstr.h:598
void clearKillInfo()
Clears kill flags on all operands.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:644
void setPCSections(MachineFunction &MF, MDNode *MD)
MachineInstr(const MachineInstr &)=delete
bool isKill() const
const MDNode * getLocCookieMD() const
For inline asm, get the !srcloc metadata node if we have it, and decode the loc cookie from it.
const MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const
int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool isMetaInstruction(QueryType Type=IgnoreBundle) const
Return true if this instruction doesn't produce any output in the form of executable instructions.
Definition: MachineInstr.h:942
iterator_range< filter_iterator< const MachineOperand *, std::function< bool(const MachineOperand &Op)> > > getDebugOperandsForReg(Register Reg) const
Definition: MachineInstr.h:623
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
void setDebugLoc(DebugLoc DL)
Replace current source information with new such.
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:995
bool isFakeUse() const
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:924
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs)
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:472
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool mayFoldInlineAsmRegOp(unsigned OpId) const
Returns true if the register operand can be folded with a load or store into a frame index.
std::tuple< Register, Register > getFirst2Regs() const
~MachineInstr()=delete
A description of a memory reference used in the backend.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
int64_t getImm() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Manage lifetime of a slot tracker for printing IR.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:363
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
Specialization of filter_iterator_base for forward iteration only.
Definition: STLExtras.h:498
An ilist node that can access its parent list.
Definition: ilist_node.h:321
A range adaptor for a pair of iterators.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This file defines classes to implement an intrusive doubly linked list class (i.e.
This file defines the ilist_node class template, which is a convenient base class for creating classe...
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
@ ExtraDefRegAllocReq
Definition: MCInstrDesc.h:181
@ ConvertibleTo3Addr
Definition: MCInstrDesc.h:175
@ MayRaiseFPException
Definition: MCInstrDesc.h:170
@ Rematerializable
Definition: MCInstrDesc.h:178
@ ExtraSrcRegAllocReq
Definition: MCInstrDesc.h:180
@ UsesCustomInserter
Definition: MCInstrDesc.h:176
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
constexpr auto adl_begin(RangeT &&range) -> decltype(adl_detail::begin_impl(std::forward< RangeT >(range)))
Returns the begin iterator to range using std::begin and function found through Argument-Dependent Lo...
Definition: ADL.h:78
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
constexpr auto adl_end(RangeT &&range) -> decltype(adl_detail::end_impl(std::forward< RangeT >(range)))
Returns the end iterator to range using std::end and functions found through Argument-Dependent Looku...
Definition: ADL.h:86
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1746
iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)
Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...
Definition: STLExtras.h:573
BumpPtrAllocatorImpl BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template parameters.
Definition: Allocator.h:382
@ Other
Any other memory.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:303
ArrayRef(const T &OneElt) -> ArrayRef< T >
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition: DenseMapInfo.h:52
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
static MachineInstr * getEmptyKey()
static unsigned getHashValue(const MachineInstr *const &MI)
static MachineInstr * getTombstoneKey()
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:65
Template traits for intrusive list.
Definition: ilist.h:90