MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc. More...
#include "llvm/CodeGen/MachineRegisterInfo.h"
Classes | |
| class | defusechain_instr_iterator |
| defusechain_iterator - This class provides iterator support for machine operands in the function that use or define a specific register. More... | |
| class | defusechain_iterator |
| reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register within the MachineFunction that corresponds to this MachineRegisterInfo object. More... | |
| class | Delegate |
| struct | PendingVirtRegMapEntry |
| struct | VRegAttrs |
| All attributes(register class or bank and low-level type) a virtual register can have. More... | |
Public Types | |
| using | reg_iterator = defusechain_iterator<true, true, false, true, false> |
| reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register. | |
| using | reg_instr_iterator |
| reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register, stepping by MachineInstr. | |
| using | reg_bundle_iterator |
| reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified register, stepping by bundle. | |
| using | reg_nodbg_iterator |
| reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register, skipping those marked as Debug. | |
| using | reg_instr_nodbg_iterator |
| reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the specified register, stepping by MachineInstr, skipping those marked as Debug. | |
| using | reg_bundle_nodbg_iterator |
| reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the specified register, stepping by bundle, skipping those marked as Debug. | |
| using | def_iterator = defusechain_iterator<false, true, false, true, false> |
| def_iterator/def_begin/def_end - Walk all defs of the specified register. | |
| using | def_instr_iterator |
| def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register, stepping by MachineInst. | |
| using | def_bundle_iterator |
| def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register, stepping by bundle. | |
| using | use_iterator = defusechain_iterator<true, false, false, true, false> |
| use_iterator/use_begin/use_end - Walk all uses of the specified register. | |
| using | use_instr_iterator |
| use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register, stepping by MachineInstr. | |
| using | use_bundle_iterator |
| use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register, stepping by bundle. | |
| using | use_nodbg_iterator |
| use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register, skipping those marked as Debug. | |
| using | use_instr_nodbg_iterator |
| use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified register, stepping by MachineInstr, skipping those marked as Debug. | |
| using | use_bundle_nodbg_iterator |
| use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specified register, stepping by bundle, skipping those marked as Debug. | |
| using | livein_iterator |
Public Member Functions | |
| LLVM_ABI | MachineRegisterInfo (MachineFunction *MF) |
| MachineRegisterInfo (const MachineRegisterInfo &)=delete | |
| MachineRegisterInfo & | operator= (const MachineRegisterInfo &)=delete |
| const TargetRegisterInfo * | getTargetRegisterInfo () const |
| void | resetDelegate (Delegate *delegate) |
| void | addDelegate (Delegate *delegate) |
| void | noteNewVirtualRegister (Register Reg) |
| void | noteCloneVirtualRegister (Register NewReg, Register SrcReg) |
| const MachineFunction & | getMF () const |
| bool | isSSA () const |
| void | leaveSSA () |
| bool | tracksLiveness () const |
| tracksLiveness - Returns true when tracking register liveness accurately. | |
| void | invalidateLiveness () |
| invalidateLiveness - Indicates that register liveness is no longer being tracked accurately. | |
| bool | shouldTrackSubRegLiveness (const TargetRegisterClass &RC) const |
Returns true if liveness for register class RC should be tracked at the subregister level. | |
| bool | shouldTrackSubRegLiveness (Register VReg) const |
| bool | subRegLivenessEnabled () const |
| bool | isUpdatedCSRsInitialized () const |
| Returns true if the updated CSR list was initialized and false otherwise. | |
| LLVM_ABI void | disableCalleeSavedRegister (MCRegister Reg) |
| Disables the register from the list of CSRs. | |
| LLVM_ABI const MCPhysReg * | getCalleeSavedRegs () const |
| Returns list of callee saved registers. | |
| LLVM_ABI void | setCalleeSavedRegs (ArrayRef< MCPhysReg > CSRs) |
| Sets the updated Callee Saved Registers list. | |
| LLVM_ABI void | addRegOperandToUseList (MachineOperand *MO) |
| Add MO to the linked list of operands for its register. | |
| LLVM_ABI void | removeRegOperandFromUseList (MachineOperand *MO) |
| Remove MO from its use-def list. | |
| LLVM_ABI void | moveOperands (MachineOperand *Dst, MachineOperand *Src, unsigned NumOps) |
| Move NumOps operands from Src to Dst, updating use-def lists as needed. | |
| LLVM_ABI void | verifyUseList (Register Reg) const |
| Verify the sanity of the use list for Reg. | |
| LLVM_ABI void | verifyUseLists () const |
| Verify the use list of all registers. | |
| reg_iterator | reg_begin (Register RegNo) const |
| iterator_range< reg_iterator > | reg_operands (Register Reg) const |
| reg_instr_iterator | reg_instr_begin (Register RegNo) const |
| iterator_range< reg_instr_iterator > | reg_instructions (Register Reg) const |
| reg_bundle_iterator | reg_bundle_begin (Register RegNo) const |
| iterator_range< reg_bundle_iterator > | reg_bundles (Register Reg) const |
| bool | reg_empty (Register RegNo) const |
| reg_empty - Return true if there are no instructions using or defining the specified register (it may be live-in). | |
| reg_nodbg_iterator | reg_nodbg_begin (Register RegNo) const |
| iterator_range< reg_nodbg_iterator > | reg_nodbg_operands (Register Reg) const |
| reg_instr_nodbg_iterator | reg_instr_nodbg_begin (Register RegNo) const |
| iterator_range< reg_instr_nodbg_iterator > | reg_nodbg_instructions (Register Reg) const |
| reg_bundle_nodbg_iterator | reg_bundle_nodbg_begin (Register RegNo) const |
| iterator_range< reg_bundle_nodbg_iterator > | reg_nodbg_bundles (Register Reg) const |
| bool | reg_nodbg_empty (Register RegNo) const |
| reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions. | |
| def_iterator | def_begin (Register RegNo) const |
| iterator_range< def_iterator > | def_operands (Register Reg) const |
| def_instr_iterator | def_instr_begin (Register RegNo) const |
| iterator_range< def_instr_iterator > | def_instructions (Register Reg) const |
| def_bundle_iterator | def_bundle_begin (Register RegNo) const |
| iterator_range< def_bundle_iterator > | def_bundles (Register Reg) const |
| bool | def_empty (Register RegNo) const |
| def_empty - Return true if there are no instructions defining the specified register (it may be live-in). | |
| StringRef | getVRegName (Register Reg) const |
| void | insertVRegByName (StringRef Name, Register Reg) |
| bool | hasOneDef (Register RegNo) const |
| Return true if there is exactly one operand defining the specified register. | |
| MachineOperand * | getOneDef (Register Reg) const |
| Returns the defining operand if there is exactly one operand defining the specified register, otherwise nullptr. | |
| use_iterator | use_begin (Register RegNo) const |
| iterator_range< use_iterator > | use_operands (Register Reg) const |
| use_instr_iterator | use_instr_begin (Register RegNo) const |
| iterator_range< use_instr_iterator > | use_instructions (Register Reg) const |
| use_bundle_iterator | use_bundle_begin (Register RegNo) const |
| iterator_range< use_bundle_iterator > | use_bundles (Register Reg) const |
| bool | use_empty (Register RegNo) const |
| use_empty - Return true if there are no instructions using the specified register. | |
| bool | hasOneUse (Register RegNo) const |
| hasOneUse - Return true if there is exactly one instruction using the specified register. | |
| use_nodbg_iterator | use_nodbg_begin (Register RegNo) const |
| iterator_range< use_nodbg_iterator > | use_nodbg_operands (Register Reg) const |
| use_instr_nodbg_iterator | use_instr_nodbg_begin (Register RegNo) const |
| iterator_range< use_instr_nodbg_iterator > | use_nodbg_instructions (Register Reg) const |
| use_bundle_nodbg_iterator | use_bundle_nodbg_begin (Register RegNo) const |
| iterator_range< use_bundle_nodbg_iterator > | use_nodbg_bundles (Register Reg) const |
| bool | use_nodbg_empty (Register RegNo) const |
| use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register. | |
| LLVM_ABI bool | hasOneNonDBGUse (Register RegNo) const |
| hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register. | |
| LLVM_ABI bool | hasOneNonDBGUser (Register RegNo) const |
| hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified register. | |
| LLVM_ABI MachineOperand * | getOneNonDBGUse (Register RegNo) const |
| If the register has a single non-Debug use, returns it; otherwise returns nullptr. | |
| LLVM_ABI MachineInstr * | getOneNonDBGUser (Register RegNo) const |
| If the register has a single non-Debug instruction using the specified register, returns it; otherwise returns nullptr. | |
| LLVM_ABI bool | hasAtMostUserInstrs (Register Reg, unsigned MaxUsers) const |
hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions. | |
| LLVM_ABI void | replaceRegWith (Register FromReg, Register ToReg) |
| replaceRegWith - Replace all instances of FromReg with ToReg in the machine function. | |
| LLVM_ABI MachineInstr * | getVRegDef (Register Reg) const |
| getVRegDef - Return the machine instr that defines the specified virtual register or null if none is found. | |
| LLVM_ABI MachineInstr * | getUniqueVRegDef (Register Reg) const |
| getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or null if none is found. | |
| LLVM_ABI void | clearKillFlags (Register Reg) const |
| clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the MachineOperand. | |
| LLVM_ABI void | dumpUses (Register RegNo) const |
| LLVM_ABI bool | isConstantPhysReg (MCRegister PhysReg) const |
| Returns true if PhysReg is unallocatable and constant throughout the function. | |
| PSetIterator | getPressureSets (VirtRegOrUnit VRegOrUnit) const |
| Get an iterator over the pressure sets affected by the virtual register or register unit. | |
| const TargetRegisterClass * | getRegClass (Register Reg) const |
| Return the register class of the specified virtual register. | |
| const TargetRegisterClass * | getRegClassOrNull (Register Reg) const |
Return the register class of Reg, or null if Reg has not been assigned a register class yet. | |
| const RegisterBank * | getRegBank (Register Reg) const |
Return the register bank of Reg. | |
| const RegisterBank * | getRegBankOrNull (Register Reg) const |
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been assigned a register class. | |
| const RegClassOrRegBank & | getRegClassOrRegBank (Register Reg) const |
Return the register bank or register class of Reg. | |
| LLVM_ABI void | setRegClass (Register Reg, const TargetRegisterClass *RC) |
| setRegClass - Set the register class of the specified virtual register. | |
| LLVM_ABI void | setRegBank (Register Reg, const RegisterBank &RegBank) |
Set the register bank to RegBank for Reg. | |
| void | setRegClassOrRegBank (Register Reg, const RegClassOrRegBank &RCOrRB) |
| LLVM_ABI const TargetRegisterClass * | constrainRegClass (Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0) |
| constrainRegClass - Constrain the register class of the specified virtual register to be a common subclass of RC and the current register class, but only if the new class has at least MinNumRegs registers. | |
| LLVM_ABI bool | constrainRegAttrs (Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0) |
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to be a common subclass or a common bank of both registers provided respectively (and a common low-level type). | |
| LLVM_ABI bool | recomputeRegClass (Register Reg) |
| recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the constraints from the instructions using Reg. | |
| LLVM_ABI Register | createVirtualRegister (const TargetRegisterClass *RegClass, StringRef Name="") |
| createVirtualRegister - Create and return a new virtual register in the function with the specified register class. | |
| VRegAttrs | getVRegAttrs (Register Reg) const |
Returns register class or bank and low level type of Reg. | |
| LLVM_ABI Register | createVirtualRegister (VRegAttrs RegAttr, StringRef Name="") |
| Create and return a new virtual register in the function with the specified register attributes(register class or bank and low level type). | |
| LLVM_ABI Register | cloneVirtualRegister (Register VReg, StringRef Name="") |
| Create and return a new virtual register in the function with the same attributes as the given register. | |
| LLT | getType (Register Reg) const |
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register. | |
| LLVM_ABI void | setType (Register VReg, LLT Ty) |
Set the low-level type of VReg to Ty. | |
| LLVM_ABI Register | createGenericVirtualRegister (LLT Ty, StringRef Name="") |
Create and return a new generic virtual register with low-level type Ty. | |
| LLVM_ABI void | clearVirtRegTypes () |
| Remove all types associated to virtual registers (after instruction selection and constraining of all generic virtual registers). | |
| LLVM_ABI Register | createIncompleteVirtualRegister (StringRef Name="") |
| Creates a new virtual register that has no register class, register bank or size assigned yet. | |
| unsigned | getNumVirtRegs () const |
| getNumVirtRegs - Return the number of virtual registers created. | |
| LLVM_ABI void | clearVirtRegs () |
| clearVirtRegs - Remove all virtual registers (after physreg assignment). | |
| void | addPendingVirtRegMapEntry (PendingVirtRegMapEntry Entry) |
| ArrayRef< PendingVirtRegMapEntry > | getPendingVirtRegMapEntries () const |
| void | clearPendingVirtRegMapEntries () |
| void | copyPendingVirtRegMapEntriesFrom (const MachineRegisterInfo &Other) |
| void | setRegAllocationHint (Register VReg, unsigned Type, Register PrefReg) |
| setRegAllocationHint - Specify a register allocation hint for the specified virtual register. | |
| void | addRegAllocationHint (Register VReg, Register PrefReg) |
| addRegAllocationHint - Add a register allocation hint to the hints vector for VReg. | |
| void | setSimpleHint (Register VReg, Register PrefReg) |
| Specify the preferred (target independent) register allocation hint for the specified virtual register. | |
| void | clearSimpleHint (Register VReg) |
| std::pair< unsigned, Register > | getRegAllocationHint (Register VReg) const |
| getRegAllocationHint - Return the register allocation hint for the specified virtual register. | |
| Register | getSimpleHint (Register VReg) const |
| getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint. | |
| const std::pair< unsigned, SmallVector< Register, 4 > > * | getRegAllocationHints (Register VReg) const |
| getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg. | |
| LLVM_ABI void | markUsesInDebugValueAsUndef (Register Reg) const |
| markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined which causes the DBG_VALUE to be deleted during LiveDebugVariables analysis. | |
| void | updateDbgUsersToReg (MCRegister OldReg, MCRegister NewReg, ArrayRef< MachineInstr * > Users) const |
| updateDbgUsersToReg - Update a collection of debug instructions to refer to the designated register. | |
| LLVM_ABI bool | isPhysRegModified (MCRegister PhysReg, bool SkipNoReturnDef=false) const |
| Return true if the specified register is modified in this function. | |
| LLVM_ABI bool | isPhysRegUsed (MCRegister PhysReg, bool SkipRegMaskTest=false) const |
| Return true if the specified register is modified or read in this function. | |
| void | addPhysRegsUsedFromRegMask (const uint32_t *RegMask) |
| addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. | |
| const BitVector & | getUsedPhysRegsMask () const |
| LLVM_ABI void | freezeReservedRegs () |
| freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before allocation begins. | |
| void | reserveReg (MCRegister PhysReg, const TargetRegisterInfo *TRI) |
| reserveReg – Mark a register as reserved so checks like isAllocatable will not suggest using it. | |
| bool | reservedRegsFrozen () const |
| reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved registers stays constant. | |
| bool | canReserveReg (MCRegister PhysReg) const |
| canReserveReg - Returns true if PhysReg can be used as a reserved register. | |
| const BitVector & | getReservedRegs () const |
| getReservedRegs - Returns a reference to the frozen set of reserved registers. | |
| bool | isReserved (MCRegister PhysReg) const |
| isReserved - Returns true when PhysReg is a reserved register. | |
| LLVM_ABI bool | isReservedRegUnit (MCRegUnit Unit) const |
| Returns true when the given register unit is considered reserved. | |
| bool | isAllocatable (MCRegister PhysReg) const |
| isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been reserved. | |
| void | addLiveIn (MCRegister Reg, Register vreg=Register()) |
| addLiveIn - Add the specified register as a live-in. | |
| livein_iterator | livein_begin () const |
| livein_iterator | livein_end () const |
| bool | livein_empty () const |
| ArrayRef< std::pair< MCRegister, Register > > | liveins () const |
| LLVM_ABI bool | isLiveIn (Register Reg) const |
| LLVM_ABI MCRegister | getLiveInPhysReg (Register VReg) const |
| getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical register. | |
| LLVM_ABI Register | getLiveInVirtReg (MCRegister PReg) const |
| getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual register. | |
| LLVM_ABI void | EmitLiveInCopies (MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII) |
| EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block. | |
| LLVM_ABI LaneBitmask | getMaxLaneMaskForVReg (Register Reg) const |
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual register Reg. | |
Static Public Member Functions | |
| static reg_iterator | reg_end () |
| static reg_instr_iterator | reg_instr_end () |
| static reg_bundle_iterator | reg_bundle_end () |
| static reg_nodbg_iterator | reg_nodbg_end () |
| static reg_instr_nodbg_iterator | reg_instr_nodbg_end () |
| static reg_bundle_nodbg_iterator | reg_bundle_nodbg_end () |
| static def_iterator | def_end () |
| static def_instr_iterator | def_instr_end () |
| static def_bundle_iterator | def_bundle_end () |
| static use_iterator | use_end () |
| static use_instr_iterator | use_instr_end () |
| static use_bundle_iterator | use_bundle_end () |
| static use_nodbg_iterator | use_nodbg_end () |
| static use_instr_nodbg_iterator | use_instr_nodbg_end () |
| static use_bundle_nodbg_iterator | use_bundle_nodbg_end () |
Friends | |
| template<bool, bool, bool, bool, bool> | |
| class | defusechain_iterator |
| template<bool, bool, bool, bool> | |
| class | defusechain_instr_iterator |
Detailed Description
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Definition at line 53 of file MachineRegisterInfo.h.
Member Typedef Documentation
◆ def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register, stepping by bundle.
Definition at line 427 of file MachineRegisterInfo.h.
◆ def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register, stepping by MachineInst.
Definition at line 411 of file MachineRegisterInfo.h.
◆ def_iterator
| using llvm::MachineRegisterInfo::def_iterator = defusechain_iterator<false, true, false, true, false> |
def_iterator/def_begin/def_end - Walk all defs of the specified register.
Definition at line 399 of file MachineRegisterInfo.h.
◆ livein_iterator
Definition at line 1049 of file MachineRegisterInfo.h.
◆ reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified register, stepping by bundle.
Definition at line 325 of file MachineRegisterInfo.h.
◆ reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the specified register, stepping by bundle, skipping those marked as Debug.
Definition at line 378 of file MachineRegisterInfo.h.
◆ reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register, stepping by MachineInstr.
Definition at line 309 of file MachineRegisterInfo.h.
◆ reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the specified register, stepping by MachineInstr, skipping those marked as Debug.
Definition at line 361 of file MachineRegisterInfo.h.
◆ reg_iterator
| using llvm::MachineRegisterInfo::reg_iterator = defusechain_iterator<true, true, false, true, false> |
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
Definition at line 297 of file MachineRegisterInfo.h.
◆ reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register, skipping those marked as Debug.
Definition at line 344 of file MachineRegisterInfo.h.
◆ use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register, stepping by bundle.
Definition at line 506 of file MachineRegisterInfo.h.
◆ use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specified register, stepping by bundle, skipping those marked as Debug.
Definition at line 574 of file MachineRegisterInfo.h.
◆ use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register, stepping by MachineInstr.
Definition at line 490 of file MachineRegisterInfo.h.
◆ use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified register, stepping by MachineInstr, skipping those marked as Debug.
Definition at line 557 of file MachineRegisterInfo.h.
◆ use_iterator
| using llvm::MachineRegisterInfo::use_iterator = defusechain_iterator<true, false, false, true, false> |
use_iterator/use_begin/use_end - Walk all uses of the specified register.
Definition at line 478 of file MachineRegisterInfo.h.
◆ use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register, skipping those marked as Debug.
Definition at line 540 of file MachineRegisterInfo.h.
Constructor & Destructor Documentation
◆ MachineRegisterInfo() [1/2]
|
explicit |
Definition at line 43 of file MachineRegisterInfo.cpp.
References EnableSubRegLiveness, llvm::MCRegisterInfo::getNumRegs(), and getTargetRegisterInfo().
Referenced by copyPendingVirtRegMapEntriesFrom(), MachineRegisterInfo(), and operator=().
◆ MachineRegisterInfo() [2/2]
|
delete |
References MachineRegisterInfo().
Member Function Documentation
◆ addDelegate()
|
inline |
Definition at line 183 of file MachineRegisterInfo.h.
References assert().
Referenced by llvm::GCNTargetMachine::registerMachineRegisterInfoCallback().
◆ addLiveIn()
|
inline |
addLiveIn - Add the specified register as a live-in.
Note that it is an error to add the same register to the same set more than once.
Definition at line 1043 of file MachineRegisterInfo.h.
References Reg.
Referenced by addLiveIn(), llvm::MachineFunction::addLiveIn(), allocateHSAUserSGPRs(), buildGitPtr(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::SIFrameLowering::emitCSRSpillStores(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), llvm::MipsFunctionInfo::initGlobalBaseReg(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::WebAssemblyCallLowering::lowerFormalArguments(), and llvm::SparcTargetLowering::LowerFormalArguments_32().
◆ addPendingVirtRegMapEntry()
|
inline |
Definition at line 822 of file MachineRegisterInfo.h.
References assert().
◆ addPhysRegsUsedFromRegMask()
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
This corresponds to the bit mask attached to register mask operands.
Definition at line 953 of file MachineRegisterInfo.h.
Referenced by llvm::MIRParserImpl::setupRegisterInfo().
◆ addRegAllocationHint()
addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.
Definition at line 855 of file MachineRegisterInfo.h.
References assert(), getNumVirtRegs(), llvm::Register::index2VirtReg(), and llvm::Register::isVirtual().
Referenced by llvm::VirtRegAuxInfo::weightCalcHelper().
◆ addRegOperandToUseList()
| void MachineRegisterInfo::addRegOperandToUseList | ( | MachineOperand * | MO | ) |
Add MO to the linked list of operands for its register.
Definition at line 271 of file MachineRegisterInfo.cpp.
References assert(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDef(), and llvm::Last.
Referenced by llvm::MachineInstr::addOperand(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::MachineOperand::setIsDef(), and llvm::MachineOperand::setReg().
◆ canReserveReg()
|
inline |
canReserveReg - Returns true if PhysReg can be used as a reserved register.
Any register can be reserved before freezeReservedRegs() is called.
Definition at line 996 of file MachineRegisterInfo.h.
References llvm::MCRegister::id(), and reservedRegsFrozen().
Referenced by llvm::ARMBaseRegisterInfo::canRealignStack(), llvm::LoongArchRegisterInfo::canRealignStack(), llvm::M68kRegisterInfo::canRealignStack(), llvm::MipsRegisterInfo::canRealignStack(), and llvm::X86RegisterInfo::canRealignStack().
◆ clearKillFlags()
| void MachineRegisterInfo::clearKillFlags | ( | Register | Reg | ) | const |
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the MachineOperand.
This function is used by optimization passes which extend register lifetimes and need only preserve conservative kill flag information.
Definition at line 453 of file MachineRegisterInfo.cpp.
References use_operands().
Referenced by combineFPFusedMultiply(), emitIndirectDst(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::HexagonInstrInfo::expandPostRAPseudo(), genIndexedMultiply(), hoistAndMergeSGPRInits(), insertPHI(), llvm::AArch64InstrInfo::insertSelect(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::RISCVInstrInfo::optimizeCondBranch(), llvm::HexagonInstrInfo::PredicateInstruction(), and llvm::SelectionDAGISel::runOnMachineFunction().
◆ clearPendingVirtRegMapEntries()
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inline |
Definition at line 833 of file MachineRegisterInfo.h.
◆ clearSimpleHint()
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inline |
Definition at line 867 of file MachineRegisterInfo.h.
References assert().
Referenced by llvm::VirtRegAuxInfo::weightCalcHelper().
◆ clearVirtRegs()
| void MachineRegisterInfo::clearVirtRegs | ( | ) |
clearVirtRegs - Remove all virtual registers (after physreg assignment).
Definition at line 204 of file MachineRegisterInfo.cpp.
References llvm::errs(), getNumVirtRegs(), getTargetRegisterInfo(), I, llvm::Register::index2VirtReg(), MI, llvm::printReg(), reg_instructions(), and verifyUseList().
Referenced by llvm::LoongArchInstrInfo::insertIndirectBranch(), llvm::RISCVInstrInfo::insertIndirectBranch(), llvm::SIInstrInfo::insertIndirectBranch(), llvm::XtensaInstrInfo::insertIndirectBranch(), and llvm::scavengeFrameVirtualRegs().
◆ clearVirtRegTypes()
| void MachineRegisterInfo::clearVirtRegTypes | ( | ) |
Remove all types associated to virtual registers (after instruction selection and constraining of all generic virtual registers).
Definition at line 201 of file MachineRegisterInfo.cpp.
Referenced by llvm::InstructionSelect::selectMachineFunction().
◆ cloneVirtualRegister()
Create and return a new virtual register in the function with the same attributes as the given register.
Definition at line 176 of file MachineRegisterInfo.cpp.
References createIncompleteVirtualRegister(), getType(), noteCloneVirtualRegister(), and setType().
Referenced by llvm::SITargetLowering::AddMemOpInit(), llvm::SIInstrInfo::convertToThreeAddress(), getLegalRegBank(), and llvm::CallLowering::lowerCall().
◆ constrainRegAttrs()
| bool MachineRegisterInfo::constrainRegAttrs | ( | Register | Reg, |
| Register | ConstrainingReg, | ||
| unsigned | MinNumRegs = 0 ) |
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to be a common subclass or a common bank of both registers provided respectively (and a common low-level type).
Do nothing if any of the attributes (classes, banks, or low-level types) of the registers are deemed incompatible, or if the resulting register will have a class smaller than before and of size less than MinNumRegs. Return true if such register attributes exist, false otherwise.
- Note
- Use this method instead of constrainRegClass and RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
Definition at line 90 of file MachineRegisterInfo.cpp.
References llvm::cast(), constrainRegClass(), getRegClassOrRegBank(), getType(), llvm::isa(), llvm::LLT::isValid(), setRegClassOrRegBank(), and setType().
◆ constrainRegClass()
| const TargetRegisterClass * MachineRegisterInfo::constrainRegClass | ( | Register | Reg, |
| const TargetRegisterClass * | RC, | ||
| unsigned | MinNumRegs = 0 ) |
constrainRegClass - Constrain the register class of the specified virtual register to be a common subclass of RC and the current register class, but only if the new class has at least MinNumRegs registers.
Return the new register class, or NULL if no such class exists. This should only be used when the constraint is known to be trivial, like GR32 -> GR32_NOSP. Beware of increasing register pressure.
- Note
- Assumes that the register has a register class assigned. Use RegisterBankInfo::constrainGenericRegister in GlobalISel's InstructionSelect pass and constrainRegAttrs in every other pass, including non-select passes of GlobalISel, instead.
Definition at line 84 of file MachineRegisterInfo.cpp.
References getRegClass().
Referenced by llvm::MachineBasicBlock::addLiveIn(), AdjustBaseAndOffset(), llvm::X86InstrInfo::classifyLEAReg(), cloneInstr(), llvm::RegisterBankInfo::constrainGenericRegister(), constrainRegAttrs(), llvm::X86InstrInfo::convertToThreeAddress(), createPostIncLoadStore(), llvm::AArch64InstrInfo::emitLdStWithAddr(), fixupSetCC(), llvm::ARMBaseInstrInfo::foldImmediate(), llvm::SIInstrInfo::foldImmediate(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::RISCVInstrInfo::foldMemoryOperandImpl(), llvm::SIInstrInfo::foldMemoryOperandImpl(), genFNegatedMAD(), genFusedMultiply(), genIndexedMultiply(), genMaddR(), llvm::AArch64InstrInfo::insertSelect(), llvm::SystemZInstrInfo::insertSelect(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), llvm::AArch64RegisterInfo::materializeFrameBaseRegister(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), llvm::PPCRegisterInfo::materializeFrameBaseRegister(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::RISCVInstrInfo::optimizeSelect(), llvm::PeelSingleBlockLoop(), llvm::TargetInstrInfo::reassociateOps(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::InstructionSelect::selectInstr(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::Thumb2InstrInfo::storeRegToStackSlot(), UpdateOperandRegClass(), and updateOperandRegConstraints().
◆ copyPendingVirtRegMapEntriesFrom()
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inline |
Definition at line 835 of file MachineRegisterInfo.h.
References assert(), getNumVirtRegs(), MachineRegisterInfo(), and llvm::Other.
◆ createGenericVirtualRegister()
Create and return a new generic virtual register with low-level type Ty.
Definition at line 191 of file MachineRegisterInfo.cpp.
References createIncompleteVirtualRegister(), noteNewVirtualRegister(), and setType().
Referenced by llvm::DstOp::addDefToMIB(), allocateHSAUserSGPRs(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::applyMappingSBufferLoad(), llvm::AMDGPULegalizerInfo::buildAbsGlobalAddress(), llvm::buildAPFixedPointInst(), llvm::buildAtomicCompareExchangeInst(), llvm::buildAtomicRMWInst(), llvm::buildBoolRegister(), llvm::SPIRVGlobalRegistry::buildConstantInt(), llvm::MachineIRBuilder::buildMaskLowPtrBits(), castBufferRsrcFromV4I32(), convertPtrToInt(), createTypeVReg(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::extractParts(), llvm::extractParts(), generateAssignInstrs(), generateAssignType(), llvm::generateGroupInst(), llvm::generateImageSizeQueryInst(), llvm::generateReadImageInst(), llvm::genWorkgroupQuery(), llvm::AMDGPULegalizerInfo::getImplicitArgPtr(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::CallLowering::handleAssignments(), insertInlineAsmProcess(), llvm::CallLowering::insertSRetIncomingArgument(), llvm::AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::RISCVLegalizerInfo::legalizeCustom(), llvm::AMDGPULegalizerInfo::legalizeFExp(), llvm::AMDGPULegalizerInfo::legalizeFFloor(), llvm::AMDGPULegalizerInfo::legalizeFlogCommon(), llvm::AMDGPULegalizerInfo::legalizeFSQRTF32(), llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeInsertVectorElt(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), legalizeLoad(), llvm::AMDGPULegalizerInfo::legalizeMul(), llvm::AMDGPULegalizerInfo::legalizeSignedDIV_REM(), legalizeSpvExtractElt(), legalizeSpvInsertElt(), legalizeStore(), llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(), llvm::AMDGPULegalizerInfo::legalizeWorkGroupId(), llvm::AMDGPULegalizerInfo::legalizeWorkitemIDIntrinsic(), llvm::MipsCallLowering::lowerCall(), llvm::SPIRVCallLowering::lowerCall(), llvm::AArch64CallLowering::lowerFormalArguments(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::MachineIRBuilder::materializePtrAdd(), mergeVectorRegsToResultRegs(), llvm::AMDGPUCallLowering::passSpecialInputs(), and llvm::AMDGPURegisterBankInfo::split64BitValueForMapping().
◆ createIncompleteVirtualRegister()
Creates a new virtual register that has no register class, register bank or size assigned yet.
This is only allowed to be used temporarily while constructing machine instructions. Most operations are undefined on an incomplete register until one of setRegClass(), setRegBank() or setSize() has been called on it.
Definition at line 143 of file MachineRegisterInfo.cpp.
References getNumVirtRegs(), llvm::Register::index2VirtReg(), and insertVRegByName().
Referenced by cloneVirtualRegister(), createGenericVirtualRegister(), createVirtualRegister(), createVirtualRegister(), and llvm::PerFunctionMIParsingState::getVRegInfo().
◆ createVirtualRegister() [1/2]
| Register MachineRegisterInfo::createVirtualRegister | ( | const TargetRegisterClass * | RegClass, |
| StringRef | Name = "" ) |
createVirtualRegister - Create and return a new virtual register in the function with the specified register class.
Definition at line 154 of file MachineRegisterInfo.cpp.
References assert(), createIncompleteVirtualRegister(), llvm::TargetRegisterClass::isAllocatable(), and noteNewVirtualRegister().
Referenced by llvm::DstOp::addDefToMIB(), addLiveIn(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineFunction::addLiveIn(), llvm::SITargetLowering::AddMemOpInit(), llvm::RISCVRegisterInfo::adjustReg(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), attachMEMCPYScratchRegs(), llvm::SPIRVGlobalRegistry::buildConstantSampler(), llvm::buildEnqueueKernel(), llvm::SIInstrInfo::buildExtractSubReg(), llvm::buildNDRange(), llvm::AMDGPURegisterBankInfo::buildReadFirstLane(), buildRegSequence(), buildRSRC(), llvm::buildSRetInst(), llvm::AMDGPURegisterBankInfo::buildVCopy(), buildWasmArgument(), llvm::X86InstrInfo::classifyLEAReg(), cloneInstr(), llvm::constrainRegToClass(), llvm::AMDGPU::createLaneMaskReg(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::SIInstrInfo::createReadFirstLaneFromCopyToPhysReg(), llvm::createVirtualRegister(), llvm::HexagonInstrInfo::createVR(), llvm::AArch64FrameLowering::eliminateCallFramePseudoInstr(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::CSKYRegisterInfo::eliminateFrameIndex(), llvm::LoongArchRegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::RISCVRegisterInfo::eliminateFrameIndex(), llvm::SystemZRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), emitBuildPairF64Pseudo(), llvm::AArch64TargetLowering::EmitCheckMatchingVL(), llvm::LoongArchTargetLowering::emitDynamicProbedAlloc(), llvm::RISCVTargetLowering::emitDynamicProbedAlloc(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::SystemZTargetLowering::emitEHSjLjLongJmp(), llvm::VETargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::SystemZTargetLowering::emitEHSjLjSetJmp(), llvm::VETargetLowering::emitEHSjLjSetJmp(), emitFROUND(), llvm::SITargetLowering::emitGWSMemViolTestLoop(), emitIndirectDst(), emitIndirectSrc(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::AArch64InstrInfo::emitLdStWithAddr(), emitLoadM0FromVGPRLoop(), llvm::PPCTargetLowering::emitProbedAlloca(), llvm::CSKYFrameLowering::emitPrologue(), llvm::MipsSEFrameLowering::emitPrologue(), llvm::RISCVFrameLowering::emitPrologue(), emitPseudoCTPOP(), emitPseudoVMSKCOND(), emitPseudoXVINSGR2VR(), emitQuietFCMP(), llvm::MSP430TargetLowering::EmitShiftInstr(), llvm::VETargetLowering::emitSjLjDispatchBlock(), emitThumbRegPlusImmInReg(), emitVecCondBranchPseudo(), emitVFROUND_NOEXCEPT_MASK(), emitXBegin(), llvm::SIInstrInfo::enforceOperandRCAlignment(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), expand64BitV_CNDMASK(), llvm::SIInstrInfo::expandMovDPP64(), extractRsrcPtr(), llvm::AArch64TargetLowering::fixupPtrauthDiscriminator(), fixupSetCC(), llvm::ARMBaseInstrInfo::foldImmediate(), llvm::SIInstrInfo::foldImmediate(), llvm::SystemZInstrInfo::foldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), forceReg(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), generateGatherLanePattern(), llvm::generateReadImageInst(), llvm::generateSampleImageInst(), genNeg(), genShXAddAddShift(), genSubAdd2SubSub(), genTPEntry(), genTPLoopBody(), llvm::SIInstrInfo::getAddNoCarry(), getArgBaseReg(), llvm::FunctionLoweringInfo::getCatchPadExceptionPointerVReg(), llvm::CSKYInstrInfo::getGlobalBaseReg(), llvm::MipsFunctionInfo::getGlobalBaseReg(), getIndirectSGPRIdx(), llvm::SPIRVGlobalRegistry::getOrAddMemAliasingINTELInst(), llvm::SPIRVGlobalRegistry::getOrCreateGlobalVariableWithBinding(), handleNDDOrNFInstructions(), INITIALIZE_PASS(), llvm::AArch64TargetLowering::insertCopiesSplitCSR(), llvm::SITargetLowering::insertCopiesSplitCSR(), llvm::SIInstrInfo::insertEQ(), llvm::LoongArchInstrInfo::insertIndirectBranch(), llvm::RISCVInstrInfo::insertIndirectBranch(), llvm::SIInstrInfo::insertIndirectBranch(), llvm::XtensaInstrInfo::insertIndirectBranch(), llvm::SIInstrInfo::insertNE(), InsertNewDef(), insertPHI(), llvm::AArch64InstrInfo::insertSelect(), llvm::PPCInstrInfo::insertSelect(), llvm::SIInstrInfo::insertSelect(), llvm::SystemZInstrInfo::insertSelect(), llvm::SIInstrInfo::insertSimulatedTrap(), llvm::SIInstrInfo::insertVectorSelect(), is64bitDefwithZeroHigh64bit(), llvm::AMDGPULegalizerInfo::legalizeFDIV32(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVALUt16(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::SystemZInstrInfo::loadImmediate(), loadM0FromVGPR(), llvm::SPIRVCallLowering::lowerCall(), llvm::WebAssemblyCallLowering::lowerCall(), LowerCallResults(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDMRRestore(), llvm::PPCRegisterInfo::lowerDMRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), LowerFPToInt(), llvm::InlineAsmLowering::lowerInlineAsm(), LowerMemcpy(), LowerMemset(), llvm::WebAssemblyCallLowering::lowerReturn(), llvm::RISCVRegisterInfo::lowerSegmentSpillReload(), llvm::PPCRegisterInfo::lowerWACCRestore(), llvm::PPCRegisterInfo::lowerWACCSpilling(), lowerWaveReduce(), llvm::AArch64RegisterInfo::materializeFrameBaseRegister(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), llvm::PPCRegisterInfo::materializeFrameBaseRegister(), llvm::RISCVRegisterInfo::materializeFrameBaseRegister(), llvm::SIRegisterInfo::materializeFrameBaseRegister(), maybeRewriteToDrop(), maybeRewriteToFallthrough(), moveAndTeeForMultiUse(), moveForSingleUse(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::CSKYInstrInfo::movImm(), llvm::RISCVInstrInfo::mulImm(), llvm::PeelSingleBlockLoop(), llvm::SITargetLowering::PostISelFolding(), prepareDAGLevelOperands(), llvm::PPCRegisterInfo::prepareDynamicAlloca(), llvm::VETargetLowering::prepareMBB(), llvm::VETargetLowering::prepareSymbol(), llvm::PPCInstrInfo::promoteInstr32To64ForElimEXTSW(), llvm::SIInstrInfo::readlaneVGPRToSGPR(), llvm::TargetInstrInfo::reassociateOps(), llvm::TargetInstrInfo::reduceAccumulatorTree(), rematerializeCheapDef(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), and selectCopy().
◆ createVirtualRegister() [2/2]
Create and return a new virtual register in the function with the specified register attributes(register class or bank and low level type).
Definition at line 167 of file MachineRegisterInfo.cpp.
References createIncompleteVirtualRegister(), noteNewVirtualRegister(), llvm::MachineRegisterInfo::VRegAttrs::RCOrRB, setType(), and llvm::MachineRegisterInfo::VRegAttrs::Ty.
◆ def_begin()
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inline |
Definition at line 400 of file MachineRegisterInfo.h.
Referenced by def_empty(), def_operands(), FollowCopyChain(), llvm::getDefSrcRegIgnoringCopies(), getOneDef(), getTileShape(), isPhysRegModified(), MustSaveLR(), and llvm::MachineFunction::salvageCopySSAImpl().
◆ def_bundle_begin()
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inline |
Definition at line 429 of file MachineRegisterInfo.h.
Referenced by def_bundles().
◆ def_bundle_end()
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inlinestatic |
Definition at line 432 of file MachineRegisterInfo.h.
Referenced by def_bundles().
◆ def_bundles()
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inline |
Definition at line 436 of file MachineRegisterInfo.h.
References def_bundle_begin(), def_bundle_end(), llvm::make_range(), and Reg.
◆ def_empty()
def_empty - Return true if there are no instructions defining the specified register (it may be live-in).
Definition at line 442 of file MachineRegisterInfo.h.
References def_begin(), and def_end().
Referenced by llvm::RISCVFrameLowering::determineCalleeSaves(), getAnySgprS1(), getUniqueVRegDef(), HandleDestructivePredicateHint(), isConstantPhysReg(), isSSA(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::MachineOperand::print(), llvm::SwiftErrorValueTracking::propagateVRegs(), and llvm::InstructionSelect::selectMachineFunction().
◆ def_end()
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inlinestatic |
Definition at line 403 of file MachineRegisterInfo.h.
Referenced by def_empty(), def_operands(), llvm::getDefSrcRegIgnoringCopies(), getOneDef(), isPhysRegModified(), MustSaveLR(), and scavengeVReg().
◆ def_instr_begin()
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inline |
Definition at line 413 of file MachineRegisterInfo.h.
Referenced by def_instructions(), getUniqueVRegDef(), getVRegDef(), and llvm::InstructionSelect::selectMachineFunction().
◆ def_instr_end()
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inlinestatic |
Definition at line 416 of file MachineRegisterInfo.h.
Referenced by def_instructions(), getUniqueVRegDef(), and getVRegDef().
◆ def_instructions()
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inline |
Definition at line 421 of file MachineRegisterInfo.h.
References def_instr_begin(), def_instr_end(), llvm::make_range(), and Reg.
Referenced by findImplictDefMIFromReg(), llvm::findPHICopyInsertPoint(), llvm::AArch64RegisterInfo::getRegAllocationHints(), llvm::SystemZRegisterInfo::getRegAllocationHints(), hasArgumentDef(), hoistAndMergeSGPRInits(), isDefBetween(), isImplicitlyDefined(), regIsPICBase(), llvm::AArch64RegisterInfo::shouldCoalesce(), and llvm::stableHashValue().
◆ def_operands()
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inline |
Definition at line 405 of file MachineRegisterInfo.h.
References def_begin(), def_end(), llvm::make_range(), and Reg.
Referenced by llvm::LiveInterval::computeSubRangeUndefs(), llvm::ShapeT::deduceImm(), llvm::AArch64RegisterInfo::getRegAllocationHints(), hasOneDef(), hasTiedDef(), and scavengeVReg().
◆ disableCalleeSavedRegister()
| void MachineRegisterInfo::disableCalleeSavedRegister | ( | MCRegister | Reg | ) |
Disables the register from the list of CSRs.
I.e. the register will not appear as part of the CSR mask.
- See also
- UpdatedCalleeSavedRegs.
Definition at line 620 of file MachineRegisterInfo.cpp.
References assert(), llvm::erase(), getTargetRegisterInfo(), I, llvm::MCRegAliasIterator::isValid(), Reg, and TRI.
◆ dumpUses()
| LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses | ( | Register | RegNo | ) | const |
Definition at line 523 of file MachineRegisterInfo.cpp.
References I, LLVM_DUMP_METHOD, and use_instructions().
◆ EmitLiveInCopies()
| void MachineRegisterInfo::EmitLiveInCopies | ( | MachineBasicBlock * | EntryMBB, |
| const TargetRegisterInfo & | TRI, | ||
| const TargetInstrInfo & | TII ) |
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
Definition at line 486 of file MachineRegisterInfo.cpp.
References llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), TII, TRI, and use_nodbg_empty().
◆ freezeReservedRegs()
| void MachineRegisterInfo::freezeReservedRegs | ( | ) |
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before allocation begins.
Definition at line 529 of file MachineRegisterInfo.cpp.
References assert(), llvm::TargetRegisterInfo::getReservedRegs(), and getTargetRegisterInfo().
Referenced by createFrameHelperMachineFunction(), llvm::TargetLoweringBase::finalizeLowering(), llvm::MIRParserImpl::initializeMachineFunction(), and llvm::AArch64FrameLowering::spillCalleeSavedRegisters().
◆ getCalleeSavedRegs()
Returns list of callee saved registers.
The function returns the updated CSR list (after taking into account registers that are disabled from the CSR list).
Definition at line 643 of file MachineRegisterInfo.cpp.
References llvm::TargetRegisterInfo::getCalleeSavedRegs(), getTargetRegisterInfo(), and I.
Referenced by addCalleeSavedRegs(), addCalleeSavedRegs(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::CSKYFrameLowering::determineCalleeSaves(), llvm::RISCVFrameLowering::determineCalleeSaves(), llvm::TargetFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::determinePrologEpilogSGPRSaves(), llvm::VETargetLowering::emitSjLjDispatchBlock(), findScratchNonCalleeSaveRegister(), getLiveRegsForEntryMBB(), llvm::MachineFrameInfo::getPristineRegs(), HandleDestructivePredicateHint(), isACalleeSavedRegister(), llvm::RISCVRegisterInfo::needsFrameBaseReg(), llvm::RegisterClassInfo::runOnMachineFunction(), llvm::X86MachineFunctionInfo::setRestoreBasePointer(), and llvm::SIMachineFunctionInfo::splitWWMSpillRegisters().
◆ getLiveInPhysReg()
| MCRegister MachineRegisterInfo::getLiveInPhysReg | ( | Register | VReg | ) | const |
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical register.
Definition at line 467 of file MachineRegisterInfo.cpp.
References liveins().
Referenced by orderRegForMul(), and llvm::TargetLowering::parametersInCSRMatch().
◆ getLiveInVirtReg()
| Register MachineRegisterInfo::getLiveInVirtReg | ( | MCRegister | PReg | ) | const |
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual register.
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical register.
Definition at line 476 of file MachineRegisterInfo.cpp.
References liveins(), and Register.
Referenced by llvm::MachineFunction::addLiveIn(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), and llvm::getFunctionLiveInPhysReg().
◆ getMaxLaneMaskForVReg()
| LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg | ( | Register | Reg | ) | const |
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual register Reg.
Definition at line 515 of file MachineRegisterInfo.cpp.
References assert(), llvm::TargetRegisterClass::getLaneMask(), and getRegClass().
Referenced by llvm::VirtRegAuxInfo::allUsesAvailableAt(), llvm::AnalyzeVirtRegLanesInBundle(), collectVirtualRegUses(), llvm::LiveInterval::computeSubRangeUndefs(), llvm::SIRegisterInfo::findReachingDef(), getDefRegMask(), getInstReadLaneMask(), getLanesWithProperty(), llvm::getLiveLaneMask(), getLiveLaneMaskAt(), and llvm::LiveInterval::verify().
◆ getMF()
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inline |
Definition at line 201 of file MachineRegisterInfo.h.
Referenced by llvm::RISCVRegisterInfo::getConstrainedRegClassForOperand(), and llvm::WebAssemblyDebugValueManager::WebAssemblyDebugValueManager().
◆ getNumVirtRegs()
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inline |
getNumVirtRegs - Return the number of virtual registers created.
Definition at line 817 of file MachineRegisterInfo.h.
Referenced by addImplicitDefs(), addRegAllocationHint(), attemptDebugCopyProp(), llvm::VirtRegAuxInfo::calculateSpillWeightsAndHints(), clearVirtRegs(), copyPendingVirtRegMapEntriesFrom(), createIncompleteVirtualRegister(), llvm::SITargetLowering::finalizeLowering(), getAnySgprS1(), llvm::getLiveRegs(), llvm::LiveRegSet::init(), llvm::WebAssemblyFunctionInfo::initWARegs(), isSSA(), llvm::SPIRV::lowerBuiltinType(), llvm::print(), llvm::scavengeFrameVirtualRegs(), scavengeFrameVirtualRegsInBlock(), llvm::InstructionSelect::selectMachineFunction(), setRegAllocationHint(), llvm::MachineBasicBlock::SplitCriticalEdge(), and verifyUseLists().
◆ getOneDef()
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inline |
Returns the defining operand if there is exactly one operand defining the specified register, otherwise nullptr.
Definition at line 466 of file MachineRegisterInfo.h.
References def_begin(), def_end(), and Reg.
Referenced by findSingleRegDef(), HandleDestructivePredicateHint(), and isSSA().
◆ getOneNonDBGUse()
| MachineOperand * MachineRegisterInfo::getOneNonDBGUse | ( | Register | RegNo | ) | const |
If the register has a single non-Debug use, returns it; otherwise returns nullptr.
Definition at line 433 of file MachineRegisterInfo.cpp.
References llvm::hasSingleElement(), and use_nodbg_operands().
Referenced by findSingleRegUse().
◆ getOneNonDBGUser()
| MachineInstr * MachineRegisterInfo::getOneNonDBGUser | ( | Register | RegNo | ) | const |
If the register has a single non-Debug instruction using the specified register, returns it; otherwise returns nullptr.
Definition at line 438 of file MachineRegisterInfo.cpp.
References llvm::hasSingleElement(), and use_nodbg_instructions().
◆ getPendingVirtRegMapEntries()
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inline |
Definition at line 829 of file MachineRegisterInfo.h.
◆ getPressureSets()
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inline |
Get an iterator over the pressure sets affected by the virtual register or register unit.
Definition at line 1321 of file MachineRegisterInfo.h.
Referenced by llvm::PressureDiff::addPressureChange(), decreaseSetPressure(), and increaseSetPressure().
◆ getRegAllocationHint()
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inline |
getRegAllocationHint - Return the register allocation hint for the specified virtual register.
If there are many hints, this returns the one with the greatest weight.
Definition at line 877 of file MachineRegisterInfo.h.
References assert(), llvm::Register::id(), llvm::Register::isVirtual(), and Register.
Referenced by llvm::ARMBaseRegisterInfo::getRegAllocationHints(), llvm::RISCVRegisterInfo::getRegAllocationHints(), llvm::SIRegisterInfo::getRegAllocationHints(), getSimpleHint(), llvm::ARMBaseRegisterInfo::updateRegAllocHint(), llvm::RISCVRegisterInfo::updateRegAllocHint(), and llvm::VirtRegAuxInfo::weightCalcHelper().
◆ getRegAllocationHints()
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inline |
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.
Definition at line 897 of file MachineRegisterInfo.h.
References assert(), and llvm::Register::isVirtual().
Referenced by llvm::TargetRegisterInfo::getRegAllocationHints().
◆ getRegBank()
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inline |
Return the register bank of Reg.
This shouldn't be used directly unless Reg has a register bank.
Definition at line 693 of file MachineRegisterInfo.h.
References llvm::cast(), and Reg.
◆ getRegBankOrNull()
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inline |
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been assigned a register class.
- Note
- It is possible to get the register bank from the register class via RegisterBankInfo::getRegBankFromRegClass.
Definition at line 701 of file MachineRegisterInfo.h.
References llvm::dyn_cast_if_present(), and Reg.
Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::applyMappingMAD_64_32(), constrainRegToBank(), fixupPHIOpBanks(), getAnySgprS1(), isLaneMaskFromSameBlock(), and verifyRegBankOnOperands().
◆ getRegClass()
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inline |
Return the register class of the specified virtual register.
This shouldn't be used directly unless Reg has a register class.
- See also
- getRegClassOrNull when this might happen.
Definition at line 669 of file MachineRegisterInfo.h.
References assert(), llvm::cast(), llvm::isa(), and Reg.
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::MachineFunction::addLiveIn(), canFoldCopy(), canFoldIntoCSel(), llvm::AArch64InstrInfo::canInsertSelect(), llvm::PPCInstrInfo::canInsertSelect(), llvm::SIInstrInfo::canInsertSelect(), llvm::SystemZInstrInfo::canInsertSelect(), llvm::X86InstrInfo::canInsertSelect(), cloneInstr(), constrainRegClass(), convertImplicitDefToConstZero(), llvm::VirtRegAuxInfo::copyHint(), llvm::NVPTXInstrInfo::copyPhysReg(), llvm::AllocationOrder::create(), llvm::definesATypeRegister(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::dumpMaxRegPressure(), llvm::LiveDebugVariables::LDVImpl::emitDebugValues(), llvm::SystemZTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::SystemZTargetLowering::emitEHSjLjSetJmp(), llvm::VETargetLowering::emitEHSjLjSetJmp(), emitIndirectDst(), emitIndirectSrc(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::AArch64InstrInfo::emitLdStWithAddr(), emitXBegin(), llvm::HexagonBlockRanges::expandToSubRegs(), llvm::AArch64TargetLowering::fixupPtrauthDiscriminator(), llvm::ARMBaseInstrInfo::foldImmediate(), llvm::SIInstrInfo::foldImmediate(), llvm::SystemZInstrInfo::foldImmediate(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::RISCVInstrInfo::foldMemoryOperandImpl(), llvm::SIInstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), generateGatherLanePattern(), genFNegatedMAD(), genSubAdd2SubSub(), getCopyRegClasses(), GetCostForDef(), getMaxLaneMaskForVReg(), llvm::PPCInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpRegClass(), getRC32(), llvm::AArch64RegisterInfo::getRegAllocationHints(), llvm::ARMBaseRegisterInfo::getRegAllocationHints(), llvm::PPCRegisterInfo::getRegAllocationHints(), llvm::SystemZRegisterInfo::getRegAllocationHints(), llvm::X86RegisterInfo::getRegAllocationHints(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::GCNRegPressure::getRegKind(), llvm::TargetRegisterInfo::getRegSizeInBits(), getRegTy(), HandleDestructivePredicateHint(), llvm::GCNRegPressure::inc(), insertPHI(), llvm::AArch64InstrInfo::insertSelect(), llvm::PPCInstrInfo::insertSelect(), llvm::SIInstrInfo::insertSelect(), llvm::SystemZInstrInfo::insertSelect(), llvm::X86InstrInfo::insertSelect(), llvm::SIInstrInfo::insertVectorSelect(), is64bitDefwithZeroHigh64bit(), isCheapCopy(), isCrossCopy(), isFPR64(), isGPR64(), llvm::SIInstrInfo::isLegalRegOperand(), isNonFoldablePartialRegisterLoad(), llvm::isOfRegClass(), llvm::SIInstrInfo::isSafeToSink(), llvm::GCNRPTarget::isSaveBeneficial(), llvm::SIRegisterInfo::isSGPRReg(), isSVERegOp(), isTileRegister(), isTupleInsertInstr(), llvm::RISCVInstrInfo::isVRegCopy(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsFLAT(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::SIInstrInfo::legalizeOperandsVALUt16(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::WebAssemblyMCInstLower::lower(), LowerCallResults(), LowerFPToInt(), llvm::InlineAsmLowering::lowerInlineAsm(), lowerWaveReduce(), maybeRewriteToDrop(), maybeRewriteToFallthrough(), moveAndTeeForMultiUse(), moveForSingleUse(), llvm::SIInstrInfo::moveToVALUImpl(), onlyAllocateTileRegisters(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::RISCVInstrInfo::optimizeSelect(), llvm::PeelSingleBlockLoop(), prepareDAGLevelOperands(), PrintNodeInfo(), llvm::PPCInstrInfo::promoteInstr32To64ForElimEXTSW(), propagateLocalCopies(), llvm::PSetIterator::PSetIterator(), llvm::SIInstrInfo::readlaneVGPRToSGPR(), recomputeRegClass(), llvm::TargetInstrInfo::reduceAccumulatorTree(), llvm::SIInstrInfo::regUsesConstantBus(), rematerializeCheapDef(), llvm::SelectionDAGISel::runOnMachineFunction(), scavengeVReg(), llvm::InstructionSelect::selectMachineFunction(), llvm::CoalescerPair::setRegisters(), suppressEGPRRegClass(), tryChangeVGPRtoSGPRinCopy(), UpdateOperandRegClass(), llvm::SIInstrInfo::usesConstantBus(), llvm::RISCVInstrInfo::verifyInstruction(), and llvm::VirtRegAuxInfo::weightCalcHelper().
◆ getRegClassOrNull()
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inline |
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
- Note
- A null register class can only happen when these two conditions are met:
- Generic virtual registers are created.
- The machine function has not completely been through the instruction selection process. None of this condition is possible without GlobalISel for now. In other words, if GlobalISel is not used or if the query happens after the select pass, using getRegClass is safe.
Definition at line 686 of file MachineRegisterInfo.h.
References llvm::dyn_cast_if_present(), and Reg.
Referenced by addConstantsToTrack(), llvm::AMDGPULegalizerInfo::buildAbsGlobalAddress(), llvm::buildAtomicCompareExchangeInst(), buildOpBitcast(), llvm::buildSRetInst(), llvm::canReplaceReg(), llvm::constrainOperandRegClass(), llvm::SITargetLowering::finalizeLowering(), generateAssignInstrs(), llvm::generateMulExtendedInst(), llvm::AArch64RegisterBankInfo::getInstrMapping(), getRegClass(), llvm::AMDGPULegalizerInfo::legalizeConstHwRegRead(), llvm::SPIRVCallLowering::lowerCall(), llvm::processInstr(), propagateLocalCopies(), propagateSPIRVType(), requiresSpirvType(), llvm::InstructionSelect::selectInstr(), llvm::InstructionSelect::selectMachineFunction(), llvm::setRegClassIfNull(), llvm::setRegClassType(), shouldTrackSubRegLiveness(), and llvm::updateRegType().
◆ getRegClassOrRegBank()
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inline |
Return the register bank or register class of Reg.
- Note
- Before the register bank gets assigned (i.e., before the RegBankSelect pass)
Regmay not have either.
Definition at line 709 of file MachineRegisterInfo.h.
References Reg.
Referenced by buildWasmArgument(), llvm::canReplaceReg(), llvm::RegisterBankInfo::constrainGenericRegister(), constrainRegAttrs(), llvm::RISCVRegisterInfo::getConstrainedRegClassForOperand(), llvm::SIRegisterInfo::getConstrainedRegClassForOperand(), llvm::WebAssemblyRegisterInfo::getConstrainedRegClassForOperand(), llvm::RegisterBankInfo::getRegBank(), getVRegAttrs(), and selectDebugInstr().
◆ getReservedRegs()
getReservedRegs - Returns a reference to the frozen set of reserved registers.
This method should always be preferred to calling TRI::getReservedRegs() when possible.
Definition at line 1003 of file MachineRegisterInfo.h.
References assert(), and reservedRegsFrozen().
Referenced by llvm::rdf::DataFlowGraph::build(), llvm::TargetRegisterInfo::getAllocatableSet(), and isReserved().
◆ getSimpleHint()
getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint.
Definition at line 888 of file MachineRegisterInfo.h.
References assert(), getRegAllocationHint(), llvm::Register::isVirtual(), and Register.
◆ getTargetRegisterInfo()
|
inline |
Definition at line 171 of file MachineRegisterInfo.h.
Referenced by llvm::addLiveIns(), llvm::VirtRegAuxInfo::allUsesAvailableAt(), clearVirtRegs(), collectVirtualRegUses(), llvm::computeLiveIns(), llvm::LiveInterval::computeSubRangeUndefs(), constrainRegClass(), disableCalleeSavedRegister(), llvm::dumpMaxRegPressure(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::execMayBeModifiedBeforeAnyUse(), llvm::execMayBeModifiedBeforeUse(), findSurvivorBackwards(), findUseBetween(), freezeReservedRegs(), generateAssignType(), getCalleeSavedRegs(), getDefRegMask(), llvm::RegisterBankInfo::getRegBankFromConstraints(), llvm::GCNRegPressure::getRegKind(), llvm::GCNRegPressure::inc(), llvm::LiveRegSet::init(), llvm::X86InstrInfo::insertSelect(), isAllocatable(), isConstantPhysReg(), isCrossCopy(), llvm::isOfRegClass(), isPhysRegModified(), isPhysRegUsed(), isReservedRegUnit(), llvm::GCNRPTarget::isSaveBeneficial(), isTupleInsertInstr(), llvm::RISCVInstrInfo::isVRegCopy(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), MachineRegisterInfo(), matchUniformityAndLLT(), llvm::print(), printMBB(), PrintNodeInfo(), llvm::PPCInstrInfo::promoteInstr32To64ForElimEXTSW(), llvm::PSetIterator::PSetIterator(), llvm::recomputeLivenessFlags(), recomputeRegClass(), replaceRegWith(), llvm::GCNRegPressurePrinter::runOnMachineFunction(), llvm::MachineFunction::salvageCopySSAImpl(), scavengeFrameVirtualRegsInBlock(), scavengeVReg(), llvm::ARMBaseRegisterInfo::shouldCoalesce(), spillVGPRtoAGPR(), llvm::tryFoldSPUpdateIntoPushPop(), updateDbgUsersToReg(), verifyUseList(), and verifyUseLists().
◆ getType()
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition at line 792 of file MachineRegisterInfo.h.
References Reg.
Referenced by llvm::RegisterBankInfo::applyDefaultMapping(), llvm::AMDGPURegisterBankInfo::applyMappingBFE(), llvm::AMDGPURegisterBankInfo::applyMappingDynStackAlloc(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::applyMappingLoad(), llvm::AMDGPURegisterBankInfo::applyMappingSBufferLoad(), llvm::MIPatternMatch::bind_helper< LLT >::bind(), buildAnyextOrCopy(), llvm::buildAPFixedPointInst(), llvm::buildAtomicCompareExchangeInst(), llvm::buildAtomicRMWInst(), llvm::CallLowering::buildCopyFromRegs(), llvm::CallLowering::buildCopyToRegs(), llvm::AMDGPURegisterBankInfo::buildReadFirstLane(), llvm::buildSRetInst(), llvm::AMDGPURegisterBankInfo::buildVCopy(), canCreateUndefOrPoison(), llvm::canReplaceReg(), castBufferRsrcFromV4I32(), castBufferRsrcToV4I32(), cloneVirtualRegister(), llvm::AArch64TargetLowering::computeNumSignBitsForTargetInstr(), llvm::ConstantFoldExtOp(), constantFoldFpUnary(), llvm::ConstantFoldICmp(), llvm::ConstantFoldUnaryIntOp(), constrainRegAttrs(), constrainRegToBank(), deduceAndAssignTypeForGUnmerge(), deduceIntTypeFromResult(), deduceTypeFromResultRegister(), deduceTypeFromSingleOperand(), emitLoadFromConstantPool(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::extractParts(), llvm::extractVectorParts(), llvm::AMDGPU::SetOfRulesForOpcode::findMappingForMI(), llvm::AMDGPULegalizerInfo::fixStoreSourceType(), fixupPHIOpBanks(), foldTruncOfI32Constant(), generateAssignInstrs(), generateAssignType(), llvm::generateGroupInst(), llvm::generateSelectInst(), getAnySgprS1(), llvm::AMDGPU::getBaseWithConstantOffset(), llvm::RISCVRegisterInfo::getConstrainedRegClassForOperand(), llvm::SIRegisterInfo::getConstrainedRegClassForOperand(), llvm::getDefSrcRegIgnoringCopies(), llvm::SIInstrInfo::getGenericValueUniformity(), llvm::AMDGPULegalizerInfo::getImplicitArgPtr(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::PPCRegisterBankInfo::getInstrMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), llvm::WebAssemblyRegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), llvm::DstOp::getLLTTy(), llvm::SrcOp::getLLTTy(), llvm::RegisterBankInfo::getRegBank(), llvm::RegisterBankInfo::getRegBankFromConstraints(), llvm::TargetRegisterInfo::getRegSizeInBits(), getSalvageOpsForTrunc(), getTestBitReg(), getTruncStoreByteOffset(), getTypeFromTypeIdx(), llvm::MachineInstr::getTypeToPrint(), llvm::AMDGPURegisterBankInfo::getValueMappingForPtr(), getVectorShiftImm(), getVRegAttrs(), llvm::CallLowering::handleAssignments(), llvm::AMDGPULegalizerInfo::handleD16VData(), llvm::AMDGPURegisterBankInfo::handleD16VData(), hasSameNumEltsOnAllVectorOperands(), llvm::CallLowering::insertSRetLoads(), llvm::CallLowering::insertSRetStores(), llvm::SITargetLowering::isCanonicalized(), llvm::isConstantOrConstantSplatVector(), isExtractHiElt(), isFPExtFromF16OrConst(), isFPIntrinsic(), llvm::isKnownToBeAPowerOfTwo(), isLshrHalf(), isSameBitWidth(), isShlHalf(), isTruncHalf(), isVectorOfTwoOrScalar(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg(), llvm::AMDGPULegalizerInfo::legalizeBufferLoad(), llvm::AMDGPULegalizerInfo::legalizeBufferStore(), llvm::AMDGPULegalizerInfo::legalizeBuildVector(), llvm::AMDGPULegalizerInfo::legalizeBVHIntersectRayIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeCTLS(), llvm::AMDGPULegalizerInfo::legalizeCTLZ_CTTZ(), llvm::AMDGPULegalizerInfo::legalizeCTLZ_ZERO_POISON(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::MipsLegalizerInfo::legalizeCustom(), llvm::RISCVLegalizerInfo::legalizeCustom(), llvm::SPIRVLegalizerInfo::legalizeCustom(), llvm::AMDGPULegalizerInfo::legalizeExtract(), llvm::AMDGPULegalizerInfo::legalizeExtractVectorElt(), llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV64(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFExp(), llvm::AMDGPULegalizerInfo::legalizeFFloor(), llvm::AMDGPULegalizerInfo::legalizeFFREXP(), llvm::AMDGPULegalizerInfo::legalizeFlogCommon(), llvm::AMDGPULegalizerInfo::legalizeFMad(), llvm::AMDGPULegalizerInfo::legalizeFPTOI(), llvm::AMDGPULegalizerInfo::legalizeFrem(), llvm::AMDGPULegalizerInfo::legalizeFroundeven(), llvm::AMDGPULegalizerInfo::legalizeFSQRT(), llvm::AMDGPULegalizerInfo::legalizeFSQRTF64(), llvm::AMDGPULegalizerInfo::legalizeGetFPEnv(), llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeInsert(), llvm::AMDGPULegalizerInfo::legalizeInsertVectorElt(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::RISCVLegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), llvm::AMDGPULegalizerInfo::legalizeLaneOp(), legalizeLoad(), llvm::AMDGPULegalizerInfo::legalizeLoad(), llvm::AMDGPULegalizerInfo::legalizeMul(), llvm::AMDGPULegalizerInfo::legalizePointerAsRsrcIntrin(), llvm::AMDGPULegalizerInfo::legalizeRsqClampIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeSetFPEnv(), llvm::AMDGPULegalizerInfo::legalizeSignedDIV_REM(), llvm::AMDGPULegalizerInfo::legalizeSinCos(), legalizeSpvBitcast(), legalizeSpvConstComposite(), legalizeSpvExtractElt(), legalizeSpvInsertElt(), legalizeStore(), llvm::AMDGPULegalizerInfo::legalizeStore(), llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM(), llvm::AArch64CallLowering::lowerCall(), llvm::AMDGPUCallLowering::lowerChainCall(), llvm::AArch64CallLowering::lowerFormalArguments(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::MIPatternMatch::CheckType::match(), llvm::MIPatternMatch::deferred_helper< LLT >::match(), matchUniformityAndLLT(), mergeVectorRegsToResultRegs(), opMustUseVOP3Encoding(), preferGPRForFPImm(), llvm::processInstr(), propagateSPIRVType(), registerSpirvTypeForNewInstructions(), selectCopy(), selectDebugInstr(), llvm::InstructionSelect::selectMachineFunction(), selectMergeValues(), selectUnmergeValues(), llvm::MipsRegisterBankInfo::setRegBank(), llvm::setRegClassType(), setRegsToType(), shiftAmountKnownInRange(), llvm::AMDGPULegalizerInfo::splitBufferOffsets(), unsupportedBinOp(), llvm::updateRegType(), valueIsKnownNeverF32Denorm(), llvm::RegisterBankInfo::InstructionMapping::verify(), widenScalarType(), and X86SelectAddress().
◆ getUniqueVRegDef()
| MachineInstr * MachineRegisterInfo::getUniqueVRegDef | ( | Register | Reg | ) | const |
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or null if none is found.
If there are multiple definitions or no definition, return null.
Definition at line 417 of file MachineRegisterInfo.cpp.
References def_empty(), def_instr_begin(), def_instr_end(), and I.
Referenced by llvm::ARMBaseInstrInfo::analyzeLoopForPipelining(), llvm::PPCInstrInfo::analyzeLoopForPipelining(), llvm::buildEnqueueKernel(), canCombine(), canCombine(), canCombine(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::SIInstrInfo::foldImmediate(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), generateGatherLanePattern(), genFNegatedMAD(), genFusedMultiply(), genIndexedMultiply(), genMaddR(), genShXAddAddShift(), genSubAdd2SubSub(), llvm::TargetInstrInfo::getAccumulatorChain(), llvm::getBlockStructInstr(), llvm::getConstFromIntrinsic(), llvm::X86InstrInfo::getConstValDefinedInReg(), getDynAllocaAmount(), llvm::PPCInstrInfo::getFMAPatterns(), getFMULPatterns(), getFNEGPatterns(), getFoldableImm(), getGatherLanePattern(), llvm::BPFInstrInfo::getJumpTableIndex(), llvm::X86InstrInfo::getJumpTableIndex(), getJumpTableIndexFromReg(), getMinimumVLForVSLIDEDOWN_VX(), getVRegDef(), llvm::X86InstrInfo::hasCommutePreference(), llvm::RISCVInstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableSibling(), hasSameValue(), isImplicitlyDef(), isVCmpResult(), llvm::SIInstrInfo::legalizeGenericOperand(), lookThroughCopies(), matchFoldableAnd(), matchFoldableShift(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::SparcInstrInfo::optimizeCompareInstr(), llvm::TargetRegisterInfo::shouldRegionSplitForVirtReg(), and llvm::WebAssemblyFunctionInfo::stackifyVReg().
◆ getUsedPhysRegsMask()
Definition at line 957 of file MachineRegisterInfo.h.
Referenced by llvm::RISCVFrameLowering::determineCalleeSaves().
◆ getVRegAttrs()
Returns register class or bank and low level type of Reg.
Always safe to use. Special values are returned when Reg does not have some of the attributes.
Definition at line 777 of file MachineRegisterInfo.h.
References getRegClassOrRegBank(), getType(), and Reg.
◆ getVRegDef()
| MachineInstr * MachineRegisterInfo::getVRegDef | ( | Register | Reg | ) | const |
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is found.
This assumes that the code is in SSA form, so there should only be one definition.
Definition at line 404 of file MachineRegisterInfo.cpp.
References assert(), def_instr_begin(), def_instr_end(), and I.
Referenced by addConstantsToTrack(), llvm::AArch64InstrInfo::analyzeBranchPredicate(), llvm::RISCVInstrInfo::analyzeLoopForPipelining(), llvm::MIPatternMatch::bind_helper< const MachineInstr * >::bind(), llvm::MIPatternMatch::bind_helper< MachineInstr * >::bind(), BitOp3_Op(), calcNextStatus(), canCombineFPFusedMultiply(), canCompareBeNewValueJump(), canCreateUndefOrPoison(), canEmitConjunction(), canFoldAsPredicatedOp(), llvm::AArch64InstrInfo::canFoldIntoAddrMode(), canFoldIntoCSel(), canFoldIntoSelect(), llvm::PPCInstrInfo::combineRLWINM(), llvm::SITargetLowering::computeKnownAlignForTargetInstr(), llvm::RISCVTargetLowering::computeKnownBitsForTargetInstr(), llvm::SITargetLowering::computeKnownBitsForTargetInstr(), llvm::AArch64TargetLowering::computeNumSignBitsForTargetInstr(), llvm::AMDGPUTargetLowering::computeNumSignBitsForTargetInstr(), llvm::constrainOperandRegClass(), deduceGEPType(), definedBySignExtendingOp(), definedByZeroExtendingOp(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), emitPseudoXVINSGR2VR(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::AArch64GISelUtils::extractPtrauthBlendDiscriminators(), llvm::PPCInstrInfo::finalizeInsInstrs(), llvm::SPIRVTargetLowering::finalizeLowering(), findLoopComponents(), findLoopIncrementValue(), llvm::SPIRVIRMapping::findMI(), findRedundantFlagInstr(), findStartOfTree(), findUniqueOperandDefinedInLoop(), fixupPHIOpBanks(), foldTruncOfI32Constant(), llvm::RISCVInstrInfo::genAlternativeCodeSequence(), generateAssignInstrs(), getAnySgprS1(), llvm::getConstantFPVRegVal(), llvm::PPCInstrInfo::getConstantFromConstantPool(), llvm::getDef(), llvm::getDefInstrMaybeConstant(), llvm::getDefSrcRegIgnoringCopies(), getEffectiveImm(), llvm::PPCInstrInfo::getFMAPatterns(), llvm::getFunctionLiveInPhysReg(), llvm::getIConstantFromReg(), llvm::SIInstrInfo::getImmOrMaterializedImm(), getIndVarInfo(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::PPCRegisterBankInfo::getInstrMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), getLegalRegBank(), llvm::SPIRVGlobalRegistry::getOrCreateOpTypeSampledImage(), getShape(), getTypeReg(), getVectorShiftImm(), llvm::getVRegDef(), llvm::getVRegSubRegDef(), llvm::RISCVInstrInfo::hasReassociableSibling(), isAGPRCopy(), llvm::GIMatchTableExecutor::isBaseWithConstantOffset(), llvm::SITargetLowering::isCanonicalized(), llvm::isConstantOrConstantVector(), isConstReg(), isConstReg(), llvm::isCycleInvariant(), isDefinedOutside(), isExtractHiElt(), isFPExtFromF16OrConst(), llvm::RISCVInstrInfo::isFromLoadImm(), isGuaranteedNotToBeUndefOrPoison(), isKnownNonNull(), isLaneMaskFromSameBlock(), llvm::MachineLoop::isLoopInvariant(), llvm::SIInstrInfo::isSafeToSink(), isSignExtendedW(), isSignExtendedW(), llvm::PPCInstrInfo::isSignOrZeroExtended(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::TargetRegisterInfo::lookThruCopyLike(), llvm::TargetRegisterInfo::lookThruSingleUseCopyChain(), lookUpCopyChain(), LowerMemcpy(), LowerMemset(), MatchingStackOffset(), MatchingStackOffset(), llvm::SIInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::TargetInstrInfo::optimizeLoadInstr(), llvm::passCopy(), processBlockAddr(), llvm::ARMBaseInstrInfo::produceSameValue(), llvm::PPCInstrInfo::promoteInstr32To64ForElimEXTSW(), propagateSPIRVType(), removeCopies(), llvm::saveUsesAndErase(), SearchOptions::SearchOptions(), stripVRegCopies(), updatePHIs(), llvm::updateRegType(), validateFunCallMachineDef(), valueIsKnownNeverF32Denorm(), and llvm::SSAUpdaterTraits< MachineSSAUpdater >::ValueIsPHI().
◆ getVRegName()
Definition at line 444 of file MachineRegisterInfo.h.
References Reg.
Referenced by llvm::printReg().
◆ hasAtMostUserInstrs()
hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions.
Definition at line 443 of file MachineRegisterInfo.cpp.
References llvm::hasNItemsOrLess(), use_instr_nodbg_begin(), and use_instr_nodbg_end().
◆ hasOneDef()
Return true if there is exactly one operand defining the specified register.
Definition at line 460 of file MachineRegisterInfo.h.
References def_operands(), and llvm::hasSingleElement().
Referenced by HandleDestructivePredicateHint(), isSafeToMove(), isSSA(), moveForSingleUse(), llvm::AArch64InstrInfo::optimizeCondBranch(), and llvm::MachineFunction::salvageCopySSAImpl().
◆ hasOneNonDBGUse()
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition at line 425 of file MachineRegisterInfo.cpp.
References llvm::hasSingleElement(), and use_nodbg_operands().
Referenced by canCombine(), canCombine(), canCombine(), canCombineFPFusedMultiply(), canEmitConjunction(), canFoldAsPredicatedOp(), llvm::AArch64InstrInfo::canFoldIntoAddrMode(), canFoldIntoSelect(), combineFPFusedMultiply(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::PPCTargetLowering::emitProbedAlloca(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::ARMBaseInstrInfo::foldImmediate(), llvm::SIInstrInfo::foldImmediate(), llvm::SystemZInstrInfo::foldImmediate(), llvm::VEInstrInfo::foldImmediate(), llvm::PPCInstrInfo::getFMAPatterns(), getFNEGPatterns(), getFoldedI64LoadOpcode(), getGatherLanePattern(), getTestBitReg(), llvm::TargetInstrInfo::hasReassociableSibling(), hasSingleUse(), isOperandKill(), llvm::AMDGPUTargetLowering::isReassocProfitable(), llvm::SITargetLowering::isReassocProfitable(), llvm::TargetLowering::isReassocProfitable(), llvm::TargetRegisterInfo::lookThruSingleUseCopyChain(), llvm::MIPatternMatch::OneNonDBGUse_match< SubPatternT >::match(), matchFoldableCopyToI64Ext(), matchFoldableSExtFromPromotedI32(), matchFoldableShift(), matchLoadAndBytePosition(), moveForSingleUse(), oneUseDominatesOtherUses(), llvm::SIInstrInfo::optimizeCompareInstr(), llvm::SparcInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), and verifyCFIntrinsic().
◆ hasOneNonDBGUser()
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified register.
Said instruction may have multiple uses.
Definition at line 429 of file MachineRegisterInfo.cpp.
References llvm::hasSingleElement(), and use_nodbg_instructions().
Referenced by llvm::TargetInstrInfo::getAccumulatorReassociationPatterns().
◆ hasOneUse()
hasOneUse - Return true if there is exactly one instruction using the specified register.
Definition at line 525 of file MachineRegisterInfo.h.
References llvm::CallingConv::Tail.
Referenced by foldVGPRCopyIntoRegSequence(), hasSingleUse(), insertInlineAsmProcess(), llvm::MIPatternMatch::OneUse_match< SubPatternT >::match(), llvm::PPCInstrInfo::optimizeCompareInstr(), and llvm::RISCVInstrInfo::optimizeCondBranch().
◆ insertVRegByName()
Definition at line 448 of file MachineRegisterInfo.h.
Referenced by createIncompleteVirtualRegister().
◆ invalidateLiveness()
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inline |
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
This should be called by late passes that invalidate the liveness information.
Definition at line 230 of file MachineRegisterInfo.h.
◆ isAllocatable()
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inline |
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been reserved.
Allocatable registers may show up in the allocation order of some virtual register, so a register allocator needs to track its liveness and availability.
Definition at line 1032 of file MachineRegisterInfo.h.
References getTargetRegisterInfo(), llvm::TargetRegisterInfo::isInAllocatableClass(), and isReserved().
Referenced by computeLiveOuts(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), llvm::SIRegisterInfo::findUnusedRegister(), llvm::PPCRegisterInfo::getCalleeSavedRegs(), isConstantPhysReg(), and llvm::VirtRegAuxInfo::weightCalcHelper().
◆ isConstantPhysReg()
| bool MachineRegisterInfo::isConstantPhysReg | ( | MCRegister | PhysReg | ) | const |
Returns true if PhysReg is unallocatable and constant throughout the function.
Writing to a constant register has no effect.
Definition at line 535 of file MachineRegisterInfo.cpp.
References assert(), def_empty(), getTargetRegisterInfo(), isAllocatable(), llvm::MCRegister::isPhysical(), llvm::MCRegAliasIterator::isValid(), and TRI.
Referenced by llvm::VirtRegAuxInfo::allUsesAvailableAt(), canFoldAsPredicatedOp(), isCallerPreservedOrConstPhysReg(), llvm::isCycleInvariant(), and llvm::TargetInstrInfo::isReMaterializableImpl().
◆ isLiveIn()
Definition at line 458 of file MachineRegisterInfo.cpp.
References liveins().
Referenced by llvm::X86FrameLowering::adjustForHiPEPrologue(), llvm::X86FrameLowering::adjustForSegmentedStacks(), llvm::AMDGPUResourceUsageAnalysisImpl::analyzeResourceUsage(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::ARMFrameLowering::determineCalleeSaves(), getPrologueDeath(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), isSignExtendedW(), isSignExtendedW(), llvm::PPCInstrInfo::isSignOrZeroExtended(), pushRegsToStack(), reservePrivateMemoryRegs(), llvm::M68kFrameLowering::spillCalleeSavedRegisters(), llvm::PPCFrameLowering::spillCalleeSavedRegisters(), llvm::Thumb1FrameLowering::spillCalleeSavedRegisters(), and llvm::X86FrameLowering::spillCalleeSavedRegisters().
◆ isPhysRegModified()
| bool MachineRegisterInfo::isPhysRegModified | ( | MCRegister | PhysReg, |
| bool | SkipNoReturnDef = false ) const |
Return true if the specified register is modified in this function.
This checks that no defining machine operands exist for the register or any of its aliases. Definitions found on functions marked noreturn are ignored, to consider them pass 'true' for optional parameter SkipNoReturnDef. The register is also considered modified when it is set in the UsedPhysRegMask.
Definition at line 592 of file MachineRegisterInfo.cpp.
References def_begin(), def_end(), getTargetRegisterInfo(), llvm::MCRegister::id(), isNoReturnDef(), llvm::MCRegAliasIterator::isValid(), llvm::make_range(), and TRI.
Referenced by llvm::PPCFrameLowering::assignCalleeSavedSpillSlots(), llvm::SIFrameLowering::determineCalleeSaves(), llvm::TargetFrameLowering::determineCalleeSaves(), llvm::XCoreFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::determineCalleeSavesSGPR(), isSafeToMove(), and isXPLeafCandidate().
◆ isPhysRegUsed()
| bool MachineRegisterInfo::isPhysRegUsed | ( | MCRegister | PhysReg, |
| bool | SkipRegMaskTest = false ) const |
Return true if the specified register is modified or read in this function.
This checks that no machine operands exist for the register or any of its aliases. If SkipRegMaskTest is false, the register is considered used when it is set in the UsedPhysRegMask.
Definition at line 607 of file MachineRegisterInfo.cpp.
References getTargetRegisterInfo(), llvm::MCRegister::id(), llvm::MCRegAliasIterator::isValid(), reg_nodbg_empty(), and TRI.
Referenced by llvm::AMDGPUResourceUsageAnalysisImpl::analyzeResourceUsage(), llvm::PPCFrameLowering::assignCalleeSavedSpillSlots(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::SIFrameLowering::determinePrologEpilogSGPRSaves(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), findUnusedRegister(), llvm::SIRegisterInfo::findUnusedRegister(), llvm::SIRegisterInfo::getNumUsedPhysRegs(), needToReserveScavengingSpillSlots(), llvm::ExecutionDomainFix::runOnMachineFunction(), and verifyLeafProcRegUse().
◆ isReserved()
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inline |
isReserved - Returns true when PhysReg is a reserved register.
Reserved registers may belong to an allocatable register class, but the target has explicitly requested that they are not used.
Definition at line 1014 of file MachineRegisterInfo.h.
References getReservedRegs(), llvm::MCRegister::id(), and llvm::BitVector::test().
Referenced by addHints(), llvm::addLiveIns(), llvm::LivePhysRegs::available(), llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIFrameLowering::emitCSRSpillStores(), llvm::RISCVFrameLowering::emitPrologue(), llvm::X86FrameLowering::emitPrologue(), llvm::X86RegisterInfo::findDeadCallerSavedReg(), findRegisterToSaveX5To(), findScratchNonCalleeSaveRegister(), findSurvivorBackwards(), findUnusedRegister(), llvm::ARMBaseRegisterInfo::getRegAllocationHints(), llvm::RISCVRegisterInfo::getRegAllocationHints(), llvm::SIRegisterInfo::getRegAllocationHints(), llvm::SystemZRegisterInfo::getRegAllocationHints(), llvm::TargetRegisterInfo::getRegAllocationHints(), llvm::X86RegisterInfo::getRegAllocationHints(), isAllocatable(), llvm::SIRegisterInfo::isAsmClobberable(), llvm::MachineInstr::isDead(), pushRegsToStack(), RemoveLoadsIntoFakeUses::run(), llvm::AArch64FrameLowering::spillCalleeSavedRegisters(), toggleKills(), and updateLiveness().
◆ isReservedRegUnit()
| bool MachineRegisterInfo::isReservedRegUnit | ( | MCRegUnit | Unit | ) | const |
Returns true when the given register unit is considered reserved.
Register units are considered reserved when for at least one of their root registers, the root register and all super registers are reserved. This currently iterates the register hierarchy and may be slower than expected.
Definition at line 668 of file MachineRegisterInfo.cpp.
References llvm::all_of(), getTargetRegisterInfo(), llvm::MCRegUnitRootIterator::isValid(), and TRI.
◆ isSSA()
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inline |
Definition at line 214 of file MachineRegisterInfo.h.
Referenced by llvm::PPCInstrInfo::convertToImmediateForm(), llvm::execMayBeModifiedBeforeAnyUse(), llvm::execMayBeModifiedBeforeUse(), llvm::SIInstrInfo::expandMovDPP64(), llvm::PPCInstrInfo::foldFrameOffset(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::getVRegSubRegDef(), llvm::SystemZInstrInfo::loadImmediate(), llvm::PPCInstrInfo::optimizeCmpPostRA(), splitMBB(), and llvm::SIInstrInfo::verifyInstruction().
◆ isUpdatedCSRsInitialized()
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inline |
Returns true if the updated CSR list was initialized and false otherwise.
Definition at line 251 of file MachineRegisterInfo.h.
◆ leaveSSA()
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Definition at line 217 of file MachineRegisterInfo.h.
◆ livein_begin()
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Definition at line 1051 of file MachineRegisterInfo.h.
◆ livein_empty()
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inline |
Definition at line 1053 of file MachineRegisterInfo.h.
Referenced by llvm::R600InstrInfo::getIndirectIndexBegin().
◆ livein_end()
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Definition at line 1052 of file MachineRegisterInfo.h.
◆ liveins()
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Definition at line 1055 of file MachineRegisterInfo.h.
Referenced by llvm::rdf::DataFlowGraph::build(), checkFnHasLiveInYmmOrZmm(), llvm::R600InstrInfo::getIndirectIndexBegin(), getLiveInPhysReg(), getLiveInVirtReg(), isLiveIn(), and processIfEntryValueDbgDeclare().
◆ markUsesInDebugValueAsUndef()
| void MachineRegisterInfo::markUsesInDebugValueAsUndef | ( | Register | Reg | ) | const |
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined which causes the DBG_VALUE to be deleted during LiveDebugVariables analysis.
Definition at line 554 of file MachineRegisterInfo.cpp.
References llvm::make_early_inc_range(), use_instructions(), and UseMI.
◆ moveOperands()
| void MachineRegisterInfo::moveOperands | ( | MachineOperand * | Dst, |
| MachineOperand * | Src, | ||
| unsigned | NumOps ) |
Move NumOps operands from Src to Dst, updating use-def lists as needed.
The Dst range is assumed to be uninitialized memory. (Or it may contain operands that won't be destroyed, which is OK because the MO destructor is trivial anyway).
The Src and Dst ranges may overlap.
Definition at line 339 of file MachineRegisterInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, assert(), and llvm::Next.
Referenced by llvm::SIInstrInfo::moveFlatAddrToVGPR(), and moveOperands().
◆ noteCloneVirtualRegister()
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Definition at line 196 of file MachineRegisterInfo.h.
Referenced by cloneVirtualRegister().
◆ noteNewVirtualRegister()
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Definition at line 191 of file MachineRegisterInfo.h.
References Reg.
Referenced by createGenericVirtualRegister(), createVirtualRegister(), and createVirtualRegister().
◆ operator=()
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delete |
References MachineRegisterInfo().
◆ recomputeRegClass()
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the constraints from the instructions using Reg.
Returns true if Reg was upgraded.
This method can be used after constraints have been removed from a virtual register, for example after removing instructions or splitting the live range.
Definition at line 120 of file MachineRegisterInfo.cpp.
References getRegClass(), getTargetRegisterInfo(), MI, reg_nodbg_operands(), setRegClass(), TII, and TRI.
◆ reg_begin()
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Definition at line 298 of file MachineRegisterInfo.h.
Referenced by reg_empty(), and reg_operands().
◆ reg_bundle_begin()
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Definition at line 327 of file MachineRegisterInfo.h.
Referenced by reg_bundles().
◆ reg_bundle_end()
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Definition at line 330 of file MachineRegisterInfo.h.
Referenced by reg_bundles().
◆ reg_bundle_nodbg_begin()
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Definition at line 380 of file MachineRegisterInfo.h.
Referenced by reg_nodbg_bundles().
◆ reg_bundle_nodbg_end()
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Definition at line 383 of file MachineRegisterInfo.h.
Referenced by reg_nodbg_bundles().
◆ reg_bundles()
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Definition at line 334 of file MachineRegisterInfo.h.
References llvm::make_range(), Reg, reg_bundle_begin(), and reg_bundle_end().
◆ reg_empty()
reg_empty - Return true if there are no instructions using or defining the specified register (it may be live-in).
Definition at line 340 of file MachineRegisterInfo.h.
References reg_begin(), and reg_end().
◆ reg_end()
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inlinestatic |
Definition at line 301 of file MachineRegisterInfo.h.
Referenced by reg_empty(), and reg_operands().
◆ reg_instr_begin()
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Definition at line 311 of file MachineRegisterInfo.h.
Referenced by reg_instructions().
◆ reg_instr_end()
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Definition at line 314 of file MachineRegisterInfo.h.
Referenced by reg_instructions().
◆ reg_instr_nodbg_begin()
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Definition at line 363 of file MachineRegisterInfo.h.
Referenced by reg_nodbg_instructions(), and llvm::VirtRegAuxInfo::weightCalcHelper().
◆ reg_instr_nodbg_end()
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inlinestatic |
Definition at line 366 of file MachineRegisterInfo.h.
Referenced by reg_nodbg_instructions(), and llvm::VirtRegAuxInfo::weightCalcHelper().
◆ reg_instructions()
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Definition at line 319 of file MachineRegisterInfo.h.
References llvm::make_range(), Reg, reg_instr_begin(), and reg_instr_end().
Referenced by clearVirtRegs(), and llvm::SystemZRegisterInfo::getRegAllocationHints().
◆ reg_nodbg_begin()
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Definition at line 346 of file MachineRegisterInfo.h.
Referenced by reg_nodbg_empty(), and reg_nodbg_operands().
◆ reg_nodbg_bundles()
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Definition at line 388 of file MachineRegisterInfo.h.
References llvm::make_range(), Reg, reg_bundle_nodbg_begin(), and reg_bundle_nodbg_end().
◆ reg_nodbg_empty()
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition at line 394 of file MachineRegisterInfo.h.
References reg_nodbg_begin(), and reg_nodbg_end().
Referenced by llvm::VirtRegAuxInfo::calculateSpillWeightsAndHints(), insertVZeroUpper(), and isPhysRegUsed().
◆ reg_nodbg_end()
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inlinestatic |
Definition at line 349 of file MachineRegisterInfo.h.
Referenced by reg_nodbg_empty(), and reg_nodbg_operands().
◆ reg_nodbg_instructions()
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Definition at line 371 of file MachineRegisterInfo.h.
References llvm::make_range(), Reg, reg_instr_nodbg_begin(), and reg_instr_nodbg_end().
Referenced by llvm::dumpMaxRegPressure(), llvm::PPCRegisterInfo::getRegAllocationHints(), llvm::SystemZRegisterInfo::getRegAllocationHints(), and isTerminalReg().
◆ reg_nodbg_operands()
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inline |
Definition at line 354 of file MachineRegisterInfo.h.
References llvm::make_range(), Reg, reg_nodbg_begin(), and reg_nodbg_end().
Referenced by computeWeight(), llvm::RISCVRegisterInfo::getRegAllocationHints(), llvm::X86RegisterInfo::getRegAllocationHints(), llvm::VirtRegAuxInfo::isRematerializable(), recomputeRegClass(), scavengeVReg(), and tryChangeVGPRtoSGPRinCopy().
◆ reg_operands()
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Definition at line 303 of file MachineRegisterInfo.h.
References llvm::make_range(), Reg, reg_begin(), and reg_end().
Referenced by canMemFoldInlineAsm(), llvm::ConnectedVNInfoEqClasses::Distribute(), hasAnyNonFlatUseOfReg(), replaceRegWith(), and verifyUseList().
◆ removeRegOperandFromUseList()
| void MachineRegisterInfo::removeRegOperandFromUseList | ( | MachineOperand * | MO | ) |
Remove MO from its use-def list.
Definition at line 310 of file MachineRegisterInfo.cpp.
References assert(), llvm::MachineOperand::getReg(), and llvm::Next.
Referenced by llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::MachineInstr::removeOperand(), llvm::MachineOperand::setIsDef(), and llvm::MachineOperand::setReg().
◆ replaceRegWith()
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
This is like llvm-level X->replaceAllUsesWith(Y), except that it also changes any definitions of the register as well.
Note that it is usually necessary to first constrain ToReg's register class and register bank to match the FromReg constraints using one of the methods:
constrainRegClass(ToReg, getRegClass(FromReg)) constrainRegAttrs(ToReg, FromReg) RegisterBankInfo::constrainGenericRegister(ToReg, *MRI.getRegClass(FromReg), MRI)
These functions will return a falsy result if the virtual registers have incompatible constraints.
Note that if ToReg is a physical register the function will replace and apply sub registers to ToReg in order to obtain a final/proper physical register.
This is like llvm-level X->replaceAllUsesWith(Y), except that it also changes any definitions of the register as well. If ToReg is a physical register we apply the sub register to obtain the final/proper physical register.
Definition at line 386 of file MachineRegisterInfo.cpp.
References assert(), getTargetRegisterInfo(), llvm::Register::isPhysical(), llvm::make_early_inc_range(), reg_operands(), and TRI.
Referenced by addConstantsToTrack(), llvm::SIFrameLowering::determinePrologEpilogSGPRSaves(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::SITargetLowering::finalizeLowering(), generateAssignInstrs(), insertBitcasts(), llvm::LoongArchInstrInfo::insertIndirectBranch(), llvm::RISCVInstrInfo::insertIndirectBranch(), llvm::SIInstrInfo::insertIndirectBranch(), llvm::XtensaInstrInfo::insertIndirectBranch(), insertInlineAsmProcess(), llvm::AMDGPULegalizerInfo::legalizeExtract(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::SelectionDAGISel::runOnMachineFunction(), scavengeVReg(), llvm::InstructionSelect::selectInstr(), llvm::InstructionSelect::selectMachineFunction(), and llvm::SIMachineFunctionInfo::shiftWwmVGPRsToLowestRange().
◆ reservedRegsFrozen()
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inline |
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved registers stays constant.
Definition at line 989 of file MachineRegisterInfo.h.
Referenced by canReserveReg(), llvm::SPIRVTargetLowering::finalizeLowering(), getReservedRegs(), llvm::X86RegisterInfo::getReservedRegs(), isCallerPreservedOrConstPhysReg(), llvm::SIInstrInfo::isLegalRegOperand(), and reserveReg().
◆ reserveReg()
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inline |
reserveReg – Mark a register as reserved so checks like isAllocatable will not suggest using it.
This should not be used during the middle of a function walk, or when liveness info is available.
Definition at line 978 of file MachineRegisterInfo.h.
References assert(), reservedRegsFrozen(), and TRI.
Referenced by llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR(), llvm::SIFrameLowering::determinePrologEpilogSGPRSaves(), llvm::SIFrameLowering::processFunctionBeforeFrameIndicesReplaced(), and llvm::SIMachineFunctionInfo::shiftWwmVGPRsToLowestRange().
◆ resetDelegate()
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inline |
Definition at line 175 of file MachineRegisterInfo.h.
References assert().
◆ setCalleeSavedRegs()
Sets the updated Callee Saved Registers list.
Notice that it will override ant previously disabled/saved CSRs.
Definition at line 656 of file MachineRegisterInfo.cpp.
References llvm::append_range().
Referenced by llvm::RISCVFrameLowering::determineCalleeSaves(), and llvm::AArch64RegisterInfo::UpdateCustomCalleeSavedRegs().
◆ setRegAllocationHint()
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inline |
setRegAllocationHint - Specify a register allocation hint for the specified virtual register.
This is typically used by target, and in case of an earlier hint it will be overwritten.
Definition at line 844 of file MachineRegisterInfo.h.
References assert(), getNumVirtRegs(), llvm::Register::index2VirtReg(), and llvm::Register::isVirtual().
Referenced by llvm::SIInstrInfo::getAddNoCarry(), setSimpleHint(), llvm::ARMBaseRegisterInfo::updateRegAllocHint(), and llvm::RISCVRegisterInfo::updateRegAllocHint().
◆ setRegBank()
| void MachineRegisterInfo::setRegBank | ( | Register | Reg, |
| const RegisterBank & | RegBank ) |
Set the register bank to RegBank for Reg.
Definition at line 63 of file MachineRegisterInfo.cpp.
Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::applyMappingLoad(), llvm::AMDGPURegisterBankInfo::applyMappingMAD_64_32(), llvm::AMDGPURegisterBankInfo::applyMappingSBufferLoad(), llvm::AMDGPURegisterBankInfo::applyMappingSMULU64(), llvm::AMDGPURegisterBankInfo::buildReadFirstLane(), constrainRegToBank(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), fixupPHIOpBanks(), foldTruncOfI32Constant(), reinsertVectorIndexAdd(), llvm::MipsRegisterBankInfo::setRegBank(), llvm::MIRParserImpl::setupRegisterInfo(), and llvm::AMDGPURegisterBankInfo::split64BitValueForMapping().
◆ setRegClass()
| void MachineRegisterInfo::setRegClass | ( | Register | Reg, |
| const TargetRegisterClass * | RC ) |
setRegClass - Set the register class of the specified virtual register.
Definition at line 58 of file MachineRegisterInfo.cpp.
References assert(), and llvm::TargetRegisterClass::isAllocatable().
Referenced by addConstantsToTrack(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPULegalizerInfo::buildAbsGlobalAddress(), llvm::buildAPFixedPointInst(), llvm::buildAtomicCompareExchangeInst(), llvm::buildAtomicRMWInst(), llvm::buildBoolRegister(), llvm::SPIRVGlobalRegistry::buildConstantInt(), llvm::buildEnqueueKernel(), llvm::buildMemSemanticsReg(), buildOpBitcast(), llvm::buildPipeInst(), llvm::buildScopeReg(), llvm::buildSRetInst(), buildWasmArgument(), llvm::RegisterBankInfo::constrainGenericRegister(), constrainRegClass(), convertPtrToInt(), createStackTemporaryForVector(), createTypeVReg(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), llvm::SITargetLowering::finalizeLowering(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), generateAssignType(), llvm::generateGroupInst(), llvm::generateImageSizeQueryInst(), llvm::generateMulExtendedInst(), llvm::generateReadImageInst(), llvm::genWorkgroupQuery(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), insertInlineAsmProcess(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeConstHwRegRead(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIsAddrSpace(), legalizeSpvExtractElt(), legalizeSpvInsertElt(), llvm::AMDGPULegalizerInfo::legalizeWorkGroupId(), llvm::SPIRVCallLowering::lowerCall(), llvm::WebAssemblyCallLowering::lowerCall(), llvm::processInstr(), propagateSPIRVType(), recomputeRegClass(), llvm::SIInstrInfo::reMaterialize(), llvm::InstructionSelect::selectInstr(), llvm::setRegClassIfNull(), llvm::setRegClassType(), llvm::MIRParserImpl::setupRegisterInfo(), suppressEGPRRegClass(), tryChangeVGPRtoSGPRinCopy(), and llvm::updateRegType().
◆ setRegClassOrRegBank()
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inline |
Definition at line 719 of file MachineRegisterInfo.h.
References Reg.
Referenced by constrainRegAttrs().
◆ setSimpleHint()
Specify the preferred (target independent) register allocation hint for the specified virtual register.
Definition at line 863 of file MachineRegisterInfo.h.
References setRegAllocationHint().
Referenced by emitLoadM0FromVGPRLoop(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), and llvm::MIRParserImpl::setupRegisterInfo().
◆ setType()
Set the low-level type of VReg to Ty.
Definition at line 185 of file MachineRegisterInfo.cpp.
Referenced by llvm::SITargetLowering::allocateHSAUserSGPRs(), llvm::SITargetLowering::allocateSpecialEntryInputVGPRs(), allocateVGPR32Input(), llvm::RegisterBankInfo::applyDefaultMapping(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::applyMappingLoad(), llvm::buildAtomicCompareExchangeInst(), llvm::CallLowering::buildCopyFromRegs(), llvm::AMDGPURegisterBankInfo::buildReadFirstLane(), llvm::buildSRetInst(), buildWasmArgument(), cloneVirtualRegister(), constrainRegAttrs(), createGenericVirtualRegister(), llvm::createVirtualRegister(), createVirtualRegister(), generateAssignInstrs(), llvm::getFunctionLiveInPhysReg(), insertInlineAsmProcess(), llvm::SPIRVCallLowering::lowerCall(), llvm::WebAssemblyCallLowering::lowerCall(), llvm::WebAssemblyCallLowering::lowerReturn(), llvm::processInstr(), llvm::setRegClassType(), setRegsToType(), llvm::updateRegType(), and widenScalarType().
◆ shouldTrackSubRegLiveness() [1/2]
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Returns true if liveness for register class RC should be tracked at the subregister level.
Definition at line 234 of file MachineRegisterInfo.h.
References llvm::TargetRegisterClass::HasDisjunctSubRegs, and subRegLivenessEnabled().
Referenced by shouldTrackSubRegLiveness().
◆ shouldTrackSubRegLiveness() [2/2]
Definition at line 237 of file MachineRegisterInfo.h.
References assert(), getRegClassOrNull(), llvm::Register::isVirtual(), LLVM_LIKELY, and shouldTrackSubRegLiveness().
◆ subRegLivenessEnabled()
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inline |
Definition at line 242 of file MachineRegisterInfo.h.
Referenced by llvm::AArch64RegisterInfo::shouldCoalesce(), and shouldTrackSubRegLiveness().
◆ tracksLiveness()
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inline |
tracksLiveness - Returns true when tracking register liveness accurately.
(see MachineFUnctionProperties::Property description for details)
Definition at line 221 of file MachineRegisterInfo.h.
Referenced by llvm::rdf::DataFlowGraph::build(), findRenameRegForSameLdStRegPair(), llvm::BranchFolder::OptimizeFunction(), and llvm::MachineBasicBlock::print().
◆ updateDbgUsersToReg()
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inline |
updateDbgUsersToReg - Update a collection of debug instructions to refer to the designated register.
Definition at line 909 of file MachineRegisterInfo.h.
References assert(), getTargetRegisterInfo(), llvm_unreachable, MI, and Users.
◆ use_begin()
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inline |
Definition at line 479 of file MachineRegisterInfo.h.
Referenced by use_empty(), and use_operands().
◆ use_bundle_begin()
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Definition at line 508 of file MachineRegisterInfo.h.
Referenced by use_bundles().
◆ use_bundle_end()
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inlinestatic |
Definition at line 511 of file MachineRegisterInfo.h.
Referenced by use_bundles().
◆ use_bundle_nodbg_begin()
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Definition at line 576 of file MachineRegisterInfo.h.
Referenced by use_nodbg_bundles().
◆ use_bundle_nodbg_end()
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Definition at line 579 of file MachineRegisterInfo.h.
Referenced by use_nodbg_bundles().
◆ use_bundles()
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Definition at line 515 of file MachineRegisterInfo.h.
References llvm::make_range(), Reg, use_bundle_begin(), and use_bundle_end().
◆ use_empty()
use_empty - Return true if there are no instructions using the specified register.
Definition at line 521 of file MachineRegisterInfo.h.
References use_begin(), and use_end().
Referenced by llvm::AArch64TargetLowering::EmitEntryPStateSM(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::NVPTXFrameLowering::emitPrologue(), foldTruncOfI32Constant(), GetInitialOffset(), llvm::PPCInstrInfo::optimizeCompareInstr(), rematerializeCheapDef(), llvm::SelectionDAGISel::runOnMachineFunction(), and llvm::InstructionSelect::selectMachineFunction().
◆ use_end()
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inlinestatic |
Definition at line 482 of file MachineRegisterInfo.h.
Referenced by use_empty(), and use_operands().
◆ use_instr_begin()
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Definition at line 492 of file MachineRegisterInfo.h.
Referenced by findAssignTypeInstr(), foldVGPRCopyIntoRegSequence(), llvm::TargetInstrInfo::getAccumulatorReassociationPatterns(), insertInlineAsmProcess(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::InstructionSelect::selectMachineFunction(), and use_instructions().
◆ use_instr_end()
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inlinestatic |
Definition at line 495 of file MachineRegisterInfo.h.
Referenced by findAssignTypeInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), and use_instructions().
◆ use_instr_nodbg_begin()
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Definition at line 559 of file MachineRegisterInfo.h.
Referenced by getFoldedI64LoadOpcode(), hasAtMostUserInstrs(), hasMoreUses(), isSimpleIf(), matchFoldableCopyToI64Ext(), matchFoldableSExtFromPromotedI32(), matchFoldableShift(), use_nodbg_instructions(), and verifyCFIntrinsic().
◆ use_instr_nodbg_end()
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inlinestatic |
Definition at line 562 of file MachineRegisterInfo.h.
Referenced by hasAtMostUserInstrs(), hasMoreUses(), isSimpleIf(), and use_nodbg_instructions().
◆ use_instructions()
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Definition at line 500 of file MachineRegisterInfo.h.
References llvm::make_range(), Reg, use_instr_begin(), and use_instr_end().
Referenced by llvm::GISelChangeObserver::changingAllUsesOfReg(), dumpUses(), eliminateMove(), fixupSetCC(), isASCastInGVar(), isCopyFeedingInvariantStore(), isDefLiveOut(), markUsesInDebugValueAsUndef(), suppressEGPRRegClassInRegAndUses(), and traverseMoveUse().
◆ use_nodbg_begin()
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Definition at line 542 of file MachineRegisterInfo.h.
Referenced by llvm::dumpMaxRegPressure(), oneUseDominatesOtherUses(), use_nodbg_empty(), and use_nodbg_operands().
◆ use_nodbg_bundles()
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Definition at line 584 of file MachineRegisterInfo.h.
References llvm::make_range(), Reg, use_bundle_nodbg_begin(), and use_bundle_nodbg_end().
◆ use_nodbg_empty()
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition at line 590 of file MachineRegisterInfo.h.
References use_nodbg_begin(), and use_nodbg_end().
Referenced by addImplicitDefs(), llvm::PPCInstrInfo::combineRLWINM(), EmitLiveInCopies(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::PPCInstrInfo::foldImmediate(), llvm::SIInstrInfo::foldImmediate(), llvm::SystemZInstrInfo::foldImmediate(), llvm::isTriviallyDead(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::SIInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), and llvm::SIInstrInfo::reMaterialize().
◆ use_nodbg_end()
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inlinestatic |
Definition at line 545 of file MachineRegisterInfo.h.
Referenced by llvm::dumpMaxRegPressure(), use_nodbg_empty(), and use_nodbg_operands().
◆ use_nodbg_instructions()
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inline |
Definition at line 567 of file MachineRegisterInfo.h.
References llvm::make_range(), Reg, use_instr_nodbg_begin(), and use_instr_nodbg_end().
Referenced by allUsesHaveSourceMods(), llvm::NVPTXInstrInfo::commuteInstructionImpl(), deduceTypeFromUses(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::PPCRegisterBankInfo::getInstrMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), getOneNonDBGUser(), llvm::AArch64RegisterInfo::getRegAllocationHints(), hasAssignType(), hasOneNonDBGUser(), isDead(), llvm::MachineInstr::isDead(), preferGPRForFPImm(), and llvm::AArch64RegisterInfo::shouldCoalesce().
◆ use_nodbg_operands()
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inline |
Definition at line 550 of file MachineRegisterInfo.h.
References llvm::make_range(), Reg, use_nodbg_begin(), and use_nodbg_end().
Referenced by dominatesAllUsesOf(), llvm::execMayBeModifiedBeforeAnyUse(), findUseBetween(), getOneNonDBGUse(), hasAllNBitUsers(), hasAllNBitUsers(), hasOneNonDBGUse(), hasSingleUse(), oneUseDominatesOtherUses(), replaceDominatedUses(), and rescheduleCanonically().
◆ use_operands()
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inline |
Definition at line 484 of file MachineRegisterInfo.h.
References llvm::make_range(), Reg, use_begin(), and use_end().
Referenced by llvm::MachineInstr::changeDebugValuesDefReg(), clearKillFlags(), hasUseAfterLoop(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::PeelSingleBlockLoop(), propagateLocalCopies(), replaceRegUsesAfterLoop(), llvm::salvageDebugInfo(), and tryCompressVPMOVPattern().
◆ verifyUseList()
| void MachineRegisterInfo::verifyUseList | ( | Register | Reg | ) | const |
Verify the sanity of the use list for Reg.
Definition at line 223 of file MachineRegisterInfo.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, assert(), llvm::errs(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), getTargetRegisterInfo(), llvm::MachineOperand::isReg(), MI, llvm::printReg(), and reg_operands().
Referenced by clearVirtRegs(), and verifyUseLists().
◆ verifyUseLists()
| void MachineRegisterInfo::verifyUseLists | ( | ) | const |
Verify the use list of all registers.
Definition at line 261 of file MachineRegisterInfo.cpp.
References getNumVirtRegs(), getTargetRegisterInfo(), llvm::Register::index2VirtReg(), and verifyUseList().
Friends And Related Symbol Documentation
◆ defusechain_instr_iterator
Definition at line 293 of file MachineRegisterInfo.h.
◆ defusechain_iterator
Definition at line 292 of file MachineRegisterInfo.h.
The documentation for this class was generated from the following files:
- include/llvm/CodeGen/MachineRegisterInfo.h
- lib/CodeGen/MachineRegisterInfo.cpp
Generated on for LLVM by
1.14.0