LLVM  11.0.0git
ThumbRegisterInfo.cpp
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1 //===-- ThumbRegisterInfo.cpp - Thumb-1 Register Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb-1 implementation of the TargetRegisterInfo
10 // class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ThumbRegisterInfo.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "ARMSubtarget.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/LLVMContext.h"
33 
34 namespace llvm {
36 }
37 
38 using namespace llvm;
39 
41 
42 const TargetRegisterClass *
44  const MachineFunction &MF) const {
47 
48  if (ARM::tGPRRegClass.hasSubClassEq(RC))
49  return &ARM::tGPRRegClass;
51 }
52 
53 const TargetRegisterClass *
55  unsigned Kind) const {
58  return &ARM::tGPRRegClass;
59 }
60 
63  const DebugLoc &dl, unsigned DestReg,
64  unsigned SubIdx, int Val,
65  ARMCC::CondCodes Pred, unsigned PredReg,
66  unsigned MIFlags) {
67  MachineFunction &MF = *MBB.getParent();
68  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
69  const TargetInstrInfo &TII = *STI.getInstrInfo();
71  const Constant *C = ConstantInt::get(
73  unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align(4));
74 
75  BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
76  .addReg(DestReg, getDefRegState(true), SubIdx)
77  .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
78  .setMIFlags(MIFlags);
79 }
80 
83  const DebugLoc &dl, unsigned DestReg,
84  unsigned SubIdx, int Val,
85  ARMCC::CondCodes Pred, unsigned PredReg,
86  unsigned MIFlags) {
87  MachineFunction &MF = *MBB.getParent();
90  const Constant *C = ConstantInt::get(
92  unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align(4));
93 
94  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
95  .addReg(DestReg, getDefRegState(true), SubIdx)
96  .addConstantPoolIndex(Idx)
98  .setMIFlags(MIFlags);
99 }
100 
101 /// emitLoadConstPool - Emits a load from constpool to materialize the
102 /// specified immediate.
105  const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val,
106  ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const {
107  MachineFunction &MF = *MBB.getParent();
108  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
109  if (STI.isThumb1Only()) {
110  assert((isARMLowRegister(DestReg) || DestReg.isVirtual()) &&
111  "Thumb1 does not have ldr to high register");
112  return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
113  PredReg, MIFlags);
114  }
115  return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
116  PredReg, MIFlags);
117 }
118 
119 /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
120 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
121 /// in a register using mov / mvn sequences or load the immediate from a
122 /// constpool entry.
125  const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes,
126  bool CanChangeCC, const TargetInstrInfo &TII,
127  const ARMBaseRegisterInfo &MRI, unsigned MIFlags = MachineInstr::NoFlags) {
128  MachineFunction &MF = *MBB.getParent();
129  const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>();
130  bool isHigh = !isARMLowRegister(DestReg) ||
131  (BaseReg != 0 && !isARMLowRegister(BaseReg));
132  bool isSub = false;
133  // Subtract doesn't have high register version. Load the negative value
134  // if either base or dest register is a high register. Also, if do not
135  // issue sub as part of the sequence if condition register is to be
136  // preserved.
137  if (NumBytes < 0 && !isHigh && CanChangeCC) {
138  isSub = true;
139  NumBytes = -NumBytes;
140  }
141  Register LdReg = DestReg;
142  if (DestReg == ARM::SP)
143  assert(BaseReg == ARM::SP && "Unexpected!");
144  if (!isARMLowRegister(DestReg) && !Register::isVirtualRegister(DestReg))
145  LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
146 
147  if (NumBytes <= 255 && NumBytes >= 0 && CanChangeCC) {
148  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)
149  .add(t1CondCodeOp())
150  .addImm(NumBytes)
151  .setMIFlags(MIFlags);
152  } else if (NumBytes < 0 && NumBytes >= -255 && CanChangeCC) {
153  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)
154  .add(t1CondCodeOp())
155  .addImm(NumBytes)
156  .setMIFlags(MIFlags);
157  BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)
158  .add(t1CondCodeOp())
159  .addReg(LdReg, RegState::Kill)
160  .setMIFlags(MIFlags);
161  } else if (ST.genExecuteOnly()) {
162  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), LdReg)
163  .addImm(NumBytes).setMIFlags(MIFlags);
164  } else
165  MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes, ARMCC::AL, 0,
166  MIFlags);
167 
168  // Emit add / sub.
169  int Opc = (isSub) ? ARM::tSUBrr
170  : ((isHigh || !CanChangeCC) ? ARM::tADDhirr : ARM::tADDrr);
171  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
172  if (Opc != ARM::tADDhirr)
173  MIB = MIB.add(t1CondCodeOp());
174  if (DestReg == ARM::SP || isSub)
175  MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
176  else
177  MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
178  MIB.add(predOps(ARMCC::AL));
179 }
180 
181 /// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
182 /// a destreg = basereg + immediate in Thumb code. Tries a series of ADDs or
183 /// SUBs first, and uses a constant pool value if the instruction sequence would
184 /// be too long. This is allowed to modify the condition flags.
187  const DebugLoc &dl, Register DestReg,
188  Register BaseReg, int NumBytes,
189  const TargetInstrInfo &TII,
190  const ARMBaseRegisterInfo &MRI,
191  unsigned MIFlags) {
192  bool isSub = NumBytes < 0;
193  unsigned Bytes = (unsigned)NumBytes;
194  if (isSub) Bytes = -NumBytes;
195 
196  int CopyOpc = 0;
197  unsigned CopyBits = 0;
198  unsigned CopyScale = 1;
199  bool CopyNeedsCC = false;
200  int ExtraOpc = 0;
201  unsigned ExtraBits = 0;
202  unsigned ExtraScale = 1;
203  bool ExtraNeedsCC = false;
204 
205  // Strategy:
206  // We need to select two types of instruction, maximizing the available
207  // immediate range of each. The instructions we use will depend on whether
208  // DestReg and BaseReg are low, high or the stack pointer.
209  // * CopyOpc - DestReg = BaseReg + imm
210  // This will be emitted once if DestReg != BaseReg, and never if
211  // DestReg == BaseReg.
212  // * ExtraOpc - DestReg = DestReg + imm
213  // This will be emitted as many times as necessary to add the
214  // full immediate.
215  // If the immediate ranges of these instructions are not large enough to cover
216  // NumBytes with a reasonable number of instructions, we fall back to using a
217  // value loaded from a constant pool.
218  if (DestReg == ARM::SP) {
219  if (BaseReg == ARM::SP) {
220  // sp -> sp
221  // Already in right reg, no copy needed
222  } else {
223  // low -> sp or high -> sp
224  CopyOpc = ARM::tMOVr;
225  CopyBits = 0;
226  }
227  ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi;
228  ExtraBits = 7;
229  ExtraScale = 4;
230  } else if (isARMLowRegister(DestReg)) {
231  if (BaseReg == ARM::SP) {
232  // sp -> low
233  assert(!isSub && "Thumb1 does not have tSUBrSPi");
234  CopyOpc = ARM::tADDrSPi;
235  CopyBits = 8;
236  CopyScale = 4;
237  } else if (DestReg == BaseReg) {
238  // low -> same low
239  // Already in right reg, no copy needed
240  } else if (isARMLowRegister(BaseReg)) {
241  // low -> different low
242  CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3;
243  CopyBits = 3;
244  CopyNeedsCC = true;
245  } else {
246  // high -> low
247  CopyOpc = ARM::tMOVr;
248  CopyBits = 0;
249  }
250  ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
251  ExtraBits = 8;
252  ExtraNeedsCC = true;
253  } else /* DestReg is high */ {
254  if (DestReg == BaseReg) {
255  // high -> same high
256  // Already in right reg, no copy needed
257  } else {
258  // {low,high,sp} -> high
259  CopyOpc = ARM::tMOVr;
260  CopyBits = 0;
261  }
262  ExtraOpc = 0;
263  }
264 
265  // We could handle an unaligned immediate with an unaligned copy instruction
266  // and an aligned extra instruction, but this case is not currently needed.
267  assert(((Bytes & 3) == 0 || ExtraScale == 1) &&
268  "Unaligned offset, but all instructions require alignment");
269 
270  unsigned CopyRange = ((1 << CopyBits) - 1) * CopyScale;
271  // If we would emit the copy with an immediate of 0, just use tMOVr.
272  if (CopyOpc && Bytes < CopyScale) {
273  CopyOpc = ARM::tMOVr;
274  CopyScale = 1;
275  CopyNeedsCC = false;
276  CopyRange = 0;
277  }
278  unsigned ExtraRange = ((1 << ExtraBits) - 1) * ExtraScale; // per instruction
279  unsigned RequiredCopyInstrs = CopyOpc ? 1 : 0;
280  unsigned RangeAfterCopy = (CopyRange > Bytes) ? 0 : (Bytes - CopyRange);
281 
282  // We could handle this case when the copy instruction does not require an
283  // aligned immediate, but we do not currently do this.
284  assert(RangeAfterCopy % ExtraScale == 0 &&
285  "Extra instruction requires immediate to be aligned");
286 
287  unsigned RequiredExtraInstrs;
288  if (ExtraRange)
289  RequiredExtraInstrs = alignTo(RangeAfterCopy, ExtraRange) / ExtraRange;
290  else if (RangeAfterCopy > 0)
291  // We need an extra instruction but none is available
292  RequiredExtraInstrs = 1000000;
293  else
294  RequiredExtraInstrs = 0;
295  unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs;
296  unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
297 
298  // Use a constant pool, if the sequence of ADDs/SUBs is too expensive.
299  if (RequiredInstrs > Threshold) {
300  emitThumbRegPlusImmInReg(MBB, MBBI, dl,
301  DestReg, BaseReg, NumBytes, true,
302  TII, MRI, MIFlags);
303  return;
304  }
305 
306  // Emit zero or one copy instructions
307  if (CopyOpc) {
308  unsigned CopyImm = std::min(Bytes, CopyRange) / CopyScale;
309  Bytes -= CopyImm * CopyScale;
310 
311  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
312  if (CopyNeedsCC)
313  MIB = MIB.add(t1CondCodeOp());
314  MIB.addReg(BaseReg, RegState::Kill);
315  if (CopyOpc != ARM::tMOVr) {
316  MIB.addImm(CopyImm);
317  }
318  MIB.setMIFlags(MIFlags).add(predOps(ARMCC::AL));
319 
320  BaseReg = DestReg;
321  }
322 
323  // Emit zero or more in-place add/sub instructions
324  while (Bytes) {
325  unsigned ExtraImm = std::min(Bytes, ExtraRange) / ExtraScale;
326  Bytes -= ExtraImm * ExtraScale;
327 
328  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg);
329  if (ExtraNeedsCC)
330  MIB = MIB.add(t1CondCodeOp());
331  MIB.addReg(BaseReg)
332  .addImm(ExtraImm)
334  .setMIFlags(MIFlags);
335  }
336 }
337 
338 static void removeOperands(MachineInstr &MI, unsigned i) {
339  unsigned Op = i;
340  for (unsigned e = MI.getNumOperands(); i != e; ++i)
341  MI.RemoveOperand(Op);
342 }
343 
344 /// convertToNonSPOpcode - Change the opcode to the non-SP version, because
345 /// we're replacing the frame index with a non-SP register.
346 static unsigned convertToNonSPOpcode(unsigned Opcode) {
347  switch (Opcode) {
348  case ARM::tLDRspi:
349  return ARM::tLDRi;
350 
351  case ARM::tSTRspi:
352  return ARM::tSTRi;
353  }
354 
355  return Opcode;
356 }
357 
359  unsigned FrameRegIdx,
360  Register FrameReg, int &Offset,
361  const ARMBaseInstrInfo &TII) const {
362  MachineInstr &MI = *II;
364  assert(MBB.getParent()->getSubtarget<ARMSubtarget>().isThumb1Only() &&
365  "This isn't needed for thumb2!");
366  DebugLoc dl = MI.getDebugLoc();
367  MachineInstrBuilder MIB(*MBB.getParent(), &MI);
368  unsigned Opcode = MI.getOpcode();
369  const MCInstrDesc &Desc = MI.getDesc();
370  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
371 
372  if (Opcode == ARM::tADDframe) {
373  Offset += MI.getOperand(FrameRegIdx+1).getImm();
374  Register DestReg = MI.getOperand(0).getReg();
375 
376  emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
377  *this);
378  MBB.erase(II);
379  return true;
380  } else {
381  if (AddrMode != ARMII::AddrModeT1_s)
382  llvm_unreachable("Unsupported addressing mode!");
383 
384  unsigned ImmIdx = FrameRegIdx + 1;
385  int InstrOffs = MI.getOperand(ImmIdx).getImm();
386  unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
387  unsigned Scale = 4;
388 
389  Offset += InstrOffs * Scale;
390  assert((Offset & (Scale - 1)) == 0 && "Can't encode this offset!");
391 
392  // Common case: small offset, fits into instruction.
393  MachineOperand &ImmOp = MI.getOperand(ImmIdx);
394  int ImmedOffset = Offset / Scale;
395  unsigned Mask = (1 << NumBits) - 1;
396 
397  if ((unsigned)Offset <= Mask * Scale) {
398  // Replace the FrameIndex with the frame register (e.g., sp).
399  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
400  ImmOp.ChangeToImmediate(ImmedOffset);
401 
402  // If we're using a register where sp was stored, convert the instruction
403  // to the non-SP version.
404  unsigned NewOpc = convertToNonSPOpcode(Opcode);
405  if (NewOpc != Opcode && FrameReg != ARM::SP)
406  MI.setDesc(TII.get(NewOpc));
407 
408  return true;
409  }
410 
411  NumBits = 5;
412  Mask = (1 << NumBits) - 1;
413 
414  // If this is a thumb spill / restore, we will be using a constpool load to
415  // materialize the offset.
416  if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
417  ImmOp.ChangeToImmediate(0);
418  } else {
419  // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
420  ImmedOffset = ImmedOffset & Mask;
421  ImmOp.ChangeToImmediate(ImmedOffset);
422  Offset &= ~(Mask * Scale);
423  }
424  }
425 
426  return Offset == 0;
427 }
428 
430  int64_t Offset) const {
431  const MachineFunction &MF = *MI.getParent()->getParent();
432  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
433  if (!STI.isThumb1Only())
434  return ARMBaseRegisterInfo::resolveFrameIndex(MI, BaseReg, Offset);
435 
436  const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
437  int Off = Offset; // ARM doesn't need the general 64-bit offsets
438  unsigned i = 0;
439 
440  while (!MI.getOperand(i).isFI()) {
441  ++i;
442  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
443  }
444  bool Done = rewriteFrameIndex(MI, i, BaseReg, Off, TII);
445  assert (Done && "Unable to resolve frame index!");
446  (void)Done;
447 }
448 
450  int SPAdj, unsigned FIOperandNum,
451  RegScavenger *RS) const {
452  MachineInstr &MI = *II;
454  MachineFunction &MF = *MBB.getParent();
455  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
456  if (!STI.isThumb1Only())
457  return ARMBaseRegisterInfo::eliminateFrameIndex(II, SPAdj, FIOperandNum,
458  RS);
459 
460  Register VReg;
461  const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
462  DebugLoc dl = MI.getDebugLoc();
463  MachineInstrBuilder MIB(*MBB.getParent(), &MI);
464 
465  Register FrameReg;
466  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
467  const ARMFrameLowering *TFI = getFrameLowering(MF);
468  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
469 
470  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
471  // call frame setup/destroy instructions have already been eliminated. That
472  // means the stack pointer cannot be used to access the emergency spill slot
473  // when !hasReservedCallFrame().
474 #ifndef NDEBUG
475  if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
477  "Cannot use SP to access the emergency spill slot in "
478  "functions without a reserved call frame");
480  "Cannot use SP to access the emergency spill slot in "
481  "functions with variable sized frame objects");
482  }
483 #endif // NDEBUG
484 
485  // Special handling of dbg_value instructions.
486  if (MI.isDebugValue()) {
487  MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/);
488  MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
489  return;
490  }
491 
492  // Modify MI as necessary to handle as much of 'Offset' as possible
494  "This eliminateFrameIndex only supports Thumb1!");
495  if (rewriteFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
496  return;
497 
498  // If we get here, the immediate doesn't fit into the instruction. We folded
499  // as much as possible above, handle the rest, providing a register that is
500  // SP+LargeImm.
501  assert(Offset && "This code isn't needed if offset already handled!");
502 
503  unsigned Opcode = MI.getOpcode();
504 
505  // Remove predicate first.
506  int PIdx = MI.findFirstPredOperandIdx();
507  if (PIdx != -1)
508  removeOperands(MI, PIdx);
509 
510  if (MI.mayLoad()) {
511  // Use the destination register to materialize sp + offset.
512  Register TmpReg = MI.getOperand(0).getReg();
513  bool UseRR = false;
514  if (Opcode == ARM::tLDRspi) {
515  if (FrameReg == ARM::SP || STI.genExecuteOnly())
516  emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
517  Offset, false, TII, *this);
518  else {
519  emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset);
520  UseRR = true;
521  }
522  } else {
523  emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII,
524  *this);
525  }
526 
527  MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
528  MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
529  if (UseRR)
530  // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
531  // register. The offset is already handled in the vreg value.
532  MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
533  false);
534  } else if (MI.mayStore()) {
535  VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
536  bool UseRR = false;
537 
538  if (Opcode == ARM::tSTRspi) {
539  if (FrameReg == ARM::SP || STI.genExecuteOnly())
540  emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg,
541  Offset, false, TII, *this);
542  else {
543  emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
544  UseRR = true;
545  }
546  } else
547  emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
548  *this);
549  MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
550  MI.getOperand(FIOperandNum).ChangeToRegister(VReg, false, false, true);
551  if (UseRR)
552  // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
553  // register. The offset is already handled in the vreg value.
554  MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
555  false);
556  } else {
557  llvm_unreachable("Unexpected opcode!");
558  }
559 
560  // Add predicate back if it's needed.
561  if (MI.isPredicable())
562  MIB.add(predOps(ARMCC::AL));
563 }
564 
565 bool
567  if (MF.getSubtarget<ARMSubtarget>().isThumb1Only()) {
568  // For Thumb1, the emergency spill slot must be some small positive
569  // offset from the base/stack pointer.
570  return false;
571  }
572  // For Thumb2, put the emergency spill slot next to FP.
573  return true;
574 }
uint64_t CallInst * C
const MachineInstrBuilder & add(const MachineOperand &MO) const
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:21
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static void removeOperands(MachineInstr &MI, unsigned i)
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:409
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:187
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:822
A debug info location.
Definition: DebugLoc.h:33
bool isThumb1Only() const
Definition: ARMSubtarget.h:784
static unsigned convertToNonSPOpcode(unsigned Opcode)
convertToNonSPOpcode - Change the opcode to the non-SP version, because we&#39;re replacing the frame ind...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Function & getFunction()
Return the LLVM function that this machine code represents.
bool genExecuteOnly() const
Definition: ARMSubtarget.h:694
MachineBasicBlock & MBB
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:537
static void emitThumb2LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:459
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
bool useFPForScavengingIndex(const MachineFunction &MF) const override
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:456
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:453
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
static void emitThumb1LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags)
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:92
virtual const TargetInstrInfo * getInstrInfo() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, Register PredReg=Register(), unsigned MIFlags=MachineInstr::NoFlags) const override
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
int ResolveFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg, int SPAdj) const
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getDefRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:955
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:305
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
constexpr double e
Definition: MathExtras.h:58
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:545
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:230
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
bool isDebugValue() const
MachineOperand class - Representation of each machine instruction operand.
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:786
bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII) const
int64_t getImm() const
static cl::opt< unsigned > Threshold("loop-unswitch-threshold", cl::desc("Max loop size to unswitch"), cl::init(100), cl::Hidden)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:280
cl::opt< bool > ReuseFrameIndexVals
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:160
Representation of each machine instruction.
Definition: MachineInstr.h:62
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:158
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:186
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, Register PredReg=Register(), unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:62
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=MachineInstr::NoFlags)
emitThumbRegPlusImmInReg - Emits a series of instructions to materialize a destreg = basereg + immedi...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:942
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
IRTranslator LLVM IR MI
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:466
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MachineBasicBlock MachineBasicBlock::iterator MBBI
Wrapper class representing virtual and physical registers.
Definition: Register.h:19