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13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
14 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
25 #include "llvm/IR/IntrinsicsARM.h"
29 #define GET_INSTRINFO_HEADER
30 #include "ARMGenInstrInfo.inc"
34 class ARMBaseRegisterInfo;
45 unsigned LoadImmOpc,
unsigned LoadOpc)
const;
103 unsigned OpIdx2)
const override;
107 std::optional<DestSourcePair>
112 std::optional<ParamLoadedValue>
145 bool AllowModify =
false)
const override;
147 int *BytesRemoved =
nullptr)
const override;
151 int *BytesAdded =
nullptr)
const override;
166 int PIdx =
MI.findFirstPredOperandIdx();
178 bool SkipDead)
const override;
199 unsigned SrcReg,
bool KillSrc,
202 unsigned DestReg,
bool KillSrc,
207 bool KillSrc)
const override;
236 unsigned SubIdx,
unsigned State,
248 int64_t &Offset2)
const override;
259 int64_t Offset1, int64_t Offset2,
260 unsigned NumLoads)
const override;
267 unsigned NumCycles,
unsigned ExtraPredCycles,
272 unsigned NumF,
unsigned ExtraF,
277 return NumCycles == 1;
281 unsigned NumInsts)
const override;
292 Register &SrcReg2, int64_t &CmpMask,
293 int64_t &CmpValue)
const override;
300 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
305 unsigned &FalseOp,
bool &Optimizable)
const override;
309 bool)
const override;
322 unsigned UseIdx)
const override;
324 SDNode *DefNode,
unsigned DefIdx,
325 SDNode *UseNode,
unsigned UseIdx)
const override;
328 std::pair<uint16_t, uint16_t>
341 std::pair<unsigned, unsigned>
350 bool OutlineFromLinkOnceODRs)
const override;
352 std::vector<outliner::Candidate> &RepeatedSequenceLocs)
const override;
354 Function &
F, std::vector<outliner::Candidate> &Candidates)
const override;
356 unsigned Flags)
const override;
358 unsigned &Flags)
const override;
370 return MI->getOpcode() == ARM::t2LoopEndDec ||
371 MI->getOpcode() == ARM::t2DoLoopStartTP ||
372 MI->getOpcode() == ARM::t2WhileLoopStartLR ||
373 MI->getOpcode() == ARM::t2WhileLoopStartTP;
378 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
391 bool CFI,
bool Auth)
const;
427 unsigned DefIdx,
unsigned DefAlign)
const;
431 unsigned DefIdx,
unsigned DefAlign)
const;
435 unsigned UseIdx,
unsigned UseAlign)
const;
439 unsigned UseIdx,
unsigned UseAlign)
const;
442 unsigned DefIdx,
unsigned DefAlign,
444 unsigned UseIdx,
unsigned UseAlign)
const;
451 const MCInstrDesc &UseMCID,
unsigned UseAdj)
const;
453 unsigned getPredicationCost(
const MachineInstr &
MI)
const override;
457 unsigned *PredCost =
nullptr)
const override;
466 unsigned UseIdx)
const override;
469 unsigned DefIdx)
const override;
484 bool isReallyTriviallyReMaterializable(
const MachineInstr &
MI)
const override;
501 return MLxEntryMap.
count(Opcode);
508 unsigned &AddSubOpc,
bool &NegAcc,
509 bool &HasLane)
const;
515 return MLxHazardOpcodes.
count(Opcode);
532 return MI.getOperand(3).getReg();
543 unsigned PredReg = 0) {
565 return Opc ==
ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
572 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
573 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
574 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
575 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
576 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
577 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
578 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
579 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
580 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
581 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
582 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
583 Opc == ARM::MVE_VPST;
591 case ARM::MVE_VCMPf32:
592 return ARM::MVE_VPTv4f32;
593 case ARM::MVE_VCMPf16:
594 return ARM::MVE_VPTv8f16;
595 case ARM::MVE_VCMPi8:
596 return ARM::MVE_VPTv16i8;
597 case ARM::MVE_VCMPi16:
598 return ARM::MVE_VPTv8i16;
599 case ARM::MVE_VCMPi32:
600 return ARM::MVE_VPTv4i32;
601 case ARM::MVE_VCMPu8:
602 return ARM::MVE_VPTv16u8;
603 case ARM::MVE_VCMPu16:
604 return ARM::MVE_VPTv8u16;
605 case ARM::MVE_VCMPu32:
606 return ARM::MVE_VPTv4u32;
607 case ARM::MVE_VCMPs8:
608 return ARM::MVE_VPTv16s8;
609 case ARM::MVE_VCMPs16:
610 return ARM::MVE_VPTv8s16;
611 case ARM::MVE_VCMPs32:
612 return ARM::MVE_VPTv4s32;
614 case ARM::MVE_VCMPf32r:
615 return ARM::MVE_VPTv4f32r;
616 case ARM::MVE_VCMPf16r:
617 return ARM::MVE_VPTv8f16r;
618 case ARM::MVE_VCMPi8r:
619 return ARM::MVE_VPTv16i8r;
620 case ARM::MVE_VCMPi16r:
621 return ARM::MVE_VPTv8i16r;
622 case ARM::MVE_VCMPi32r:
623 return ARM::MVE_VPTv4i32r;
624 case ARM::MVE_VCMPu8r:
625 return ARM::MVE_VPTv16u8r;
626 case ARM::MVE_VCMPu16r:
627 return ARM::MVE_VPTv8u16r;
628 case ARM::MVE_VCMPu32r:
629 return ARM::MVE_VPTv4u32r;
630 case ARM::MVE_VCMPs8r:
631 return ARM::MVE_VPTv16s8r;
632 case ARM::MVE_VCMPs16r:
633 return ARM::MVE_VPTv8s16r;
634 case ARM::MVE_VCMPs32r:
635 return ARM::MVE_VPTv4s32r;
641 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
645 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
646 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
652 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
656 int Opc =
MI.getOpcode();
662 case ARM::BLX_pred_noip:
664 case ARM::BMOVPCRX_CALL:
665 case ARM::TCRETURNri:
669 case ARM::tBLXr_noip:
671 case ARM::tBLXNS_CALL:
679 case ARM::BMOVPCB_CALL:
682 case ARM::TCRETURNdi:
692 case ARM::tBL_PUSHLR:
693 case ARM::tTAILJMPdND:
704 int opc =
MI.getOpcode();
710 return Opc == ARM::SpeculationBarrierISBDSBEndBB ||
711 Opc == ARM::SpeculationBarrierSBEndBB ||
712 Opc == ARM::t2SpeculationBarrierISBDSBEndBB ||
713 Opc == ARM::t2SpeculationBarrierSBEndBB;
717 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
718 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
719 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
723 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
724 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
728 return Opc == ARM::SUBri ||
729 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||
730 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||
731 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;
735 return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;
748 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
753 if (featureBits[ARM::HasV8_1MMainlineOps] &&
754 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
761 unsigned Opc =
MI.getOpcode();
763 case ARM::SEH_StackAlloc:
764 case ARM::SEH_SaveRegs:
765 case ARM::SEH_SaveRegs_Ret:
766 case ARM::SEH_SaveSP:
767 case ARM::SEH_SaveFRegs:
768 case ARM::SEH_SaveLR:
770 case ARM::SEH_Nop_Ret:
771 case ARM::SEH_PrologEnd:
772 case ARM::SEH_EpilogStart:
773 case ARM::SEH_EpilogEnd:
797 const DebugLoc &dl, Register DestReg,
798 Register BaseReg,
int NumBytes,
800 const ARMBaseInstrInfo &
TII,
unsigned MIFlags = 0);
804 const DebugLoc &dl, Register DestReg,
805 Register BaseReg,
int NumBytes,
807 const ARMBaseInstrInfo &
TII,
unsigned MIFlags = 0);
810 const DebugLoc &dl, Register DestReg,
811 Register BaseReg,
int NumBytes,
812 const TargetInstrInfo &
TII,
813 const ARMBaseRegisterInfo &
MRI,
814 unsigned MIFlags = 0);
822 MachineFunction &MF, MachineInstr *
MI,
830 Register FrameReg,
int &
Offset,
831 const ARMBaseInstrInfo &
TII);
834 Register FrameReg,
int &
Offset,
835 const ARMBaseInstrInfo &
TII,
836 const TargetRegisterInfo *
TRI);
841 const TargetRegisterInfo *
TRI);
846 const TargetRegisterInfo *
TRI);
859 const ARMSubtarget *Subtarget,
860 bool ForCodesize =
false);
866 const ARMSubtarget *Subtarget,
867 bool ForCodesize =
false);
874 switch (
MI.getOpcode()) {
891 return Scale *
MI.getOperand(ImmOp).getImm();
910 return Imm >= 0 &&
Imm < ((1 << 8) * 1);
912 return Imm < 0 && -
Imm < ((1 << 8) * 1);
916 return Imm >= 0 &&
Imm < ((1 << 12) * 1);
926 if (IntInst ==
nullptr)
929 return (IntrinsicID == Intrinsic::masked_gather ||
930 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base ||
931 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated ||
932 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb ||
933 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated ||
934 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset ||
935 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated);
940 if (IntInst ==
nullptr)
943 return (IntrinsicID == Intrinsic::masked_scatter ||
944 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base ||
945 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated ||
946 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb ||
947 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated ||
948 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset ||
949 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated);
954 if (IntInst ==
nullptr)
965 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond)
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
This is an optimization pass for GlobalISel generic memory operations.
std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
MachineInstrBuilder & UseMI
unsigned getFramePred(const MachineInstr &MI) const
Returns predicate register associated with the given frame instruction.
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
VFP/NEON execution domains.
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
Reg
All possible values of the reg field in the ModR/M byte.
Represents one node in the SelectionDAG.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
InstrType
Represents how an instruction should be mapped by the outliner.
static bool isCondBranchOpcode(int Opc)
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value description...
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
Container class for subtarget features.
static bool isUncondBranchOpcode(int Opc)
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const
The information necessary to create an outlined function for some class of candidate.
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
MachineInstr * findCMPToFoldIntoCBZ(MachineInstr *Br, const TargetRegisterInfo *TRI)
Search backwards from a tBcc to find a tCMPi8 against 0, meaning we can convert them to a tCBZ or tCB...
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
unsigned const TargetRegisterInfo * TRI
static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)
isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...
bool isGather(IntrinsicInst *IntInst)
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
A pair composed of a register and a sub-register index.
int getAddSubImmediate(MachineInstr &MI)
unsigned getBLXOpcode(const MachineFunction &MF)
static bool isSEHInstruction(const MachineInstr &MI)
unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override
TargetInstrInfo - Interface to description of machine instruction set.
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
static MachineOperand CreateImm(int64_t Val)
bool isGatherScatter(IntrinsicInst *IntInst)
(vector float) vec_cmpeq(*A, *B) C
std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Returns the size of the specified MachineInstr.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
bool shouldSink(const MachineInstr &MI) const override
const HexagonInstrInfo * TII
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
Describe properties that are true of each instruction in the target description file.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
unsigned getNumLDMAddresses(const MachineInstr &MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
void breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
static bool isPopOpcode(int Opc)
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
static unsigned VCMPOpcodeToVPT(unsigned Opcode)
TargetInstrInfo::RegSubRegPairAndIdx RegSubRegPairAndIdx
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool isPredicable(const MachineInstr &MI) const override
isPredicable - Return true if the specified instruction can be predicated.
static bool isIndirectBranchOpcode(int Opc)
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const override
static bool isCPSRDefined(const MachineInstr &MI)
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
static bool isVPTOpcode(int Opc)
Provide an instruction scheduling machine model to CodeGen passes.
Representation of each machine instruction.
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition,...
unsigned getMatchingCondBranchOpcode(unsigned Opc)
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
An individual sequence of instructions to be replaced with a call to an outlined function.
unsigned getBLXpredOpcode(const MachineFunction &MF)
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)
bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI)
Return true if Reg is defd between From and To.
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB)
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isLegalAddressImm(unsigned Opcode, int Imm, const TargetInstrInfo *TII)
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
unsigned gettBLXrOpcode(const MachineFunction &MF)
A Module instance is used to store all the information related to an LLVM module.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
MachineInstrBundleIterator< MachineInstr > iterator
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, unsigned Inactive)
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
SmallVector< MachineOperand, 4 > Cond
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
StringRef - Represent a constant reference to a string, i.e.
MachineBasicBlock MachineBasicBlock::iterator MBBI
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
ARM supports the MachineOutliner.
TargetSubtargetInfo - Generic base class for all target subtargets.
static bool isIndirectCall(const MachineInstr &MI)
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
unsigned getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isScatter(IntrinsicInst *IntInst)
bool isPredicated(const MachineInstr &MI) const override
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const override
A wrapper class for inspecting calls to intrinsic functions.
static bool isPushOpcode(int Opc)
static bool isJumpTableBranchOpcode(int Opc)
unsigned ConstantMaterializationCost(unsigned Val, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns the number of instructions required to materialize the given constant in a register,...
static bool isIndirectControlFlowNotComingBack(const MachineInstr &MI)
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
Enable outlining by default at -Oz.
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
ARMBaseInstrInfo(const ARMSubtarget &STI)
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
BlockVerifier::State From
static bool isSpeculationBarrierEndBBOpcode(int Opc)
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
const ARMSubtarget & getSubtarget() const
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override
APFloat abs(APFloat X)
Returns the absolute value of the argument.
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
static bool isMovRegOpcode(int Opc)
Itinerary data supplied by a subtarget to be used by a target.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
static bool isSubImmOpcode(int Opc)
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
Wrapper class representing physical registers. Should be passed by value.
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns true if Val1 has a lower Constant Materialization Cost than Val2.