13#ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
14#define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
25#include "llvm/IR/IntrinsicsARM.h"
29#define GET_INSTRINFO_HEADER
30#include "ARMGenInstrInfo.inc"
34class ARMBaseRegisterInfo;
45 unsigned LoadImmOpc,
unsigned LoadOpc)
const;
103 unsigned OpIdx2)
const override;
107 std::optional<DestSourcePair>
112 std::optional<ParamLoadedValue>
145 bool AllowModify =
false)
const override;
147 int *BytesRemoved =
nullptr)
const override;
151 int *BytesAdded =
nullptr)
const override;
166 int PIdx =
MI.findFirstPredOperandIdx();
178 bool SkipDead)
const override;
190 int &FrameIndex)
const override;
192 int &FrameIndex)
const override;
194 int &FrameIndex)
const override;
196 int &FrameIndex)
const override;
199 unsigned SrcReg,
bool KillSrc,
202 unsigned DestReg,
bool KillSrc,
207 bool KillSrc)
const override;
211 bool isKill,
int FrameIndex,
236 unsigned SubIdx,
unsigned State,
248 int64_t &Offset2)
const override;
259 int64_t Offset1, int64_t Offset2,
260 unsigned NumLoads)
const override;
267 unsigned NumCycles,
unsigned ExtraPredCycles,
272 unsigned NumF,
unsigned ExtraF,
277 return NumCycles == 1;
281 unsigned NumInsts)
const override;
292 Register &SrcReg2, int64_t &CmpMask,
293 int64_t &CmpValue)
const override;
300 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
305 unsigned &FalseOp,
bool &Optimizable)
const override;
309 bool)
const override;
323 unsigned UseIdx)
const override;
325 SDNode *DefNode,
unsigned DefIdx,
327 unsigned UseIdx)
const override;
330 std::pair<uint16_t, uint16_t>
343 std::pair<unsigned, unsigned>
352 bool OutlineFromLinkOnceODRs)
const override;
354 std::vector<outliner::Candidate> &RepeatedSequenceLocs)
const override;
356 Function &
F, std::vector<outliner::Candidate> &Candidates)
const override;
358 unsigned Flags)
const override;
360 unsigned &Flags)
const override;
372 return MI->getOpcode() == ARM::t2LoopEndDec ||
373 MI->getOpcode() == ARM::t2DoLoopStartTP ||
374 MI->getOpcode() == ARM::t2WhileLoopStartLR ||
375 MI->getOpcode() == ARM::t2WhileLoopStartTP;
380 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
393 bool CFI,
bool Auth)
const;
428 unsigned DefClass,
unsigned DefIdx,
429 unsigned DefAlign)
const;
432 unsigned DefClass,
unsigned DefIdx,
433 unsigned DefAlign)
const;
436 unsigned UseClass,
unsigned UseIdx,
437 unsigned UseAlign)
const;
440 unsigned UseClass,
unsigned UseIdx,
441 unsigned UseAlign)
const;
444 unsigned DefIdx,
unsigned DefAlign,
447 unsigned UseAlign)
const;
449 std::optional<unsigned> getOperandLatencyImpl(
451 unsigned DefIdx,
const MCInstrDesc &DefMCID,
unsigned DefAdj,
453 unsigned UseIdx,
const MCInstrDesc &UseMCID,
unsigned UseAdj)
const;
455 unsigned getPredicationCost(
const MachineInstr &
MI)
const override;
459 unsigned *PredCost =
nullptr)
const override;
468 unsigned UseIdx)
const override;
471 unsigned DefIdx)
const override;
486 bool isReallyTriviallyReMaterializable(
const MachineInstr &
MI)
const override;
510 unsigned &AddSubOpc,
bool &NegAcc,
511 bool &HasLane)
const;
534 return MI.getOperand(3).getReg();
545 unsigned PredReg = 0) {
567 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
574 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
575 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
576 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
577 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
578 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
579 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
580 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
581 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
582 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
583 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
584 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
585 Opc == ARM::MVE_VPST;
593 case ARM::MVE_VCMPf32:
594 return ARM::MVE_VPTv4f32;
595 case ARM::MVE_VCMPf16:
596 return ARM::MVE_VPTv8f16;
597 case ARM::MVE_VCMPi8:
598 return ARM::MVE_VPTv16i8;
599 case ARM::MVE_VCMPi16:
600 return ARM::MVE_VPTv8i16;
601 case ARM::MVE_VCMPi32:
602 return ARM::MVE_VPTv4i32;
603 case ARM::MVE_VCMPu8:
604 return ARM::MVE_VPTv16u8;
605 case ARM::MVE_VCMPu16:
606 return ARM::MVE_VPTv8u16;
607 case ARM::MVE_VCMPu32:
608 return ARM::MVE_VPTv4u32;
609 case ARM::MVE_VCMPs8:
610 return ARM::MVE_VPTv16s8;
611 case ARM::MVE_VCMPs16:
612 return ARM::MVE_VPTv8s16;
613 case ARM::MVE_VCMPs32:
614 return ARM::MVE_VPTv4s32;
616 case ARM::MVE_VCMPf32r:
617 return ARM::MVE_VPTv4f32r;
618 case ARM::MVE_VCMPf16r:
619 return ARM::MVE_VPTv8f16r;
620 case ARM::MVE_VCMPi8r:
621 return ARM::MVE_VPTv16i8r;
622 case ARM::MVE_VCMPi16r:
623 return ARM::MVE_VPTv8i16r;
624 case ARM::MVE_VCMPi32r:
625 return ARM::MVE_VPTv4i32r;
626 case ARM::MVE_VCMPu8r:
627 return ARM::MVE_VPTv16u8r;
628 case ARM::MVE_VCMPu16r:
629 return ARM::MVE_VPTv8u16r;
630 case ARM::MVE_VCMPu32r:
631 return ARM::MVE_VPTv4u32r;
632 case ARM::MVE_VCMPs8r:
633 return ARM::MVE_VPTv16s8r;
634 case ARM::MVE_VCMPs16r:
635 return ARM::MVE_VPTv8s16r;
636 case ARM::MVE_VCMPs32r:
637 return ARM::MVE_VPTv4s32r;
643 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
647 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
648 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
654 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
658 int Opc =
MI.getOpcode();
664 case ARM::BLX_pred_noip:
666 case ARM::BMOVPCRX_CALL:
667 case ARM::TCRETURNri:
671 case ARM::tBLXr_noip:
673 case ARM::tBLXNS_CALL:
681 case ARM::BMOVPCB_CALL:
684 case ARM::TCRETURNdi:
694 case ARM::tBL_PUSHLR:
695 case ARM::tTAILJMPdND:
706 int opc =
MI.getOpcode();
712 return Opc == ARM::SpeculationBarrierISBDSBEndBB ||
713 Opc == ARM::SpeculationBarrierSBEndBB ||
714 Opc == ARM::t2SpeculationBarrierISBDSBEndBB ||
715 Opc == ARM::t2SpeculationBarrierSBEndBB;
719 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
720 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
721 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
725 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
726 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
730 return Opc == ARM::SUBri ||
731 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||
732 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||
733 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;
737 return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;
750 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
755 if (featureBits[ARM::HasV8_1MMainlineOps] &&
756 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
763 unsigned Opc =
MI.getOpcode();
765 case ARM::SEH_StackAlloc:
766 case ARM::SEH_SaveRegs:
767 case ARM::SEH_SaveRegs_Ret:
768 case ARM::SEH_SaveSP:
769 case ARM::SEH_SaveFRegs:
770 case ARM::SEH_SaveLR:
772 case ARM::SEH_Nop_Ret:
773 case ARM::SEH_PrologEnd:
774 case ARM::SEH_EpilogStart:
775 case ARM::SEH_EpilogEnd:
799 const DebugLoc &dl, Register DestReg,
800 Register BaseReg,
int NumBytes,
802 const ARMBaseInstrInfo &
TII,
unsigned MIFlags = 0);
806 const DebugLoc &dl, Register DestReg,
807 Register BaseReg,
int NumBytes,
809 const ARMBaseInstrInfo &
TII,
unsigned MIFlags = 0);
812 const DebugLoc &dl, Register DestReg,
813 Register BaseReg,
int NumBytes,
814 const TargetInstrInfo &
TII,
815 const ARMBaseRegisterInfo &
MRI,
816 unsigned MIFlags = 0);
824 MachineFunction &MF, MachineInstr *
MI,
832 Register FrameReg,
int &
Offset,
833 const ARMBaseInstrInfo &
TII);
836 Register FrameReg,
int &
Offset,
837 const ARMBaseInstrInfo &
TII,
838 const TargetRegisterInfo *
TRI);
843 const TargetRegisterInfo *
TRI);
848 const TargetRegisterInfo *
TRI);
861 const ARMSubtarget *Subtarget,
862 bool ForCodesize =
false);
868 const ARMSubtarget *Subtarget,
869 bool ForCodesize =
false);
876 switch (
MI.getOpcode()) {
893 return Scale *
MI.getOperand(ImmOp).getImm();
904 return std::abs(Imm) < ((1 << 7) * 1);
906 return std::abs(Imm) < ((1 << 7) * 2) && Imm % 2 == 0;
908 return std::abs(Imm) < ((1 << 7) * 4) && Imm % 4 == 0;
910 return std::abs(Imm) < ((1 << 8) * 1);
912 return Imm >= 0 && Imm < ((1 << 8) * 1);
914 return Imm < 0 && -Imm < ((1 << 8) * 1);
916 return std::abs(Imm) < ((1 << 8) * 4) && Imm % 4 == 0;
918 return Imm >= 0 && Imm < ((1 << 12) * 1);
920 return std::abs(Imm) < ((1 << 12) * 1);
928 if (IntInst ==
nullptr)
931 return (IntrinsicID == Intrinsic::masked_gather ||
932 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base ||
933 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated ||
934 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb ||
935 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated ||
936 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset ||
937 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated);
942 if (IntInst ==
nullptr)
945 return (IntrinsicID == Intrinsic::masked_scatter ||
946 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base ||
947 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated ||
948 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb ||
949 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated ||
950 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset ||
951 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated);
956 if (IntInst ==
nullptr)
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
BlockVerifier::State From
This file defines the DenseMap class.
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
PowerPC TLS Dynamic Call Fixup
TargetInstrInfo::RegSubRegPairAndIdx RegSubRegPairAndIdx
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
static constexpr uint32_t Opcode
bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
static bool isCPSRDefined(const MachineInstr &MI)
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
outliner::InstrType getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
unsigned getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
unsigned getNumLDMAddresses(const MachineInstr &MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Returns the size of the specified MachineInstr.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const
std::optional< outliner::OutlinedFunction > getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
ARM supports the MachineOutliner.
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
Enable outlining by default at -Oz.
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
bool isPredicated(const MachineInstr &MI) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
bool isPredicable(const MachineInstr &MI) const override
isPredicable - Return true if the specified instruction can be predicated.
unsigned getFramePred(const MachineInstr &MI) const
Returns predicate register associated with the given frame instruction.
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value description...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const override
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
bool expandPostRAPseudo(MachineInstr &MI) const override
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
VFP/NEON execution domains.
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
void breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
const ARMSubtarget & getSubtarget() const
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
bool shouldSink(const MachineInstr &MI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class represents an Operation in the Expression.
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Container class for subtarget features.
Itinerary data supplied by a subtarget to be used by a target.
A wrapper class for inspecting calls to intrinsic functions.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Describe properties that are true of each instruction in the target description file.
Wrapper class representing physical registers. Should be passed by value.
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Wrapper class representing virtual and physical registers.
Represents one node in the SelectionDAG.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
TargetSubtargetInfo - Generic base class for all target subtargets.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
static bool isIndirectCall(const MachineInstr &MI)
MachineInstr * findCMPToFoldIntoCBZ(MachineInstr *Br, const TargetRegisterInfo *TRI)
Search backwards from a tBcc to find a tCMPi8 against 0, meaning we can convert them to a tCBZ or tCB...
static bool isCondBranchOpcode(int Opc)
bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns true if Val1 has a lower Constant Materialization Cost than Val2.
static bool isPushOpcode(int Opc)
void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond)
unsigned getBLXpredOpcode(const MachineFunction &MF)
static bool isIndirectBranchOpcode(int Opc)
static bool isVPTOpcode(int Opc)
bool isLegalAddressImm(unsigned Opcode, int Imm, const TargetInstrInfo *TII)
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)
bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI)
Return true if Reg is defd between From and To.
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
static bool isSEHInstruction(const MachineInstr &MI)
static bool isMovRegOpcode(int Opc)
bool isGather(IntrinsicInst *IntInst)
static bool isSubImmOpcode(int Opc)
bool isGatherScatter(IntrinsicInst *IntInst)
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
static bool isJumpTableBranchOpcode(int Opc)
static bool isPopOpcode(int Opc)
void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, unsigned Inactive)
static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)
isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...
void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg)
unsigned ConstantMaterializationCost(unsigned Val, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns the number of instructions required to materialize the given constant in a register,...
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
static bool isIndirectControlFlowNotComingBack(const MachineInstr &MI)
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition,...
unsigned getMatchingCondBranchOpcode(unsigned Opc)
static bool isUncondBranchOpcode(int Opc)
bool isScatter(IntrinsicInst *IntInst)
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
static unsigned VCMPOpcodeToVPT(unsigned Opcode)
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
unsigned gettBLXrOpcode(const MachineFunction &MF)
int getAddSubImmediate(MachineInstr &MI)
static bool isSpeculationBarrierEndBBOpcode(int Opc)
unsigned getBLXOpcode(const MachineFunction &MF)
void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB)
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Description of the encoding of one expression Op.
A pair composed of a register and a sub-register index.
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.