LLVM 20.0.0git
ARMBaseInstrInfo.h
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1//===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Base ARM implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
14#define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15
16#include "ARMBaseRegisterInfo.h"
19#include "llvm/ADT/DenseMap.h"
20#include "llvm/ADT/SmallSet.h"
29#include "llvm/IR/IntrinsicsARM.h"
31#include <array>
32#include <cstdint>
33
34#define GET_INSTRINFO_HEADER
35#include "ARMGenInstrInfo.inc"
36
37namespace llvm {
38
39class ARMBaseRegisterInfo;
40class ARMSubtarget;
41
43 const ARMSubtarget &Subtarget;
44
45protected:
46 // Can be only subclassed.
47 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
48
50 unsigned LoadImmOpc, unsigned LoadOpc) const;
51
52 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
53 /// and \p DefIdx.
54 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
55 /// the list is modeled as <Reg:SubReg, SubIdx>.
56 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
57 /// two elements:
58 /// - %1:sub1, sub0
59 /// - %2<:0>, sub1
60 ///
61 /// \returns true if it is possible to build such an input sequence
62 /// with the pair \p MI, \p DefIdx. False otherwise.
63 ///
64 /// \pre MI.isRegSequenceLike().
66 const MachineInstr &MI, unsigned DefIdx,
67 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
68
69 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
70 /// and \p DefIdx.
71 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
72 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
73 /// - %1:sub1, sub0
74 ///
75 /// \returns true if it is possible to build such an input sequence
76 /// with the pair \p MI, \p DefIdx. False otherwise.
77 ///
78 /// \pre MI.isExtractSubregLike().
79 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
80 RegSubRegPairAndIdx &InputReg) const override;
81
82 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
83 /// and \p DefIdx.
84 /// \p [out] BaseReg and \p [out] InsertedReg contain
85 /// the equivalent inputs of INSERT_SUBREG.
86 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
87 /// - BaseReg: %0:sub0
88 /// - InsertedReg: %1:sub1, sub3
89 ///
90 /// \returns true if it is possible to build such an input sequence
91 /// with the pair \p MI, \p DefIdx. False otherwise.
92 ///
93 /// \pre MI.isInsertSubregLike().
94 bool
95 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
96 RegSubRegPair &BaseReg,
97 RegSubRegPairAndIdx &InsertedReg) const override;
98
99 /// Commutes the operands in the given instruction.
100 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
101 ///
102 /// Do not call this method for a non-commutable instruction or for
103 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
104 /// Even though the instruction is commutable, the method may still
105 /// fail to commute the operands, null pointer is returned in such cases.
107 unsigned OpIdx1,
108 unsigned OpIdx2) const override;
109 /// If the specific machine instruction is an instruction that moves/copies
110 /// value from one register to another register return destination and source
111 /// registers as machine operands.
112 std::optional<DestSourcePair>
113 isCopyInstrImpl(const MachineInstr &MI) const override;
114
115 /// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to
116 /// enhance debug entry value descriptions for ARM targets.
117 std::optional<ParamLoadedValue>
118 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
119
120public:
121 // Return whether the target has an explicit NOP encoding.
122 bool hasNOP() const;
123
124 // Return the non-pre/post incrementing version of 'Opc'. Return 0
125 // if there is not such an opcode.
126 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
127
129 LiveIntervals *LIS) const override;
130
131 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
132 const ARMSubtarget &getSubtarget() const { return Subtarget; }
133
136 const ScheduleDAG *DAG) const override;
137
140 const ScheduleDAGMI *DAG) const override;
141
144 const ScheduleDAG *DAG) const override;
145
146 // Branch analysis.
148 MachineBasicBlock *&FBB,
150 bool AllowModify = false) const override;
152 int *BytesRemoved = nullptr) const override;
155 const DebugLoc &DL,
156 int *BytesAdded = nullptr) const override;
157
158 bool
160
161 // Predication support.
162 bool isPredicated(const MachineInstr &MI) const override;
163
164 // MIR printer helper function to annotate Operands with a comment.
165 std::string
167 unsigned OpIdx,
168 const TargetRegisterInfo *TRI) const override;
169
171 int PIdx = MI.findFirstPredOperandIdx();
172 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
173 : ARMCC::AL;
174 }
175
177 ArrayRef<MachineOperand> Pred) const override;
178
180 ArrayRef<MachineOperand> Pred2) const override;
181
182 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
183 bool SkipDead) const override;
184
185 bool isPredicable(const MachineInstr &MI) const override;
186
187 // CPSR defined in instruction
188 static bool isCPSRDefined(const MachineInstr &MI);
189
190 /// GetInstSize - Returns the size of the specified MachineInstr.
191 ///
192 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
193
195 int &FrameIndex) const override;
197 int &FrameIndex) const override;
199 int &FrameIndex) const override;
201 int &FrameIndex) const override;
202
204 unsigned SrcReg, bool KillSrc,
205 const ARMSubtarget &Subtarget) const;
207 unsigned DestReg, bool KillSrc,
208 const ARMSubtarget &Subtarget) const;
209
211 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
212 bool KillSrc) const override;
213
216 bool isKill, int FrameIndex,
217 const TargetRegisterClass *RC,
218 const TargetRegisterInfo *TRI,
219 Register VReg) const override;
220
223 int FrameIndex, const TargetRegisterClass *RC,
224 const TargetRegisterInfo *TRI,
225 Register VReg) const override;
226
227 bool expandPostRAPseudo(MachineInstr &MI) const override;
228
229 bool shouldSink(const MachineInstr &MI) const override;
230
232 Register DestReg, unsigned SubIdx,
233 const MachineInstr &Orig,
234 const TargetRegisterInfo &TRI) const override;
235
238 const MachineInstr &Orig) const override;
239
241 unsigned SubIdx, unsigned State,
242 const TargetRegisterInfo *TRI) const;
243
244 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
245 const MachineRegisterInfo *MRI) const override;
246
247 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
248 /// determine if two loads are loading from the same base address. It should
249 /// only return true if the base pointers are the same and the only
250 /// differences between the two addresses is the offset. It also returns the
251 /// offsets by reference.
252 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
253 int64_t &Offset2) const override;
254
255 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
256 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
257 /// should be scheduled togther. On some targets if two loads are loading from
258 /// addresses in the same cache line, it's better if they are scheduled
259 /// together. This function takes two integers that represent the load offsets
260 /// from the common base address. It returns true if it decides it's desirable
261 /// to schedule the two loads together. "NumLoads" is the number of loads that
262 /// have already been scheduled after Load1.
263 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
264 int64_t Offset1, int64_t Offset2,
265 unsigned NumLoads) const override;
266
268 const MachineBasicBlock *MBB,
269 const MachineFunction &MF) const override;
270
272 unsigned NumCycles, unsigned ExtraPredCycles,
273 BranchProbability Probability) const override;
274
275 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
276 unsigned ExtraT, MachineBasicBlock &FMBB,
277 unsigned NumF, unsigned ExtraF,
278 BranchProbability Probability) const override;
279
281 BranchProbability Probability) const override {
282 return NumCycles == 1;
283 }
284
286 unsigned NumInsts) const override;
287 unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override;
288
290 MachineBasicBlock &FMBB) const override;
291
292 /// analyzeCompare - For a comparison instruction, return the source registers
293 /// in SrcReg and SrcReg2 if having two register operands, and the value it
294 /// compares against in CmpValue. Return true if the comparison instruction
295 /// can be analyzed.
296 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
297 Register &SrcReg2, int64_t &CmpMask,
298 int64_t &CmpValue) const override;
299
300 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
301 /// that we can remove a "comparison with zero"; Remove a redundant CMP
302 /// instruction if the flags can be updated in the same way by an earlier
303 /// instruction such as SUB.
304 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
305 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
306 const MachineRegisterInfo *MRI) const override;
307
308 bool analyzeSelect(const MachineInstr &MI,
309 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
310 unsigned &FalseOp, bool &Optimizable) const override;
311
314 bool) const override;
315
316 /// foldImmediate - 'Reg' is known to be defined by a move immediate
317 /// instruction, try to fold the immediate into the use instruction.
319 MachineRegisterInfo *MRI) const override;
320
321 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
322 const MachineInstr &MI) const override;
323
324 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
325 const MachineInstr &DefMI,
326 unsigned DefIdx,
327 const MachineInstr &UseMI,
328 unsigned UseIdx) const override;
329 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
330 SDNode *DefNode, unsigned DefIdx,
331 SDNode *UseNode,
332 unsigned UseIdx) const override;
333
334 /// VFP/NEON execution domains.
335 std::pair<uint16_t, uint16_t>
336 getExecutionDomain(const MachineInstr &MI) const override;
337 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
338
339 unsigned
341 const TargetRegisterInfo *) const override;
343 const TargetRegisterInfo *TRI) const override;
344
345 /// Get the number of addresses by LDM or VLDM or zero for unknown.
346 unsigned getNumLDMAddresses(const MachineInstr &MI) const;
347
348 std::pair<unsigned, unsigned>
349 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
354
355 /// ARM supports the MachineOutliner.
357 bool OutlineFromLinkOnceODRs) const override;
358 std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo(
359 const MachineModuleInfo &MMI,
360 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
362 Function &F, std::vector<outliner::Candidate> &Candidates) const override;
365 unsigned Flags) const override;
367 unsigned &Flags) const override;
369 const outliner::OutlinedFunction &OF) const override;
373 outliner::Candidate &C) const override;
374
375 /// Enable outlining by default at -Oz.
377
378 bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override {
379 return MI->getOpcode() == ARM::t2LoopEndDec ||
380 MI->getOpcode() == ARM::t2DoLoopStartTP ||
381 MI->getOpcode() == ARM::t2WhileLoopStartLR ||
382 MI->getOpcode() == ARM::t2WhileLoopStartTP;
383 }
384
385 /// Analyze loop L, which must be a single-basic-block loop, and if the
386 /// conditions can be understood enough produce a PipelinerLoopInfo object.
387 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
388 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
389
390private:
391 /// Returns an unused general-purpose register which can be used for
392 /// constructing an outlined call if one exists. Returns 0 otherwise.
393 Register findRegisterToSaveLRTo(outliner::Candidate &C) const;
394
395 /// Adds an instruction which saves the link register on top of the stack into
396 /// the MachineBasicBlock \p MBB at position \p It. If \p Auth is true,
397 /// compute and store an authentication code alongiside the link register.
398 /// If \p CFI is true, emit CFI instructions.
399 void saveLROnStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator It,
400 bool CFI, bool Auth) const;
401
402 /// Adds an instruction which restores the link register from the top the
403 /// stack into the MachineBasicBlock \p MBB at position \p It. If \p Auth is
404 /// true, restore an authentication code and authenticate LR.
405 /// If \p CFI is true, emit CFI instructions.
406 void restoreLRFromStack(MachineBasicBlock &MBB,
407 MachineBasicBlock::iterator It, bool CFI,
408 bool Auth) const;
409
410 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
411 /// for the case when the LR is saved in the register \p Reg.
412 void emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
414 Register Reg) const;
415
416 /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
417 /// after the LR is was restored from a register.
418 void emitCFIForLRRestoreFromReg(MachineBasicBlock &MBB,
420 /// \brief Sets the offsets on outlined instructions in \p MBB which use SP
421 /// so that they will be valid post-outlining.
422 ///
423 /// \param MBB A \p MachineBasicBlock in an outlined function.
424 void fixupPostOutline(MachineBasicBlock &MBB) const;
425
426 /// Returns true if the machine instruction offset can handle the stack fixup
427 /// and updates it if requested.
428 bool checkAndUpdateStackOffset(MachineInstr *MI, int64_t Fixup,
429 bool Updt) const;
430
431 unsigned getInstBundleLength(const MachineInstr &MI) const;
432
433 std::optional<unsigned> getVLDMDefCycle(const InstrItineraryData *ItinData,
434 const MCInstrDesc &DefMCID,
435 unsigned DefClass, unsigned DefIdx,
436 unsigned DefAlign) const;
437 std::optional<unsigned> getLDMDefCycle(const InstrItineraryData *ItinData,
438 const MCInstrDesc &DefMCID,
439 unsigned DefClass, unsigned DefIdx,
440 unsigned DefAlign) const;
441 std::optional<unsigned> getVSTMUseCycle(const InstrItineraryData *ItinData,
442 const MCInstrDesc &UseMCID,
443 unsigned UseClass, unsigned UseIdx,
444 unsigned UseAlign) const;
445 std::optional<unsigned> getSTMUseCycle(const InstrItineraryData *ItinData,
446 const MCInstrDesc &UseMCID,
447 unsigned UseClass, unsigned UseIdx,
448 unsigned UseAlign) const;
449 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
450 const MCInstrDesc &DefMCID,
451 unsigned DefIdx, unsigned DefAlign,
452 const MCInstrDesc &UseMCID,
453 unsigned UseIdx,
454 unsigned UseAlign) const;
455
456 std::optional<unsigned> getOperandLatencyImpl(
457 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
458 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
459 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
460 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const;
461
462 unsigned getPredicationCost(const MachineInstr &MI) const override;
463
464 unsigned getInstrLatency(const InstrItineraryData *ItinData,
465 const MachineInstr &MI,
466 unsigned *PredCost = nullptr) const override;
467
468 unsigned getInstrLatency(const InstrItineraryData *ItinData,
469 SDNode *Node) const override;
470
471 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
473 const MachineInstr &DefMI, unsigned DefIdx,
474 const MachineInstr &UseMI,
475 unsigned UseIdx) const override;
476 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
477 const MachineInstr &DefMI,
478 unsigned DefIdx) const override;
479
480 /// verifyInstruction - Perform target specific instruction verification.
481 bool verifyInstruction(const MachineInstr &MI,
482 StringRef &ErrInfo) const override;
483
484 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
485
486 void expandMEMCPY(MachineBasicBlock::iterator) const;
487
488 /// Identify instructions that can be folded into a MOVCC instruction, and
489 /// return the defining instruction.
490 MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
491 const TargetInstrInfo *TII) const;
492
493 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
494
495private:
496 /// Modeling special VFP / NEON fp MLA / MLS hazards.
497
498 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
499 /// MLx table.
501
502 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
503 /// stalls when scheduled together with fp MLA / MLS opcodes.
504 SmallSet<unsigned, 16> MLxHazardOpcodes;
505
506public:
507 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
508 /// instruction.
509 bool isFpMLxInstruction(unsigned Opcode) const {
510 return MLxEntryMap.count(Opcode);
511 }
512
513 /// isFpMLxInstruction - This version also returns the multiply opcode and the
514 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
515 /// the MLX instructions with an extra lane operand.
516 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
517 unsigned &AddSubOpc, bool &NegAcc,
518 bool &HasLane) const;
519
520 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
521 /// will cause stalls when scheduled after (within 4-cycle window) a fp
522 /// MLA / MLS instruction.
523 bool canCauseFpMLxStall(unsigned Opcode) const {
524 return MLxHazardOpcodes.count(Opcode);
525 }
526
527 /// Returns true if the instruction has a shift by immediate that can be
528 /// executed in one cycle less.
529 bool isSwiftFastImmShift(const MachineInstr *MI) const;
530
531 /// Returns predicate register associated with the given frame instruction.
532 unsigned getFramePred(const MachineInstr &MI) const {
533 assert(isFrameInstr(MI));
534 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
535 // - argument declared in the pattern:
536 // 0 - frame size
537 // 1 - arg of CALLSEQ_START/CALLSEQ_END
538 // 2 - predicate code (like ARMCC::AL)
539 // - added by predOps:
540 // 3 - predicate reg
541 return MI.getOperand(3).getReg();
542 }
543
544 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
545 Register Reg) const override;
546
547 unsigned getUndefInitOpcode(unsigned RegClassID) const override {
548 if (RegClassID == ARM::MQPRRegClass.getID())
549 return ARM::PseudoARMInitUndefMQPR;
550 if (RegClassID == ARM::SPRRegClass.getID())
551 return ARM::PseudoARMInitUndefSPR;
552 if (RegClassID == ARM::DPR_VFP2RegClass.getID())
553 return ARM::PseudoARMInitUndefDPR_VFP2;
554 if (RegClassID == ARM::GPRRegClass.getID())
555 return ARM::PseudoARMInitUndefGPR;
556
557 llvm_unreachable("Unexpected register class.");
558 }
559};
560
561/// Get the operands corresponding to the given \p Pred value. By default, the
562/// predicate register is assumed to be 0 (no register), but you can pass in a
563/// \p PredReg if that is not the case.
564static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
565 unsigned PredReg = 0) {
566 return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
567 MachineOperand::CreateReg(PredReg, false)}};
568}
569
570/// Get the operand corresponding to the conditional code result. By default,
571/// this is 0 (no register).
572static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
573 return MachineOperand::CreateReg(CCReg, false);
574}
575
576/// Get the operand corresponding to the conditional code result for Thumb1.
577/// This operand will always refer to CPSR and it will have the Define flag set.
578/// You can optionally set the Dead flag by means of \p isDead.
579static inline MachineOperand t1CondCodeOp(bool isDead = false) {
580 return MachineOperand::CreateReg(ARM::CPSR,
581 /*Define*/ true, /*Implicit*/ false,
582 /*Kill*/ false, isDead);
583}
584
585static inline
586bool isUncondBranchOpcode(int Opc) {
587 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
588}
589
590// This table shows the VPT instruction variants, i.e. the different
591// mask field encodings, see also B5.6. Predication/conditional execution in
592// the ArmARM.
593static inline bool isVPTOpcode(int Opc) {
594 return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
595 Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
596 Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
597 Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
598 Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
599 Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
600 Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
601 Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
602 Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
603 Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
604 Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
605 Opc == ARM::MVE_VPST;
606}
607
608static inline
609unsigned VCMPOpcodeToVPT(unsigned Opcode) {
610 switch (Opcode) {
611 default:
612 return 0;
613 case ARM::MVE_VCMPf32:
614 return ARM::MVE_VPTv4f32;
615 case ARM::MVE_VCMPf16:
616 return ARM::MVE_VPTv8f16;
617 case ARM::MVE_VCMPi8:
618 return ARM::MVE_VPTv16i8;
619 case ARM::MVE_VCMPi16:
620 return ARM::MVE_VPTv8i16;
621 case ARM::MVE_VCMPi32:
622 return ARM::MVE_VPTv4i32;
623 case ARM::MVE_VCMPu8:
624 return ARM::MVE_VPTv16u8;
625 case ARM::MVE_VCMPu16:
626 return ARM::MVE_VPTv8u16;
627 case ARM::MVE_VCMPu32:
628 return ARM::MVE_VPTv4u32;
629 case ARM::MVE_VCMPs8:
630 return ARM::MVE_VPTv16s8;
631 case ARM::MVE_VCMPs16:
632 return ARM::MVE_VPTv8s16;
633 case ARM::MVE_VCMPs32:
634 return ARM::MVE_VPTv4s32;
635
636 case ARM::MVE_VCMPf32r:
637 return ARM::MVE_VPTv4f32r;
638 case ARM::MVE_VCMPf16r:
639 return ARM::MVE_VPTv8f16r;
640 case ARM::MVE_VCMPi8r:
641 return ARM::MVE_VPTv16i8r;
642 case ARM::MVE_VCMPi16r:
643 return ARM::MVE_VPTv8i16r;
644 case ARM::MVE_VCMPi32r:
645 return ARM::MVE_VPTv4i32r;
646 case ARM::MVE_VCMPu8r:
647 return ARM::MVE_VPTv16u8r;
648 case ARM::MVE_VCMPu16r:
649 return ARM::MVE_VPTv8u16r;
650 case ARM::MVE_VCMPu32r:
651 return ARM::MVE_VPTv4u32r;
652 case ARM::MVE_VCMPs8r:
653 return ARM::MVE_VPTv16s8r;
654 case ARM::MVE_VCMPs16r:
655 return ARM::MVE_VPTv8s16r;
656 case ARM::MVE_VCMPs32r:
657 return ARM::MVE_VPTv4s32r;
658 }
659}
660
661static inline
662bool isCondBranchOpcode(int Opc) {
663 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
664}
665
666static inline bool isJumpTableBranchOpcode(int Opc) {
667 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
668 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
669 Opc == ARM::t2BR_JT;
670}
671
672static inline
674 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
675}
676
677static inline bool isIndirectCall(const MachineInstr &MI) {
678 int Opc = MI.getOpcode();
679 switch (Opc) {
680 // indirect calls:
681 case ARM::BLX:
682 case ARM::BLX_noip:
683 case ARM::BLX_pred:
684 case ARM::BLX_pred_noip:
685 case ARM::BX_CALL:
686 case ARM::BMOVPCRX_CALL:
687 case ARM::TCRETURNri:
688 case ARM::TCRETURNrinotr12:
689 case ARM::TAILJMPr:
690 case ARM::TAILJMPr4:
691 case ARM::tBLXr:
692 case ARM::tBLXr_noip:
693 case ARM::tBLXNSr:
694 case ARM::tBLXNS_CALL:
695 case ARM::tBX_CALL:
696 case ARM::tTAILJMPr:
698 return true;
699 // direct calls:
700 case ARM::BL:
701 case ARM::BL_pred:
702 case ARM::BMOVPCB_CALL:
703 case ARM::BL_PUSHLR:
704 case ARM::BLXi:
705 case ARM::TCRETURNdi:
706 case ARM::TAILJMPd:
707 case ARM::SVC:
708 case ARM::HVC:
709 case ARM::TPsoft:
710 case ARM::tTAILJMPd:
711 case ARM::t2SMC:
712 case ARM::t2HVC:
713 case ARM::tBL:
714 case ARM::tBLXi:
715 case ARM::tBL_PUSHLR:
716 case ARM::tTAILJMPdND:
717 case ARM::tSVC:
718 case ARM::tTPsoft:
720 return false;
721 }
723 return false;
724}
725
727 int opc = MI.getOpcode();
728 return MI.isReturn() || isIndirectBranchOpcode(MI.getOpcode()) ||
730}
731
732static inline bool isSpeculationBarrierEndBBOpcode(int Opc) {
733 return Opc == ARM::SpeculationBarrierISBDSBEndBB ||
734 Opc == ARM::SpeculationBarrierSBEndBB ||
735 Opc == ARM::t2SpeculationBarrierISBDSBEndBB ||
736 Opc == ARM::t2SpeculationBarrierSBEndBB;
737}
738
739static inline bool isPopOpcode(int Opc) {
740 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
741 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
742 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
743}
744
745static inline bool isPushOpcode(int Opc) {
746 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
747 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
748}
749
750static inline bool isSubImmOpcode(int Opc) {
751 return Opc == ARM::SUBri ||
752 Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||
753 Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||
754 Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;
755}
756
757static inline bool isMovRegOpcode(int Opc) {
758 return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;
759}
760/// isValidCoprocessorNumber - decide whether an explicit coprocessor
761/// number is legal in generic instructions like CDP. The answer can
762/// vary with the subtarget.
763static inline bool isValidCoprocessorNumber(unsigned Num,
764 const FeatureBitset& featureBits) {
765 // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
766 // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
767 // useful for code which is shared with older architectures which do not know
768 // the new VFP/NEON mnemonics.
769
770 // Armv8-A disallows everything *other* than 111x (CP14 and CP15).
771 if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
772 return false;
773
774 // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
775 // which clash with MVE.
776 if (featureBits[ARM::HasV8_1MMainlineOps] &&
777 ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
778 return false;
779
780 return true;
781}
782
783static inline bool isSEHInstruction(const MachineInstr &MI) {
784 unsigned Opc = MI.getOpcode();
785 switch (Opc) {
786 case ARM::SEH_StackAlloc:
787 case ARM::SEH_SaveRegs:
788 case ARM::SEH_SaveRegs_Ret:
789 case ARM::SEH_SaveSP:
790 case ARM::SEH_SaveFRegs:
791 case ARM::SEH_SaveLR:
792 case ARM::SEH_Nop:
793 case ARM::SEH_Nop_Ret:
794 case ARM::SEH_PrologEnd:
795 case ARM::SEH_EpilogStart:
796 case ARM::SEH_EpilogEnd:
797 return true;
798 default:
799 return false;
800 }
801}
802
803/// getInstrPredicate - If instruction is predicated, returns its predicate
804/// condition, otherwise returns AL. It also returns the condition code
805/// register by reference.
806ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
807
808unsigned getMatchingCondBranchOpcode(unsigned Opc);
809
810/// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
811/// the instruction is encoded with an 'S' bit is determined by the optional
812/// CPSR def operand.
813unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
814
815/// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
816/// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
817/// code.
818void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
820 const DebugLoc &dl, Register DestReg,
821 Register BaseReg, int NumBytes,
822 ARMCC::CondCodes Pred, Register PredReg,
823 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
824
825void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
827 const DebugLoc &dl, Register DestReg,
828 Register BaseReg, int NumBytes,
829 ARMCC::CondCodes Pred, Register PredReg,
830 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
831void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
833 const DebugLoc &dl, Register DestReg,
834 Register BaseReg, int NumBytes,
835 const TargetInstrInfo &TII,
836 const ARMBaseRegisterInfo &MRI,
837 unsigned MIFlags = 0);
838
839/// Tries to add registers to the reglist of a given base-updating
840/// push/pop instruction to adjust the stack by an additional
841/// NumBytes. This can save a few bytes per function in code-size, but
842/// obviously generates more memory traffic. As such, it only takes
843/// effect in functions being optimised for size.
844bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
845 MachineFunction &MF, MachineInstr *MI,
846 unsigned NumBytes);
847
848/// rewriteARMFrameIndex / rewriteT2FrameIndex -
849/// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
850/// offset could not be handled directly in MI, and return the left-over
851/// portion by reference.
852bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
853 Register FrameReg, int &Offset,
854 const ARMBaseInstrInfo &TII);
855
856bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
857 Register FrameReg, int &Offset,
858 const ARMBaseInstrInfo &TII,
859 const TargetRegisterInfo *TRI);
860
861/// Return true if Reg is defd between From and To
864 const TargetRegisterInfo *TRI);
865
866/// Search backwards from a tBcc to find a tCMPi8 against 0, meaning
867/// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found.
868MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br,
869 const TargetRegisterInfo *TRI);
870
871void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB);
872void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg);
873
874void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond);
875void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond,
876 unsigned Inactive);
877
878/// Returns the number of instructions required to materialize the given
879/// constant in a register, or 3 if a literal pool load is needed.
880/// If ForCodesize is specified, an approximate cost in bytes is returned.
881unsigned ConstantMaterializationCost(unsigned Val,
882 const ARMSubtarget *Subtarget,
883 bool ForCodesize = false);
884
885/// Returns true if Val1 has a lower Constant Materialization Cost than Val2.
886/// Uses the cost from ConstantMaterializationCost, first with ForCodesize as
887/// specified. If the scores are equal, return the comparison for !ForCodesize.
888bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2,
889 const ARMSubtarget *Subtarget,
890 bool ForCodesize = false);
891
892// Return the immediate if this is ADDri or SUBri, scaled as appropriate.
893// Returns 0 for unknown instructions.
895 int Scale = 1;
896 unsigned ImmOp;
897 switch (MI.getOpcode()) {
898 case ARM::t2ADDri:
899 ImmOp = 2;
900 break;
901 case ARM::t2SUBri:
902 case ARM::t2SUBri12:
903 ImmOp = 2;
904 Scale = -1;
905 break;
906 case ARM::tSUBi3:
907 case ARM::tSUBi8:
908 ImmOp = 3;
909 Scale = -1;
910 break;
911 default:
912 return 0;
913 }
914 return Scale * MI.getOperand(ImmOp).getImm();
915}
916
917// Given a memory access Opcode, check that the give Imm would be a valid Offset
918// for this instruction using its addressing mode.
919inline bool isLegalAddressImm(unsigned Opcode, int Imm,
920 const TargetInstrInfo *TII) {
921 const MCInstrDesc &Desc = TII->get(Opcode);
922 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
923 switch (AddrMode) {
925 return std::abs(Imm) < ((1 << 7) * 1);
927 return std::abs(Imm) < ((1 << 7) * 2) && Imm % 2 == 0;
929 return std::abs(Imm) < ((1 << 7) * 4) && Imm % 4 == 0;
931 return std::abs(Imm) < ((1 << 8) * 1);
933 return Imm >= 0 && Imm < ((1 << 8) * 1);
935 return Imm < 0 && -Imm < ((1 << 8) * 1);
937 return std::abs(Imm) < ((1 << 8) * 4) && Imm % 4 == 0;
939 return Imm >= 0 && Imm < ((1 << 12) * 1);
940 case ARMII::AddrMode2:
941 return std::abs(Imm) < ((1 << 12) * 1);
942 default:
943 llvm_unreachable("Unhandled Addressing mode");
944 }
945}
946
947// Return true if the given intrinsic is a gather
948inline bool isGather(IntrinsicInst *IntInst) {
949 if (IntInst == nullptr)
950 return false;
951 unsigned IntrinsicID = IntInst->getIntrinsicID();
952 return (IntrinsicID == Intrinsic::masked_gather ||
953 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base ||
954 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated ||
955 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb ||
956 IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated ||
957 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset ||
958 IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated);
959}
960
961// Return true if the given intrinsic is a scatter
962inline bool isScatter(IntrinsicInst *IntInst) {
963 if (IntInst == nullptr)
964 return false;
965 unsigned IntrinsicID = IntInst->getIntrinsicID();
966 return (IntrinsicID == Intrinsic::masked_scatter ||
967 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base ||
968 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated ||
969 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb ||
970 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated ||
971 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset ||
972 IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated);
973}
974
975// Return true if the given intrinsic is a gather or scatter
976inline bool isGatherScatter(IntrinsicInst *IntInst) {
977 if (IntInst == nullptr)
978 return false;
979 return isGather(IntInst) || isScatter(IntInst);
980}
981
982unsigned getBLXOpcode(const MachineFunction &MF);
983unsigned gettBLXrOpcode(const MachineFunction &MF);
984unsigned getBLXpredOpcode(const MachineFunction &MF);
985
986} // end namespace llvm
987
988#endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
BlockVerifier::State From
This file defines the DenseMap class.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
uint64_t IntrinsicInst * II
PowerPC TLS Dynamic Call Fixup
TargetInstrInfo::RegSubRegPairAndIdx RegSubRegPairAndIdx
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
static bool isCPSRDefined(const MachineInstr &MI)
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
unsigned getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
unsigned getNumLDMAddresses(const MachineInstr &MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Returns the size of the specified MachineInstr.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
ARM supports the MachineOutliner.
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
Enable outlining by default at -Oz.
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
bool isPredicated(const MachineInstr &MI) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
bool isPredicable(const MachineInstr &MI) const override
isPredicable - Return true if the specified instruction can be predicated.
unsigned getFramePred(const MachineInstr &MI) const
Returns predicate register associated with the given frame instruction.
Register isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value description...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const override
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
unsigned getUndefInitOpcode(unsigned RegClassID) const override
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
std::optional< outliner::OutlinedFunction > getOutliningCandidateInfo(const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const override
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
VFP/NEON execution domains.
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Register isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const ARMSubtarget & getSubtarget() const
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
bool shouldSink(const MachineInstr &MI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:151
Container class for subtarget features.
Itinerary data supplied by a subtarget to be used by a target.
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:48
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:55
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MachineInstrBundleIterator< MachineInstr > iterator
Representation of each machine instruction.
Definition: MachineInstr.h:69
This class contains meta information specific to a module.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:323
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:166
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
TargetSubtargetInfo - Generic base class for all target subtargets.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
static bool isIndirectCall(const MachineInstr &MI)
MachineInstr * findCMPToFoldIntoCBZ(MachineInstr *Br, const TargetRegisterInfo *TRI)
Search backwards from a tBcc to find a tCMPi8 against 0, meaning we can convert them to a tCBZ or tCB...
static bool isCondBranchOpcode(int Opc)
bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns true if Val1 has a lower Constant Materialization Cost than Val2.
static bool isPushOpcode(int Opc)
void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond)
unsigned getBLXpredOpcode(const MachineFunction &MF)
static bool isIndirectBranchOpcode(int Opc)
static bool isVPTOpcode(int Opc)
bool isLegalAddressImm(unsigned Opcode, int Imm, const TargetInstrInfo *TII)
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)
bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI)
Return true if Reg is defd between From and To.
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
static bool isSEHInstruction(const MachineInstr &MI)
static bool isMovRegOpcode(int Opc)
bool isGather(IntrinsicInst *IntInst)
static bool isSubImmOpcode(int Opc)
bool isGatherScatter(IntrinsicInst *IntInst)
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
static bool isJumpTableBranchOpcode(int Opc)
static bool isPopOpcode(int Opc)
void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, unsigned Inactive)
static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)
isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...
void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg)
unsigned ConstantMaterializationCost(unsigned Val, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns the number of instructions required to materialize the given constant in a register,...
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
static bool isIndirectControlFlowNotComingBack(const MachineInstr &MI)
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition,...
unsigned getMatchingCondBranchOpcode(unsigned Opc)
static bool isUncondBranchOpcode(int Opc)
bool isScatter(IntrinsicInst *IntInst)
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
static unsigned VCMPOpcodeToVPT(unsigned Opcode)
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
unsigned gettBLXrOpcode(const MachineFunction &MF)
int getAddSubImmediate(MachineInstr &MI)
static bool isSpeculationBarrierEndBBOpcode(int Opc)
unsigned getBLXOpcode(const MachineFunction &MF)
void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB)
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Description of the encoding of one expression Op.
A pair composed of a register and a sub-register index.
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.