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ARMBaseInstrInfo.h
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1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
14 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/IR/IntrinsicInst.h"
25 #include "llvm/IR/IntrinsicsARM.h"
26 #include <array>
27 #include <cstdint>
28 
29 #define GET_INSTRINFO_HEADER
30 #include "ARMGenInstrInfo.inc"
31 
32 namespace llvm {
33 
34 class ARMBaseRegisterInfo;
35 class ARMSubtarget;
36 
38  const ARMSubtarget &Subtarget;
39 
40 protected:
41  // Can be only subclassed.
42  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
43 
45  unsigned LoadImmOpc, unsigned LoadOpc) const;
46 
47  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
48  /// and \p DefIdx.
49  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
50  /// the list is modeled as <Reg:SubReg, SubIdx>.
51  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
52  /// two elements:
53  /// - %1:sub1, sub0
54  /// - %2<:0>, sub1
55  ///
56  /// \returns true if it is possible to build such an input sequence
57  /// with the pair \p MI, \p DefIdx. False otherwise.
58  ///
59  /// \pre MI.isRegSequenceLike().
61  const MachineInstr &MI, unsigned DefIdx,
62  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
63 
64  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
65  /// and \p DefIdx.
66  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
67  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
68  /// - %1:sub1, sub0
69  ///
70  /// \returns true if it is possible to build such an input sequence
71  /// with the pair \p MI, \p DefIdx. False otherwise.
72  ///
73  /// \pre MI.isExtractSubregLike().
74  bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
75  RegSubRegPairAndIdx &InputReg) const override;
76 
77  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
78  /// and \p DefIdx.
79  /// \p [out] BaseReg and \p [out] InsertedReg contain
80  /// the equivalent inputs of INSERT_SUBREG.
81  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
82  /// - BaseReg: %0:sub0
83  /// - InsertedReg: %1:sub1, sub3
84  ///
85  /// \returns true if it is possible to build such an input sequence
86  /// with the pair \p MI, \p DefIdx. False otherwise.
87  ///
88  /// \pre MI.isInsertSubregLike().
89  bool
90  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
91  RegSubRegPair &BaseReg,
92  RegSubRegPairAndIdx &InsertedReg) const override;
93 
94  /// Commutes the operands in the given instruction.
95  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
96  ///
97  /// Do not call this method for a non-commutable instruction or for
98  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
99  /// Even though the instruction is commutable, the method may still
100  /// fail to commute the operands, null pointer is returned in such cases.
102  unsigned OpIdx1,
103  unsigned OpIdx2) const override;
104  /// If the specific machine instruction is an instruction that moves/copies
105  /// value from one register to another register return destination and source
106  /// registers as machine operands.
108  isCopyInstrImpl(const MachineInstr &MI) const override;
109 
110  /// Specialization of \ref TargetInstrInfo::describeLoadedValue, used to
111  /// enhance debug entry value descriptions for ARM targets.
113  Register Reg) const override;
114 
115 public:
116  // Return whether the target has an explicit NOP encoding.
117  bool hasNOP() const;
118 
119  // Return the non-pre/post incrementing version of 'Opc'. Return 0
120  // if there is not such an opcode.
121  virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
122 
124  LiveIntervals *LIS) const override;
125 
126  virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
127  const ARMSubtarget &getSubtarget() const { return Subtarget; }
128 
131  const ScheduleDAG *DAG) const override;
132 
135  const ScheduleDAGMI *DAG) const override;
136 
139  const ScheduleDAG *DAG) const override;
140 
141  // Branch analysis.
143  MachineBasicBlock *&FBB,
145  bool AllowModify = false) const override;
147  int *BytesRemoved = nullptr) const override;
150  const DebugLoc &DL,
151  int *BytesAdded = nullptr) const override;
152 
153  bool
155 
156  // Predication support.
157  bool isPredicated(const MachineInstr &MI) const override;
158 
159  // MIR printer helper function to annotate Operands with a comment.
160  std::string
162  unsigned OpIdx,
163  const TargetRegisterInfo *TRI) const override;
164 
166  int PIdx = MI.findFirstPredOperandIdx();
167  return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
168  : ARMCC::AL;
169  }
170 
172  ArrayRef<MachineOperand> Pred) const override;
173 
175  ArrayRef<MachineOperand> Pred2) const override;
176 
177  bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
178  bool SkipDead) const override;
179 
180  bool isPredicable(const MachineInstr &MI) const override;
181 
182  // CPSR defined in instruction
183  static bool isCPSRDefined(const MachineInstr &MI);
184 
185  /// GetInstSize - Returns the size of the specified MachineInstr.
186  ///
187  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
188 
189  unsigned isLoadFromStackSlot(const MachineInstr &MI,
190  int &FrameIndex) const override;
191  unsigned isStoreToStackSlot(const MachineInstr &MI,
192  int &FrameIndex) const override;
193  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
194  int &FrameIndex) const override;
195  unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
196  int &FrameIndex) const override;
197 
199  unsigned SrcReg, bool KillSrc,
200  const ARMSubtarget &Subtarget) const;
202  unsigned DestReg, bool KillSrc,
203  const ARMSubtarget &Subtarget) const;
204 
206  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
207  bool KillSrc) const override;
208 
211  Register SrcReg, bool isKill, int FrameIndex,
212  const TargetRegisterClass *RC,
213  const TargetRegisterInfo *TRI) const override;
214 
217  Register DestReg, int FrameIndex,
218  const TargetRegisterClass *RC,
219  const TargetRegisterInfo *TRI) const override;
220 
221  bool expandPostRAPseudo(MachineInstr &MI) const override;
222 
223  bool shouldSink(const MachineInstr &MI) const override;
224 
226  Register DestReg, unsigned SubIdx,
227  const MachineInstr &Orig,
228  const TargetRegisterInfo &TRI) const override;
229 
230  MachineInstr &
232  const MachineInstr &Orig) const override;
233 
234  const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
235  unsigned SubIdx, unsigned State,
236  const TargetRegisterInfo *TRI) const;
237 
238  bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
239  const MachineRegisterInfo *MRI) const override;
240 
241  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
242  /// determine if two loads are loading from the same base address. It should
243  /// only return true if the base pointers are the same and the only
244  /// differences between the two addresses is the offset. It also returns the
245  /// offsets by reference.
246  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
247  int64_t &Offset2) const override;
248 
249  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
250  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
251  /// should be scheduled togther. On some targets if two loads are loading from
252  /// addresses in the same cache line, it's better if they are scheduled
253  /// together. This function takes two integers that represent the load offsets
254  /// from the common base address. It returns true if it decides it's desirable
255  /// to schedule the two loads together. "NumLoads" is the number of loads that
256  /// have already been scheduled after Load1.
257  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
258  int64_t Offset1, int64_t Offset2,
259  unsigned NumLoads) const override;
260 
262  const MachineBasicBlock *MBB,
263  const MachineFunction &MF) const override;
264 
266  unsigned NumCycles, unsigned ExtraPredCycles,
267  BranchProbability Probability) const override;
268 
269  bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
270  unsigned ExtraT, MachineBasicBlock &FMBB,
271  unsigned NumF, unsigned ExtraF,
272  BranchProbability Probability) const override;
273 
275  BranchProbability Probability) const override {
276  return NumCycles == 1;
277  }
278 
280  unsigned NumInsts) const override;
281  unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override;
282 
284  MachineBasicBlock &FMBB) const override;
285 
286  /// analyzeCompare - For a comparison instruction, return the source registers
287  /// in SrcReg and SrcReg2 if having two register operands, and the value it
288  /// compares against in CmpValue. Return true if the comparison instruction
289  /// can be analyzed.
290  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
291  Register &SrcReg2, int64_t &CmpMask,
292  int64_t &CmpValue) const override;
293 
294  /// optimizeCompareInstr - Convert the instruction to set the zero flag so
295  /// that we can remove a "comparison with zero"; Remove a redundant CMP
296  /// instruction if the flags can be updated in the same way by an earlier
297  /// instruction such as SUB.
298  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
299  Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
300  const MachineRegisterInfo *MRI) const override;
301 
302  bool analyzeSelect(const MachineInstr &MI,
303  SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
304  unsigned &FalseOp, bool &Optimizable) const override;
305 
308  bool) const override;
309 
310  /// FoldImmediate - 'Reg' is known to be defined by a move immediate
311  /// instruction, try to fold the immediate into the use instruction.
313  MachineRegisterInfo *MRI) const override;
314 
315  unsigned getNumMicroOps(const InstrItineraryData *ItinData,
316  const MachineInstr &MI) const override;
317 
318  int getOperandLatency(const InstrItineraryData *ItinData,
319  const MachineInstr &DefMI, unsigned DefIdx,
320  const MachineInstr &UseMI,
321  unsigned UseIdx) const override;
322  int getOperandLatency(const InstrItineraryData *ItinData,
323  SDNode *DefNode, unsigned DefIdx,
324  SDNode *UseNode, unsigned UseIdx) const override;
325 
326  /// VFP/NEON execution domains.
327  std::pair<uint16_t, uint16_t>
328  getExecutionDomain(const MachineInstr &MI) const override;
329  void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
330 
331  unsigned
332  getPartialRegUpdateClearance(const MachineInstr &, unsigned,
333  const TargetRegisterInfo *) const override;
334  void breakPartialRegDependency(MachineInstr &, unsigned,
335  const TargetRegisterInfo *TRI) const override;
336 
337  /// Get the number of addresses by LDM or VLDM or zero for unknown.
338  unsigned getNumLDMAddresses(const MachineInstr &MI) const;
339 
340  std::pair<unsigned, unsigned>
341  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
346 
347  /// ARM supports the MachineOutliner.
349  bool OutlineFromLinkOnceODRs) const override;
351  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
353  Function &F, std::vector<outliner::Candidate> &Candidates) const override;
355  unsigned Flags) const override;
357  unsigned &Flags) const override;
359  const outliner::OutlinedFunction &OF) const override;
363  outliner::Candidate &C) const override;
364 
365  /// Enable outlining by default at -Oz.
366  bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
367 
368  bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override {
369  return MI->getOpcode() == ARM::t2LoopEndDec ||
370  MI->getOpcode() == ARM::t2DoLoopStartTP ||
371  MI->getOpcode() == ARM::t2WhileLoopStartLR ||
372  MI->getOpcode() == ARM::t2WhileLoopStartTP;
373  }
374 
375  /// Analyze loop L, which must be a single-basic-block loop, and if the
376  /// conditions can be understood enough produce a PipelinerLoopInfo object.
377  std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
378  analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override;
379 
380 private:
381  /// Returns an unused general-purpose register which can be used for
382  /// constructing an outlined call if one exists. Returns 0 otherwise.
383  Register findRegisterToSaveLRTo(outliner::Candidate &C) const;
384 
385  /// Adds an instruction which saves the link register on top of the stack into
386  /// the MachineBasicBlock \p MBB at position \p It. If \p Auth is true,
387  /// compute and store an authentication code alongiside the link register.
388  /// If \p CFI is true, emit CFI instructions.
389  void saveLROnStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator It,
390  bool CFI, bool Auth) const;
391 
392  /// Adds an instruction which restores the link register from the top the
393  /// stack into the MachineBasicBlock \p MBB at position \p It. If \p Auth is
394  /// true, restore an authentication code and authenticate LR.
395  /// If \p CFI is true, emit CFI instructions.
396  void restoreLRFromStack(MachineBasicBlock &MBB,
397  MachineBasicBlock::iterator It, bool CFI,
398  bool Auth) const;
399 
400  /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
401  /// for the case when the LR is saved in the register \p Reg.
402  void emitCFIForLRSaveToReg(MachineBasicBlock &MBB,
404  Register Reg) const;
405 
406  /// Emit CFI instructions into the MachineBasicBlock \p MBB at position \p It,
407  /// after the LR is was restored from a register.
408  void emitCFIForLRRestoreFromReg(MachineBasicBlock &MBB,
409  MachineBasicBlock::iterator It) const;
410  /// \brief Sets the offsets on outlined instructions in \p MBB which use SP
411  /// so that they will be valid post-outlining.
412  ///
413  /// \param MBB A \p MachineBasicBlock in an outlined function.
414  void fixupPostOutline(MachineBasicBlock &MBB) const;
415 
416  /// Returns true if the machine instruction offset can handle the stack fixup
417  /// and updates it if requested.
418  bool checkAndUpdateStackOffset(MachineInstr *MI, int64_t Fixup,
419  bool Updt) const;
420 
421  unsigned getInstBundleLength(const MachineInstr &MI) const;
422 
423  int getVLDMDefCycle(const InstrItineraryData *ItinData,
424  const MCInstrDesc &DefMCID,
425  unsigned DefClass,
426  unsigned DefIdx, unsigned DefAlign) const;
427  int getLDMDefCycle(const InstrItineraryData *ItinData,
428  const MCInstrDesc &DefMCID,
429  unsigned DefClass,
430  unsigned DefIdx, unsigned DefAlign) const;
431  int getVSTMUseCycle(const InstrItineraryData *ItinData,
432  const MCInstrDesc &UseMCID,
433  unsigned UseClass,
434  unsigned UseIdx, unsigned UseAlign) const;
435  int getSTMUseCycle(const InstrItineraryData *ItinData,
436  const MCInstrDesc &UseMCID,
437  unsigned UseClass,
438  unsigned UseIdx, unsigned UseAlign) const;
439  int getOperandLatency(const InstrItineraryData *ItinData,
440  const MCInstrDesc &DefMCID,
441  unsigned DefIdx, unsigned DefAlign,
442  const MCInstrDesc &UseMCID,
443  unsigned UseIdx, unsigned UseAlign) const;
444 
445  int getOperandLatencyImpl(const InstrItineraryData *ItinData,
446  const MachineInstr &DefMI, unsigned DefIdx,
447  const MCInstrDesc &DefMCID, unsigned DefAdj,
448  const MachineOperand &DefMO, unsigned Reg,
449  const MachineInstr &UseMI, unsigned UseIdx,
450  const MCInstrDesc &UseMCID, unsigned UseAdj) const;
451 
452  unsigned getPredicationCost(const MachineInstr &MI) const override;
453 
454  unsigned getInstrLatency(const InstrItineraryData *ItinData,
455  const MachineInstr &MI,
456  unsigned *PredCost = nullptr) const override;
457 
458  int getInstrLatency(const InstrItineraryData *ItinData,
459  SDNode *Node) const override;
460 
461  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
462  const MachineRegisterInfo *MRI,
463  const MachineInstr &DefMI, unsigned DefIdx,
464  const MachineInstr &UseMI,
465  unsigned UseIdx) const override;
466  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
467  const MachineInstr &DefMI,
468  unsigned DefIdx) const override;
469 
470  /// verifyInstruction - Perform target specific instruction verification.
471  bool verifyInstruction(const MachineInstr &MI,
472  StringRef &ErrInfo) const override;
473 
474  virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
475 
476  void expandMEMCPY(MachineBasicBlock::iterator) const;
477 
478  /// Identify instructions that can be folded into a MOVCC instruction, and
479  /// return the defining instruction.
480  MachineInstr *canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI,
481  const TargetInstrInfo *TII) const;
482 
483  bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
484  AAResults *AA) const override;
485 
486 private:
487  /// Modeling special VFP / NEON fp MLA / MLS hazards.
488 
489  /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
490  /// MLx table.
491  DenseMap<unsigned, unsigned> MLxEntryMap;
492 
493  /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
494  /// stalls when scheduled together with fp MLA / MLS opcodes.
495  SmallSet<unsigned, 16> MLxHazardOpcodes;
496 
497 public:
498  /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
499  /// instruction.
500  bool isFpMLxInstruction(unsigned Opcode) const {
501  return MLxEntryMap.count(Opcode);
502  }
503 
504  /// isFpMLxInstruction - This version also returns the multiply opcode and the
505  /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
506  /// the MLX instructions with an extra lane operand.
507  bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
508  unsigned &AddSubOpc, bool &NegAcc,
509  bool &HasLane) const;
510 
511  /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
512  /// will cause stalls when scheduled after (within 4-cycle window) a fp
513  /// MLA / MLS instruction.
514  bool canCauseFpMLxStall(unsigned Opcode) const {
515  return MLxHazardOpcodes.count(Opcode);
516  }
517 
518  /// Returns true if the instruction has a shift by immediate that can be
519  /// executed in one cycle less.
520  bool isSwiftFastImmShift(const MachineInstr *MI) const;
521 
522  /// Returns predicate register associated with the given frame instruction.
523  unsigned getFramePred(const MachineInstr &MI) const {
524  assert(isFrameInstr(MI));
525  // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
526  // - argument declared in the pattern:
527  // 0 - frame size
528  // 1 - arg of CALLSEQ_START/CALLSEQ_END
529  // 2 - predicate code (like ARMCC::AL)
530  // - added by predOps:
531  // 3 - predicate reg
532  return MI.getOperand(3).getReg();
533  }
534 
536  Register Reg) const override;
537 };
538 
539 /// Get the operands corresponding to the given \p Pred value. By default, the
540 /// predicate register is assumed to be 0 (no register), but you can pass in a
541 /// \p PredReg if that is not the case.
542 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
543  unsigned PredReg = 0) {
544  return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
545  MachineOperand::CreateReg(PredReg, false)}};
546 }
547 
548 /// Get the operand corresponding to the conditional code result. By default,
549 /// this is 0 (no register).
550 static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
551  return MachineOperand::CreateReg(CCReg, false);
552 }
553 
554 /// Get the operand corresponding to the conditional code result for Thumb1.
555 /// This operand will always refer to CPSR and it will have the Define flag set.
556 /// You can optionally set the Dead flag by means of \p isDead.
557 static inline MachineOperand t1CondCodeOp(bool isDead = false) {
558  return MachineOperand::CreateReg(ARM::CPSR,
559  /*Define*/ true, /*Implicit*/ false,
560  /*Kill*/ false, isDead);
561 }
562 
563 static inline
564 bool isUncondBranchOpcode(int Opc) {
565  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
566 }
567 
568 // This table shows the VPT instruction variants, i.e. the different
569 // mask field encodings, see also B5.6. Predication/conditional execution in
570 // the ArmARM.
571 static inline bool isVPTOpcode(int Opc) {
572  return Opc == ARM::MVE_VPTv16i8 || Opc == ARM::MVE_VPTv16u8 ||
573  Opc == ARM::MVE_VPTv16s8 || Opc == ARM::MVE_VPTv8i16 ||
574  Opc == ARM::MVE_VPTv8u16 || Opc == ARM::MVE_VPTv8s16 ||
575  Opc == ARM::MVE_VPTv4i32 || Opc == ARM::MVE_VPTv4u32 ||
576  Opc == ARM::MVE_VPTv4s32 || Opc == ARM::MVE_VPTv4f32 ||
577  Opc == ARM::MVE_VPTv8f16 || Opc == ARM::MVE_VPTv16i8r ||
578  Opc == ARM::MVE_VPTv16u8r || Opc == ARM::MVE_VPTv16s8r ||
579  Opc == ARM::MVE_VPTv8i16r || Opc == ARM::MVE_VPTv8u16r ||
580  Opc == ARM::MVE_VPTv8s16r || Opc == ARM::MVE_VPTv4i32r ||
581  Opc == ARM::MVE_VPTv4u32r || Opc == ARM::MVE_VPTv4s32r ||
582  Opc == ARM::MVE_VPTv4f32r || Opc == ARM::MVE_VPTv8f16r ||
583  Opc == ARM::MVE_VPST;
584 }
585 
586 static inline
587 unsigned VCMPOpcodeToVPT(unsigned Opcode) {
588  switch (Opcode) {
589  default:
590  return 0;
591  case ARM::MVE_VCMPf32:
592  return ARM::MVE_VPTv4f32;
593  case ARM::MVE_VCMPf16:
594  return ARM::MVE_VPTv8f16;
595  case ARM::MVE_VCMPi8:
596  return ARM::MVE_VPTv16i8;
597  case ARM::MVE_VCMPi16:
598  return ARM::MVE_VPTv8i16;
599  case ARM::MVE_VCMPi32:
600  return ARM::MVE_VPTv4i32;
601  case ARM::MVE_VCMPu8:
602  return ARM::MVE_VPTv16u8;
603  case ARM::MVE_VCMPu16:
604  return ARM::MVE_VPTv8u16;
605  case ARM::MVE_VCMPu32:
606  return ARM::MVE_VPTv4u32;
607  case ARM::MVE_VCMPs8:
608  return ARM::MVE_VPTv16s8;
609  case ARM::MVE_VCMPs16:
610  return ARM::MVE_VPTv8s16;
611  case ARM::MVE_VCMPs32:
612  return ARM::MVE_VPTv4s32;
613 
614  case ARM::MVE_VCMPf32r:
615  return ARM::MVE_VPTv4f32r;
616  case ARM::MVE_VCMPf16r:
617  return ARM::MVE_VPTv8f16r;
618  case ARM::MVE_VCMPi8r:
619  return ARM::MVE_VPTv16i8r;
620  case ARM::MVE_VCMPi16r:
621  return ARM::MVE_VPTv8i16r;
622  case ARM::MVE_VCMPi32r:
623  return ARM::MVE_VPTv4i32r;
624  case ARM::MVE_VCMPu8r:
625  return ARM::MVE_VPTv16u8r;
626  case ARM::MVE_VCMPu16r:
627  return ARM::MVE_VPTv8u16r;
628  case ARM::MVE_VCMPu32r:
629  return ARM::MVE_VPTv4u32r;
630  case ARM::MVE_VCMPs8r:
631  return ARM::MVE_VPTv16s8r;
632  case ARM::MVE_VCMPs16r:
633  return ARM::MVE_VPTv8s16r;
634  case ARM::MVE_VCMPs32r:
635  return ARM::MVE_VPTv4s32r;
636  }
637 }
638 
639 static inline
640 bool isCondBranchOpcode(int Opc) {
641  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
642 }
643 
644 static inline bool isJumpTableBranchOpcode(int Opc) {
645  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
646  Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
647  Opc == ARM::t2BR_JT;
648 }
649 
650 static inline
651 bool isIndirectBranchOpcode(int Opc) {
652  return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
653 }
654 
655 static inline bool isIndirectCall(const MachineInstr &MI) {
656  int Opc = MI.getOpcode();
657  switch (Opc) {
658  // indirect calls:
659  case ARM::BLX:
660  case ARM::BLX_noip:
661  case ARM::BLX_pred:
662  case ARM::BLX_pred_noip:
663  case ARM::BX_CALL:
664  case ARM::BMOVPCRX_CALL:
665  case ARM::TCRETURNri:
666  case ARM::TAILJMPr:
667  case ARM::TAILJMPr4:
668  case ARM::tBLXr:
669  case ARM::tBLXr_noip:
670  case ARM::tBLXNSr:
671  case ARM::tBLXNS_CALL:
672  case ARM::tBX_CALL:
673  case ARM::tTAILJMPr:
675  return true;
676  // direct calls:
677  case ARM::BL:
678  case ARM::BL_pred:
679  case ARM::BMOVPCB_CALL:
680  case ARM::BL_PUSHLR:
681  case ARM::BLXi:
682  case ARM::TCRETURNdi:
683  case ARM::TAILJMPd:
684  case ARM::SVC:
685  case ARM::HVC:
686  case ARM::TPsoft:
687  case ARM::tTAILJMPd:
688  case ARM::t2SMC:
689  case ARM::t2HVC:
690  case ARM::tBL:
691  case ARM::tBLXi:
692  case ARM::tBL_PUSHLR:
693  case ARM::tTAILJMPdND:
694  case ARM::tSVC:
695  case ARM::tTPsoft:
697  return false;
698  }
700  return false;
701 }
702 
704  int opc = MI.getOpcode();
705  return MI.isReturn() || isIndirectBranchOpcode(MI.getOpcode()) ||
707 }
708 
709 static inline bool isSpeculationBarrierEndBBOpcode(int Opc) {
710  return Opc == ARM::SpeculationBarrierISBDSBEndBB ||
711  Opc == ARM::SpeculationBarrierSBEndBB ||
712  Opc == ARM::t2SpeculationBarrierISBDSBEndBB ||
713  Opc == ARM::t2SpeculationBarrierSBEndBB;
714 }
715 
716 static inline bool isPopOpcode(int Opc) {
717  return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
718  Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
719  Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
720 }
721 
722 static inline bool isPushOpcode(int Opc) {
723  return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
724  Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
725 }
726 
727 static inline bool isSubImmOpcode(int Opc) {
728  return Opc == ARM::SUBri ||
729  Opc == ARM::tSUBi3 || Opc == ARM::tSUBi8 ||
730  Opc == ARM::tSUBSi3 || Opc == ARM::tSUBSi8 ||
731  Opc == ARM::t2SUBri || Opc == ARM::t2SUBri12 || Opc == ARM::t2SUBSri;
732 }
733 
734 static inline bool isMovRegOpcode(int Opc) {
735  return Opc == ARM::MOVr || Opc == ARM::tMOVr || Opc == ARM::t2MOVr;
736 }
737 /// isValidCoprocessorNumber - decide whether an explicit coprocessor
738 /// number is legal in generic instructions like CDP. The answer can
739 /// vary with the subtarget.
740 static inline bool isValidCoprocessorNumber(unsigned Num,
741  const FeatureBitset& featureBits) {
742  // In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
743  // coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
744  // useful for code which is shared with older architectures which do not know
745  // the new VFP/NEON mnemonics.
746 
747  // Armv8-A disallows everything *other* than 111x (CP14 and CP15).
748  if (featureBits[ARM::HasV8Ops] && (Num & 0xE) != 0xE)
749  return false;
750 
751  // Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
752  // which clash with MVE.
753  if (featureBits[ARM::HasV8_1MMainlineOps] &&
754  ((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
755  return false;
756 
757  return true;
758 }
759 
760 static inline bool isSEHInstruction(const MachineInstr &MI) {
761  unsigned Opc = MI.getOpcode();
762  switch (Opc) {
763  case ARM::SEH_StackAlloc:
764  case ARM::SEH_SaveRegs:
765  case ARM::SEH_SaveRegs_Ret:
766  case ARM::SEH_SaveSP:
767  case ARM::SEH_SaveFRegs:
768  case ARM::SEH_SaveLR:
769  case ARM::SEH_Nop:
770  case ARM::SEH_Nop_Ret:
771  case ARM::SEH_PrologEnd:
772  case ARM::SEH_EpilogStart:
773  case ARM::SEH_EpilogEnd:
774  return true;
775  default:
776  return false;
777  }
778 }
779 
780 /// getInstrPredicate - If instruction is predicated, returns its predicate
781 /// condition, otherwise returns AL. It also returns the condition code
782 /// register by reference.
783 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg);
784 
785 unsigned getMatchingCondBranchOpcode(unsigned Opc);
786 
787 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
788 /// the instruction is encoded with an 'S' bit is determined by the optional
789 /// CPSR def operand.
790 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
791 
792 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
793 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
794 /// code.
795 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
797  const DebugLoc &dl, Register DestReg,
798  Register BaseReg, int NumBytes,
799  ARMCC::CondCodes Pred, Register PredReg,
800  const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
801 
802 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
804  const DebugLoc &dl, Register DestReg,
805  Register BaseReg, int NumBytes,
806  ARMCC::CondCodes Pred, Register PredReg,
807  const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
808 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
810  const DebugLoc &dl, Register DestReg,
811  Register BaseReg, int NumBytes,
812  const TargetInstrInfo &TII,
813  const ARMBaseRegisterInfo &MRI,
814  unsigned MIFlags = 0);
815 
816 /// Tries to add registers to the reglist of a given base-updating
817 /// push/pop instruction to adjust the stack by an additional
818 /// NumBytes. This can save a few bytes per function in code-size, but
819 /// obviously generates more memory traffic. As such, it only takes
820 /// effect in functions being optimised for size.
821 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
822  MachineFunction &MF, MachineInstr *MI,
823  unsigned NumBytes);
824 
825 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
826 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
827 /// offset could not be handled directly in MI, and return the left-over
828 /// portion by reference.
829 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
830  Register FrameReg, int &Offset,
831  const ARMBaseInstrInfo &TII);
832 
833 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
834  Register FrameReg, int &Offset,
835  const ARMBaseInstrInfo &TII,
836  const TargetRegisterInfo *TRI);
837 
838 /// Return true if Reg is defd between From and To
841  const TargetRegisterInfo *TRI);
842 
843 /// Search backwards from a tBcc to find a tCMPi8 against 0, meaning
844 /// we can convert them to a tCBZ or tCBNZ. Return nullptr if not found.
845 MachineInstr *findCMPToFoldIntoCBZ(MachineInstr *Br,
846  const TargetRegisterInfo *TRI);
847 
848 void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB);
849 void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg);
850 
851 void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond);
852 void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond,
853  unsigned Inactive);
854 
855 /// Returns the number of instructions required to materialize the given
856 /// constant in a register, or 3 if a literal pool load is needed.
857 /// If ForCodesize is specified, an approximate cost in bytes is returned.
858 unsigned ConstantMaterializationCost(unsigned Val,
859  const ARMSubtarget *Subtarget,
860  bool ForCodesize = false);
861 
862 /// Returns true if Val1 has a lower Constant Materialization Cost than Val2.
863 /// Uses the cost from ConstantMaterializationCost, first with ForCodesize as
864 /// specified. If the scores are equal, return the comparison for !ForCodesize.
865 bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2,
866  const ARMSubtarget *Subtarget,
867  bool ForCodesize = false);
868 
869 // Return the immediate if this is ADDri or SUBri, scaled as appropriate.
870 // Returns 0 for unknown instructions.
872  int Scale = 1;
873  unsigned ImmOp;
874  switch (MI.getOpcode()) {
875  case ARM::t2ADDri:
876  ImmOp = 2;
877  break;
878  case ARM::t2SUBri:
879  case ARM::t2SUBri12:
880  ImmOp = 2;
881  Scale = -1;
882  break;
883  case ARM::tSUBi3:
884  case ARM::tSUBi8:
885  ImmOp = 3;
886  Scale = -1;
887  break;
888  default:
889  return 0;
890  }
891  return Scale * MI.getOperand(ImmOp).getImm();
892 }
893 
894 // Given a memory access Opcode, check that the give Imm would be a valid Offset
895 // for this instruction using its addressing mode.
896 inline bool isLegalAddressImm(unsigned Opcode, int Imm,
897  const TargetInstrInfo *TII) {
898  const MCInstrDesc &Desc = TII->get(Opcode);
899  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
900  switch (AddrMode) {
902  return std::abs(Imm) < ((1 << 7) * 1);
904  return std::abs(Imm) < ((1 << 7) * 2) && Imm % 2 == 0;
906  return std::abs(Imm) < ((1 << 7) * 4) && Imm % 4 == 0;
908  return std::abs(Imm) < ((1 << 8) * 1);
910  return Imm >= 0 && Imm < ((1 << 8) * 1);
912  return Imm < 0 && -Imm < ((1 << 8) * 1);
914  return std::abs(Imm) < ((1 << 8) * 4) && Imm % 4 == 0;
916  return Imm >= 0 && Imm < ((1 << 12) * 1);
917  case ARMII::AddrMode2:
918  return std::abs(Imm) < ((1 << 12) * 1);
919  default:
920  llvm_unreachable("Unhandled Addressing mode");
921  }
922 }
923 
924 // Return true if the given intrinsic is a gather
925 inline bool isGather(IntrinsicInst *IntInst) {
926  if (IntInst == nullptr)
927  return false;
928  unsigned IntrinsicID = IntInst->getIntrinsicID();
929  return (IntrinsicID == Intrinsic::masked_gather ||
930  IntrinsicID == Intrinsic::arm_mve_vldr_gather_base ||
931  IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_predicated ||
932  IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb ||
933  IntrinsicID == Intrinsic::arm_mve_vldr_gather_base_wb_predicated ||
934  IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset ||
935  IntrinsicID == Intrinsic::arm_mve_vldr_gather_offset_predicated);
936 }
937 
938 // Return true if the given intrinsic is a scatter
939 inline bool isScatter(IntrinsicInst *IntInst) {
940  if (IntInst == nullptr)
941  return false;
942  unsigned IntrinsicID = IntInst->getIntrinsicID();
943  return (IntrinsicID == Intrinsic::masked_scatter ||
944  IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base ||
945  IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_predicated ||
946  IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb ||
947  IntrinsicID == Intrinsic::arm_mve_vstr_scatter_base_wb_predicated ||
948  IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset ||
949  IntrinsicID == Intrinsic::arm_mve_vstr_scatter_offset_predicated);
950 }
951 
952 // Return true if the given intrinsic is a gather or scatter
953 inline bool isGatherScatter(IntrinsicInst *IntInst) {
954  if (IntInst == nullptr)
955  return false;
956  return isGather(IntInst) || isScatter(IntInst);
957 }
958 
959 unsigned getBLXOpcode(const MachineFunction &MF);
960 unsigned gettBLXrOpcode(const MachineFunction &MF);
961 unsigned getBLXpredOpcode(const MachineFunction &MF);
962 
963 } // end namespace llvm
964 
965 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
llvm::ARMBaseInstrInfo::optimizeSelect
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
Definition: ARMBaseInstrInfo.cpp:2350
llvm::ARMBaseInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Definition: ARMBaseInstrInfo.cpp:353
llvm::ARMBaseInstrInfo::duplicate
MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const override
Definition: ARMBaseInstrInfo.cpp:1831
llvm::ARMBaseInstrInfo::isFpMLxInstruction
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
Definition: ARMBaseInstrInfo.h:500
llvm::addPredicatedMveVpredNOp
void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond)
Definition: ARMBaseInstrInfo.cpp:876
llvm::ARMBaseInstrInfo::buildOutlinedFrame
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
Definition: ARMBaseInstrInfo.cpp:6584
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::ARMBaseInstrInfo::isAddImmediate
Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
Definition: ARMBaseInstrInfo.cpp:5537
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::ARMBaseInstrInfo::isMBBSafeToOutlineFrom
bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const override
Definition: ARMBaseInstrInfo.cpp:6207
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::ARMBaseInstrInfo::getFramePred
unsigned getFramePred(const MachineInstr &MI) const
Returns predicate register associated with the given frame instruction.
Definition: ARMBaseInstrInfo.h:523
llvm::ARMBaseInstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Definition: ARMBaseInstrInfo.cpp:2054
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
IntrinsicInst.h
llvm::ARMII::AddrModeT2_i8neg
@ AddrModeT2_i8neg
Definition: ARMBaseInfo.h:200
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: ARMBaseInstrInfo.cpp:5509
llvm::Function
Definition: Function.h:60
llvm::emitT2RegPlusImmediate
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Definition: Thumb2InstrInfo.cpp:287
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:53
llvm::ARMII::AddrModeT2_i8s4
@ AddrModeT2_i8s4
Definition: ARMBaseInfo.h:203
llvm::ARMBaseInstrInfo::getExecutionDomain
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
VFP/NEON execution domains.
Definition: ARMBaseInstrInfo.cpp:5020
llvm::ARMBaseInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: ARMBaseInstrInfo.cpp:1113
llvm::convertAddSubFlagsOpcode
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
Definition: ARMBaseInstrInfo.cpp:2470
llvm::ARMBaseInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: ARMBaseInstrInfo.cpp:1303
llvm::ARMBaseInstrInfo::areLoadsFromSameBasePtr
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
Definition: ARMBaseInstrInfo.cpp:1943
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::ARMBaseInstrInfo::SubsumesPredicate
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Definition: ARMBaseInstrInfo.cpp:632
MachineBasicBlock.h
llvm::ARMBaseInstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
Definition: ARMBaseInstrInfo.cpp:2265
llvm::ARMBaseInstrInfo::isProfitableToIfCvt
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: ARMBaseInstrInfo.cpp:2105
llvm::ARMII::AddrMode2
@ AddrMode2
Definition: ARMBaseInfo.h:188
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::ARMBaseInstrInfo::getUnindexedOpcode
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:33
DenseMap.h
TargetInstrInfo.h
llvm::isCondBranchOpcode
static bool isCondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:461
llvm::SmallSet< unsigned, 16 >
llvm::Optional
Definition: APInt.h:33
llvm::DenseMapBase::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:147
llvm::ARMBaseInstrInfo::CreateTargetHazardRecognizer
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
Definition: ARMBaseInstrInfo.cpp:127
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::ARMBaseInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: ARMBaseInstrInfo.cpp:1369
llvm::isUncondBranchOpcode
static bool isUncondBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:459
llvm::ARMBaseInstrInfo::getPredicate
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const
Definition: ARMBaseInstrInfo.h:165
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:214
llvm::ARMBaseInstrInfo::expandLoadStackGuardBase
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
Definition: ARMBaseInstrInfo.cpp:4906
llvm::findCMPToFoldIntoCBZ
MachineInstr * findCMPToFoldIntoCBZ(MachineInstr *Br, const TargetRegisterInfo *TRI)
Search backwards from a tBcc to find a tCMPi8 against 0, meaning we can convert them to a tCBZ or tCB...
Definition: ARMBaseInstrInfo.cpp:5575
llvm::ARMBaseInstrInfo::isProfitableToDupForIfCvt
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: ARMBaseInstrInfo.h:274
llvm::ARMBaseInstrInfo::PredicateInstruction
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Definition: ARMBaseInstrInfo.cpp:599
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1622
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::isValidCoprocessorNumber
static bool isValidCoprocessorNumber(unsigned Num, const FeatureBitset &featureBits)
isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instruct...
Definition: ARMBaseInstrInfo.h:740
llvm::isGather
bool isGather(IntrinsicInst *IntInst)
Definition: ARMBaseInstrInfo.h:925
llvm::ARMBaseInstrInfo::isProfitableToUnpredicate
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: ARMBaseInstrInfo.cpp:2232
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetInstrInfo::RegSubRegPair
A pair composed of a register and a sub-register index.
Definition: TargetInstrInfo.h:491
llvm::getAddSubImmediate
int getAddSubImmediate(MachineInstr &MI)
Definition: ARMBaseInstrInfo.h:871
llvm::getBLXOpcode
unsigned getBLXOpcode(const MachineFunction &MF)
Definition: ARMBaseInstrInfo.cpp:6738
llvm::isSEHInstruction
static bool isSEHInstruction(const MachineInstr &MI)
Definition: ARMBaseInstrInfo.h:760
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:205
llvm::ARMBaseInstrInfo::predictBranchSizeForIfCvt
unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const override
Definition: ARMBaseInstrInfo.cpp:2209
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::ARMBaseInstrInfo::getOutliningCandidateInfo
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
Definition: ARMBaseInstrInfo.cpp:5850
ARMBaseInfo.h
llvm::ARMBaseInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
Definition: ARMBaseInstrInfo.cpp:2797
llvm::AAResults
Definition: AliasAnalysis.h:511
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::isGatherScatter
bool isGatherScatter(IntrinsicInst *IntInst)
Definition: ARMBaseInstrInfo.h:953
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::ARMBaseInstrInfo::createMIROperandComment
std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
Definition: ARMBaseInstrInfo.cpp:574
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::ARMII::AddrModeT2_i7s4
@ AddrModeT2_i7s4
Definition: ARMBaseInfo.h:207
llvm::ARMBaseInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Returns the size of the specified MachineInstr.
Definition: ARMBaseInstrInfo.cpp:775
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:710
llvm::ARMBaseInstrInfo::shouldSink
bool shouldSink(const MachineInstr &MI) const override
Definition: ARMBaseInstrInfo.cpp:3284
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::ARMBaseInstrInfo::insertOutlinedCall
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
Definition: ARMBaseInstrInfo.cpp:6660
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::ARMBaseInstrInfo::getNumLDMAddresses
unsigned getNumLDMAddresses(const MachineInstr &MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
Definition: ARMBaseInstrInfo.cpp:3698
llvm::ARMBaseInstrInfo::breakPartialRegDependency
void breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
Definition: ARMBaseInstrInfo.cpp:5379
llvm::ARMBaseInstrInfo::analyzeSelect
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
Definition: ARMBaseInstrInfo.cpp:2328
llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
Definition: ARMBaseInstrInfo.cpp:5458
llvm::isPopOpcode
static bool isPopOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:716
llvm::ARMBaseInstrInfo::isLoadFromStackSlotPostFE
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
Definition: ARMBaseInstrInfo.cpp:1611
llvm::VCMPOpcodeToVPT
static unsigned VCMPOpcodeToVPT(unsigned Opcode)
Definition: ARMBaseInstrInfo.h:587
llvm::ARMII::AddrModeT2_i7
@ AddrModeT2_i7
Definition: ARMBaseInfo.h:209
RegSubRegPairAndIdx
TargetInstrInfo::RegSubRegPairAndIdx RegSubRegPairAndIdx
Definition: PeepholeOptimizer.cpp:101
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::ARMBaseInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: ARMBaseInstrInfo.cpp:549
llvm::ARMBaseInstrInfo::isCopyInstrImpl
Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is an instruction that moves/copies value from one register to an...
Definition: ARMBaseInstrInfo.cpp:1055
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::ARMBaseInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: ARMBaseInstrInfo.cpp:496
ARMGenInstrInfo
llvm::ARMBaseInstrInfo::isPredicable
bool isPredicable(const MachineInstr &MI) const override
isPredicable - Return true if the specified instruction can be predicated.
Definition: ARMBaseInstrInfo.cpp:721
llvm::isIndirectBranchOpcode
static bool isIndirectBranchOpcode(int Opc)
Definition: AArch64InstrInfo.h:478
llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
Definition: ARMBaseInstrInfo.cpp:5481
llvm::ARMBaseInstrInfo::mergeOutliningCandidateAttributes
void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const override
Definition: ARMBaseInstrInfo.cpp:6172
llvm::ARMBaseInstrInfo::isCPSRDefined
static bool isCPSRDefined(const MachineInstr &MI)
Definition: ARMBaseInstrInfo.cpp:682
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:166
llvm::isVPTOpcode
static bool isVPTOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:571
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::ARMBaseInstrInfo::describeLoadedValue
Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Specialization of TargetInstrInfo::describeLoadedValue, used to enhance debug entry value description...
Definition: ARMBaseInstrInfo.cpp:1071
llvm::getInstrPredicate
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition,...
Definition: ARMBaseInstrInfo.cpp:2242
llvm::getMatchingCondBranchOpcode
unsigned getMatchingCondBranchOpcode(unsigned Opc)
Definition: ARMBaseInstrInfo.cpp:2254
llvm::ARMBaseInstrInfo::produceSameValue
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
Definition: ARMBaseInstrInfo.cpp:1855
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:37
llvm::getBLXpredOpcode
unsigned getBLXpredOpcode(const MachineFunction &MF)
Definition: ARMBaseInstrInfo.cpp:6748
llvm::rewriteT2FrameIndex
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)
Definition: Thumb2InstrInfo.cpp:530
llvm::DenseMap< unsigned, unsigned >
llvm::registerDefinedBetween
bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI)
Return true if Reg is defd between From and To.
Definition: ARMBaseInstrInfo.cpp:5565
llvm::condCodeOp
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
Definition: ARMBaseInstrInfo.h:550
llvm::ARMII::AddrModeT2_i8pos
@ AddrModeT2_i8pos
Definition: ARMBaseInfo.h:199
llvm::addUnpredicatedMveVpredNOp
void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB)
Definition: ARMBaseInstrInfo.cpp:864
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::ARMII::AddrModeMask
@ AddrModeMask
Definition: ARMBaseInfo.h:303
llvm::ARMBaseInstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
Definition: ARMBaseInstrInfo.cpp:3005
llvm::ARMBaseInstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
Definition: ARMBaseInstrInfo.cpp:177
llvm::ARMBaseInstrInfo::CreateTargetMIHazardRecognizer
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
Definition: ARMBaseInstrInfo.cpp:140
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::isLegalAddressImm
bool isLegalAddressImm(unsigned Opcode, int Imm, const TargetInstrInfo *TII)
Definition: ARMBaseInstrInfo.h:896
llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
Definition: ARMBaseInstrInfo.cpp:5431
llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Definition: ARMBaseInstrInfo.cpp:163
llvm::ARMBaseInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: ARMBaseInstrInfo.cpp:1680
llvm::tryFoldSPUpdateIntoPushPop
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
Definition: ARMBaseInstrInfo.cpp:2518
llvm::ARMBaseInstrInfo::copyToCPSR
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
Definition: ARMBaseInstrInfo.cpp:844
llvm::gettBLXrOpcode
unsigned gettBLXrOpcode(const MachineFunction &MF)
Definition: ARMBaseInstrInfo.cpp:6743
llvm::ARMII::AddrModeT2_i7s2
@ AddrModeT2_i7s2
Definition: ARMBaseInfo.h:208
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:242
llvm::rewriteARMFrameIndex
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
Definition: ARMBaseInstrInfo.cpp:2640
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::addPredicatedMveVpredROp
void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond, unsigned Inactive)
Definition: ARMBaseInstrInfo.cpp:882
llvm::ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: ARMBaseInstrInfo.cpp:5515
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::ARMBaseInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: ARMBaseInstrInfo.cpp:469
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ARMBaseInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
Definition: ARMBaseInstrInfo.cpp:3302
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ARMBaseInstrInfo::getOutliningType
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
Definition: ARMBaseInstrInfo.cpp:6256
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
Node
Definition: ItaniumDemangle.h:155
llvm::ARMBaseInstrInfo::getNumMicroOps
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override
Definition: ARMBaseInstrInfo.cpp:3752
llvm::ARMBaseInstrInfo::getRegisterInfo
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
llvm::ARMBaseInstrInfo::isFunctionSafeToOutlineFrom
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
ARM supports the MachineOutliner.
Definition: ARMBaseInstrInfo.cpp:6184
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
llvm::isIndirectCall
static bool isIndirectCall(const MachineInstr &MI)
Definition: ARMBaseInstrInfo.h:655
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ARMBaseInstrInfo::analyzeLoopForPipelining
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
Definition: ARMBaseInstrInfo.cpp:6818
llvm::ARMBaseRegisterInfo
Definition: ARMBaseRegisterInfo.h:127
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance
unsigned getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
Definition: ARMBaseInstrInfo.cpp:5318
llvm::ARMBaseInstrInfo::reMaterialize
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
Definition: ARMBaseInstrInfo.cpp:1803
llvm::ARMBaseInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
Definition: ARMBaseInstrInfo.cpp:4355
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:345
llvm::ARMII::AddrModeT2_i12
@ AddrModeT2_i12
Definition: ARMBaseInfo.h:197
llvm::ARMII::AddrModeT2_i8
@ AddrModeT2_i8
Definition: ARMBaseInfo.h:198
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::isScatter
bool isScatter(IntrinsicInst *IntInst)
Definition: ARMBaseInstrInfo.h:939
llvm::ARMBaseInstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Definition: ARMBaseInstrInfo.cpp:558
llvm::ARMCC::CondCodes
CondCodes
Definition: ARMBaseInfo.h:30
llvm::ARMBaseInstrInfo::ClobbersPredicate
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
Definition: ARMBaseInstrInfo.cpp:658
llvm::ARMBaseInstrInfo::extraSizeToPredicateInstructions
unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const override
Definition: ARMBaseInstrInfo.cpp:2195
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::isPushOpcode
static bool isPushOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:722
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
AA
llvm::isJumpTableBranchOpcode
static bool isJumpTableBranchOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:644
llvm::ConstantMaterializationCost
unsigned ConstantMaterializationCost(unsigned Val, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns the number of instructions required to materialize the given constant in a register,...
Definition: ARMBaseInstrInfo.cpp:5606
llvm::MachineInstr::IgnoreBundle
@ IgnoreBundle
Definition: MachineInstr.h:767
llvm::isIndirectControlFlowNotComingBack
static bool isIndirectControlFlowNotComingBack(const MachineInstr &MI)
Definition: ARMBaseInstrInfo.h:703
llvm::ARMBaseInstrInfo::shouldOutlineFromFunctionByDefault
bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override
Enable outlining by default at -Oz.
Definition: ARMBaseInstrInfo.cpp:6724
MachineInstrBuilder.h
llvm::ARMBaseInstrInfo::copyFromCPSR
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
Definition: ARMBaseInstrInfo.cpp:824
llvm::ARMBaseInstrInfo::ARMBaseInstrInfo
ARMBaseInstrInfo(const ARMSubtarget &STI)
Definition: ARMBaseInstrInfo.cpp:113
llvm::ARMBaseInstrInfo::AddDReg
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
Definition: ARMBaseInstrInfo.cpp:1101
llvm::ARMBaseInstrInfo::hasNOP
bool hasNOP() const
Definition: ARMBaseInstrInfo.cpp:5413
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::ARMBaseInstrInfo::isStoreToStackSlotPostFE
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
Definition: ARMBaseInstrInfo.cpp:1355
llvm::emitARMRegPlusImmediate
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
Definition: ARMBaseInstrInfo.cpp:2477
llvm::emitThumbRegPlusImmediate
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
Definition: ThumbRegisterInfo.cpp:185
llvm::addUnpredicatedMveVpredROp
void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, Register DestReg)
Definition: ARMBaseInstrInfo.cpp:870
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MachineOperand.h
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:542
llvm::LiveVariables
Definition: LiveVariables.h:47
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::isSpeculationBarrierEndBBOpcode
static bool isSpeculationBarrierEndBBOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:709
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::ARMBaseInstrInfo::canCauseFpMLxStall
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
Definition: ARMBaseInstrInfo.h:514
llvm::ARMBaseInstrInfo::getSubtarget
const ARMSubtarget & getSubtarget() const
Definition: ARMBaseInstrInfo.h:127
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::ARMBaseInstrInfo::isUnspillableTerminatorImpl
bool isUnspillableTerminatorImpl(const MachineInstr *MI) const override
Definition: ARMBaseInstrInfo.h:368
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1282
llvm::ARMBaseInstrInfo::setExecutionDomain
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
Definition: ARMBaseInstrInfo.cpp:5110
llvm::ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Definition: ARMBaseInstrInfo.cpp:5524
llvm::ARMBaseInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: ARMBaseInstrInfo.cpp:1553
llvm::isMovRegOpcode
static bool isMovRegOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:734
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::ARMBaseInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: ARMBaseInstrInfo.cpp:888
llvm::t1CondCodeOp
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
Definition: ARMBaseInstrInfo.h:557
llvm::isSubImmOpcode
static bool isSubImmOpcode(int Opc)
Definition: ARMBaseInstrInfo.h:727
llvm::ARMBaseInstrInfo::isSwiftFastImmShift
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
Definition: ARMBaseInstrInfo.cpp:5417
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
SmallSet.h
llvm::ARMBaseInstrInfo::shouldScheduleLoadsNear
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
Definition: ARMBaseInstrInfo.cpp:2024
llvm::HasLowerConstantMaterializationCost
bool HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2, const ARMSubtarget *Subtarget, bool ForCodesize=false)
Returns true if Val1 has a lower Constant Materialization Cost than Val2.
Definition: ARMBaseInstrInfo.cpp:5639