LLVM 20.0.0git
MachineRegisterInfo.h
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1//===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the MachineRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
14#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/IndexedMap.h"
22#include "llvm/ADT/StringSet.h"
31#include "llvm/MC/LaneBitmask.h"
32#include <cassert>
33#include <cstddef>
34#include <cstdint>
35#include <iterator>
36#include <memory>
37#include <utility>
38#include <vector>
39
40namespace llvm {
41
42class PSetIterator;
43
44/// Convenient type to represent either a register class or a register bank.
47
48/// MachineRegisterInfo - Keep track of information for virtual and physical
49/// registers, including vreg register classes, use/def chains for registers,
50/// etc.
52public:
53 class Delegate {
54 virtual void anchor();
55
56 public:
57 virtual ~Delegate() = default;
58
61 Register SrcReg) {
63 }
64 };
65
66private:
68 SmallPtrSet<Delegate *, 1> TheDelegates;
69
70 /// True if subregister liveness is tracked.
71 const bool TracksSubRegLiveness;
72
73 /// VRegInfo - Information we keep for each virtual register.
74 ///
75 /// Each element in this list contains the register class of the vreg and the
76 /// start of the use/def list for the register.
80
81 /// Map for recovering vreg name from vreg number.
82 /// This map is used by the MIR Printer.
84
85 /// StringSet that is used to unique vreg names.
86 StringSet<> VRegNames;
87
88 /// The flag is true upon \p UpdatedCSRs initialization
89 /// and false otherwise.
90 bool IsUpdatedCSRsInitialized = false;
91
92 /// Contains the updated callee saved register list.
93 /// As opposed to the static list defined in register info,
94 /// all registers that were disabled are removed from the list.
96
97 /// RegAllocHints - This vector records register allocation hints for
98 /// virtual registers. For each virtual register, it keeps a pair of hint
99 /// type and hints vector making up the allocation hints. Only the first
100 /// hint may be target specific, and in that case this is reflected by the
101 /// first member of the pair being non-zero. If the hinted register is
102 /// virtual, it means the allocator should prefer the physical register
103 /// allocated to it if any.
106 RegAllocHints;
107
108 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
109 /// physical registers.
110 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
111
112 /// getRegUseDefListHead - Return the head pointer for the register use/def
113 /// list for the specified virtual or physical register.
114 MachineOperand *&getRegUseDefListHead(Register RegNo) {
115 if (RegNo.isVirtual())
116 return VRegInfo[RegNo.id()].second;
117 return PhysRegUseDefLists[RegNo.id()];
118 }
119
120 MachineOperand *getRegUseDefListHead(Register RegNo) const {
121 if (RegNo.isVirtual())
122 return VRegInfo[RegNo.id()].second;
123 return PhysRegUseDefLists[RegNo.id()];
124 }
125
126 /// Get the next element in the use-def chain.
127 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
128 assert(MO && MO->isReg() && "This is not a register operand!");
129 return MO->Contents.Reg.Next;
130 }
131
132 /// UsedPhysRegMask - Additional used physregs including aliases.
133 /// This bit vector represents all the registers clobbered by function calls.
134 BitVector UsedPhysRegMask;
135
136 /// ReservedRegs - This is a bit vector of reserved registers. The target
137 /// may change its mind about which registers should be reserved. This
138 /// vector is the frozen set of reserved registers when register allocation
139 /// started.
140 BitVector ReservedRegs;
141
142 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
143 /// Map generic virtual registers to their low-level type.
144 VRegToTypeMap VRegToType;
145
146 /// Keep track of the physical registers that are live in to the function.
147 /// Live in values are typically arguments in registers. LiveIn values are
148 /// allowed to have virtual registers associated with them, stored in the
149 /// second element.
150 std::vector<std::pair<MCRegister, Register>> LiveIns;
151
152public:
153 explicit MachineRegisterInfo(MachineFunction *MF);
156
158 return MF->getSubtarget().getRegisterInfo();
159 }
160
161 void resetDelegate(Delegate *delegate) {
162 // Ensure another delegate does not take over unless the current
163 // delegate first unattaches itself.
164 assert(TheDelegates.count(delegate) &&
165 "Only an existing delegate can perform reset!");
166 TheDelegates.erase(delegate);
167 }
168
169 void addDelegate(Delegate *delegate) {
170 assert(delegate && !TheDelegates.count(delegate) &&
171 "Attempted to add null delegate, or to change it without "
172 "first resetting it!");
173
174 TheDelegates.insert(delegate);
175 }
176
178 for (auto *TheDelegate : TheDelegates)
179 TheDelegate->MRI_NoteNewVirtualRegister(Reg);
180 }
181
183 for (auto *TheDelegate : TheDelegates)
184 TheDelegate->MRI_NoteCloneVirtualRegister(NewReg, SrcReg);
185 }
186
187 const MachineFunction &getMF() const { return *MF; }
188
189 //===--------------------------------------------------------------------===//
190 // Function State
191 //===--------------------------------------------------------------------===//
192
193 // isSSA - Returns true when the machine function is in SSA form. Early
194 // passes require the machine function to be in SSA form where every virtual
195 // register has a single defining instruction.
196 //
197 // The TwoAddressInstructionPass and PHIElimination passes take the machine
198 // function out of SSA form when they introduce multiple defs per virtual
199 // register.
200 bool isSSA() const {
201 return MF->getProperties().hasProperty(
203 }
204
205 // leaveSSA - Indicates that the machine function is no longer in SSA form.
206 void leaveSSA() {
208 }
209
210 /// tracksLiveness - Returns true when tracking register liveness accurately.
211 /// (see MachineFUnctionProperties::Property description for details)
212 bool tracksLiveness() const {
213 return MF->getProperties().hasProperty(
215 }
216
217 /// invalidateLiveness - Indicates that register liveness is no longer being
218 /// tracked accurately.
219 ///
220 /// This should be called by late passes that invalidate the liveness
221 /// information.
223 MF->getProperties().reset(
225 }
226
227 /// Returns true if liveness for register class @p RC should be tracked at
228 /// the subregister level.
231 }
233 assert(VReg.isVirtual() && "Must pass a VReg");
234 const TargetRegisterClass *RC = getRegClassOrNull(VReg);
235 return LLVM_LIKELY(RC) ? shouldTrackSubRegLiveness(*RC) : false;
236 }
238 return TracksSubRegLiveness;
239 }
240
241 //===--------------------------------------------------------------------===//
242 // Register Info
243 //===--------------------------------------------------------------------===//
244
245 /// Returns true if the updated CSR list was initialized and false otherwise.
246 bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
247
248 /// Disables the register from the list of CSRs.
249 /// I.e. the register will not appear as part of the CSR mask.
250 /// \see UpdatedCalleeSavedRegs.
252
253 /// Returns list of callee saved registers.
254 /// The function returns the updated CSR list (after taking into account
255 /// registers that are disabled from the CSR list).
256 const MCPhysReg *getCalleeSavedRegs() const;
257
258 /// Sets the updated Callee Saved Registers list.
259 /// Notice that it will override ant previously disabled/saved CSRs.
261
262 // Strictly for use by MachineInstr.cpp.
264
265 // Strictly for use by MachineInstr.cpp.
267
268 // Strictly for use by MachineInstr.cpp.
269 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
270
271 /// Verify the sanity of the use list for Reg.
272 void verifyUseList(Register Reg) const;
273
274 /// Verify the use list of all registers.
275 void verifyUseLists() const;
276
277 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
278 /// and uses of a register within the MachineFunction that corresponds to this
279 /// MachineRegisterInfo object.
280 template<bool Uses, bool Defs, bool SkipDebug,
281 bool ByOperand, bool ByInstr, bool ByBundle>
282 class defusechain_iterator;
283 template<bool Uses, bool Defs, bool SkipDebug,
284 bool ByOperand, bool ByInstr, bool ByBundle>
285 class defusechain_instr_iterator;
286
287 // Make it a friend so it can access getNextOperandForReg().
288 template<bool, bool, bool, bool, bool, bool>
290 template<bool, bool, bool, bool, bool, bool>
292
293 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
294 /// register.
298 return reg_iterator(getRegUseDefListHead(RegNo));
299 }
300 static reg_iterator reg_end() { return reg_iterator(nullptr); }
301
303 return make_range(reg_begin(Reg), reg_end());
304 }
305
306 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
307 /// of the specified register, stepping by MachineInstr.
311 return reg_instr_iterator(getRegUseDefListHead(RegNo));
312 }
314 return reg_instr_iterator(nullptr);
315 }
316
320 }
321
322 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
323 /// of the specified register, stepping by bundle.
327 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
328 }
330 return reg_bundle_iterator(nullptr);
331 }
332
335 }
336
337 /// reg_empty - Return true if there are no instructions using or defining the
338 /// specified register (it may be live-in).
339 bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); }
340
341 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
342 /// of the specified register, skipping those marked as Debug.
346 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
347 }
349 return reg_nodbg_iterator(nullptr);
350 }
351
355 }
356
357 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
358 /// all defs and uses of the specified register, stepping by MachineInstr,
359 /// skipping those marked as Debug.
363 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
364 }
366 return reg_instr_nodbg_iterator(nullptr);
367 }
368
372 }
373
374 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
375 /// all defs and uses of the specified register, stepping by bundle,
376 /// skipping those marked as Debug.
380 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
381 }
383 return reg_bundle_nodbg_iterator(nullptr);
384 }
385
389 }
390
391 /// reg_nodbg_empty - Return true if the only instructions using or defining
392 /// Reg are Debug instructions.
393 bool reg_nodbg_empty(Register RegNo) const {
394 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
395 }
396
397 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
401 return def_iterator(getRegUseDefListHead(RegNo));
402 }
403 static def_iterator def_end() { return def_iterator(nullptr); }
404
406 return make_range(def_begin(Reg), def_end());
407 }
408
409 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
410 /// specified register, stepping by MachineInst.
414 return def_instr_iterator(getRegUseDefListHead(RegNo));
415 }
417 return def_instr_iterator(nullptr);
418 }
419
423 }
424
425 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
426 /// specified register, stepping by bundle.
430 return def_bundle_iterator(getRegUseDefListHead(RegNo));
431 }
433 return def_bundle_iterator(nullptr);
434 }
435
438 }
439
440 /// def_empty - Return true if there are no instructions defining the
441 /// specified register (it may be live-in).
442 bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); }
443
445 return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : "";
446 }
447
449 assert((Name.empty() || !VRegNames.contains(Name)) &&
450 "Named VRegs Must be Unique.");
451 if (!Name.empty()) {
452 VRegNames.insert(Name);
453 VReg2Name.grow(Reg);
454 VReg2Name[Reg] = Name.str();
455 }
456 }
457
458 /// Return true if there is exactly one operand defining the specified
459 /// register.
460 bool hasOneDef(Register RegNo) const {
461 return hasSingleElement(def_operands(RegNo));
462 }
463
464 /// Returns the defining operand if there is exactly one operand defining the
465 /// specified register, otherwise nullptr.
468 if (DI == def_end()) // No defs.
469 return nullptr;
470
471 def_iterator OneDef = DI;
472 if (++DI == def_end())
473 return &*OneDef;
474 return nullptr; // Multiple defs.
475 }
476
477 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
481 return use_iterator(getRegUseDefListHead(RegNo));
482 }
483 static use_iterator use_end() { return use_iterator(nullptr); }
484
486 return make_range(use_begin(Reg), use_end());
487 }
488
489 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
490 /// specified register, stepping by MachineInstr.
494 return use_instr_iterator(getRegUseDefListHead(RegNo));
495 }
497 return use_instr_iterator(nullptr);
498 }
499
503 }
504
505 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
506 /// specified register, stepping by bundle.
510 return use_bundle_iterator(getRegUseDefListHead(RegNo));
511 }
513 return use_bundle_iterator(nullptr);
514 }
515
518 }
519
520 /// use_empty - Return true if there are no instructions using the specified
521 /// register.
522 bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); }
523
524 /// hasOneUse - Return true if there is exactly one instruction using the
525 /// specified register.
526 bool hasOneUse(Register RegNo) const {
527 return hasSingleElement(use_operands(RegNo));
528 }
529
530 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
531 /// specified register, skipping those marked as Debug.
535 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
536 }
538 return use_nodbg_iterator(nullptr);
539 }
540
544 }
545
546 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
547 /// all uses of the specified register, stepping by MachineInstr, skipping
548 /// those marked as Debug.
552 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
553 }
555 return use_instr_nodbg_iterator(nullptr);
556 }
557
561 }
562
563 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
564 /// all uses of the specified register, stepping by bundle, skipping
565 /// those marked as Debug.
569 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
570 }
572 return use_bundle_nodbg_iterator(nullptr);
573 }
574
578 }
579
580 /// use_nodbg_empty - Return true if there are no non-Debug instructions
581 /// using the specified register.
582 bool use_nodbg_empty(Register RegNo) const {
583 return use_nodbg_begin(RegNo) == use_nodbg_end();
584 }
585
586 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
587 /// use of the specified register.
588 bool hasOneNonDBGUse(Register RegNo) const;
589
590 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
591 /// instruction using the specified register. Said instruction may have
592 /// multiple uses.
593 bool hasOneNonDBGUser(Register RegNo) const;
594
595
596 /// hasAtMostUses - Return true if the given register has at most \p MaxUsers
597 /// non-debug user instructions.
598 bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const;
599
600 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
601 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
602 /// except that it also changes any definitions of the register as well.
603 ///
604 /// Note that it is usually necessary to first constrain ToReg's register
605 /// class and register bank to match the FromReg constraints using one of the
606 /// methods:
607 ///
608 /// constrainRegClass(ToReg, getRegClass(FromReg))
609 /// constrainRegAttrs(ToReg, FromReg)
610 /// RegisterBankInfo::constrainGenericRegister(ToReg,
611 /// *MRI.getRegClass(FromReg), MRI)
612 ///
613 /// These functions will return a falsy result if the virtual registers have
614 /// incompatible constraints.
615 ///
616 /// Note that if ToReg is a physical register the function will replace and
617 /// apply sub registers to ToReg in order to obtain a final/proper physical
618 /// register.
619 void replaceRegWith(Register FromReg, Register ToReg);
620
621 /// getVRegDef - Return the machine instr that defines the specified virtual
622 /// register or null if none is found. This assumes that the code is in SSA
623 /// form, so there should only be one definition.
625
626 /// getUniqueVRegDef - Return the unique machine instr that defines the
627 /// specified virtual register or null if none is found. If there are
628 /// multiple definitions or no definition, return null.
630
631 /// clearKillFlags - Iterate over all the uses of the given register and
632 /// clear the kill flag from the MachineOperand. This function is used by
633 /// optimization passes which extend register lifetimes and need only
634 /// preserve conservative kill flag information.
635 void clearKillFlags(Register Reg) const;
636
637 void dumpUses(Register RegNo) const;
638
639 /// Returns true if PhysReg is unallocatable and constant throughout the
640 /// function. Writing to a constant register has no effect.
641 bool isConstantPhysReg(MCRegister PhysReg) const;
642
643 /// Get an iterator over the pressure sets affected by the given physical or
644 /// virtual register. If RegUnit is physical, it must be a register unit (from
645 /// MCRegUnitIterator).
647
648 //===--------------------------------------------------------------------===//
649 // Virtual Register Info
650 //===--------------------------------------------------------------------===//
651
652 /// Return the register class of the specified virtual register.
653 /// This shouldn't be used directly unless \p Reg has a register class.
654 /// \see getRegClassOrNull when this might happen.
656 assert(isa<const TargetRegisterClass *>(VRegInfo[Reg.id()].first) &&
657 "Register class not set, wrong accessor");
658 return cast<const TargetRegisterClass *>(VRegInfo[Reg.id()].first);
659 }
660
661 /// Return the register class of \p Reg, or null if Reg has not been assigned
662 /// a register class yet.
663 ///
664 /// \note A null register class can only happen when these two
665 /// conditions are met:
666 /// 1. Generic virtual registers are created.
667 /// 2. The machine function has not completely been through the
668 /// instruction selection process.
669 /// None of this condition is possible without GlobalISel for now.
670 /// In other words, if GlobalISel is not used or if the query happens after
671 /// the select pass, using getRegClass is safe.
673 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
674 return dyn_cast_if_present<const TargetRegisterClass *>(Val);
675 }
676
677 /// Return the register bank of \p Reg.
678 /// This shouldn't be used directly unless \p Reg has a register bank.
680 return cast<const RegisterBank *>(VRegInfo[Reg.id()].first);
681 }
682
683 /// Return the register bank of \p Reg, or null if Reg has not been assigned
684 /// a register bank or has been assigned a register class.
685 /// \note It is possible to get the register bank from the register class via
686 /// RegisterBankInfo::getRegBankFromRegClass.
688 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
689 return dyn_cast_if_present<const RegisterBank *>(Val);
690 }
691
692 /// Return the register bank or register class of \p Reg.
693 /// \note Before the register bank gets assigned (i.e., before the
694 /// RegBankSelect pass) \p Reg may not have either.
696 return VRegInfo[Reg].first;
697 }
698
699 /// setRegClass - Set the register class of the specified virtual register.
701
702 /// Set the register bank to \p RegBank for \p Reg.
703 void setRegBank(Register Reg, const RegisterBank &RegBank);
704
706 const RegClassOrRegBank &RCOrRB){
707 VRegInfo[Reg].first = RCOrRB;
708 }
709
710 /// constrainRegClass - Constrain the register class of the specified virtual
711 /// register to be a common subclass of RC and the current register class,
712 /// but only if the new class has at least MinNumRegs registers. Return the
713 /// new register class, or NULL if no such class exists.
714 /// This should only be used when the constraint is known to be trivial, like
715 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
716 ///
717 /// \note Assumes that the register has a register class assigned.
718 /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
719 /// InstructionSelect pass and constrainRegAttrs in every other pass,
720 /// including non-select passes of GlobalISel, instead.
722 const TargetRegisterClass *RC,
723 unsigned MinNumRegs = 0);
724
725 /// Constrain the register class or the register bank of the virtual register
726 /// \p Reg (and low-level type) to be a common subclass or a common bank of
727 /// both registers provided respectively (and a common low-level type). Do
728 /// nothing if any of the attributes (classes, banks, or low-level types) of
729 /// the registers are deemed incompatible, or if the resulting register will
730 /// have a class smaller than before and of size less than \p MinNumRegs.
731 /// Return true if such register attributes exist, false otherwise.
732 ///
733 /// \note Use this method instead of constrainRegClass and
734 /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
735 /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
736 bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
737 unsigned MinNumRegs = 0);
738
739 /// recomputeRegClass - Try to find a legal super-class of Reg's register
740 /// class that still satisfies the constraints from the instructions using
741 /// Reg. Returns true if Reg was upgraded.
742 ///
743 /// This method can be used after constraints have been removed from a
744 /// virtual register, for example after removing instructions or splitting
745 /// the live range.
747
748 /// createVirtualRegister - Create and return a new virtual register in the
749 /// function with the specified register class.
751 StringRef Name = "");
752
753 /// All attributes(register class or bank and low-level type) a virtual
754 /// register can have.
755 struct VRegAttrs {
758 };
759
760 /// Returns register class or bank and low level type of \p Reg. Always safe
761 /// to use. Special values are returned when \p Reg does not have some of the
762 /// attributes.
765 }
766
767 /// Create and return a new virtual register in the function with the
768 /// specified register attributes(register class or bank and low level type).
769 Register createVirtualRegister(VRegAttrs RegAttr, StringRef Name = "");
770
771 /// Create and return a new virtual register in the function with the same
772 /// attributes as the given register.
774
775 /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
776 /// (target independent) virtual register.
778 if (Reg.isVirtual() && VRegToType.inBounds(Reg))
779 return VRegToType[Reg];
780 return LLT{};
781 }
782
783 /// Set the low-level type of \p VReg to \p Ty.
784 void setType(Register VReg, LLT Ty);
785
786 /// Create and return a new generic virtual register with low-level
787 /// type \p Ty.
789
790 /// Remove all types associated to virtual registers (after instruction
791 /// selection and constraining of all generic virtual registers).
792 void clearVirtRegTypes();
793
794 /// Creates a new virtual register that has no register class, register bank
795 /// or size assigned yet. This is only allowed to be used
796 /// temporarily while constructing machine instructions. Most operations are
797 /// undefined on an incomplete register until one of setRegClass(),
798 /// setRegBank() or setSize() has been called on it.
800
801 /// getNumVirtRegs - Return the number of virtual registers created.
802 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
803
804 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
805 void clearVirtRegs();
806
807 /// setRegAllocationHint - Specify a register allocation hint for the
808 /// specified virtual register. This is typically used by target, and in case
809 /// of an earlier hint it will be overwritten.
810 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
811 assert(VReg.isVirtual());
813 RegAllocHints[VReg].first = Type;
814 RegAllocHints[VReg].second.clear();
815 RegAllocHints[VReg].second.push_back(PrefReg);
816 }
817
818 /// addRegAllocationHint - Add a register allocation hint to the hints
819 /// vector for VReg.
821 assert(VReg.isVirtual());
823 RegAllocHints[VReg].second.push_back(PrefReg);
824 }
825
826 /// Specify the preferred (target independent) register allocation hint for
827 /// the specified virtual register.
828 void setSimpleHint(Register VReg, Register PrefReg) {
829 setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
830 }
831
833 assert (!RegAllocHints[VReg].first &&
834 "Expected to clear a non-target hint!");
835 if (RegAllocHints.inBounds(VReg))
836 RegAllocHints[VReg].second.clear();
837 }
838
839 /// getRegAllocationHint - Return the register allocation hint for the
840 /// specified virtual register. If there are many hints, this returns the
841 /// one with the greatest weight.
842 std::pair<unsigned, Register> getRegAllocationHint(Register VReg) const {
843 assert(VReg.isVirtual());
844 if (!RegAllocHints.inBounds(VReg))
845 return {0, Register()};
846 Register BestHint = (RegAllocHints[VReg.id()].second.size() ?
847 RegAllocHints[VReg.id()].second[0] : Register());
848 return {RegAllocHints[VReg.id()].first, BestHint};
849 }
850
851 /// getSimpleHint - same as getRegAllocationHint except it will only return
852 /// a target independent hint.
854 assert(VReg.isVirtual());
855 std::pair<unsigned, Register> Hint = getRegAllocationHint(VReg);
856 return Hint.first ? Register() : Hint.second;
857 }
858
859 /// getRegAllocationHints - Return a reference to the vector of all
860 /// register allocation hints for VReg.
861 const std::pair<unsigned, SmallVector<Register, 4>> *
863 assert(VReg.isVirtual());
864 return RegAllocHints.inBounds(VReg) ? &RegAllocHints[VReg] : nullptr;
865 }
866
867 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
868 /// specified register as undefined which causes the DBG_VALUE to be
869 /// deleted during LiveDebugVariables analysis.
871
872 /// updateDbgUsersToReg - Update a collection of debug instructions
873 /// to refer to the designated register.
876 // If this operand is a register, check whether it overlaps with OldReg.
877 // If it does, replace with NewReg.
878 auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) {
879 if (Op.isReg() &&
880 getTargetRegisterInfo()->regsOverlap(Op.getReg(), OldReg))
881 Op.setReg(NewReg);
882 };
883
884 // Iterate through (possibly several) operands to DBG_VALUEs and update
885 // each. For DBG_PHIs, only one operand will be present.
886 for (MachineInstr *MI : Users) {
887 if (MI->isDebugValue()) {
888 for (auto &Op : MI->debug_operands())
889 UpdateOp(Op);
890 assert(MI->hasDebugOperandForReg(NewReg) &&
891 "Expected debug value to have some overlap with OldReg");
892 } else if (MI->isDebugPHI()) {
893 UpdateOp(MI->getOperand(0));
894 } else {
895 llvm_unreachable("Non-DBG_VALUE, Non-DBG_PHI debug instr updated");
896 }
897 }
898 }
899
900 /// Return true if the specified register is modified in this function.
901 /// This checks that no defining machine operands exist for the register or
902 /// any of its aliases. Definitions found on functions marked noreturn are
903 /// ignored, to consider them pass 'true' for optional parameter
904 /// SkipNoReturnDef. The register is also considered modified when it is set
905 /// in the UsedPhysRegMask.
906 bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const;
907
908 /// Return true if the specified register is modified or read in this
909 /// function. This checks that no machine operands exist for the register or
910 /// any of its aliases. If SkipRegMaskTest is false, the register is
911 /// considered used when it is set in the UsedPhysRegMask.
912 bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest = false) const;
913
914 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
915 /// This corresponds to the bit mask attached to register mask operands.
917 UsedPhysRegMask.setBitsNotInMask(RegMask);
918 }
919
920 const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
921
922 //===--------------------------------------------------------------------===//
923 // Reserved Register Info
924 //===--------------------------------------------------------------------===//
925 //
926 // The set of reserved registers must be invariant during register
927 // allocation. For example, the target cannot suddenly decide it needs a
928 // frame pointer when the register allocator has already used the frame
929 // pointer register for something else.
930 //
931 // These methods can be used by target hooks like hasFP() to avoid changing
932 // the reserved register set during register allocation.
933
934 /// freezeReservedRegs - Called by the register allocator to freeze the set
935 /// of reserved registers before allocation begins.
936 void freezeReservedRegs();
937
938 /// reserveReg -- Mark a register as reserved so checks like isAllocatable
939 /// will not suggest using it. This should not be used during the middle
940 /// of a function walk, or when liveness info is available.
943 "Reserved registers haven't been frozen yet. ");
944 MCRegAliasIterator R(PhysReg, TRI, true);
945
946 for (; R.isValid(); ++R)
947 ReservedRegs.set((*R).id());
948 }
949
950 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
951 /// to ensure the set of reserved registers stays constant.
952 bool reservedRegsFrozen() const {
953 return !ReservedRegs.empty();
954 }
955
956 /// canReserveReg - Returns true if PhysReg can be used as a reserved
957 /// register. Any register can be reserved before freezeReservedRegs() is
958 /// called.
959 bool canReserveReg(MCRegister PhysReg) const {
960 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg.id());
961 }
962
963 /// getReservedRegs - Returns a reference to the frozen set of reserved
964 /// registers. This method should always be preferred to calling
965 /// TRI::getReservedRegs() when possible.
966 const BitVector &getReservedRegs() const {
968 "Reserved registers haven't been frozen yet. "
969 "Use TRI::getReservedRegs().");
970 return ReservedRegs;
971 }
972
973 /// isReserved - Returns true when PhysReg is a reserved register.
974 ///
975 /// Reserved registers may belong to an allocatable register class, but the
976 /// target has explicitly requested that they are not used.
977 bool isReserved(MCRegister PhysReg) const {
978 return getReservedRegs().test(PhysReg.id());
979 }
980
981 /// Returns true when the given register unit is considered reserved.
982 ///
983 /// Register units are considered reserved when for at least one of their
984 /// root registers, the root register and all super registers are reserved.
985 /// This currently iterates the register hierarchy and may be slower than
986 /// expected.
987 bool isReservedRegUnit(unsigned Unit) const;
988
989 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
990 /// register class and it hasn't been reserved.
991 ///
992 /// Allocatable registers may show up in the allocation order of some virtual
993 /// register, so a register allocator needs to track its liveness and
994 /// availability.
995 bool isAllocatable(MCRegister PhysReg) const {
996 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
997 !isReserved(PhysReg);
998 }
999
1000 //===--------------------------------------------------------------------===//
1001 // LiveIn Management
1002 //===--------------------------------------------------------------------===//
1003
1004 /// addLiveIn - Add the specified register as a live-in. Note that it
1005 /// is an error to add the same register to the same set more than once.
1007 LiveIns.push_back(std::make_pair(Reg, vreg));
1008 }
1009
1010 // Iteration support for the live-ins set. It's kept in sorted order
1011 // by register number.
1013 std::vector<std::pair<MCRegister,Register>>::const_iterator;
1014 livein_iterator livein_begin() const { return LiveIns.begin(); }
1015 livein_iterator livein_end() const { return LiveIns.end(); }
1016 bool livein_empty() const { return LiveIns.empty(); }
1017
1019 return LiveIns;
1020 }
1021
1022 bool isLiveIn(Register Reg) const;
1023
1024 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
1025 /// corresponding live-in physical register.
1027
1028 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
1029 /// corresponding live-in virtual register.
1031
1032 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
1033 /// into the given entry block.
1034 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
1035 const TargetRegisterInfo &TRI,
1036 const TargetInstrInfo &TII);
1037
1038 /// Returns a mask covering all bits that can appear in lane masks of
1039 /// subregisters of the virtual register @p Reg.
1041
1042 /// defusechain_iterator - This class provides iterator support for machine
1043 /// operands in the function that use or define a specific register. If
1044 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1045 /// returns defs. If neither are true then you are silly and it always
1046 /// returns end(). If SkipDebug is true it skips uses marked Debug
1047 /// when incrementing.
1048 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1049 bool ByInstr, bool ByBundle>
1052
1053 public:
1054 using iterator_category = std::forward_iterator_tag;
1056 using difference_type = std::ptrdiff_t;
1059
1060 private:
1061 MachineOperand *Op = nullptr;
1062
1064 // If the first node isn't one we're interested in, advance to one that
1065 // we are interested in.
1066 if (op) {
1067 if ((!ReturnUses && op->isUse()) ||
1068 (!ReturnDefs && op->isDef()) ||
1069 (SkipDebug && op->isDebug()))
1070 advance();
1071 }
1072 }
1073
1074 void advance() {
1075 assert(Op && "Cannot increment end iterator!");
1076 Op = getNextOperandForReg(Op);
1077
1078 // All defs come before the uses, so stop def_iterator early.
1079 if (!ReturnUses) {
1080 if (Op) {
1081 if (Op->isUse())
1082 Op = nullptr;
1083 else
1084 assert(!Op->isDebug() && "Can't have debug defs");
1085 }
1086 } else {
1087 // If this is an operand we don't care about, skip it.
1088 while (Op && ((!ReturnDefs && Op->isDef()) ||
1089 (SkipDebug && Op->isDebug())))
1090 Op = getNextOperandForReg(Op);
1091 }
1092 }
1093
1094 public:
1096
1097 bool operator==(const defusechain_iterator &x) const {
1098 return Op == x.Op;
1099 }
1100 bool operator!=(const defusechain_iterator &x) const {
1101 return !operator==(x);
1102 }
1103
1104 // Iterator traversal: forward iteration only
1106 assert(Op && "Cannot increment end iterator!");
1107 if (ByOperand)
1108 advance();
1109 else if (ByInstr) {
1110 MachineInstr *P = Op->getParent();
1111 do {
1112 advance();
1113 } while (Op && Op->getParent() == P);
1114 } else if (ByBundle) {
1116 getBundleStart(Op->getParent()->getIterator());
1117 do {
1118 advance();
1119 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1120 }
1121
1122 return *this;
1123 }
1124 defusechain_iterator operator++(int) { // Postincrement
1125 defusechain_iterator tmp = *this; ++*this; return tmp;
1126 }
1127
1128 /// getOperandNo - Return the operand # of this MachineOperand in its
1129 /// MachineInstr.
1130 unsigned getOperandNo() const {
1131 assert(Op && "Cannot dereference end iterator!");
1132 return Op - &Op->getParent()->getOperand(0);
1133 }
1134
1135 // Retrieve a reference to the current operand.
1137 assert(Op && "Cannot dereference end iterator!");
1138 return *Op;
1139 }
1140
1142 assert(Op && "Cannot dereference end iterator!");
1143 return Op;
1144 }
1145 };
1146
1147 /// defusechain_iterator - This class provides iterator support for machine
1148 /// operands in the function that use or define a specific register. If
1149 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1150 /// returns defs. If neither are true then you are silly and it always
1151 /// returns end(). If SkipDebug is true it skips uses marked Debug
1152 /// when incrementing.
1153 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1154 bool ByInstr, bool ByBundle>
1157
1158 public:
1159 using iterator_category = std::forward_iterator_tag;
1161 using difference_type = std::ptrdiff_t;
1164
1165 private:
1166 MachineOperand *Op = nullptr;
1167
1169 // If the first node isn't one we're interested in, advance to one that
1170 // we are interested in.
1171 if (op) {
1172 if ((!ReturnUses && op->isUse()) ||
1173 (!ReturnDefs && op->isDef()) ||
1174 (SkipDebug && op->isDebug()))
1175 advance();
1176 }
1177 }
1178
1179 void advance() {
1180 assert(Op && "Cannot increment end iterator!");
1181 Op = getNextOperandForReg(Op);
1182
1183 // All defs come before the uses, so stop def_iterator early.
1184 if (!ReturnUses) {
1185 if (Op) {
1186 if (Op->isUse())
1187 Op = nullptr;
1188 else
1189 assert(!Op->isDebug() && "Can't have debug defs");
1190 }
1191 } else {
1192 // If this is an operand we don't care about, skip it.
1193 while (Op && ((!ReturnDefs && Op->isDef()) ||
1194 (SkipDebug && Op->isDebug())))
1195 Op = getNextOperandForReg(Op);
1196 }
1197 }
1198
1199 public:
1201
1203 return Op == x.Op;
1204 }
1206 return !operator==(x);
1207 }
1208
1209 // Iterator traversal: forward iteration only
1211 assert(Op && "Cannot increment end iterator!");
1212 if (ByOperand)
1213 advance();
1214 else if (ByInstr) {
1215 MachineInstr *P = Op->getParent();
1216 do {
1217 advance();
1218 } while (Op && Op->getParent() == P);
1219 } else if (ByBundle) {
1221 getBundleStart(Op->getParent()->getIterator());
1222 do {
1223 advance();
1224 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1225 }
1226
1227 return *this;
1228 }
1230 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1231 }
1232
1233 // Retrieve a reference to the current operand.
1235 assert(Op && "Cannot dereference end iterator!");
1236 if (ByBundle)
1237 return *getBundleStart(Op->getParent()->getIterator());
1238 return *Op->getParent();
1239 }
1240
1241 MachineInstr *operator->() const { return &operator*(); }
1242 };
1243};
1244
1245/// Iterate over the pressure sets affected by the given physical or virtual
1246/// register. If Reg is physical, it must be a register unit (from
1247/// MCRegUnitIterator).
1249 const int *PSet = nullptr;
1250 unsigned Weight = 0;
1251
1252public:
1253 PSetIterator() = default;
1254
1256 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1257 if (RegUnit.isVirtual()) {
1258 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1259 PSet = TRI->getRegClassPressureSets(RC);
1260 Weight = TRI->getRegClassWeight(RC).RegWeight;
1261 } else {
1262 PSet = TRI->getRegUnitPressureSets(RegUnit);
1263 Weight = TRI->getRegUnitWeight(RegUnit);
1264 }
1265 if (*PSet == -1)
1266 PSet = nullptr;
1267 }
1268
1269 bool isValid() const { return PSet; }
1270
1271 unsigned getWeight() const { return Weight; }
1272
1273 unsigned operator*() const { return *PSet; }
1274
1275 void operator++() {
1276 assert(isValid() && "Invalid PSetIterator.");
1277 ++PSet;
1278 if (*PSet == -1)
1279 PSet = nullptr;
1280 }
1281};
1282
1283inline PSetIterator
1285 return PSetIterator(RegUnit, this);
1286}
1287
1288} // end namespace llvm
1289
1290#endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
unsigned const MachineRegisterInfo * MRI
This file implements the BitVector class.
#define LLVM_LIKELY(EXPR)
Definition: Compiler.h:319
std::string Name
#define op(i)
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
iv Induction Variable Users
Definition: IVUsers.cpp:48
This file implements an indexed map.
A common definition of LaneBitmask for use in TableGen and CodeGen.
unsigned const TargetRegisterInfo * TRI
unsigned Reg
#define P(N)
This file defines the PointerUnion class, which is a discriminated union of pointer types.
Remove Loads Into Fake Uses
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
StringSet - A set-like wrapper for the StringMap.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool test(unsigned Idx) const
Definition: BitVector.h:461
This class represents an Operation in the Expression.
StorageT::size_type size() const
Definition: IndexedMap.h:79
void grow(IndexT n)
Definition: IndexedMap.h:69
bool inBounds(IndexT n) const
Definition: IndexedMap.h:75
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
constexpr unsigned id() const
Definition: MCRegister.h:83
Instructions::iterator instr_iterator
bool hasProperty(Property P) const
MachineFunctionProperties & reset(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineFunctionProperties & getProperties() const
Get the function properties.
Representation of each machine instruction.
Definition: MachineInstr.h:71
MachineOperand class - Representation of each machine instruction operand.
virtual void MRI_NoteNewVirtualRegister(Register Reg)=0
virtual void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg)
defusechain_iterator - This class provides iterator support for machine operands in the function that...
bool operator==(const defusechain_instr_iterator &x) const
bool operator!=(const defusechain_instr_iterator &x) const
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool operator==(const defusechain_iterator &x) const
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
bool operator!=(const defusechain_iterator &x) const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
defusechain_instr_iterator< false, true, false, false, false, true > def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register,...
void verifyUseList(Register Reg) const
Verify the sanity of the use list for Reg.
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Register getSimpleHint(Register VReg) const
getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint.
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
defusechain_instr_iterator< true, true, true, false, false, true > reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...
reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const
void insertVRegByName(StringRef Name, Register Reg)
iterator_range< reg_bundle_iterator > reg_bundles(Register Reg) const
void verifyUseLists() const
Verify the use list of all registers.
VRegAttrs getVRegAttrs(Register Reg) const
Returns register class or bank and low level type of Reg.
static reg_iterator reg_end()
defusechain_instr_iterator< false, true, false, false, true, false > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register,...
void markUsesInDebugValueAsUndef(Register Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
const BitVector & getUsedPhysRegsMask() const
iterator_range< reg_iterator > reg_operands(Register Reg) const
bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
reg_instr_iterator reg_instr_begin(Register RegNo) const
MachineRegisterInfo & operator=(const MachineRegisterInfo &)=delete
bool isUpdatedCSRsInitialized() const
Returns true if the updated CSR list was initialized and false otherwise.
void freezeReservedRegs()
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
static use_nodbg_iterator use_nodbg_end()
defusechain_instr_iterator< true, true, true, false, true, false > reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MachineRegisterInfo(MachineFunction *MF)
reg_iterator reg_begin(Register RegNo) const
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
bool shouldTrackSubRegLiveness(Register VReg) const
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.
static reg_instr_iterator reg_instr_end()
use_instr_iterator use_instr_begin(Register RegNo) const
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const
Return the register bank or register class of Reg.
iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(Register Reg) const
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
const RegisterBank * getRegBank(Register Reg) const
Return the register bank of Reg.
static def_instr_iterator def_instr_end()
void dumpUses(Register RegNo) const
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
MachineOperand * getOneDef(Register Reg) const
Returns the defining operand if there is exactly one operand defining the specified register,...
def_iterator def_begin(Register RegNo) const
static def_bundle_iterator def_bundle_end()
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(Register Reg) const
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
defusechain_iterator< false, true, false, true, false, false > def_iterator
def_iterator/def_begin/def_end - Walk all defs of the specified register.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
def_instr_iterator def_instr_begin(Register RegNo) const
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
bool hasOneUse(Register RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
void resetDelegate(Delegate *delegate)
bool isLiveIn(Register Reg) const
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
defusechain_iterator< true, false, false, true, false, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
static use_bundle_iterator use_bundle_end()
defusechain_instr_iterator< true, false, false, false, false, true > use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register,...
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
static reg_nodbg_iterator reg_nodbg_end()
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
ArrayRef< std::pair< MCRegister, Register > > liveins() const
use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const
defusechain_instr_iterator< true, false, true, false, false, true > use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...
defusechain_instr_iterator< true, true, false, false, false, true > reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...
bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const
hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions.
static use_instr_iterator use_instr_end()
bool hasOneNonDBGUser(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
std::vector< std::pair< MCRegister, Register > >::const_iterator livein_iterator
Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level.
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
void setRegBank(Register Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
MCRegister getLiveInPhysReg(Register VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
std::pair< unsigned, Register > getRegAllocationHint(Register VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register.
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
iterator_range< def_iterator > def_operands(Register Reg) const
void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register.
void addDelegate(Delegate *delegate)
const MachineFunction & getMF() const
bool hasOneDef(Register RegNo) const
Return true if there is exactly one operand defining the specified register.
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
defusechain_iterator< true, true, false, true, false, false > reg_iterator
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
defusechain_iterator< true, true, true, true, false, false > reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register,...
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
void setSimpleHint(Register VReg, Register PrefReg)
Specify the preferred (target independent) register allocation hint for the specified virtual registe...
static def_iterator def_end()
void disableCalleeSavedRegister(MCRegister Reg)
Disables the register from the list of CSRs.
use_bundle_iterator use_bundle_begin(Register RegNo) const
livein_iterator livein_end() const
reg_bundle_iterator reg_bundle_begin(Register RegNo) const
iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const
void noteNewVirtualRegister(Register Reg)
static use_bundle_nodbg_iterator use_bundle_nodbg_end()
const std::pair< unsigned, SmallVector< Register, 4 > > * getRegAllocationHints(Register VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.
void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)
Sets the updated Callee Saved Registers list.
defusechain_instr_iterator< true, false, false, false, true, false > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register,...
static reg_bundle_iterator reg_bundle_end()
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register,...
void reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI)
reserveReg – Mark a register as reserved so checks like isAllocatable will not suggest using it.
const TargetRegisterInfo * getTargetRegisterInfo() const
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
use_iterator use_begin(Register RegNo) const
void addRegAllocationHint(Register VReg, Register PrefReg)
addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
MachineRegisterInfo(const MachineRegisterInfo &)=delete
defusechain_instr_iterator< true, false, true, false, true, false > use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...
static use_iterator use_end()
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
PSetIterator getPressureSets(Register RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)
Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...
iterator_range< def_bundle_iterator > def_bundles(Register Reg) const
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
void clearSimpleHint(Register VReg)
bool isReservedRegUnit(unsigned Unit) const
Returns true when the given register unit is considered reserved.
void noteCloneVirtualRegister(Register NewReg, Register SrcReg)
iterator_range< use_iterator > use_operands(Register Reg) const
livein_iterator livein_begin() const
reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(Register Reg) const
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
bool reg_empty(Register RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
StringRef getVRegName(Register Reg) const
defusechain_instr_iterator< true, true, false, false, true, false > reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register,...
iterator_range< use_bundle_iterator > use_bundles(Register Reg) const
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, ArrayRef< MachineInstr * > Users) const
updateDbgUsersToReg - Update a collection of debug instructions to refer to the designated register.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
def_bundle_iterator def_bundle_begin(Register RegNo) const
static use_instr_nodbg_iterator use_instr_nodbg_end()
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
Iterate over the pressure sets affected by the given physical or virtual register.
unsigned operator*() const
PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI)
unsigned getWeight() const
PSetIterator()=default
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
constexpr unsigned id() const
Definition: Register.h:103
bool erase(PtrType Ptr)
Remove pointer from the set.
Definition: SmallPtrSet.h:401
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:452
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:384
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:519
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1196
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
StringSet - A wrapper for StringMap that provides set-like functionality.
Definition: StringSet.h:23
bool contains(StringRef key) const
Check if the set contains the given key.
Definition: StringSet.h:55
std::pair< typename Base::iterator, bool > insert(StringRef key)
Definition: StringSet.h:38
TargetInstrInfo - Interface to description of machine instruction set.
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
A range adaptor for a pair of iterators.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)
Returns an iterator to the first instruction in the bundle containing I.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
Definition: STLExtras.h:322
DWARFExpression::Operation Op
All attributes(register class or bank and low-level type) a virtual register can have.