LLVM 18.0.0git
RegisterBank.h
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1//==-- llvm/CodeGen/RegisterBank.h - Register Bank ---------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file declares the API of register banks.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_REGISTERBANK_H
14#define LLVM_CODEGEN_REGISTERBANK_H
15
16#include "llvm/ADT/BitVector.h"
17
18namespace llvm {
19// Forward declarations.
20class RegisterBankInfo;
21class raw_ostream;
22class TargetRegisterClass;
23class TargetRegisterInfo;
24
25/// This class implements the register bank concept.
26/// Two instances of RegisterBank must have different ID.
27/// This property is enforced by the RegisterBankInfo class.
29private:
30 unsigned ID;
31 const char *Name;
32 BitVector ContainedRegClasses;
33
34 /// Sentinel value used to recognize register bank not properly
35 /// initialized yet.
36 static const unsigned InvalidID;
37
38 /// Only the RegisterBankInfo can initialize RegisterBank properly.
39 friend RegisterBankInfo;
40
41public:
42 RegisterBank(unsigned ID, const char *Name, const uint32_t *CoveredClasses,
43 unsigned NumRegClasses);
44
45 /// Get the identifier of this register bank.
46 unsigned getID() const { return ID; }
47
48 /// Get a user friendly name of this register bank.
49 /// Should be used only for debugging purposes.
50 const char *getName() const { return Name; }
51
52 /// Check whether this instance is ready to be used.
53 bool isValid() const;
54
55 /// Check if this register bank is valid. In other words,
56 /// if it has been properly constructed.
57 ///
58 /// \note This method does not check anything when assertions are disabled.
59 ///
60 /// \return True is the check was successful.
61 bool verify(const RegisterBankInfo &RBI, const TargetRegisterInfo &TRI) const;
62
63 /// Check whether this register bank covers \p RC.
64 /// In other words, check if this register bank fully covers
65 /// the registers that \p RC contains.
66 /// \pre isValid()
67 bool covers(const TargetRegisterClass &RC) const;
68
69 /// Check whether \p OtherRB is the same as this.
70 bool operator==(const RegisterBank &OtherRB) const;
71 bool operator!=(const RegisterBank &OtherRB) const {
72 return !this->operator==(OtherRB);
73 }
74
75 /// Dump the register mask on dbgs() stream.
76 /// The dump is verbose.
77 void dump(const TargetRegisterInfo *TRI = nullptr) const;
78
79 /// Print the register mask on OS.
80 /// If IsForDebug is false, then only the name of the register bank
81 /// is printed. Otherwise, all the fields are printing.
82 /// TRI is then used to print the name of the register classes that
83 /// this register bank covers.
84 void print(raw_ostream &OS, bool IsForDebug = false,
85 const TargetRegisterInfo *TRI = nullptr) const;
86};
87
89 RegBank.print(OS);
90 return OS;
91}
92} // End namespace llvm.
93
94#endif
This file implements the BitVector class.
unsigned const TargetRegisterInfo * TRI
ppc ctr loops verify
raw_pwrite_stream & OS
Holds all the information related to register banks.
This class implements the register bank concept.
Definition: RegisterBank.h:28
void print(raw_ostream &OS, bool IsForDebug=false, const TargetRegisterInfo *TRI=nullptr) const
Print the register mask on OS.
bool isValid() const
Check whether this instance is ready to be used.
void dump(const TargetRegisterInfo *TRI=nullptr) const
Dump the register mask on dbgs() stream.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:50
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:46
bool operator!=(const RegisterBank &OtherRB) const
Definition: RegisterBank.h:71
bool operator==(const RegisterBank &OtherRB) const
Check whether OtherRB is the same as this.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:292