LLVM  15.0.0git
MachineOperand.h
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1 //===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineOperand class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_MACHINEOPERAND_H
14 #define LLVM_CODEGEN_MACHINEOPERAND_H
15 
16 #include "llvm/ADT/DenseMapInfo.h"
17 #include "llvm/CodeGen/Register.h"
18 #include "llvm/IR/Intrinsics.h"
19 #include <cassert>
20 
21 namespace llvm {
22 
23 class LLT;
24 class BlockAddress;
25 class Constant;
26 class ConstantFP;
27 class ConstantInt;
28 class GlobalValue;
29 class MachineBasicBlock;
30 class MachineInstr;
31 class MachineRegisterInfo;
32 class MCCFIInstruction;
33 class MDNode;
34 class ModuleSlotTracker;
35 class TargetIntrinsicInfo;
36 class TargetRegisterInfo;
37 class hash_code;
38 class raw_ostream;
39 class MCSymbol;
40 
41 /// MachineOperand class - Representation of each machine instruction operand.
42 ///
43 /// This class isn't a POD type because it has a private constructor, but its
44 /// destructor must be trivial. Functions like MachineInstr::addOperand(),
45 /// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
46 /// not having to call the MachineOperand destructor.
47 ///
49 public:
50  enum MachineOperandType : unsigned char {
51  MO_Register, ///< Register operand.
52  MO_Immediate, ///< Immediate operand
53  MO_CImmediate, ///< Immediate >64bit operand
54  MO_FPImmediate, ///< Floating-point immediate operand
55  MO_MachineBasicBlock, ///< MachineBasicBlock reference
56  MO_FrameIndex, ///< Abstract Stack Frame Index
57  MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
58  MO_TargetIndex, ///< Target-dependent index+offset operand.
59  MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
60  MO_ExternalSymbol, ///< Name of external global symbol
61  MO_GlobalAddress, ///< Address of a global value
62  MO_BlockAddress, ///< Address of a basic block
63  MO_RegisterMask, ///< Mask of preserved registers.
64  MO_RegisterLiveOut, ///< Mask of live-out registers.
65  MO_Metadata, ///< Metadata reference (for debug info)
66  MO_MCSymbol, ///< MCSymbol reference (for debug/eh info)
67  MO_CFIIndex, ///< MCCFIInstruction index.
68  MO_IntrinsicID, ///< Intrinsic ID for ISel
69  MO_Predicate, ///< Generic predicate for ISel
70  MO_ShuffleMask, ///< Other IR Constant for ISel (shuffle masks)
72  };
73 
74 private:
75  /// OpKind - Specify what kind of operand this is. This discriminates the
76  /// union.
77  unsigned OpKind : 8;
78 
79  /// Subregister number for MO_Register. A value of 0 indicates the
80  /// MO_Register has no subReg.
81  ///
82  /// For all other kinds of operands, this field holds target-specific flags.
83  unsigned SubReg_TargetFlags : 12;
84 
85  /// TiedTo - Non-zero when this register operand is tied to another register
86  /// operand. The encoding of this field is described in the block comment
87  /// before MachineInstr::tieOperands().
88  unsigned TiedTo : 4;
89 
90  /// IsDef - True if this is a def, false if this is a use of the register.
91  /// This is only valid on register operands.
92  ///
93  unsigned IsDef : 1;
94 
95  /// IsImp - True if this is an implicit def or use, false if it is explicit.
96  /// This is only valid on register opderands.
97  ///
98  unsigned IsImp : 1;
99 
100  /// IsDeadOrKill
101  /// For uses: IsKill - Conservatively indicates the last use of a register
102  /// on this path through the function. A register operand with true value of
103  /// this flag must be the last use of the register, a register operand with
104  /// false value may or may not be the last use of the register. After regalloc
105  /// we can use recomputeLivenessFlags to get precise kill flags.
106  /// For defs: IsDead - True if this register is never used by a subsequent
107  /// instruction.
108  /// This is only valid on register operands.
109  unsigned IsDeadOrKill : 1;
110 
111  /// See isRenamable().
112  unsigned IsRenamable : 1;
113 
114  /// IsUndef - True if this register operand reads an "undef" value, i.e. the
115  /// read value doesn't matter. This flag can be set on both use and def
116  /// operands. On a sub-register def operand, it refers to the part of the
117  /// register that isn't written. On a full-register def operand, it is a
118  /// noop. See readsReg().
119  ///
120  /// This is only valid on registers.
121  ///
122  /// Note that an instruction may have multiple <undef> operands referring to
123  /// the same register. In that case, the instruction may depend on those
124  /// operands reading the same dont-care value. For example:
125  ///
126  /// %1 = XOR undef %2, undef %2
127  ///
128  /// Any register can be used for %2, and its value doesn't matter, but
129  /// the two operands must be the same register.
130  ///
131  unsigned IsUndef : 1;
132 
133  /// IsInternalRead - True if this operand reads a value that was defined
134  /// inside the same instruction or bundle. This flag can be set on both use
135  /// and def operands. On a sub-register def operand, it refers to the part
136  /// of the register that isn't written. On a full-register def operand, it
137  /// is a noop.
138  ///
139  /// When this flag is set, the instruction bundle must contain at least one
140  /// other def of the register. If multiple instructions in the bundle define
141  /// the register, the meaning is target-defined.
142  unsigned IsInternalRead : 1;
143 
144  /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
145  /// by the MachineInstr before all input registers are read. This is used to
146  /// model the GCC inline asm '&' constraint modifier.
147  unsigned IsEarlyClobber : 1;
148 
149  /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
150  /// not a real instruction. Such uses should be ignored during codegen.
151  unsigned IsDebug : 1;
152 
153  /// SmallContents - This really should be part of the Contents union, but
154  /// lives out here so we can get a better packed struct.
155  /// MO_Register: Register number.
156  /// OffsetedInfo: Low bits of offset.
157  union {
158  unsigned RegNo; // For MO_Register.
159  unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi.
160  } SmallContents;
161 
162  /// ParentMI - This is the instruction that this operand is embedded into.
163  /// This is valid for all operand types, when the operand is in an instr.
164  MachineInstr *ParentMI = nullptr;
165 
166  /// Contents union - This contains the payload for the various operand types.
167  union ContentsUnion {
168  ContentsUnion() {}
169  MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
170  const ConstantFP *CFP; // For MO_FPImmediate.
171  const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
172  int64_t ImmVal; // For MO_Immediate.
173  const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
174  const MDNode *MD; // For MO_Metadata.
175  MCSymbol *Sym; // For MO_MCSymbol.
176  unsigned CFIIndex; // For MO_CFI.
177  Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
178  unsigned Pred; // For MO_Predicate
179  ArrayRef<int> ShuffleMask; // For MO_ShuffleMask
180 
181  struct { // For MO_Register.
182  // Register number is in SmallContents.RegNo.
183  MachineOperand *Prev; // Access list for register. See MRI.
184  MachineOperand *Next;
185  } Reg;
186 
187  /// OffsetedInfo - This struct contains the offset and an object identifier.
188  /// this represent the object as with an optional offset from it.
189  struct {
190  union {
191  int Index; // For MO_*Index - The index itself.
192  const char *SymbolName; // For MO_ExternalSymbol.
193  const GlobalValue *GV; // For MO_GlobalAddress.
194  const BlockAddress *BA; // For MO_BlockAddress.
195  } Val;
196  // Low bits of offset are in SmallContents.OffsetLo.
197  int OffsetHi; // An offset from the object, high 32 bits.
198  } OffsetedInfo;
199  } Contents;
200 
201  explicit MachineOperand(MachineOperandType K)
202  : OpKind(K), SubReg_TargetFlags(0) {
203  // Assert that the layout is what we expect. It's easy to grow this object.
204  static_assert(alignof(MachineOperand) <= alignof(int64_t),
205  "MachineOperand shouldn't be more than 8 byte aligned");
206  static_assert(sizeof(Contents) <= 2 * sizeof(void *),
207  "Contents should be at most two pointers");
208  static_assert(sizeof(MachineOperand) <=
209  alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
210  3 * sizeof(void *)),
211  "MachineOperand too big. Should be Kind, SmallContents, "
212  "ParentMI, and Contents");
213  }
214 
215 public:
216  /// getType - Returns the MachineOperandType for this operand.
217  ///
218  MachineOperandType getType() const { return (MachineOperandType)OpKind; }
219 
220  unsigned getTargetFlags() const {
221  return isReg() ? 0 : SubReg_TargetFlags;
222  }
223  void setTargetFlags(unsigned F) {
224  assert(!isReg() && "Register operands can't have target flags");
225  SubReg_TargetFlags = F;
226  assert(SubReg_TargetFlags == F && "Target flags out of range");
227  }
228  void addTargetFlag(unsigned F) {
229  assert(!isReg() && "Register operands can't have target flags");
230  SubReg_TargetFlags |= F;
231  assert((SubReg_TargetFlags & F) && "Target flags out of range");
232  }
233 
234 
235  /// getParent - Return the instruction that this operand belongs to.
236  ///
237  MachineInstr *getParent() { return ParentMI; }
238  const MachineInstr *getParent() const { return ParentMI; }
239 
240  /// clearParent - Reset the parent pointer.
241  ///
242  /// The MachineOperand copy constructor also copies ParentMI, expecting the
243  /// original to be deleted. If a MachineOperand is ever stored outside a
244  /// MachineInstr, the parent pointer must be cleared.
245  ///
246  /// Never call clearParent() on an operand in a MachineInstr.
247  ///
248  void clearParent() { ParentMI = nullptr; }
249 
250  /// Print a subreg index operand.
251  /// MO_Immediate operands can also be subreg idices. If it's the case, the
252  /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
253  /// called to check this.
254  static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
255  const TargetRegisterInfo *TRI);
256 
257  /// Print operand target flags.
258  static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
259 
260  /// Print a MCSymbol as an operand.
261  static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
262 
263  /// Print a stack object reference.
264  static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
265  bool IsFixed, StringRef Name);
266 
267  /// Print the offset with explicit +/- signs.
268  static void printOperandOffset(raw_ostream &OS, int64_t Offset);
269 
270  /// Print an IRSlotNumber.
271  static void printIRSlotNumber(raw_ostream &OS, int Slot);
272 
273  /// Print the MachineOperand to \p os.
274  /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
275  /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
276  /// function will try to pick it up from the parent.
277  void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
278  const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
279 
280  /// More complex way of printing a MachineOperand.
281  /// \param TypeToPrint specifies the generic type to be printed on uses and
282  /// defs. It can be determined using MachineInstr::getTypeToPrint.
283  /// \param OpIdx - specifies the index of the operand in machine instruction.
284  /// This will be used by target dependent MIR formatter. Could be None if the
285  /// index is unknown, e.g. called by dump().
286  /// \param PrintDef - whether we want to print `def` on an operand which
287  /// isDef. Sometimes, if the operand is printed before '=', we don't print
288  /// `def`.
289  /// \param IsStandalone - whether we want a verbose output of the MO. This
290  /// prints extra information that can be easily inferred when printing the
291  /// whole function, but not when printing only a fragment of it.
292  /// \param ShouldPrintRegisterTies - whether we want to print register ties.
293  /// Sometimes they are easily determined by the instruction's descriptor
294  /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
295  /// \param TiedOperandIdx - if we need to print register ties this needs to
296  /// provide the index of the tied register. If not, it will be ignored.
297  /// \param TRI - provide more target-specific information to the printer.
298  /// Unlike the previous function, this one will not try and get the
299  /// information from it's parent.
300  /// \param IntrinsicInfo - same as \p TRI.
301  void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
302  Optional<unsigned> OpIdx, bool PrintDef, bool IsStandalone,
303  bool ShouldPrintRegisterTies, unsigned TiedOperandIdx,
304  const TargetRegisterInfo *TRI,
305  const TargetIntrinsicInfo *IntrinsicInfo) const;
306 
307  /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level
308  /// type to be printed the same way the full version of print(...) does it.
309  void print(raw_ostream &os, LLT TypeToPrint,
310  const TargetRegisterInfo *TRI = nullptr,
311  const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
312 
313  void dump() const;
314 
315  //===--------------------------------------------------------------------===//
316  // Accessors that tell you what kind of MachineOperand you're looking at.
317  //===--------------------------------------------------------------------===//
318 
319  /// isReg - Tests if this is a MO_Register operand.
320  bool isReg() const { return OpKind == MO_Register; }
321  /// isImm - Tests if this is a MO_Immediate operand.
322  bool isImm() const { return OpKind == MO_Immediate; }
323  /// isCImm - Test if this is a MO_CImmediate operand.
324  bool isCImm() const { return OpKind == MO_CImmediate; }
325  /// isFPImm - Tests if this is a MO_FPImmediate operand.
326  bool isFPImm() const { return OpKind == MO_FPImmediate; }
327  /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
328  bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
329  /// isFI - Tests if this is a MO_FrameIndex operand.
330  bool isFI() const { return OpKind == MO_FrameIndex; }
331  /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
332  bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
333  /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
334  bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
335  /// isJTI - Tests if this is a MO_JumpTableIndex operand.
336  bool isJTI() const { return OpKind == MO_JumpTableIndex; }
337  /// isGlobal - Tests if this is a MO_GlobalAddress operand.
338  bool isGlobal() const { return OpKind == MO_GlobalAddress; }
339  /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
340  bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
341  /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
342  bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
343  /// isRegMask - Tests if this is a MO_RegisterMask operand.
344  bool isRegMask() const { return OpKind == MO_RegisterMask; }
345  /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
346  bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
347  /// isMetadata - Tests if this is a MO_Metadata operand.
348  bool isMetadata() const { return OpKind == MO_Metadata; }
349  bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
350  bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
351  bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
352  bool isPredicate() const { return OpKind == MO_Predicate; }
353  bool isShuffleMask() const { return OpKind == MO_ShuffleMask; }
354  //===--------------------------------------------------------------------===//
355  // Accessors for Register Operands
356  //===--------------------------------------------------------------------===//
357 
358  /// getReg - Returns the register number.
359  Register getReg() const {
360  assert(isReg() && "This is not a register operand!");
361  return Register(SmallContents.RegNo);
362  }
363 
364  unsigned getSubReg() const {
365  assert(isReg() && "Wrong MachineOperand accessor");
366  return SubReg_TargetFlags;
367  }
368 
369  bool isUse() const {
370  assert(isReg() && "Wrong MachineOperand accessor");
371  return !IsDef;
372  }
373 
374  bool isDef() const {
375  assert(isReg() && "Wrong MachineOperand accessor");
376  return IsDef;
377  }
378 
379  bool isImplicit() const {
380  assert(isReg() && "Wrong MachineOperand accessor");
381  return IsImp;
382  }
383 
384  bool isDead() const {
385  assert(isReg() && "Wrong MachineOperand accessor");
386  return IsDeadOrKill & IsDef;
387  }
388 
389  bool isKill() const {
390  assert(isReg() && "Wrong MachineOperand accessor");
391  return IsDeadOrKill & !IsDef;
392  }
393 
394  bool isUndef() const {
395  assert(isReg() && "Wrong MachineOperand accessor");
396  return IsUndef;
397  }
398 
399  /// isRenamable - Returns true if this register may be renamed, i.e. it does
400  /// not generate a value that is somehow read in a way that is not represented
401  /// by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only
402  /// valid on physical register operands. Virtual registers are assumed to
403  /// always be renamable regardless of the value of this field.
404  ///
405  /// Operands that are renamable can freely be changed to any other register
406  /// that is a member of the register class returned by
407  /// MI->getRegClassConstraint().
408  ///
409  /// isRenamable can return false for several different reasons:
410  ///
411  /// - ABI constraints (since liveness is not always precisely modeled). We
412  /// conservatively handle these cases by setting all physical register
413  /// operands that didn’t start out as virtual regs to not be renamable.
414  /// Also any physical register operands created after register allocation or
415  /// whose register is changed after register allocation will not be
416  /// renamable. This state is tracked in the MachineOperand::IsRenamable
417  /// bit.
418  ///
419  /// - Opcode/target constraints: for opcodes that have complex register class
420  /// requirements (e.g. that depend on other operands/instructions), we set
421  /// hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
422  /// description. Operands belonging to instructions with opcodes that are
423  /// marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
424  /// isRenamable(). Additionally, the AllowRegisterRenaming target property
425  /// prevents any operands from being marked renamable for targets that don't
426  /// have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
427  /// values.
428  bool isRenamable() const;
429 
430  bool isInternalRead() const {
431  assert(isReg() && "Wrong MachineOperand accessor");
432  return IsInternalRead;
433  }
434 
435  bool isEarlyClobber() const {
436  assert(isReg() && "Wrong MachineOperand accessor");
437  return IsEarlyClobber;
438  }
439 
440  bool isTied() const {
441  assert(isReg() && "Wrong MachineOperand accessor");
442  return TiedTo;
443  }
444 
445  bool isDebug() const {
446  assert(isReg() && "Wrong MachineOperand accessor");
447  return IsDebug;
448  }
449 
450  /// readsReg - Returns true if this operand reads the previous value of its
451  /// register. A use operand with the <undef> flag set doesn't read its
452  /// register. A sub-register def implicitly reads the other parts of the
453  /// register being redefined unless the <undef> flag is set.
454  ///
455  /// This refers to reading the register value from before the current
456  /// instruction or bundle. Internal bundle reads are not included.
457  bool readsReg() const {
458  assert(isReg() && "Wrong MachineOperand accessor");
459  return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
460  }
461 
462  /// Return true if this operand can validly be appended to an arbitrary
463  /// operand list. i.e. this behaves like an implicit operand.
464  bool isValidExcessOperand() const {
465  if ((isReg() && isImplicit()) || isRegMask())
466  return true;
467 
468  // Debug operands
469  return isMetadata() || isMCSymbol();
470  }
471 
472  //===--------------------------------------------------------------------===//
473  // Mutators for Register Operands
474  //===--------------------------------------------------------------------===//
475 
476  /// Change the register this operand corresponds to.
477  ///
478  void setReg(Register Reg);
479 
480  void setSubReg(unsigned subReg) {
481  assert(isReg() && "Wrong MachineOperand mutator");
482  SubReg_TargetFlags = subReg;
483  assert(SubReg_TargetFlags == subReg && "SubReg out of range");
484  }
485 
486  /// substVirtReg - Substitute the current register with the virtual
487  /// subregister Reg:SubReg. Take any existing SubReg index into account,
488  /// using TargetRegisterInfo to compose the subreg indices if necessary.
489  /// Reg must be a virtual register, SubIdx can be 0.
490  ///
491  void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo&);
492 
493  /// substPhysReg - Substitute the current register with the physical register
494  /// Reg, taking any existing SubReg into account. For instance,
495  /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
496  ///
498 
499  void setIsUse(bool Val = true) { setIsDef(!Val); }
500 
501  /// Change a def to a use, or a use to a def.
502  void setIsDef(bool Val = true);
503 
504  void setImplicit(bool Val = true) {
505  assert(isReg() && "Wrong MachineOperand mutator");
506  IsImp = Val;
507  }
508 
509  void setIsKill(bool Val = true) {
510  assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
511  assert((!Val || !isDebug()) && "Marking a debug operation as kill");
512  IsDeadOrKill = Val;
513  }
514 
515  void setIsDead(bool Val = true) {
516  assert(isReg() && IsDef && "Wrong MachineOperand mutator");
517  IsDeadOrKill = Val;
518  }
519 
520  void setIsUndef(bool Val = true) {
521  assert(isReg() && "Wrong MachineOperand mutator");
522  IsUndef = Val;
523  }
524 
525  void setIsRenamable(bool Val = true);
526 
527  void setIsInternalRead(bool Val = true) {
528  assert(isReg() && "Wrong MachineOperand mutator");
529  IsInternalRead = Val;
530  }
531 
532  void setIsEarlyClobber(bool Val = true) {
533  assert(isReg() && IsDef && "Wrong MachineOperand mutator");
534  IsEarlyClobber = Val;
535  }
536 
537  void setIsDebug(bool Val = true) {
538  assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
539  IsDebug = Val;
540  }
541 
542  //===--------------------------------------------------------------------===//
543  // Accessors for various operand types.
544  //===--------------------------------------------------------------------===//
545 
546  int64_t getImm() const {
547  assert(isImm() && "Wrong MachineOperand accessor");
548  return Contents.ImmVal;
549  }
550 
551  const ConstantInt *getCImm() const {
552  assert(isCImm() && "Wrong MachineOperand accessor");
553  return Contents.CI;
554  }
555 
556  const ConstantFP *getFPImm() const {
557  assert(isFPImm() && "Wrong MachineOperand accessor");
558  return Contents.CFP;
559  }
560 
562  assert(isMBB() && "Wrong MachineOperand accessor");
563  return Contents.MBB;
564  }
565 
566  int getIndex() const {
567  assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
568  "Wrong MachineOperand accessor");
569  return Contents.OffsetedInfo.Val.Index;
570  }
571 
572  const GlobalValue *getGlobal() const {
573  assert(isGlobal() && "Wrong MachineOperand accessor");
574  return Contents.OffsetedInfo.Val.GV;
575  }
576 
577  const BlockAddress *getBlockAddress() const {
578  assert(isBlockAddress() && "Wrong MachineOperand accessor");
579  return Contents.OffsetedInfo.Val.BA;
580  }
581 
583  assert(isMCSymbol() && "Wrong MachineOperand accessor");
584  return Contents.Sym;
585  }
586 
587  unsigned getCFIIndex() const {
588  assert(isCFIIndex() && "Wrong MachineOperand accessor");
589  return Contents.CFIIndex;
590  }
591 
593  assert(isIntrinsicID() && "Wrong MachineOperand accessor");
594  return Contents.IntrinsicID;
595  }
596 
597  unsigned getPredicate() const {
598  assert(isPredicate() && "Wrong MachineOperand accessor");
599  return Contents.Pred;
600  }
601 
603  assert(isShuffleMask() && "Wrong MachineOperand accessor");
604  return Contents.ShuffleMask;
605  }
606 
607  /// Return the offset from the symbol in this operand. This always returns 0
608  /// for ExternalSymbol operands.
609  int64_t getOffset() const {
610  assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
611  isTargetIndex() || isBlockAddress()) &&
612  "Wrong MachineOperand accessor");
613  return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
614  SmallContents.OffsetLo;
615  }
616 
617  const char *getSymbolName() const {
618  assert(isSymbol() && "Wrong MachineOperand accessor");
619  return Contents.OffsetedInfo.Val.SymbolName;
620  }
621 
622  /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
623  /// It is sometimes necessary to detach the register mask pointer from its
624  /// machine operand. This static method can be used for such detached bit
625  /// mask pointers.
626  static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) {
627  // See TargetRegisterInfo.h.
628  assert(PhysReg < (1u << 30) && "Not a physical register");
629  return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
630  }
631 
632  /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
633  bool clobbersPhysReg(MCRegister PhysReg) const {
634  return clobbersPhysReg(getRegMask(), PhysReg);
635  }
636 
637  /// getRegMask - Returns a bit mask of registers preserved by this RegMask
638  /// operand.
639  const uint32_t *getRegMask() const {
640  assert(isRegMask() && "Wrong MachineOperand accessor");
641  return Contents.RegMask;
642  }
643 
644  /// Returns number of elements needed for a regmask array.
645  static unsigned getRegMaskSize(unsigned NumRegs) {
646  return (NumRegs + 31) / 32;
647  }
648 
649  /// getRegLiveOut - Returns a bit mask of live-out registers.
650  const uint32_t *getRegLiveOut() const {
651  assert(isRegLiveOut() && "Wrong MachineOperand accessor");
652  return Contents.RegMask;
653  }
654 
655  const MDNode *getMetadata() const {
656  assert(isMetadata() && "Wrong MachineOperand accessor");
657  return Contents.MD;
658  }
659 
660  //===--------------------------------------------------------------------===//
661  // Mutators for various operand types.
662  //===--------------------------------------------------------------------===//
663 
664  void setImm(int64_t immVal) {
665  assert(isImm() && "Wrong MachineOperand mutator");
666  Contents.ImmVal = immVal;
667  }
668 
669  void setCImm(const ConstantInt *CI) {
670  assert(isCImm() && "Wrong MachineOperand mutator");
671  Contents.CI = CI;
672  }
673 
674  void setFPImm(const ConstantFP *CFP) {
675  assert(isFPImm() && "Wrong MachineOperand mutator");
676  Contents.CFP = CFP;
677  }
678 
679  void setOffset(int64_t Offset) {
680  assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
681  isTargetIndex() || isBlockAddress()) &&
682  "Wrong MachineOperand mutator");
683  SmallContents.OffsetLo = unsigned(Offset);
684  Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
685  }
686 
687  void setIndex(int Idx) {
688  assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
689  "Wrong MachineOperand mutator");
690  Contents.OffsetedInfo.Val.Index = Idx;
691  }
692 
693  void setMetadata(const MDNode *MD) {
694  assert(isMetadata() && "Wrong MachineOperand mutator");
695  Contents.MD = MD;
696  }
697 
699  assert(isMBB() && "Wrong MachineOperand mutator");
700  Contents.MBB = MBB;
701  }
702 
703  /// Sets value of register mask operand referencing Mask. The
704  /// operand does not take ownership of the memory referenced by Mask, it must
705  /// remain valid for the lifetime of the operand. See CreateRegMask().
706  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
707  void setRegMask(const uint32_t *RegMaskPtr) {
708  assert(isRegMask() && "Wrong MachineOperand mutator");
709  Contents.RegMask = RegMaskPtr;
710  }
711 
713  assert(isIntrinsicID() && "Wrong MachineOperand mutator");
714  Contents.IntrinsicID = IID;
715  }
716 
717  void setPredicate(unsigned Predicate) {
718  assert(isPredicate() && "Wrong MachineOperand mutator");
719  Contents.Pred = Predicate;
720  }
721 
722  //===--------------------------------------------------------------------===//
723  // Other methods.
724  //===--------------------------------------------------------------------===//
725 
726  /// Returns true if this operand is identical to the specified operand except
727  /// for liveness related flags (isKill, isUndef and isDead). Note that this
728  /// should stay in sync with the hash_value overload below.
729  bool isIdenticalTo(const MachineOperand &Other) const;
730 
731  /// MachineOperand hash_value overload.
732  ///
733  /// Note that this includes the same information in the hash that
734  /// isIdenticalTo uses for comparison. It is thus suited for use in hash
735  /// tables which use that function for equality comparisons only. This must
736  /// stay exactly in sync with isIdenticalTo above.
737  friend hash_code hash_value(const MachineOperand &MO);
738 
739  /// ChangeToImmediate - Replace this operand with a new immediate operand of
740  /// the specified value. If an operand is known to be an immediate already,
741  /// the setImm method should be used.
742  void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags = 0);
743 
744  /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
745  /// of the specified value. If an operand is known to be an FP immediate
746  /// already, the setFPImm method should be used.
747  void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags = 0);
748 
749  /// ChangeToES - Replace this operand with a new external symbol operand.
750  void ChangeToES(const char *SymName, unsigned TargetFlags = 0);
751 
752  /// ChangeToGA - Replace this operand with a new global address operand.
753  void ChangeToGA(const GlobalValue *GV, int64_t Offset,
754  unsigned TargetFlags = 0);
755 
756  /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
757  void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags = 0);
758 
759  /// Replace this operand with a frame index.
760  void ChangeToFrameIndex(int Idx, unsigned TargetFlags = 0);
761 
762  /// Replace this operand with a target index.
763  void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
764  unsigned TargetFlags = 0);
765 
766  /// ChangeToRegister - Replace this operand with a new register operand of
767  /// the specified value. If an operand is known to be an register already,
768  /// the setReg method should be used.
769  void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
770  bool isKill = false, bool isDead = false,
771  bool isUndef = false, bool isDebug = false);
772 
773  /// getTargetIndexName - If this MachineOperand is a TargetIndex that has a
774  /// name, attempt to get the name. Returns nullptr if the TargetIndex does not
775  /// have a name. Asserts if MO is not a TargetIndex.
776  const char *getTargetIndexName() const;
777 
778  //===--------------------------------------------------------------------===//
779  // Construction methods.
780  //===--------------------------------------------------------------------===//
781 
782  static MachineOperand CreateImm(int64_t Val) {
784  Op.setImm(Val);
785  return Op;
786  }
787 
790  Op.Contents.CI = CI;
791  return Op;
792  }
793 
794  static MachineOperand CreateFPImm(const ConstantFP *CFP) {
796  Op.Contents.CFP = CFP;
797  return Op;
798  }
799 
800  static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
801  bool isKill = false, bool isDead = false,
802  bool isUndef = false,
803  bool isEarlyClobber = false,
804  unsigned SubReg = 0, bool isDebug = false,
805  bool isInternalRead = false,
806  bool isRenamable = false) {
807  assert(!(isDead && !isDef) && "Dead flag on non-def");
808  assert(!(isKill && isDef) && "Kill flag on def");
810  Op.IsDef = isDef;
811  Op.IsImp = isImp;
812  Op.IsDeadOrKill = isKill | isDead;
813  Op.IsRenamable = isRenamable;
814  Op.IsUndef = isUndef;
815  Op.IsInternalRead = isInternalRead;
816  Op.IsEarlyClobber = isEarlyClobber;
817  Op.TiedTo = 0;
818  Op.IsDebug = isDebug;
819  Op.SmallContents.RegNo = Reg;
820  Op.Contents.Reg.Prev = nullptr;
821  Op.Contents.Reg.Next = nullptr;
822  Op.setSubReg(SubReg);
823  return Op;
824  }
826  unsigned TargetFlags = 0) {
828  Op.setMBB(MBB);
829  Op.setTargetFlags(TargetFlags);
830  return Op;
831  }
832  static MachineOperand CreateFI(int Idx) {
834  Op.setIndex(Idx);
835  return Op;
836  }
837  static MachineOperand CreateCPI(unsigned Idx, int Offset,
838  unsigned TargetFlags = 0) {
840  Op.setIndex(Idx);
841  Op.setOffset(Offset);
842  Op.setTargetFlags(TargetFlags);
843  return Op;
844  }
845  static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
846  unsigned TargetFlags = 0) {
848  Op.setIndex(Idx);
849  Op.setOffset(Offset);
850  Op.setTargetFlags(TargetFlags);
851  return Op;
852  }
853  static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags = 0) {
855  Op.setIndex(Idx);
856  Op.setTargetFlags(TargetFlags);
857  return Op;
858  }
859  static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
860  unsigned TargetFlags = 0) {
862  Op.Contents.OffsetedInfo.Val.GV = GV;
863  Op.setOffset(Offset);
864  Op.setTargetFlags(TargetFlags);
865  return Op;
866  }
867  static MachineOperand CreateES(const char *SymName,
868  unsigned TargetFlags = 0) {
870  Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
871  Op.setOffset(0); // Offset is always 0.
872  Op.setTargetFlags(TargetFlags);
873  return Op;
874  }
875  static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
876  unsigned TargetFlags = 0) {
878  Op.Contents.OffsetedInfo.Val.BA = BA;
879  Op.setOffset(Offset);
880  Op.setTargetFlags(TargetFlags);
881  return Op;
882  }
883  /// CreateRegMask - Creates a register mask operand referencing Mask. The
884  /// operand does not take ownership of the memory referenced by Mask, it
885  /// must remain valid for the lifetime of the operand.
886  ///
887  /// A RegMask operand represents a set of non-clobbered physical registers
888  /// on an instruction that clobbers many registers, typically a call. The
889  /// bit mask has a bit set for each physreg that is preserved by this
890  /// instruction, as described in the documentation for
891  /// TargetRegisterInfo::getCallPreservedMask().
892  ///
893  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
894  ///
896  assert(Mask && "Missing register mask");
898  Op.Contents.RegMask = Mask;
899  return Op;
900  }
902  assert(Mask && "Missing live-out register mask");
904  Op.Contents.RegMask = Mask;
905  return Op;
906  }
907  static MachineOperand CreateMetadata(const MDNode *Meta) {
909  Op.Contents.MD = Meta;
910  return Op;
911  }
912 
914  unsigned TargetFlags = 0) {
916  Op.Contents.Sym = Sym;
917  Op.setOffset(0);
918  Op.setTargetFlags(TargetFlags);
919  return Op;
920  }
921 
922  static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
924  Op.Contents.CFIIndex = CFIIndex;
925  return Op;
926  }
927 
930  Op.Contents.IntrinsicID = ID;
931  return Op;
932  }
933 
934  static MachineOperand CreatePredicate(unsigned Pred) {
936  Op.Contents.Pred = Pred;
937  return Op;
938  }
939 
942  Op.Contents.ShuffleMask = Mask;
943  return Op;
944  }
945 
946  friend class MachineInstr;
947  friend class MachineRegisterInfo;
948 
949 private:
950  // If this operand is currently a register operand, and if this is in a
951  // function, deregister the operand from the register's use/def list.
952  void removeRegFromUses();
953 
954  /// Artificial kinds for DenseMap usage.
955  enum : unsigned char {
956  MO_Empty = MO_Last + 1,
957  MO_Tombstone,
958  };
959 
960  friend struct DenseMapInfo<MachineOperand>;
961 
962  //===--------------------------------------------------------------------===//
963  // Methods for handling register use/def lists.
964  //===--------------------------------------------------------------------===//
965 
966  /// isOnRegUseList - Return true if this operand is on a register use/def
967  /// list or false if not. This can only be called for register operands
968  /// that are part of a machine instruction.
969  bool isOnRegUseList() const {
970  assert(isReg() && "Can only add reg operand to use lists");
971  return Contents.Reg.Prev != nullptr;
972  }
973 };
974 
975 template <> struct DenseMapInfo<MachineOperand> {
978  MachineOperand::MO_Empty));
979  }
982  MachineOperand::MO_Tombstone));
983  }
984  static unsigned getHashValue(const MachineOperand &MO) {
985  return hash_value(MO);
986  }
987  static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
988  if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
989  MachineOperand::MO_Empty) ||
990  LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
991  MachineOperand::MO_Tombstone))
992  return LHS.getType() == RHS.getType();
993  return LHS.isIdenticalTo(RHS);
994  }
995 };
996 
998  MO.print(OS);
999  return OS;
1000 }
1001 
1002 // See friend declaration above. This additional declaration is required in
1003 // order to compile LLVM with IBM xlC compiler.
1004 hash_code hash_value(const MachineOperand &MO);
1005 } // namespace llvm
1006 
1007 #endif
llvm::MachineOperand::CreateCPI
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:837
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:156
llvm::MachineOperand::CreateJTI
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
Definition: MachineOperand.h:853
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:62
llvm::MachineOperand::setRegMask
void setRegMask(const uint32_t *RegMaskPtr)
Sets value of register mask operand referencing Mask.
Definition: MachineOperand.h:707
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:52
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MachineOperand::setIsInternalRead
void setIsInternalRead(bool Val=true)
Definition: MachineOperand.h:527
llvm::MachineOperand::isBlockAddress
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Definition: MachineOperand.h:342
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
llvm::MachineOperand::MachineOperandType
MachineOperandType
Definition: MachineOperand.h:50
llvm::MachineOperand::MO_ShuffleMask
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
Definition: MachineOperand.h:70
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:572
llvm::MachineOperand::MO_RegisterLiveOut
@ MO_RegisterLiveOut
Mask of live-out registers.
Definition: MachineOperand.h:64
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
llvm::DenseMapInfo< MachineOperand >::getHashValue
static unsigned getHashValue(const MachineOperand &MO)
Definition: MachineOperand.h:984
llvm::MachineOperand::printStackObjectReference
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Definition: MachineOperand.cpp:584
llvm::MachineOperand::printIRSlotNumber
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
Definition: MachineOperand.cpp:607
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:592
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:509
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:729
llvm::DenseMapInfo< MachineOperand >::isEqual
static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS)
Definition: MachineOperand.h:987
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:577
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:440
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineOperand::RegNo
unsigned RegNo
Definition: MachineOperand.h:158
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:664
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::MachineOperand::setMetadata
void setMetadata(const MDNode *MD)
Definition: MachineOperand.h:693
llvm::MachineOperand::addTargetFlag
void addTargetFlag(unsigned F)
Definition: MachineOperand.h:228
llvm::MachineOperand::isSymbol
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
Definition: MachineOperand.h:340
llvm::MachineOperand::isJTI
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
Definition: MachineOperand.h:336
llvm::MachineOperand::isMCSymbol
bool isMCSymbol() const
Definition: MachineOperand.h:349
llvm::MachineOperand::CreateMetadata
static MachineOperand CreateMetadata(const MDNode *Meta)
Definition: MachineOperand.h:907
llvm::MachineOperand::CreateCFIIndex
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
Definition: MachineOperand.h:922
llvm::MachineOperand::MO_CFIIndex
@ MO_CFIIndex
MCCFIInstruction index.
Definition: MachineOperand.h:67
llvm::MachineOperand::getTargetIndexName
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
Definition: MachineOperand.cpp:426
llvm::MachineOperand::isCImm
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Definition: MachineOperand.h:324
llvm::MachineOperand::setPredicate
void setPredicate(unsigned Predicate)
Definition: MachineOperand.h:717
llvm::Optional< unsigned >
llvm::MachineOperand::ChangeToTargetIndex
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
Definition: MachineOperand.cpp:223
llvm::MachineOperand::setIsUse
void setIsUse(bool Val=true)
Definition: MachineOperand.h:499
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::MachineOperand::ChangeToFrameIndex
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
Definition: MachineOperand.cpp:212
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:330
llvm::hash_value
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4828
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:609
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineOperand::setCImm
void setCImm(const ConstantInt *CI)
Definition: MachineOperand.h:669
llvm::MachineOperand::dump
void dump() const
Definition: MachineOperand.cpp:972
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition: MachineOperand.h:582
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:51
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::MachineOperand::CreateES
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
Definition: MachineOperand.h:867
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition: MachineOperand.cpp:580
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
llvm::MachineOperand::clobbersPhysReg
bool clobbersPhysReg(MCRegister PhysReg) const
clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
Definition: MachineOperand.h:633
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition: MachineOperand.cpp:519
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:116
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::DenseMapInfo
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition: APInt.h:34
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::MachineOperand::hash_value
friend hash_code hash_value(const MachineOperand &MO)
MachineOperand hash_value overload.
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:76
llvm::MachineOperand::isValidExcessOperand
bool isValidExcessOperand() const
Return true if this operand can validly be appended to an arbitrary operand list.
Definition: MachineOperand.h:464
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::MachineOperand::ChangeToRegister
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Definition: MachineOperand.cpp:239
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:61
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineOperand::getRegMaskSize
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
Definition: MachineOperand.h:645
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
Intrinsics.h
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::MachineOperand::getRegMask
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Definition: MachineOperand.h:639
llvm::MachineOperand::setSubReg
void setSubReg(unsigned subReg)
Definition: MachineOperand.h:480
llvm::MachineOperand::MO_FrameIndex
@ MO_FrameIndex
Abstract Stack Frame Index.
Definition: MachineOperand.h:56
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:328
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:154
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineOperand::getParent
const MachineInstr * getParent() const
Definition: MachineOperand.h:238
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::MachineOperand::ChangeToMCSymbol
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
Definition: MachineOperand.cpp:201
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::MachineOperand::CreateFI
static MachineOperand CreateFI(int Idx)
Definition: MachineOperand.h:832
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition: MachineOperand.h:223
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::MachineOperand::isRegLiveOut
bool isRegLiveOut() const
isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
Definition: MachineOperand.h:346
llvm::MachineOperand::printOperandOffset
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
Definition: MachineOperand.cpp:597
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:655
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::MachineOperand::CreateShuffleMask
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
Definition: MachineOperand.h:940
llvm::MachineOperand::MO_Metadata
@ MO_Metadata
Metadata reference (for debug info)
Definition: MachineOperand.h:65
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:626
llvm::MachineOperand::ChangeToFPImmediate
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
Definition: MachineOperand.cpp:164
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:394
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:515
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:220
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition: MachineOperand.cpp:75
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:551
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::MachineOperand::CreateMBB
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
Definition: MachineOperand.h:825
llvm::DenseMapInfo< MachineOperand >::getTombstoneKey
static MachineOperand getTombstoneKey()
Definition: MachineOperand.h:980
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:384
llvm::MachineOperand::MO_Predicate
@ MO_Predicate
Generic predicate for ISel.
Definition: MachineOperand.h:69
llvm::MachineOperand::MO_MCSymbol
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition: MachineOperand.h:66
llvm::MachineOperand::setIntrinsicID
void setIntrinsicID(Intrinsic::ID IID)
Definition: MachineOperand.h:712
llvm::MachineOperand::isCPI
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
Definition: MachineOperand.h:332
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:218
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:556
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:597
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:435
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition: MachineOperand.h:602
llvm::MachineOperand::MO_TargetIndex
@ MO_TargetIndex
Target-dependent index+offset operand.
Definition: MachineOperand.h:58
llvm::MachineOperand::CreateBA
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:875
llvm::MachineOperand::isRegMask
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
Definition: MachineOperand.h:344
llvm::MachineOperand::MO_FPImmediate
@ MO_FPImmediate
Floating-point immediate operand.
Definition: MachineOperand.h:54
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MDNode
Metadata node.
Definition: Metadata.h:944
llvm::MachineOperand::CreateMCSymbol
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
Definition: MachineOperand.h:913
llvm::MachineOperand::setIsDebug
void setIsDebug(bool Val=true)
Definition: MachineOperand.h:537
llvm::MachineOperand::isTargetIndex
bool isTargetIndex() const
isTargetIndex - Tests if this is a MO_TargetIndex operand.
Definition: MachineOperand.h:334
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:59
llvm::MachineOperand::isShuffleMask
bool isShuffleMask() const
Definition: MachineOperand.h:353
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:849
llvm::MachineOperand::MO_CImmediate
@ MO_CImmediate
Immediate >64bit operand.
Definition: MachineOperand.h:53
llvm::MachineOperand::setIsDef
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Definition: MachineOperand.cpp:99
llvm::MachineOperand::CreateIntrinsicID
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
Definition: MachineOperand.h:928
llvm::ArrayRef< int >
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
llvm::MachineOperand::CreateGA
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:859
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineOperand::ChangeToES
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Definition: MachineOperand.cpp:175
llvm::MachineOperand::isIntrinsicID
bool isIntrinsicID() const
Definition: MachineOperand.h:351
llvm::MachineOperand::setIsEarlyClobber
void setIsEarlyClobber(bool Val=true)
Definition: MachineOperand.h:532
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:520
uint32_t
llvm::MachineOperand::setIsRenamable
void setIsRenamable(bool Val=true)
Definition: MachineOperand.cpp:134
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:55
llvm::MachineOperand::MO_Last
@ MO_Last
Definition: MachineOperand.h:71
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::MachineOperand::MO_IntrinsicID
@ MO_IntrinsicID
Intrinsic ID for ISel.
Definition: MachineOperand.h:68
llvm::MachineOperand::CreateCImm
static MachineOperand CreateCImm(const ConstantInt *CI)
Definition: MachineOperand.h:788
llvm::MachineOperand::setIndex
void setIndex(int Idx)
Definition: MachineOperand.h:687
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::DenseMapInfo< MachineOperand >::getEmptyKey
static MachineOperand getEmptyKey()
Definition: MachineOperand.h:976
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineOperand::printTargetFlags
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
Definition: MachineOperand.cpp:528
llvm::AMDGPU::HSAMD::Kernel::Key::SymbolName
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
Definition: AMDGPUMetadata.h:386
llvm::MachineOperand::ChangeToGA
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
Definition: MachineOperand.cpp:188
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::MachineOperand::readsReg
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Definition: MachineOperand.h:457
llvm::MachineOperand::isMetadata
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
Definition: MachineOperand.h:348
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:60
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:566
llvm::MachineOperand::setFPImm
void setFPImm(const ConstantFP *CFP)
Definition: MachineOperand.h:674
llvm::MachineOperand::getCFIIndex
unsigned getCFIIndex() const
Definition: MachineOperand.h:587
llvm::MachineOperand::isCFIIndex
bool isCFIIndex() const
Definition: MachineOperand.h:350
llvm::MachineOperand::setImplicit
void setImplicit(bool Val=true)
Definition: MachineOperand.h:504
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:445
llvm::MachineOperand::isFPImm
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Definition: MachineOperand.h:326
llvm::MachineOperand::isPredicate
bool isPredicate() const
Definition: MachineOperand.h:352
llvm::MachineOperand::CreateRegMask
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
Definition: MachineOperand.h:895
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:617
llvm::MachineOperand::OffsetLo
unsigned OffsetLo
Definition: MachineOperand.h:159
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:53
llvm::MachineOperand::clearParent
void clearParent()
clearParent - Reset the parent pointer.
Definition: MachineOperand.h:248
llvm::MachineOperand::setMBB
void setMBB(MachineBasicBlock *MBB)
Definition: MachineOperand.h:698
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:430
llvm::MachineOperand::getRegLiveOut
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
Definition: MachineOperand.h:650
DenseMapInfo.h
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:85
Register.h
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:63
llvm::MachineOperand::CreatePredicate
static MachineOperand CreatePredicate(unsigned Pred)
Definition: MachineOperand.h:934
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::MachineOperand::CreateFPImm
static MachineOperand CreateFPImm(const ConstantFP *CFP)
Definition: MachineOperand.h:794
llvm::MachineOperand::CreateTargetIndex
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:845
llvm::ISD::MCSymbol
@ MCSymbol
Definition: ISDOpcodes.h:172
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:285
llvm::MachineOperand::CreateRegLiveOut
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
Definition: MachineOperand.h:901
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:338
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::hash_code
An opaque object representing a hash code.
Definition: Hashing.h:73
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:57
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::MachineOperand::setOffset
void setOffset(int64_t Offset)
Definition: MachineOperand.h:679