LLVM  9.0.0svn
MachineOperand.h
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1 //===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineOperand class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_MACHINEOPERAND_H
14 #define LLVM_CODEGEN_MACHINEOPERAND_H
15 
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/IR/Intrinsics.h"
18 #include "llvm/Support/DataTypes.h"
20 #include <cassert>
21 
22 namespace llvm {
23 
24 class BlockAddress;
25 class ConstantFP;
26 class ConstantInt;
27 class GlobalValue;
28 class MachineBasicBlock;
29 class MachineInstr;
30 class MachineRegisterInfo;
31 class MCCFIInstruction;
32 class MDNode;
33 class ModuleSlotTracker;
34 class TargetMachine;
35 class TargetIntrinsicInfo;
36 class TargetRegisterInfo;
37 class hash_code;
38 class raw_ostream;
39 class MCSymbol;
40 
41 /// MachineOperand class - Representation of each machine instruction operand.
42 ///
43 /// This class isn't a POD type because it has a private constructor, but its
44 /// destructor must be trivial. Functions like MachineInstr::addOperand(),
45 /// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
46 /// not having to call the MachineOperand destructor.
47 ///
49 public:
50  enum MachineOperandType : unsigned char {
51  MO_Register, ///< Register operand.
52  MO_Immediate, ///< Immediate operand
53  MO_CImmediate, ///< Immediate >64bit operand
54  MO_FPImmediate, ///< Floating-point immediate operand
55  MO_MachineBasicBlock, ///< MachineBasicBlock reference
56  MO_FrameIndex, ///< Abstract Stack Frame Index
57  MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
58  MO_TargetIndex, ///< Target-dependent index+offset operand.
59  MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
60  MO_ExternalSymbol, ///< Name of external global symbol
61  MO_GlobalAddress, ///< Address of a global value
62  MO_BlockAddress, ///< Address of a basic block
63  MO_RegisterMask, ///< Mask of preserved registers.
64  MO_RegisterLiveOut, ///< Mask of live-out registers.
65  MO_Metadata, ///< Metadata reference (for debug info)
66  MO_MCSymbol, ///< MCSymbol reference (for debug/eh info)
67  MO_CFIIndex, ///< MCCFIInstruction index.
68  MO_IntrinsicID, ///< Intrinsic ID for ISel
69  MO_Predicate, ///< Generic predicate for ISel
71  };
72 
73 private:
74  /// OpKind - Specify what kind of operand this is. This discriminates the
75  /// union.
76  unsigned OpKind : 8;
77 
78  /// Subregister number for MO_Register. A value of 0 indicates the
79  /// MO_Register has no subReg.
80  ///
81  /// For all other kinds of operands, this field holds target-specific flags.
82  unsigned SubReg_TargetFlags : 12;
83 
84  /// TiedTo - Non-zero when this register operand is tied to another register
85  /// operand. The encoding of this field is described in the block comment
86  /// before MachineInstr::tieOperands().
87  unsigned TiedTo : 4;
88 
89  /// IsDef - True if this is a def, false if this is a use of the register.
90  /// This is only valid on register operands.
91  ///
92  unsigned IsDef : 1;
93 
94  /// IsImp - True if this is an implicit def or use, false if it is explicit.
95  /// This is only valid on register opderands.
96  ///
97  unsigned IsImp : 1;
98 
99  /// IsDeadOrKill
100  /// For uses: IsKill - True if this instruction is the last use of the
101  /// register on this path through the function.
102  /// For defs: IsDead - True if this register is never used by a subsequent
103  /// instruction.
104  /// This is only valid on register operands.
105  unsigned IsDeadOrKill : 1;
106 
107  /// See isRenamable().
108  unsigned IsRenamable : 1;
109 
110  /// IsUndef - True if this register operand reads an "undef" value, i.e. the
111  /// read value doesn't matter. This flag can be set on both use and def
112  /// operands. On a sub-register def operand, it refers to the part of the
113  /// register that isn't written. On a full-register def operand, it is a
114  /// noop. See readsReg().
115  ///
116  /// This is only valid on registers.
117  ///
118  /// Note that an instruction may have multiple <undef> operands referring to
119  /// the same register. In that case, the instruction may depend on those
120  /// operands reading the same dont-care value. For example:
121  ///
122  /// %1 = XOR undef %2, undef %2
123  ///
124  /// Any register can be used for %2, and its value doesn't matter, but
125  /// the two operands must be the same register.
126  ///
127  unsigned IsUndef : 1;
128 
129  /// IsInternalRead - True if this operand reads a value that was defined
130  /// inside the same instruction or bundle. This flag can be set on both use
131  /// and def operands. On a sub-register def operand, it refers to the part
132  /// of the register that isn't written. On a full-register def operand, it
133  /// is a noop.
134  ///
135  /// When this flag is set, the instruction bundle must contain at least one
136  /// other def of the register. If multiple instructions in the bundle define
137  /// the register, the meaning is target-defined.
138  unsigned IsInternalRead : 1;
139 
140  /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
141  /// by the MachineInstr before all input registers are read. This is used to
142  /// model the GCC inline asm '&' constraint modifier.
143  unsigned IsEarlyClobber : 1;
144 
145  /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
146  /// not a real instruction. Such uses should be ignored during codegen.
147  unsigned IsDebug : 1;
148 
149  /// SmallContents - This really should be part of the Contents union, but
150  /// lives out here so we can get a better packed struct.
151  /// MO_Register: Register number.
152  /// OffsetedInfo: Low bits of offset.
153  union {
154  unsigned RegNo; // For MO_Register.
155  unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi.
156  } SmallContents;
157 
158  /// ParentMI - This is the instruction that this operand is embedded into.
159  /// This is valid for all operand types, when the operand is in an instr.
160  MachineInstr *ParentMI;
161 
162  /// Contents union - This contains the payload for the various operand types.
163  union {
164  MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
165  const ConstantFP *CFP; // For MO_FPImmediate.
166  const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
167  int64_t ImmVal; // For MO_Immediate.
168  const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
169  const MDNode *MD; // For MO_Metadata.
170  MCSymbol *Sym; // For MO_MCSymbol.
171  unsigned CFIIndex; // For MO_CFI.
172  Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
173  unsigned Pred; // For MO_Predicate
174 
175  struct { // For MO_Register.
176  // Register number is in SmallContents.RegNo.
177  MachineOperand *Prev; // Access list for register. See MRI.
179  } Reg;
180 
181  /// OffsetedInfo - This struct contains the offset and an object identifier.
182  /// this represent the object as with an optional offset from it.
183  struct {
184  union {
185  int Index; // For MO_*Index - The index itself.
186  const char *SymbolName; // For MO_ExternalSymbol.
187  const GlobalValue *GV; // For MO_GlobalAddress.
188  const BlockAddress *BA; // For MO_BlockAddress.
189  } Val;
190  // Low bits of offset are in SmallContents.OffsetLo.
191  int OffsetHi; // An offset from the object, high 32 bits.
192  } OffsetedInfo;
193  } Contents;
194 
196  : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {
197  // Assert that the layout is what we expect. It's easy to grow this object.
198  static_assert(alignof(MachineOperand) <= alignof(int64_t),
199  "MachineOperand shouldn't be more than 8 byte aligned");
200  static_assert(sizeof(Contents) <= 2 * sizeof(void *),
201  "Contents should be at most two pointers");
202  static_assert(sizeof(MachineOperand) <=
203  alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
204  3 * sizeof(void *)),
205  "MachineOperand too big. Should be Kind, SmallContents, "
206  "ParentMI, and Contents");
207  }
208 
209 public:
210  /// getType - Returns the MachineOperandType for this operand.
211  ///
212  MachineOperandType getType() const { return (MachineOperandType)OpKind; }
213 
214  unsigned getTargetFlags() const {
215  return isReg() ? 0 : SubReg_TargetFlags;
216  }
217  void setTargetFlags(unsigned F) {
218  assert(!isReg() && "Register operands can't have target flags");
219  SubReg_TargetFlags = F;
220  assert(SubReg_TargetFlags == F && "Target flags out of range");
221  }
222  void addTargetFlag(unsigned F) {
223  assert(!isReg() && "Register operands can't have target flags");
224  SubReg_TargetFlags |= F;
225  assert((SubReg_TargetFlags & F) && "Target flags out of range");
226  }
227 
228 
229  /// getParent - Return the instruction that this operand belongs to.
230  ///
231  MachineInstr *getParent() { return ParentMI; }
232  const MachineInstr *getParent() const { return ParentMI; }
233 
234  /// clearParent - Reset the parent pointer.
235  ///
236  /// The MachineOperand copy constructor also copies ParentMI, expecting the
237  /// original to be deleted. If a MachineOperand is ever stored outside a
238  /// MachineInstr, the parent pointer must be cleared.
239  ///
240  /// Never call clearParent() on an operand in a MachineInstr.
241  ///
242  void clearParent() { ParentMI = nullptr; }
243 
244  /// Print a subreg index operand.
245  /// MO_Immediate operands can also be subreg idices. If it's the case, the
246  /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
247  /// called to check this.
248  static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
249  const TargetRegisterInfo *TRI);
250 
251  /// Print operand target flags.
252  static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
253 
254  /// Print a MCSymbol as an operand.
255  static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
256 
257  /// Print a stack object reference.
258  static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
259  bool IsFixed, StringRef Name);
260 
261  /// Print the offset with explicit +/- signs.
262  static void printOperandOffset(raw_ostream &OS, int64_t Offset);
263 
264  /// Print an IRSlotNumber.
265  static void printIRSlotNumber(raw_ostream &OS, int Slot);
266 
267  /// Print the MachineOperand to \p os.
268  /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
269  /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
270  /// function will try to pick it up from the parent.
271  void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
272  const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
273 
274  /// More complex way of printing a MachineOperand.
275  /// \param TypeToPrint specifies the generic type to be printed on uses and
276  /// defs. It can be determined using MachineInstr::getTypeToPrint.
277  /// \param PrintDef - whether we want to print `def` on an operand which
278  /// isDef. Sometimes, if the operand is printed before '=', we don't print
279  /// `def`.
280  /// \param IsStandalone - whether we want a verbose output of the MO. This
281  /// prints extra information that can be easily inferred when printing the
282  /// whole function, but not when printing only a fragment of it.
283  /// \param ShouldPrintRegisterTies - whether we want to print register ties.
284  /// Sometimes they are easily determined by the instruction's descriptor
285  /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
286  /// \param TiedOperandIdx - if we need to print register ties this needs to
287  /// provide the index of the tied register. If not, it will be ignored.
288  /// \param TRI - provide more target-specific information to the printer.
289  /// Unlike the previous function, this one will not try and get the
290  /// information from it's parent.
291  /// \param IntrinsicInfo - same as \p TRI.
292  void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
293  bool PrintDef, bool IsStandalone, bool ShouldPrintRegisterTies,
294  unsigned TiedOperandIdx, const TargetRegisterInfo *TRI,
295  const TargetIntrinsicInfo *IntrinsicInfo) const;
296 
297  /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level
298  /// type to be printed the same way the full version of print(...) does it.
299  void print(raw_ostream &os, LLT TypeToPrint,
300  const TargetRegisterInfo *TRI = nullptr,
301  const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
302 
303  void dump() const;
304 
305  //===--------------------------------------------------------------------===//
306  // Accessors that tell you what kind of MachineOperand you're looking at.
307  //===--------------------------------------------------------------------===//
308 
309  /// isReg - Tests if this is a MO_Register operand.
310  bool isReg() const { return OpKind == MO_Register; }
311  /// isImm - Tests if this is a MO_Immediate operand.
312  bool isImm() const { return OpKind == MO_Immediate; }
313  /// isCImm - Test if this is a MO_CImmediate operand.
314  bool isCImm() const { return OpKind == MO_CImmediate; }
315  /// isFPImm - Tests if this is a MO_FPImmediate operand.
316  bool isFPImm() const { return OpKind == MO_FPImmediate; }
317  /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
318  bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
319  /// isFI - Tests if this is a MO_FrameIndex operand.
320  bool isFI() const { return OpKind == MO_FrameIndex; }
321  /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
322  bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
323  /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
324  bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
325  /// isJTI - Tests if this is a MO_JumpTableIndex operand.
326  bool isJTI() const { return OpKind == MO_JumpTableIndex; }
327  /// isGlobal - Tests if this is a MO_GlobalAddress operand.
328  bool isGlobal() const { return OpKind == MO_GlobalAddress; }
329  /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
330  bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
331  /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
332  bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
333  /// isRegMask - Tests if this is a MO_RegisterMask operand.
334  bool isRegMask() const { return OpKind == MO_RegisterMask; }
335  /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
336  bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
337  /// isMetadata - Tests if this is a MO_Metadata operand.
338  bool isMetadata() const { return OpKind == MO_Metadata; }
339  bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
340  bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
341  bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
342  bool isPredicate() const { return OpKind == MO_Predicate; }
343  //===--------------------------------------------------------------------===//
344  // Accessors for Register Operands
345  //===--------------------------------------------------------------------===//
346 
347  /// getReg - Returns the register number.
348  unsigned getReg() const {
349  assert(isReg() && "This is not a register operand!");
350  return SmallContents.RegNo;
351  }
352 
353  unsigned getSubReg() const {
354  assert(isReg() && "Wrong MachineOperand accessor");
355  return SubReg_TargetFlags;
356  }
357 
358  bool isUse() const {
359  assert(isReg() && "Wrong MachineOperand accessor");
360  return !IsDef;
361  }
362 
363  bool isDef() const {
364  assert(isReg() && "Wrong MachineOperand accessor");
365  return IsDef;
366  }
367 
368  bool isImplicit() const {
369  assert(isReg() && "Wrong MachineOperand accessor");
370  return IsImp;
371  }
372 
373  bool isDead() const {
374  assert(isReg() && "Wrong MachineOperand accessor");
375  return IsDeadOrKill & IsDef;
376  }
377 
378  bool isKill() const {
379  assert(isReg() && "Wrong MachineOperand accessor");
380  return IsDeadOrKill & !IsDef;
381  }
382 
383  bool isUndef() const {
384  assert(isReg() && "Wrong MachineOperand accessor");
385  return IsUndef;
386  }
387 
388  /// isRenamable - Returns true if this register may be renamed, i.e. it does
389  /// not generate a value that is somehow read in a way that is not represented
390  /// by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only
391  /// valid on physical register operands. Virtual registers are assumed to
392  /// always be renamable regardless of the value of this field.
393  ///
394  /// Operands that are renamable can freely be changed to any other register
395  /// that is a member of the register class returned by
396  /// MI->getRegClassConstraint().
397  ///
398  /// isRenamable can return false for several different reasons:
399  ///
400  /// - ABI constraints (since liveness is not always precisely modeled). We
401  /// conservatively handle these cases by setting all physical register
402  /// operands that didn’t start out as virtual regs to not be renamable.
403  /// Also any physical register operands created after register allocation or
404  /// whose register is changed after register allocation will not be
405  /// renamable. This state is tracked in the MachineOperand::IsRenamable
406  /// bit.
407  ///
408  /// - Opcode/target constraints: for opcodes that have complex register class
409  /// requirements (e.g. that depend on other operands/instructions), we set
410  /// hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
411  /// description. Operands belonging to instructions with opcodes that are
412  /// marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
413  /// isRenamable(). Additionally, the AllowRegisterRenaming target property
414  /// prevents any operands from being marked renamable for targets that don't
415  /// have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
416  /// values.
417  bool isRenamable() const;
418 
419  bool isInternalRead() const {
420  assert(isReg() && "Wrong MachineOperand accessor");
421  return IsInternalRead;
422  }
423 
424  bool isEarlyClobber() const {
425  assert(isReg() && "Wrong MachineOperand accessor");
426  return IsEarlyClobber;
427  }
428 
429  bool isTied() const {
430  assert(isReg() && "Wrong MachineOperand accessor");
431  return TiedTo;
432  }
433 
434  bool isDebug() const {
435  assert(isReg() && "Wrong MachineOperand accessor");
436  return IsDebug;
437  }
438 
439  /// readsReg - Returns true if this operand reads the previous value of its
440  /// register. A use operand with the <undef> flag set doesn't read its
441  /// register. A sub-register def implicitly reads the other parts of the
442  /// register being redefined unless the <undef> flag is set.
443  ///
444  /// This refers to reading the register value from before the current
445  /// instruction or bundle. Internal bundle reads are not included.
446  bool readsReg() const {
447  assert(isReg() && "Wrong MachineOperand accessor");
448  return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
449  }
450 
451  //===--------------------------------------------------------------------===//
452  // Mutators for Register Operands
453  //===--------------------------------------------------------------------===//
454 
455  /// Change the register this operand corresponds to.
456  ///
457  void setReg(unsigned Reg);
458 
459  void setSubReg(unsigned subReg) {
460  assert(isReg() && "Wrong MachineOperand mutator");
461  SubReg_TargetFlags = subReg;
462  assert(SubReg_TargetFlags == subReg && "SubReg out of range");
463  }
464 
465  /// substVirtReg - Substitute the current register with the virtual
466  /// subregister Reg:SubReg. Take any existing SubReg index into account,
467  /// using TargetRegisterInfo to compose the subreg indices if necessary.
468  /// Reg must be a virtual register, SubIdx can be 0.
469  ///
470  void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&);
471 
472  /// substPhysReg - Substitute the current register with the physical register
473  /// Reg, taking any existing SubReg into account. For instance,
474  /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
475  ///
476  void substPhysReg(unsigned Reg, const TargetRegisterInfo&);
477 
478  void setIsUse(bool Val = true) { setIsDef(!Val); }
479 
480  /// Change a def to a use, or a use to a def.
481  void setIsDef(bool Val = true);
482 
483  void setImplicit(bool Val = true) {
484  assert(isReg() && "Wrong MachineOperand mutator");
485  IsImp = Val;
486  }
487 
488  void setIsKill(bool Val = true) {
489  assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
490  assert((!Val || !isDebug()) && "Marking a debug operation as kill");
491  IsDeadOrKill = Val;
492  }
493 
494  void setIsDead(bool Val = true) {
495  assert(isReg() && IsDef && "Wrong MachineOperand mutator");
496  IsDeadOrKill = Val;
497  }
498 
499  void setIsUndef(bool Val = true) {
500  assert(isReg() && "Wrong MachineOperand mutator");
501  IsUndef = Val;
502  }
503 
504  void setIsRenamable(bool Val = true);
505 
506  void setIsInternalRead(bool Val = true) {
507  assert(isReg() && "Wrong MachineOperand mutator");
508  IsInternalRead = Val;
509  }
510 
511  void setIsEarlyClobber(bool Val = true) {
512  assert(isReg() && IsDef && "Wrong MachineOperand mutator");
513  IsEarlyClobber = Val;
514  }
515 
516  void setIsDebug(bool Val = true) {
517  assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
518  IsDebug = Val;
519  }
520 
521  //===--------------------------------------------------------------------===//
522  // Accessors for various operand types.
523  //===--------------------------------------------------------------------===//
524 
525  int64_t getImm() const {
526  assert(isImm() && "Wrong MachineOperand accessor");
527  return Contents.ImmVal;
528  }
529 
530  const ConstantInt *getCImm() const {
531  assert(isCImm() && "Wrong MachineOperand accessor");
532  return Contents.CI;
533  }
534 
535  const ConstantFP *getFPImm() const {
536  assert(isFPImm() && "Wrong MachineOperand accessor");
537  return Contents.CFP;
538  }
539 
541  assert(isMBB() && "Wrong MachineOperand accessor");
542  return Contents.MBB;
543  }
544 
545  int getIndex() const {
546  assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
547  "Wrong MachineOperand accessor");
548  return Contents.OffsetedInfo.Val.Index;
549  }
550 
551  const GlobalValue *getGlobal() const {
552  assert(isGlobal() && "Wrong MachineOperand accessor");
553  return Contents.OffsetedInfo.Val.GV;
554  }
555 
556  const BlockAddress *getBlockAddress() const {
557  assert(isBlockAddress() && "Wrong MachineOperand accessor");
558  return Contents.OffsetedInfo.Val.BA;
559  }
560 
562  assert(isMCSymbol() && "Wrong MachineOperand accessor");
563  return Contents.Sym;
564  }
565 
566  unsigned getCFIIndex() const {
567  assert(isCFIIndex() && "Wrong MachineOperand accessor");
568  return Contents.CFIIndex;
569  }
570 
572  assert(isIntrinsicID() && "Wrong MachineOperand accessor");
573  return Contents.IntrinsicID;
574  }
575 
576  unsigned getPredicate() const {
577  assert(isPredicate() && "Wrong MachineOperand accessor");
578  return Contents.Pred;
579  }
580 
581  /// Return the offset from the symbol in this operand. This always returns 0
582  /// for ExternalSymbol operands.
583  int64_t getOffset() const {
584  assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
585  isTargetIndex() || isBlockAddress()) &&
586  "Wrong MachineOperand accessor");
587  return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
588  SmallContents.OffsetLo;
589  }
590 
591  const char *getSymbolName() const {
592  assert(isSymbol() && "Wrong MachineOperand accessor");
593  return Contents.OffsetedInfo.Val.SymbolName;
594  }
595 
596  /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
597  /// It is sometimes necessary to detach the register mask pointer from its
598  /// machine operand. This static method can be used for such detached bit
599  /// mask pointers.
600  static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
601  // See TargetRegisterInfo.h.
602  assert(PhysReg < (1u << 30) && "Not a physical register");
603  return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
604  }
605 
606  /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
607  bool clobbersPhysReg(unsigned PhysReg) const {
608  return clobbersPhysReg(getRegMask(), PhysReg);
609  }
610 
611  /// getRegMask - Returns a bit mask of registers preserved by this RegMask
612  /// operand.
613  const uint32_t *getRegMask() const {
614  assert(isRegMask() && "Wrong MachineOperand accessor");
615  return Contents.RegMask;
616  }
617 
618  /// Returns number of elements needed for a regmask array.
619  static unsigned getRegMaskSize(unsigned NumRegs) {
620  return (NumRegs + 31) / 32;
621  }
622 
623  /// getRegLiveOut - Returns a bit mask of live-out registers.
624  const uint32_t *getRegLiveOut() const {
625  assert(isRegLiveOut() && "Wrong MachineOperand accessor");
626  return Contents.RegMask;
627  }
628 
629  const MDNode *getMetadata() const {
630  assert(isMetadata() && "Wrong MachineOperand accessor");
631  return Contents.MD;
632  }
633 
634  //===--------------------------------------------------------------------===//
635  // Mutators for various operand types.
636  //===--------------------------------------------------------------------===//
637 
638  void setImm(int64_t immVal) {
639  assert(isImm() && "Wrong MachineOperand mutator");
640  Contents.ImmVal = immVal;
641  }
642 
643  void setCImm(const ConstantInt *CI) {
644  assert(isCImm() && "Wrong MachineOperand mutator");
645  Contents.CI = CI;
646  }
647 
648  void setFPImm(const ConstantFP *CFP) {
649  assert(isFPImm() && "Wrong MachineOperand mutator");
650  Contents.CFP = CFP;
651  }
652 
653  void setOffset(int64_t Offset) {
654  assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||
655  isTargetIndex() || isBlockAddress()) &&
656  "Wrong MachineOperand mutator");
657  SmallContents.OffsetLo = unsigned(Offset);
658  Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
659  }
660 
661  void setIndex(int Idx) {
662  assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
663  "Wrong MachineOperand mutator");
664  Contents.OffsetedInfo.Val.Index = Idx;
665  }
666 
667  void setMetadata(const MDNode *MD) {
668  assert(isMetadata() && "Wrong MachineOperand mutator");
669  Contents.MD = MD;
670  }
671 
673  assert(isMBB() && "Wrong MachineOperand mutator");
674  Contents.MBB = MBB;
675  }
676 
677  /// Sets value of register mask operand referencing Mask. The
678  /// operand does not take ownership of the memory referenced by Mask, it must
679  /// remain valid for the lifetime of the operand. See CreateRegMask().
680  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
681  void setRegMask(const uint32_t *RegMaskPtr) {
682  assert(isRegMask() && "Wrong MachineOperand mutator");
683  Contents.RegMask = RegMaskPtr;
684  }
685 
686  //===--------------------------------------------------------------------===//
687  // Other methods.
688  //===--------------------------------------------------------------------===//
689 
690  /// Returns true if this operand is identical to the specified operand except
691  /// for liveness related flags (isKill, isUndef and isDead). Note that this
692  /// should stay in sync with the hash_value overload below.
693  bool isIdenticalTo(const MachineOperand &Other) const;
694 
695  /// MachineOperand hash_value overload.
696  ///
697  /// Note that this includes the same information in the hash that
698  /// isIdenticalTo uses for comparison. It is thus suited for use in hash
699  /// tables which use that function for equality comparisons only. This must
700  /// stay exactly in sync with isIdenticalTo above.
701  friend hash_code hash_value(const MachineOperand &MO);
702 
703  /// ChangeToImmediate - Replace this operand with a new immediate operand of
704  /// the specified value. If an operand is known to be an immediate already,
705  /// the setImm method should be used.
706  void ChangeToImmediate(int64_t ImmVal);
707 
708  /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
709  /// of the specified value. If an operand is known to be an FP immediate
710  /// already, the setFPImm method should be used.
711  void ChangeToFPImmediate(const ConstantFP *FPImm);
712 
713  /// ChangeToES - Replace this operand with a new external symbol operand.
714  void ChangeToES(const char *SymName, unsigned char TargetFlags = 0);
715 
716  /// ChangeToGA - Replace this operand with a new global address operand.
717  void ChangeToGA(const GlobalValue *GV, int64_t Offset,
718  unsigned char TargetFlags = 0);
719 
720  /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
721  void ChangeToMCSymbol(MCSymbol *Sym);
722 
723  /// Replace this operand with a frame index.
724  void ChangeToFrameIndex(int Idx);
725 
726  /// Replace this operand with a target index.
727  void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
728  unsigned char TargetFlags = 0);
729 
730  /// ChangeToRegister - Replace this operand with a new register operand of
731  /// the specified value. If an operand is known to be an register already,
732  /// the setReg method should be used.
733  void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
734  bool isKill = false, bool isDead = false,
735  bool isUndef = false, bool isDebug = false);
736 
737  //===--------------------------------------------------------------------===//
738  // Construction methods.
739  //===--------------------------------------------------------------------===//
740 
741  static MachineOperand CreateImm(int64_t Val) {
743  Op.setImm(Val);
744  return Op;
745  }
746 
749  Op.Contents.CI = CI;
750  return Op;
751  }
752 
755  Op.Contents.CFP = CFP;
756  return Op;
757  }
758 
759  static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
760  bool isKill = false, bool isDead = false,
761  bool isUndef = false,
762  bool isEarlyClobber = false,
763  unsigned SubReg = 0, bool isDebug = false,
764  bool isInternalRead = false,
765  bool isRenamable = false) {
766  assert(!(isDead && !isDef) && "Dead flag on non-def");
767  assert(!(isKill && isDef) && "Kill flag on def");
769  Op.IsDef = isDef;
770  Op.IsImp = isImp;
771  Op.IsDeadOrKill = isKill | isDead;
772  Op.IsRenamable = isRenamable;
773  Op.IsUndef = isUndef;
774  Op.IsInternalRead = isInternalRead;
775  Op.IsEarlyClobber = isEarlyClobber;
776  Op.TiedTo = 0;
777  Op.IsDebug = isDebug;
778  Op.SmallContents.RegNo = Reg;
779  Op.Contents.Reg.Prev = nullptr;
780  Op.Contents.Reg.Next = nullptr;
781  Op.setSubReg(SubReg);
782  return Op;
783  }
785  unsigned char TargetFlags = 0) {
787  Op.setMBB(MBB);
789  return Op;
790  }
791  static MachineOperand CreateFI(int Idx) {
793  Op.setIndex(Idx);
794  return Op;
795  }
796  static MachineOperand CreateCPI(unsigned Idx, int Offset,
797  unsigned char TargetFlags = 0) {
799  Op.setIndex(Idx);
800  Op.setOffset(Offset);
802  return Op;
803  }
804  static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
805  unsigned char TargetFlags = 0) {
807  Op.setIndex(Idx);
808  Op.setOffset(Offset);
810  return Op;
811  }
812  static MachineOperand CreateJTI(unsigned Idx, unsigned char TargetFlags = 0) {
814  Op.setIndex(Idx);
816  return Op;
817  }
818  static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
819  unsigned char TargetFlags = 0) {
821  Op.Contents.OffsetedInfo.Val.GV = GV;
822  Op.setOffset(Offset);
824  return Op;
825  }
826  static MachineOperand CreateES(const char *SymName,
827  unsigned char TargetFlags = 0) {
829  Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
830  Op.setOffset(0); // Offset is always 0.
832  return Op;
833  }
834  static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
835  unsigned char TargetFlags = 0) {
837  Op.Contents.OffsetedInfo.Val.BA = BA;
838  Op.setOffset(Offset);
840  return Op;
841  }
842  /// CreateRegMask - Creates a register mask operand referencing Mask. The
843  /// operand does not take ownership of the memory referenced by Mask, it
844  /// must remain valid for the lifetime of the operand.
845  ///
846  /// A RegMask operand represents a set of non-clobbered physical registers
847  /// on an instruction that clobbers many registers, typically a call. The
848  /// bit mask has a bit set for each physreg that is preserved by this
849  /// instruction, as described in the documentation for
850  /// TargetRegisterInfo::getCallPreservedMask().
851  ///
852  /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
853  ///
855  assert(Mask && "Missing register mask");
857  Op.Contents.RegMask = Mask;
858  return Op;
859  }
861  assert(Mask && "Missing live-out register mask");
863  Op.Contents.RegMask = Mask;
864  return Op;
865  }
866  static MachineOperand CreateMetadata(const MDNode *Meta) {
868  Op.Contents.MD = Meta;
869  return Op;
870  }
871 
873  unsigned char TargetFlags = 0) {
875  Op.Contents.Sym = Sym;
876  Op.setOffset(0);
878  return Op;
879  }
880 
883  Op.Contents.CFIIndex = CFIIndex;
884  return Op;
885  }
886 
889  Op.Contents.IntrinsicID = ID;
890  return Op;
891  }
892 
895  Op.Contents.Pred = Pred;
896  return Op;
897  }
898 
899  friend class MachineInstr;
900  friend class MachineRegisterInfo;
901 
902 private:
903  // If this operand is currently a register operand, and if this is in a
904  // function, deregister the operand from the register's use/def list.
905  void removeRegFromUses();
906 
907  /// Artificial kinds for DenseMap usage.
908  enum : unsigned char {
909  MO_Empty = MO_Last + 1,
910  MO_Tombstone,
911  };
912 
913  friend struct DenseMapInfo<MachineOperand>;
914 
915  //===--------------------------------------------------------------------===//
916  // Methods for handling register use/def lists.
917  //===--------------------------------------------------------------------===//
918 
919  /// isOnRegUseList - Return true if this operand is on a register use/def
920  /// list or false if not. This can only be called for register operands
921  /// that are part of a machine instruction.
922  bool isOnRegUseList() const {
923  assert(isReg() && "Can only add reg operand to use lists");
924  return Contents.Reg.Prev != nullptr;
925  }
926 };
927 
928 template <> struct DenseMapInfo<MachineOperand> {
930  return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
931  MachineOperand::MO_Empty));
932  }
934  return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
935  MachineOperand::MO_Tombstone));
936  }
937  static unsigned getHashValue(const MachineOperand &MO) {
938  return hash_value(MO);
939  }
940  static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
941  if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
942  MachineOperand::MO_Empty) ||
943  LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
944  MachineOperand::MO_Tombstone))
945  return LHS.getType() == RHS.getType();
946  return LHS.isIdenticalTo(RHS);
947  }
948 };
949 
951  MO.print(OS);
952  return OS;
953 }
954 
955 // See friend declaration above. This additional declaration is required in
956 // order to compile LLVM with IBM xlC compiler.
958 } // namespace llvm
959 
960 #endif
unsigned getTargetFlags() const
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
static MachineOperand getTombstoneKey()
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static MachineOperand CreateCImm(const ConstantInt *CI)
MachineBasicBlock * getMBB() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned char TargetFlags=0)
void setTargetFlags(unsigned F)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
const uint32_t * RegMask
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
void setFPImm(const ConstantFP *CFP)
bool isRegLiveOut() const
isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
bool isTargetIndex() const
isTargetIndex - Tests if this is a MO_TargetIndex operand.
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
static MachineOperand CreateJTI(unsigned Idx, unsigned char TargetFlags=0)
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
unsigned getReg() const
getReg - Returns the register number.
void setIsUndef(bool Val=true)
Intrinsic::ID IntrinsicID
Address of indexed Jump Table for switch.
unsigned getSubReg() const
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
MachineBasicBlock reference.
unsigned const TargetRegisterInfo * TRI
Metadata node.
Definition: Metadata.h:863
void setIsDead(bool Val=true)
F(f)
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:684
Manage lifetime of a slot tracker for printing IR.
Mask of live-out registers.
void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
const ConstantFP * CFP
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setIsRenamable(bool Val=true)
bool isInternalRead() const
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Mask of preserved registers.
bool isEarlyClobber() const
void ChangeToMCSymbol(MCSymbol *Sym)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
bool isIntrinsicID() const
The address of a basic block.
Definition: Constants.h:839
bool isCFIIndex() const
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned char TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
MCCFIInstruction index.
const ConstantFP * getFPImm() const
void ChangeToES(const char *SymName, unsigned char TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Target-dependent index+offset operand.
void setImplicit(bool Val=true)
unsigned SubReg
Name of external global symbol.
void setIndex(int Idx)
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
const char * getSymbolName() const
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
ELFYAML::ELF_STO Other
Definition: ELFYAML.cpp:851
unsigned getCFIIndex() const
void setIsEarlyClobber(bool Val=true)
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
Immediate >64bit operand.
void setRegMask(const uint32_t *RegMaskPtr)
Sets value of register mask operand referencing Mask.
struct llvm::MachineOperand::@168::@170 Reg
void clearParent()
clearParent - Reset the parent pointer.
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
bool isPredicate() const
static MachineOperand CreatePredicate(unsigned Pred)
const GlobalValue * GV
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Address of a global value.
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned char TargetFlags=0)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
const GlobalValue * getGlobal() const
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
void setMBB(MachineBasicBlock *MBB)
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned char TargetFlags=0)
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Address of a basic block.
union llvm::MachineOperand::@168::@171::@172 Val
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
void setImm(int64_t immVal)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned char TargetFlags=0)
void setIsInternalRead(bool Val=true)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned char TargetFlags=0)
static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS)
void setOffset(int64_t Offset)
bool clobbersPhysReg(unsigned PhysReg) const
clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isMCSymbol() const
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
void setIsKill(bool Val=true)
TargetIntrinsicInfo - Interface to description of machine instruction set.
const ConstantInt * CI
static MachineOperand getEmptyKey()
static MachineOperand CreateMetadata(const MDNode *Meta)
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Generic predicate for ISel.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
MachineBasicBlock * MBB
MachineOperand class - Representation of each machine instruction operand.
Intrinsic::ID getIntrinsicID() const
void ChangeToFPImmediate(const ConstantFP *FPImm)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value...
int64_t getImm() const
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
void setMetadata(const MDNode *MD)
friend hash_code hash_value(const MachineOperand &MO)
MachineOperand hash_value overload.
MCSymbol reference (for debug/eh info)
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
static MachineOperand CreateES(const char *SymName, unsigned char TargetFlags=0)
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
An opaque object representing a hash code.
Definition: Hashing.h:71
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
void addTargetFlag(unsigned F)
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0)
MachineOperand * Prev
static unsigned getHashValue(const MachineOperand &MO)
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
int64_t getOffset() const
Return the offset from the symbol in this operand.
const BlockAddress * getBlockAddress() const
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
void setIsUse(bool Val=true)
void setSubReg(unsigned subReg)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void setCImm(const ConstantInt *CI)
Abstract Stack Frame Index.
const BlockAddress * BA
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:2038
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned char TargetFlags=0)
Replace this operand with a target index.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCSymbol * getMCSymbol() const
Floating-point immediate operand.
const char * SymbolName
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
MachineOperand * Next
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Address of indexed Constant in Constant Pool.
void setIsDebug(bool Val=true)
const ConstantInt * getCImm() const
struct llvm::MachineOperand::@168::@171 OffsetedInfo
OffsetedInfo - This struct contains the offset and an object identifier.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MachineOperand CreateFI(int Idx)
const MDNode * getMetadata() const
bool isImplicit() const
Metadata reference (for debug info)
const MachineInstr * getParent() const
unsigned getPredicate() const