LLVM  17.0.0git
MachineOperand.cpp
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1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/FoldingSet.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
24 #include "llvm/Config/llvm-config.h"
25 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/Instructions.h"
29 #include "llvm/MC/MCDwarf.h"
32 #include <optional>
33 
34 using namespace llvm;
35 
36 static cl::opt<int>
37  PrintRegMaskNumRegs("print-regmask-num-regs",
38  cl::desc("Number of registers to limit to when "
39  "printing regmask operands in IR dumps. "
40  "unlimited = -1"),
41  cl::init(32), cl::Hidden);
42 
44  if (const MachineInstr *MI = MO.getParent())
45  if (const MachineBasicBlock *MBB = MI->getParent())
46  if (const MachineFunction *MF = MBB->getParent())
47  return MF;
48  return nullptr;
49 }
50 
52  return const_cast<MachineFunction *>(
53  getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
54 }
55 
57  if (getReg() == Reg)
58  return; // No change.
59 
60  // Clear the IsRenamable bit to keep it conservatively correct.
61  IsRenamable = false;
62 
63  // Otherwise, we have to change the register. If this operand is embedded
64  // into a machine function, we need to update the old and new register's
65  // use/def lists.
66  if (MachineFunction *MF = getMFIfAvailable(*this)) {
67  MachineRegisterInfo &MRI = MF->getRegInfo();
69  SmallContents.RegNo = Reg;
71  return;
72  }
73 
74  // Otherwise, just change the register, no problem. :)
75  SmallContents.RegNo = Reg;
76 }
77 
79  const TargetRegisterInfo &TRI) {
80  assert(Reg.isVirtual());
81  if (SubIdx && getSubReg())
82  SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
83  setReg(Reg);
84  if (SubIdx)
85  setSubReg(SubIdx);
86 }
87 
90  if (getSubReg()) {
92  // Note that getSubReg() may return 0 if the sub-register doesn't exist.
93  // That won't happen in legal code.
94  setSubReg(0);
95  if (isDef())
96  setIsUndef(false);
97  }
98  setReg(Reg);
99 }
100 
101 /// Change a def to a use, or a use to a def.
102 void MachineOperand::setIsDef(bool Val) {
103  assert(isReg() && "Wrong MachineOperand accessor");
104  assert((!Val || !isDebug()) && "Marking a debug operation as def");
105  if (IsDef == Val)
106  return;
107  assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
108  // MRI may keep uses and defs in different list positions.
109  if (MachineFunction *MF = getMFIfAvailable(*this)) {
110  MachineRegisterInfo &MRI = MF->getRegInfo();
112  IsDef = Val;
114  return;
115  }
116  IsDef = Val;
117 }
118 
120  assert(isReg() && "Wrong MachineOperand accessor");
121  assert(getReg().isPhysical() &&
122  "isRenamable should only be checked on physical registers");
123  if (!IsRenamable)
124  return false;
125 
126  const MachineInstr *MI = getParent();
127  if (!MI)
128  return true;
129 
130  if (isDef())
131  return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
132 
133  assert(isUse() && "Reg is not def or use");
134  return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
135 }
136 
138  assert(isReg() && "Wrong MachineOperand accessor");
139  assert(getReg().isPhysical() &&
140  "setIsRenamable should only be called on physical registers");
141  IsRenamable = Val;
142 }
143 
144 // If this operand is currently a register operand, and if this is in a
145 // function, deregister the operand from the register's use/def list.
146 void MachineOperand::removeRegFromUses() {
147  if (!isReg() || !isOnRegUseList())
148  return;
149 
150  if (MachineFunction *MF = getMFIfAvailable(*this))
151  MF->getRegInfo().removeRegOperandFromUseList(this);
152 }
153 
154 /// ChangeToImmediate - Replace this operand with a new immediate operand of
155 /// the specified value. If an operand is known to be an immediate already,
156 /// the setImm method should be used.
157 void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
158  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
159 
160  removeRegFromUses();
161 
162  OpKind = MO_Immediate;
163  Contents.ImmVal = ImmVal;
164  setTargetFlags(TargetFlags);
165 }
166 
168  unsigned TargetFlags) {
169  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
170 
171  removeRegFromUses();
172 
173  OpKind = MO_FPImmediate;
174  Contents.CFP = FPImm;
175  setTargetFlags(TargetFlags);
176 }
177 
178 void MachineOperand::ChangeToES(const char *SymName,
179  unsigned TargetFlags) {
180  assert((!isReg() || !isTied()) &&
181  "Cannot change a tied operand into an external symbol");
182 
183  removeRegFromUses();
184 
185  OpKind = MO_ExternalSymbol;
186  Contents.OffsetedInfo.Val.SymbolName = SymName;
187  setOffset(0); // Offset is always 0.
188  setTargetFlags(TargetFlags);
189 }
190 
192  unsigned TargetFlags) {
193  assert((!isReg() || !isTied()) &&
194  "Cannot change a tied operand into a global address");
195 
196  removeRegFromUses();
197 
198  OpKind = MO_GlobalAddress;
199  Contents.OffsetedInfo.Val.GV = GV;
200  setOffset(Offset);
201  setTargetFlags(TargetFlags);
202 }
203 
204 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
205  assert((!isReg() || !isTied()) &&
206  "Cannot change a tied operand into an MCSymbol");
207 
208  removeRegFromUses();
209 
210  OpKind = MO_MCSymbol;
211  Contents.Sym = Sym;
212  setTargetFlags(TargetFlags);
213 }
214 
215 void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
216  assert((!isReg() || !isTied()) &&
217  "Cannot change a tied operand into a FrameIndex");
218 
219  removeRegFromUses();
220 
221  OpKind = MO_FrameIndex;
222  setIndex(Idx);
223  setTargetFlags(TargetFlags);
224 }
225 
226 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
227  unsigned TargetFlags) {
228  assert((!isReg() || !isTied()) &&
229  "Cannot change a tied operand into a FrameIndex");
230 
231  removeRegFromUses();
232 
233  OpKind = MO_TargetIndex;
234  setIndex(Idx);
235  setOffset(Offset);
236  setTargetFlags(TargetFlags);
237 }
238 
239 void MachineOperand::ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx,
240  unsigned TargetFlags) {
241  assert((!isReg() || !isTied()) &&
242  "Cannot change a tied operand into a DbgInstrRef");
243 
244  removeRegFromUses();
245 
246  OpKind = MO_DbgInstrRef;
247  setInstrRefInstrIndex(InstrIdx);
248  setInstrRefOpIndex(OpIdx);
249  setTargetFlags(TargetFlags);
250 }
251 
252 /// ChangeToRegister - Replace this operand with a new register operand of
253 /// the specified value. If an operand is known to be an register already,
254 /// the setReg method should be used.
255 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
256  bool isKill, bool isDead, bool isUndef,
257  bool isDebug) {
258  MachineRegisterInfo *RegInfo = nullptr;
259  if (MachineFunction *MF = getMFIfAvailable(*this))
260  RegInfo = &MF->getRegInfo();
261  // If this operand is already a register operand, remove it from the
262  // register's use/def lists.
263  bool WasReg = isReg();
264  if (RegInfo && WasReg)
265  RegInfo->removeRegOperandFromUseList(this);
266 
267  // Ensure debug instructions set debug flag on register uses.
268  const MachineInstr *MI = getParent();
269  if (!isDef && MI && MI->isDebugInstr())
270  isDebug = true;
271 
272  // Change this to a register and set the reg#.
273  assert(!(isDead && !isDef) && "Dead flag on non-def");
274  assert(!(isKill && isDef) && "Kill flag on def");
275  OpKind = MO_Register;
276  SmallContents.RegNo = Reg;
277  SubReg_TargetFlags = 0;
278  IsDef = isDef;
279  IsImp = isImp;
280  IsDeadOrKill = isKill | isDead;
281  IsRenamable = false;
282  IsUndef = isUndef;
283  IsInternalRead = false;
284  IsEarlyClobber = false;
285  IsDebug = isDebug;
286  // Ensure isOnRegUseList() returns false.
287  Contents.Reg.Prev = nullptr;
288  // Preserve the tie when the operand was already a register.
289  if (!WasReg)
290  TiedTo = 0;
291 
292  // If this operand is embedded in a function, add the operand to the
293  // register's use/def list.
294  if (RegInfo)
295  RegInfo->addRegOperandToUseList(this);
296 }
297 
298 /// isIdenticalTo - Return true if this operand is identical to the specified
299 /// operand. Note that this should stay in sync with the hash_value overload
300 /// below.
302  if (getType() != Other.getType() ||
303  getTargetFlags() != Other.getTargetFlags())
304  return false;
305 
306  switch (getType()) {
308  return getReg() == Other.getReg() && isDef() == Other.isDef() &&
309  getSubReg() == Other.getSubReg();
311  return getImm() == Other.getImm();
313  return getCImm() == Other.getCImm();
315  return getFPImm() == Other.getFPImm();
317  return getMBB() == Other.getMBB();
319  return getIndex() == Other.getIndex();
322  return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
324  return getIndex() == Other.getIndex();
326  return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
328  return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
329  getOffset() == Other.getOffset();
331  return getBlockAddress() == Other.getBlockAddress() &&
332  getOffset() == Other.getOffset();
335  // Shallow compare of the two RegMasks
336  const uint32_t *RegMask = getRegMask();
337  const uint32_t *OtherRegMask = Other.getRegMask();
338  if (RegMask == OtherRegMask)
339  return true;
340 
341  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
342  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
343  unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
344  // Deep compare of the two RegMasks
345  return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
346  }
347  // We don't know the size of the RegMask, so we can't deep compare the two
348  // reg masks.
349  return false;
350  }
352  return getMCSymbol() == Other.getMCSymbol();
354  return getInstrRefInstrIndex() == Other.getInstrRefInstrIndex() &&
355  getInstrRefOpIndex() == Other.getInstrRefOpIndex();
357  return getCFIIndex() == Other.getCFIIndex();
359  return getMetadata() == Other.getMetadata();
361  return getIntrinsicID() == Other.getIntrinsicID();
363  return getPredicate() == Other.getPredicate();
365  return getShuffleMask() == Other.getShuffleMask();
366  }
367  llvm_unreachable("Invalid machine operand type");
368 }
369 
370 // Note: this must stay exactly in sync with isIdenticalTo above.
372  switch (MO.getType()) {
374  // Register operands don't have target flags.
375  return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
377  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
379  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
381  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
383  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
385  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
388  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
389  MO.getOffset());
391  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
393  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
394  StringRef(MO.getSymbolName()));
396  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
397  MO.getOffset());
399  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
400  MO.getOffset());
403  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
404  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
405  unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
406  const uint32_t *RegMask = MO.getRegMask();
407  std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize);
408  return hash_combine(MO.getType(), MO.getTargetFlags(),
409  stable_hash_combine_array(RegMaskHashes.data(),
410  RegMaskHashes.size()));
411  }
412 
413  assert(0 && "MachineOperand not associated with any MachineFunction");
414  return hash_combine(MO.getType(), MO.getTargetFlags());
415  }
417  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
419  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
421  return hash_combine(MO.getType(), MO.getTargetFlags(),
424  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
426  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
428  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
430  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
431  }
432  llvm_unreachable("Invalid machine operand type");
433 }
434 
435 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
436 // it.
437 static void tryToGetTargetInfo(const MachineOperand &MO,
438  const TargetRegisterInfo *&TRI,
439  const TargetIntrinsicInfo *&IntrinsicInfo) {
440  if (const MachineFunction *MF = getMFIfAvailable(MO)) {
441  TRI = MF->getSubtarget().getRegisterInfo();
442  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
443  }
444 }
445 
446 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
447  const auto *TII = MF.getSubtarget().getInstrInfo();
448  assert(TII && "expected instruction info");
449  auto Indices = TII->getSerializableTargetIndices();
450  auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
451  return I.first == Index;
452  });
453  if (Found != Indices.end())
454  return Found->second;
455  return nullptr;
456 }
457 
459  const MachineFunction *MF = getMFIfAvailable(*this);
460  return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
461 }
462 
463 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
465  for (const auto &I : Flags) {
466  if (I.first == TF) {
467  return I.second;
468  }
469  }
470  return nullptr;
471 }
472 
473 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
474  const TargetRegisterInfo *TRI) {
475  if (!TRI) {
476  OS << "%dwarfreg." << DwarfReg;
477  return;
478  }
479 
480  if (std::optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
481  OS << printReg(*Reg, TRI);
482  else
483  OS << "<badreg>";
484 }
485 
487  ModuleSlotTracker &MST) {
488  OS << "%ir-block.";
489  if (BB.hasName()) {
490  printLLVMNameWithoutPrefix(OS, BB.getName());
491  return;
492  }
493  std::optional<int> Slot;
494  if (const Function *F = BB.getParent()) {
495  if (F == MST.getCurrentFunction()) {
496  Slot = MST.getLocalSlot(&BB);
497  } else if (const Module *M = F->getParent()) {
498  ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
499  CustomMST.incorporateFunction(*F);
500  Slot = CustomMST.getLocalSlot(&BB);
501  }
502  }
503  if (Slot)
505  else
506  OS << "<unknown>";
507 }
508 
510  SyncScope::ID SSID,
512  switch (SSID) {
513  case SyncScope::System:
514  break;
515  default:
516  if (SSNs.empty())
518 
519  OS << "syncscope(\"";
520  printEscapedString(SSNs[SSID], OS);
521  OS << "\") ";
522  break;
523  }
524 }
525 
526 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
527  unsigned TMMOFlag) {
528  auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
529  for (const auto &I : Flags) {
530  if (I.first == TMMOFlag) {
531  return I.second;
532  }
533  }
534  return nullptr;
535 }
536 
537 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
538  const MachineFrameInfo *MFI) {
539  StringRef Name;
540  if (MFI) {
541  IsFixed = MFI->isFixedObjectIndex(FrameIndex);
542  if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
543  if (Alloca->hasName())
544  Name = Alloca->getName();
545  if (IsFixed)
547  }
549 }
550 
552  const TargetRegisterInfo *TRI) {
553  OS << "%subreg.";
554  if (TRI && Index != 0 && Index < TRI->getNumSubRegIndices())
555  OS << TRI->getSubRegIndexName(Index);
556  else
557  OS << Index;
558 }
559 
561  const MachineOperand &Op) {
562  if (!Op.getTargetFlags())
563  return;
564  const MachineFunction *MF = getMFIfAvailable(Op);
565  if (!MF)
566  return;
567 
568  const auto *TII = MF->getSubtarget().getInstrInfo();
569  assert(TII && "expected instruction info");
570  auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
571  OS << "target-flags(";
572  const bool HasDirectFlags = Flags.first;
573  const bool HasBitmaskFlags = Flags.second;
574  if (!HasDirectFlags && !HasBitmaskFlags) {
575  OS << "<unknown>) ";
576  return;
577  }
578  if (HasDirectFlags) {
579  if (const auto *Name = getTargetFlagName(TII, Flags.first))
580  OS << Name;
581  else
582  OS << "<unknown target flag>";
583  }
584  if (!HasBitmaskFlags) {
585  OS << ") ";
586  return;
587  }
588  bool IsCommaNeeded = HasDirectFlags;
589  unsigned BitMask = Flags.second;
591  for (const auto &Mask : BitMasks) {
592  // Check if the flag's bitmask has the bits of the current mask set.
593  if ((BitMask & Mask.first) == Mask.first) {
594  if (IsCommaNeeded)
595  OS << ", ";
596  IsCommaNeeded = true;
597  OS << Mask.second;
598  // Clear the bits which were serialized from the flag's bitmask.
599  BitMask &= ~(Mask.first);
600  }
601  }
602  if (BitMask) {
603  // When the resulting flag's bitmask isn't zero, we know that we didn't
604  // serialize all of the bit flags.
605  if (IsCommaNeeded)
606  OS << ", ";
607  OS << "<unknown bitmask target flag>";
608  }
609  OS << ") ";
610 }
611 
613  OS << "<mcsymbol " << Sym << ">";
614 }
615 
617  unsigned FrameIndex,
618  bool IsFixed, StringRef Name) {
619  if (IsFixed) {
620  OS << "%fixed-stack." << FrameIndex;
621  return;
622  }
623 
624  OS << "%stack." << FrameIndex;
625  if (!Name.empty())
626  OS << '.' << Name;
627 }
628 
630  if (Offset == 0)
631  return;
632  if (Offset < 0) {
633  OS << " - " << -Offset;
634  return;
635  }
636  OS << " + " << Offset;
637 }
638 
640  if (Slot == -1)
641  OS << "<badref>";
642  else
643  OS << Slot;
644 }
645 
646 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
647  const TargetRegisterInfo *TRI) {
648  switch (CFI.getOperation()) {
650  OS << "same_value ";
651  if (MCSymbol *Label = CFI.getLabel())
652  MachineOperand::printSymbol(OS, *Label);
653  printCFIRegister(CFI.getRegister(), OS, TRI);
654  break;
656  OS << "remember_state ";
657  if (MCSymbol *Label = CFI.getLabel())
658  MachineOperand::printSymbol(OS, *Label);
659  break;
661  OS << "restore_state ";
662  if (MCSymbol *Label = CFI.getLabel())
663  MachineOperand::printSymbol(OS, *Label);
664  break;
666  OS << "offset ";
667  if (MCSymbol *Label = CFI.getLabel())
668  MachineOperand::printSymbol(OS, *Label);
669  printCFIRegister(CFI.getRegister(), OS, TRI);
670  OS << ", " << CFI.getOffset();
671  break;
673  OS << "def_cfa_register ";
674  if (MCSymbol *Label = CFI.getLabel())
675  MachineOperand::printSymbol(OS, *Label);
676  printCFIRegister(CFI.getRegister(), OS, TRI);
677  break;
679  OS << "def_cfa_offset ";
680  if (MCSymbol *Label = CFI.getLabel())
681  MachineOperand::printSymbol(OS, *Label);
682  OS << CFI.getOffset();
683  break;
685  OS << "def_cfa ";
686  if (MCSymbol *Label = CFI.getLabel())
687  MachineOperand::printSymbol(OS, *Label);
688  printCFIRegister(CFI.getRegister(), OS, TRI);
689  OS << ", " << CFI.getOffset();
690  break;
692  OS << "llvm_def_aspace_cfa ";
693  if (MCSymbol *Label = CFI.getLabel())
694  MachineOperand::printSymbol(OS, *Label);
695  printCFIRegister(CFI.getRegister(), OS, TRI);
696  OS << ", " << CFI.getOffset();
697  OS << ", " << CFI.getAddressSpace();
698  break;
700  OS << "rel_offset ";
701  if (MCSymbol *Label = CFI.getLabel())
702  MachineOperand::printSymbol(OS, *Label);
703  printCFIRegister(CFI.getRegister(), OS, TRI);
704  OS << ", " << CFI.getOffset();
705  break;
707  OS << "adjust_cfa_offset ";
708  if (MCSymbol *Label = CFI.getLabel())
709  MachineOperand::printSymbol(OS, *Label);
710  OS << CFI.getOffset();
711  break;
713  OS << "restore ";
714  if (MCSymbol *Label = CFI.getLabel())
715  MachineOperand::printSymbol(OS, *Label);
716  printCFIRegister(CFI.getRegister(), OS, TRI);
717  break;
719  OS << "escape ";
720  if (MCSymbol *Label = CFI.getLabel())
721  MachineOperand::printSymbol(OS, *Label);
722  if (!CFI.getValues().empty()) {
723  size_t e = CFI.getValues().size() - 1;
724  for (size_t i = 0; i < e; ++i)
725  OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
726  OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
727  }
728  break;
729  }
731  OS << "undefined ";
732  if (MCSymbol *Label = CFI.getLabel())
733  MachineOperand::printSymbol(OS, *Label);
734  printCFIRegister(CFI.getRegister(), OS, TRI);
735  break;
737  OS << "register ";
738  if (MCSymbol *Label = CFI.getLabel())
739  MachineOperand::printSymbol(OS, *Label);
740  printCFIRegister(CFI.getRegister(), OS, TRI);
741  OS << ", ";
742  printCFIRegister(CFI.getRegister2(), OS, TRI);
743  break;
745  OS << "window_save ";
746  if (MCSymbol *Label = CFI.getLabel())
747  MachineOperand::printSymbol(OS, *Label);
748  break;
750  OS << "negate_ra_sign_state ";
751  if (MCSymbol *Label = CFI.getLabel())
752  MachineOperand::printSymbol(OS, *Label);
753  break;
754  default:
755  // TODO: Print the other CFI Operations.
756  OS << "<unserializable cfi directive>";
757  break;
758  }
759 }
760 
762  const TargetIntrinsicInfo *IntrinsicInfo) const {
763  print(OS, LLT{}, TRI, IntrinsicInfo);
764 }
765 
766 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
767  const TargetRegisterInfo *TRI,
768  const TargetIntrinsicInfo *IntrinsicInfo) const {
769  tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
770  ModuleSlotTracker DummyMST(nullptr);
771  print(OS, DummyMST, TypeToPrint, std::nullopt, /*PrintDef=*/false,
772  /*IsStandalone=*/true,
773  /*ShouldPrintRegisterTies=*/true,
774  /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
775 }
776 
778  LLT TypeToPrint, std::optional<unsigned> OpIdx,
779  bool PrintDef, bool IsStandalone,
780  bool ShouldPrintRegisterTies,
781  unsigned TiedOperandIdx,
782  const TargetRegisterInfo *TRI,
783  const TargetIntrinsicInfo *IntrinsicInfo) const {
784  printTargetFlags(OS, *this);
785  switch (getType()) {
787  Register Reg = getReg();
788  if (isImplicit())
789  OS << (isDef() ? "implicit-def " : "implicit ");
790  else if (PrintDef && isDef())
791  // Print the 'def' flag only when the operand is defined after '='.
792  OS << "def ";
793  if (isInternalRead())
794  OS << "internal ";
795  if (isDead())
796  OS << "dead ";
797  if (isKill())
798  OS << "killed ";
799  if (isUndef())
800  OS << "undef ";
801  if (isEarlyClobber())
802  OS << "early-clobber ";
803  if (getReg().isPhysical() && isRenamable())
804  OS << "renamable ";
805  // isDebug() is exactly true for register operands of a DBG_VALUE. So we
806  // simply infer it when parsing and do not need to print it.
807 
808  const MachineRegisterInfo *MRI = nullptr;
809  if (Reg.isVirtual()) {
810  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
811  MRI = &MF->getRegInfo();
812  }
813  }
814 
815  OS << printReg(Reg, TRI, 0, MRI);
816  // Print the sub register.
817  if (unsigned SubReg = getSubReg()) {
818  if (TRI)
819  OS << '.' << TRI->getSubRegIndexName(SubReg);
820  else
821  OS << ".subreg" << SubReg;
822  }
823  // Print the register class / bank.
824  if (Reg.isVirtual()) {
825  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
826  const MachineRegisterInfo &MRI = MF->getRegInfo();
827  if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
828  OS << ':';
829  OS << printRegClassOrBank(Reg, MRI, TRI);
830  }
831  }
832  }
833  // Print ties.
834  if (ShouldPrintRegisterTies && isTied() && !isDef())
835  OS << "(tied-def " << TiedOperandIdx << ")";
836  // Print types.
837  if (TypeToPrint.isValid())
838  OS << '(' << TypeToPrint << ')';
839  break;
840  }
842  const MIRFormatter *Formatter = nullptr;
843  if (const MachineFunction *MF = getMFIfAvailable(*this)) {
844  const auto *TII = MF->getSubtarget().getInstrInfo();
845  assert(TII && "expected instruction info");
846  Formatter = TII->getMIRFormatter();
847  }
848  if (Formatter)
849  Formatter->printImm(OS, *getParent(), OpIdx, getImm());
850  else
851  OS << getImm();
852  break;
853  }
855  getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
856  break;
858  getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
859  break;
861  OS << printMBBReference(*getMBB());
862  break;
864  int FrameIndex = getIndex();
865  bool IsFixed = false;
866  const MachineFrameInfo *MFI = nullptr;
867  if (const MachineFunction *MF = getMFIfAvailable(*this))
868  MFI = &MF->getFrameInfo();
869  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
870  break;
871  }
873  OS << "%const." << getIndex();
875  break;
877  OS << "target-index(";
878  const char *Name = "<unknown>";
879  if (const MachineFunction *MF = getMFIfAvailable(*this))
880  if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
881  Name = TargetIndexName;
882  OS << Name << ')';
884  break;
885  }
888  break;
890  getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
892  break;
894  StringRef Name = getSymbolName();
895  OS << '&';
896  if (Name.empty()) {
897  OS << "\"\"";
898  } else {
899  printLLVMNameWithoutPrefix(OS, Name);
900  }
902  break;
903  }
905  OS << "blockaddress(";
906  getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
907  MST);
908  OS << ", ";
909  printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
910  OS << ')';
912  break;
913  }
915  OS << "<regmask";
916  if (TRI) {
917  unsigned NumRegsInMask = 0;
918  unsigned NumRegsEmitted = 0;
919  for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
920  unsigned MaskWord = i / 32;
921  unsigned MaskBit = i % 32;
922  if (getRegMask()[MaskWord] & (1 << MaskBit)) {
923  if (PrintRegMaskNumRegs < 0 ||
924  NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
925  OS << " " << printReg(i, TRI);
926  NumRegsEmitted++;
927  }
928  NumRegsInMask++;
929  }
930  }
931  if (NumRegsEmitted != NumRegsInMask)
932  OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
933  } else {
934  OS << " ...";
935  }
936  OS << ">";
937  break;
938  }
940  const uint32_t *RegMask = getRegLiveOut();
941  OS << "liveout(";
942  if (!TRI) {
943  OS << "<unknown>";
944  } else {
945  bool IsCommaNeeded = false;
946  for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
947  if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
948  if (IsCommaNeeded)
949  OS << ", ";
950  OS << printReg(Reg, TRI);
951  IsCommaNeeded = true;
952  }
953  }
954  }
955  OS << ")";
956  break;
957  }
959  getMetadata()->printAsOperand(OS, MST);
960  break;
962  printSymbol(OS, *getMCSymbol());
963  break;
965  OS << "dbg-instr-ref(" << getInstrRefInstrIndex() << ", "
966  << getInstrRefOpIndex() << ')';
967  break;
968  }
970  if (const MachineFunction *MF = getMFIfAvailable(*this))
971  printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
972  else
973  OS << "<cfi directive>";
974  break;
975  }
978  if (ID < Intrinsic::num_intrinsics)
979  OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
980  else if (IntrinsicInfo)
981  OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
982  else
983  OS << "intrinsic(" << ID << ')';
984  break;
985  }
987  auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
988  OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
989  << CmpInst::getPredicateName(Pred) << ')';
990  break;
991  }
993  OS << "shufflemask(";
995  StringRef Separator;
996  for (int Elt : Mask) {
997  if (Elt == -1)
998  OS << Separator << "undef";
999  else
1000  OS << Separator << Elt;
1001  Separator = ", ";
1002  }
1003 
1004  OS << ')';
1005  break;
1006  }
1007 }
1008 
1009 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1010 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
1011 #endif
1012 
1013 //===----------------------------------------------------------------------===//
1014 // MachineMemOperand Implementation
1015 //===----------------------------------------------------------------------===//
1016 
1017 /// getAddrSpace - Return the LLVM IR address space number that this pointer
1018 /// points into.
1019 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
1020 
1021 /// isDereferenceable - Return true if V is always dereferenceable for
1022 /// Offset + Size byte.
1024  const DataLayout &DL) const {
1025  if (!V.is<const Value *>())
1026  return false;
1027 
1028  const Value *BasePtr = V.get<const Value *>();
1029  if (BasePtr == nullptr)
1030  return false;
1031 
1033  BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
1034 }
1035 
1036 /// getConstantPool - Return a MachinePointerInfo record that refers to the
1037 /// constant pool.
1040 }
1041 
1042 /// getFixedStack - Return a MachinePointerInfo record that refers to the
1043 /// the specified FrameIndex.
1045  int FI, int64_t Offset) {
1047 }
1048 
1051 }
1052 
1054  return MachinePointerInfo(MF.getPSVManager().getGOT());
1055 }
1056 
1058  int64_t Offset, uint8_t ID) {
1060 }
1061 
1064 }
1065 
1067  LLT type, Align a, const AAMDNodes &AAInfo,
1068  const MDNode *Ranges, SyncScope::ID SSID,
1069  AtomicOrdering Ordering,
1070  AtomicOrdering FailureOrdering)
1071  : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1072  AAInfo(AAInfo), Ranges(Ranges) {
1073  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1074  isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1075  "invalid pointer value");
1076  assert((isLoad() || isStore()) && "Not a load/store!");
1077 
1078  AtomicInfo.SSID = static_cast<unsigned>(SSID);
1079  assert(getSyncScopeID() == SSID && "Value truncated");
1080  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1081  assert(getSuccessOrdering() == Ordering && "Value truncated");
1082  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1083  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1084 }
1085 
1087  uint64_t s, Align a,
1088  const AAMDNodes &AAInfo,
1089  const MDNode *Ranges, SyncScope::ID SSID,
1090  AtomicOrdering Ordering,
1091  AtomicOrdering FailureOrdering)
1092  : MachineMemOperand(ptrinfo, f,
1093  s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
1094  AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1095 
1096 /// Profile - Gather unique data for the object.
1097 ///
1099  ID.AddInteger(getOffset());
1100  ID.AddInteger(getMemoryType().getUniqueRAWLLTData());
1101  ID.AddPointer(getOpaqueValue());
1102  ID.AddInteger(getFlags());
1103  ID.AddInteger(getBaseAlign().value());
1104 }
1105 
1107  // The Value and Offset may differ due to CSE. But the flags and size
1108  // should be the same.
1109  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1110  assert((MMO->getSize() == ~UINT64_C(0) || getSize() == ~UINT64_C(0) ||
1111  MMO->getSize() == getSize()) &&
1112  "Size mismatch!");
1113 
1114  if (MMO->getBaseAlign() >= getBaseAlign()) {
1115  // Update the alignment value.
1116  BaseAlign = MMO->getBaseAlign();
1117  // Also update the base and offset, because the new alignment may
1118  // not be applicable with the old ones.
1119  PtrInfo = MMO->PtrInfo;
1120  }
1121 }
1122 
1123 /// getAlign - Return the minimum known alignment in bytes of the
1124 /// actual memory reference.
1126  return commonAlignment(getBaseAlign(), getOffset());
1127 }
1128 
1131  const LLVMContext &Context,
1132  const MachineFrameInfo *MFI,
1133  const TargetInstrInfo *TII) const {
1134  OS << '(';
1135  if (isVolatile())
1136  OS << "volatile ";
1137  if (isNonTemporal())
1138  OS << "non-temporal ";
1139  if (isDereferenceable())
1140  OS << "dereferenceable ";
1141  if (isInvariant())
1142  OS << "invariant ";
1143  if (TII) {
1146  << "\" ";
1149  << "\" ";
1152  << "\" ";
1153  } else {
1155  OS << "\"MOTargetFlag1\" ";
1157  OS << "\"MOTargetFlag2\" ";
1159  OS << "\"MOTargetFlag3\" ";
1160  }
1161 
1162  assert((isLoad() || isStore()) &&
1163  "machine memory operand must be a load or store (or both)");
1164  if (isLoad())
1165  OS << "load ";
1166  if (isStore())
1167  OS << "store ";
1168 
1169  printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1170 
1172  OS << toIRString(getSuccessOrdering()) << ' ';
1174  OS << toIRString(getFailureOrdering()) << ' ';
1175 
1176  if (getMemoryType().isValid())
1177  OS << '(' << getMemoryType() << ')';
1178  else
1179  OS << "unknown-size";
1180 
1181  if (const Value *Val = getValue()) {
1182  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1183  MIRFormatter::printIRValue(OS, *Val, MST);
1184  } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1185  OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1186  assert(PVal && "Expected a pseudo source value");
1187  switch (PVal->kind()) {
1189  OS << "stack";
1190  break;
1192  OS << "got";
1193  break;
1195  OS << "jump-table";
1196  break;
1198  OS << "constant-pool";
1199  break;
1201  int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1202  bool IsFixed = true;
1203  printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1204  break;
1205  }
1207  OS << "call-entry ";
1208  cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1209  OS, /*PrintType=*/false, MST);
1210  break;
1212  OS << "call-entry &";
1214  OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1215  break;
1216  default: {
1217  const MIRFormatter *Formatter = TII->getMIRFormatter();
1218  // FIXME: This is not necessarily the correct MIR serialization format for
1219  // a custom pseudo source value, but at least it allows
1220  // MIR printing to work on a target with custom pseudo source
1221  // values.
1222  OS << "custom \"";
1223  Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1224  OS << '\"';
1225  break;
1226  }
1227  }
1228  } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1229  OS << ((isLoad() && isStore()) ? " on "
1230  : isLoad() ? " from "
1231  : " into ")
1232  << "unknown-address";
1233  }
1235  if (getSize() > 0 && getAlign() != getSize())
1236  OS << ", align " << getAlign().value();
1237  if (getAlign() != getBaseAlign())
1238  OS << ", basealign " << getBaseAlign().value();
1239  auto AAInfo = getAAInfo();
1240  if (AAInfo.TBAA) {
1241  OS << ", !tbaa ";
1242  AAInfo.TBAA->printAsOperand(OS, MST);
1243  }
1244  if (AAInfo.Scope) {
1245  OS << ", !alias.scope ";
1246  AAInfo.Scope->printAsOperand(OS, MST);
1247  }
1248  if (AAInfo.NoAlias) {
1249  OS << ", !noalias ";
1250  AAInfo.NoAlias->printAsOperand(OS, MST);
1251  }
1252  if (getRanges()) {
1253  OS << ", !range ";
1254  getRanges()->printAsOperand(OS, MST);
1255  }
1256  // FIXME: Implement addrspace printing/parsing in MIR.
1257  // For now, print this even though parsing it is not available in MIR.
1258  if (unsigned AS = getAddrSpace())
1259  OS << ", addrspace " << AS;
1260 
1261  OS << ')';
1262 }
llvm::Intrinsic::getBaseName
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
Definition: Function.cpp:970
i
i
Definition: README.txt:29
llvm::MCCFIInstruction::OpWindowSave
@ OpWindowSave
Definition: MCDwarf.h:496
llvm::MIRFormatter::printIRValue
static void printIRValue(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Helper functions to print IR value as MIR serialization format which will be useful for target specif...
Definition: MIRPrinter.cpp:939
printCFI
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
Definition: MachineOperand.cpp:646
llvm::MachineMemOperand::MachineMemOperand
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
Definition: MachineOperand.cpp:1086
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:62
llvm::MachineMemOperand::isStore
bool isStore() const
Definition: MachineMemOperand.h:288
llvm::PseudoSourceValueManager::getGOT
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like).
Definition: PseudoSourceValue.cpp:112
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:52
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:492
llvm::PointerUnion::isNull
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:142
llvm::ModuleSlotTracker::getLocalSlot
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:884
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::PseudoSourceValue::GlobalValueCallEntry
@ GlobalValueCallEntry
Definition: PseudoSourceValue.h:43
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::MCCFIInstruction::OpRelOffset
@ OpRelOffset
Definition: MCDwarf.h:490
tryToGetTargetInfo
static void tryToGetTargetInfo(const MachineOperand &MO, const TargetRegisterInfo *&TRI, const TargetIntrinsicInfo *&IntrinsicInfo)
Definition: MachineOperand.cpp:437
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:114
llvm::MCCFIInstruction::OpDefCfaRegister
@ OpDefCfaRegister
Definition: MCDwarf.h:487
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:718
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1125
llvm::MachineOperand::MO_ShuffleMask
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
Definition: MachineOperand.h:70
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:579
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:51
Loads.h
llvm::MachineOperand::MO_RegisterLiveOut
@ MO_RegisterLiveOut
Mask of live-out registers.
Definition: MachineOperand.h:64
llvm::Function
Definition: Function.h:59
llvm::MachineMemOperand::print
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
Definition: MachineOperand.cpp:1129
llvm::MCCFIInstruction::OpOffset
@ OpOffset
Definition: MCDwarf.h:485
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:95
getMFIfAvailable
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
Definition: MachineOperand.cpp:43
llvm::MachinePointerInfo::getConstantPool
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
Definition: MachineOperand.cpp:1038
llvm::MachineOperand::printStackObjectReference
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
Definition: MachineOperand.cpp:616
llvm::MachineOperand::printIRSlotNumber
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
Definition: MachineOperand.cpp:639
llvm::stable_hash_combine_array
stable_hash stable_hash_combine_array(const stable_hash *P, size_t C)
Definition: StableHashing.h:92
llvm::MachineOperand::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Definition: MachineOperand.h:609
llvm::MachinePointerInfo::getUnknownStack
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
Definition: MachineOperand.cpp:1062
llvm::printLLVMNameWithoutPrefix
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:354
llvm::MachineOperand::print
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
Definition: MachineOperand.cpp:761
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:584
llvm::MachineMemOperand::isLoad
bool isLoad() const
Definition: MachineMemOperand.h:287
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:226
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:118
llvm::ModuleSlotTracker::getCurrentFunction
const Function * getCurrentFunction() const
Definition: ModuleSlotTracker.h:81
llvm::MachineOperand::isTied
bool isTied() const
Definition: MachineOperand.h:447
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SyncScope::System
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:57
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:138
llvm::MachineMemOperand::MOTargetFlag2
@ MOTargetFlag2
Definition: MachineMemOperand.h:151
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::MachineMemOperand::getOpaqueValue
const void * getOpaqueValue() const
Definition: MachineMemOperand.h:216
llvm::HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
Definition: HexagonInstrInfo.cpp:2090
MachineJumpTableInfo.h
TargetInstrInfo.h
llvm::Metadata::printAsOperand
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:4884
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineOperand::MO_CFIIndex
@ MO_CFIIndex
MCCFIInstruction index.
Definition: MachineOperand.h:67
llvm::MachineOperand::getTargetIndexName
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
Definition: MachineOperand.cpp:458
llvm::MachineFunction::getPSVManager
PseudoSourceValueManager & getPSVManager() const
Definition: MachineFunction.h:632
llvm::HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
Definition: HexagonInstrInfo.cpp:2071
llvm::LLVMContext::getSyncScopeNames
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
Definition: LLVMContext.cpp:314
llvm::MachineOperand::ChangeToTargetIndex
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
Definition: MachineOperand.cpp:226
llvm::ModuleSlotTracker::incorporateFunction
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:870
llvm::MachineMemOperand::isInvariant
bool isInvariant() const
Definition: MachineMemOperand.h:292
llvm::PseudoSourceValueManager::getStack
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function,...
Definition: PseudoSourceValue.cpp:108
llvm::MachineOperand::ChangeToFrameIndex
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
Definition: MachineOperand.cpp:215
llvm::CmpInst::getPredicateName
static StringRef getPredicateName(Predicate P)
Definition: Instructions.cpp:4109
llvm::AAMDNodes::Scope
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition: Metadata.h:674
llvm::minidump::MemoryType
MemoryType
Definition: Minidump.h:98
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition: MachineMemOperand.h:257
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:626
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineOperand::dump
void dump() const
Definition: MachineOperand.cpp:1010
llvm::MIRFormatter::printImm
virtual void printImm(raw_ostream &OS, const MachineInstr &MI, std::optional< unsigned > OpIdx, int64_t Imm) const
Implement target specific printing for machine operand immediate value, so that we can have more mean...
Definition: MIRFormatter.h:39
llvm::PointerUnion::get
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:155
llvm::MachinePointerInfo::getJumpTable
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Definition: MachineOperand.cpp:1049
llvm::commonAlignment
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:212
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition: MachineOperand.h:589
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:51
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::PseudoSourceValue::JumpTable
@ JumpTable
Definition: PseudoSourceValue.h:40
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::PointerUnion::is
bool is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:150
llvm::lltok::equal
@ equal
Definition: LLToken.h:25
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
llvm::MachineOperand::printSymbol
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
Definition: MachineOperand.cpp:612
isUndef
static bool isUndef(ArrayRef< int > Mask)
Definition: HexagonISelDAGToDAGHVX.cpp:1032
llvm::TargetIntrinsicInfo
TargetIntrinsicInfo - Interface to description of machine instruction set.
Definition: TargetIntrinsicInfo.h:29
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachinePointerInfo::Offset
int64_t Offset
Offset - This is an offset from the base Value*.
Definition: MachineMemOperand.h:44
llvm::MCCFIInstruction::OpDefCfa
@ OpDefCfa
Definition: MCDwarf.h:489
llvm::MachineOperand::printSubRegIdx
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
Definition: MachineOperand.cpp:551
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:396
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:119
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:150
llvm::MCCFIInstruction::OpUndefined
@ OpUndefined
Definition: MCDwarf.h:494
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:386
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
TargetMachine.h
StableHashing.h
Constants.h
llvm::MachineMemOperand::getBaseAlign
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
Definition: MachineMemOperand.h:254
llvm::MachineOperand::ChangeToRegister
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Definition: MachineOperand.cpp:255
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:61
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:228
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:553
getTargetIndexName
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
Definition: MachineOperand.cpp:446
llvm::MachineOperand::getRegMaskSize
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
Definition: MachineOperand.h:662
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:210
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:376
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineOperand::getRegMask
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Definition: MachineOperand.h:656
llvm::MachineOperand::setSubReg
void setSubReg(unsigned subReg)
Definition: MachineOperand.h:487
llvm::MachineOperand::MO_FrameIndex
@ MO_FrameIndex
Abstract Stack Frame Index.
Definition: MachineOperand.h:56
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MCCFIInstruction::getOffset
int getOffset() const
Definition: MCDwarf.h:664
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1053
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::dwarf::Index
Index
Definition: Dwarf.h:550
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:157
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineOperand::getInstrRefInstrIndex
unsigned getInstrRefInstrIndex() const
Definition: MachineOperand.h:594
IRPrintingPasses.h
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:256
llvm::PseudoSourceValue::FixedStack
@ FixedStack
Definition: PseudoSourceValue.h:42
llvm::MachineOperand::ChangeToMCSymbol
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
Definition: MachineOperand.cpp:204
llvm::MCCFIInstruction::getOperation
OpType getOperation() const
Definition: MCDwarf.h:642
llvm::printJumpTableEntryReference
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
Definition: MachineFunction.cpp:1338
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition: MachineOperand.h:229
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:688
printCFIRegister
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
Definition: MachineOperand.cpp:473
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:407
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:243
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(const Value *v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:50
llvm::MCCFIInstruction::getRegister
unsigned getRegister() const
Definition: MCDwarf.h:645
isDebug
static bool isDebug()
Definition: HexagonGenInsert.cpp:83
llvm::MachineOperand::printOperandOffset
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
Definition: MachineOperand.cpp:629
llvm::MachineMemOperand::getSyncScopeID
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
Definition: MachineMemOperand.h:263
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MCCFIInstruction
Definition: MCDwarf.h:479
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:448
llvm::MachineMemOperand::Profile
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
Definition: MachineOperand.cpp:1098
llvm::MachineOperand::getMetadata
const MDNode * getMetadata() const
Definition: MachineOperand.h:672
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::PseudoSourceValue::ExternalSymbolCallEntry
@ ExternalSymbolCallEntry
Definition: PseudoSourceValue.h:44
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:672
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::cl::opt
Definition: CommandLine.h:1410
llvm::MachineOperand::MO_Metadata
@ MO_Metadata
Metadata reference (for debug info)
Definition: MachineOperand.h:65
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineOperand::ChangeToFPImmediate
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
Definition: MachineOperand.cpp:167
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:401
type
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference and DH registers in an instruction requiring REX prefix divb and mulb both produce results in AH If isel emits a CopyFromReg which gets turned into a movb and that can be allocated a r8b r15b To get around isel emits a CopyFromReg from AX and then right shift it down by and truncate it It s not pretty but it works We need some register allocation magic to make the hack go which would often require a callee saved register Callees usually need to keep this value live for most of their body so it doesn t add a significant burden on them We currently implement this in however this is suboptimal because it means that it would be quite awkward to implement the optimization for callers A better implementation would be to relax the LLVM IR rules for sret arguments to allow a function with an sret argument to have a non void return type
Definition: README-X86-64.txt:70
llvm::MachineOperand::getInstrRefOpIndex
unsigned getInstrRefOpIndex() const
Definition: MachineOperand.h:599
llvm::MachineOperand::setInstrRefOpIndex
void setInstrRefOpIndex(unsigned OpIdx)
Definition: MachineOperand.h:719
llvm::MCCFIInstruction::OpDefCfaOffset
@ OpDefCfaOffset
Definition: MCDwarf.h:488
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:226
llvm::MachineOperand::substVirtReg
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Definition: MachineOperand.cpp:78
llvm::MachinePointerInfo::isDereferenceable
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
Definition: MachineOperand.cpp:1023
llvm::MCCFIInstruction::OpRestore
@ OpRestore
Definition: MCDwarf.h:493
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:326
llvm::MachineOperand::getCImm
const ConstantInt * getCImm() const
Definition: MachineOperand.h:558
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineMemOperand::isDereferenceable
bool isDereferenceable() const
Definition: MachineMemOperand.h:291
uint64_t
s
multiplies can be turned into SHL s
Definition: README.txt:370
llvm::MCCFIInstruction::OpSameValue
@ OpSameValue
Definition: MCDwarf.h:482
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:31
llvm::SyncScope::ID
uint8_t ID
Definition: LLVMContext.h:46
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:391
llvm::MachineOperand::MO_Predicate
@ MO_Predicate
Generic predicate for ISel.
Definition: MachineOperand.h:69
I
#define I(x, y, z)
Definition: MD5.cpp:58
StringExtras.h
llvm::MachineOperand::MO_MCSymbol
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
Definition: MachineOperand.h:66
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
llvm::MCRegisterInfo::getLLVMRegNum
std::optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
Definition: MCRegisterInfo.cpp:81
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:224
llvm::MachineOperand::getFPImm
const ConstantFP * getFPImm() const
Definition: MachineOperand.h:563
llvm::MachineOperand::getPredicate
unsigned getPredicate() const
Definition: MachineOperand.h:614
llvm::PseudoSourceValue::ConstantPool
@ ConstantPool
Definition: PseudoSourceValue.h:41
llvm::MCCFIInstruction::getRegister2
unsigned getRegister2() const
Definition: MCDwarf.h:654
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:442
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:265
llvm::MachineMemOperand::getSuccessOrdering
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
Definition: MachineMemOperand.h:270
MIRFormatter.h
llvm::MachineOperand::getShuffleMask
ArrayRef< int > getShuffleMask() const
Definition: MachineOperand.h:619
llvm::MachineOperand::MO_TargetIndex
@ MO_TargetIndex
Target-dependent index+offset operand.
Definition: MachineOperand.h:58
PrintRegMaskNumRegs
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
llvm::MachineMemOperand::getMemoryType
LLT getMemoryType() const
Return the memory type of the memory reference.
Definition: MachineMemOperand.h:232
llvm::MCCFIInstruction::OpAdjustCfaOffset
@ OpAdjustCfaOffset
Definition: MCDwarf.h:491
llvm::MachineOperand::MO_FPImmediate
@ MO_FPImmediate
Floating-point immediate operand.
Definition: MachineOperand.h:54
printFrameIndex
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
Definition: MachineOperand.cpp:537
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:366
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::MDNode
Metadata node.
Definition: Metadata.h:943
llvm::MachineOperand::setInstrRefInstrIndex
void setInstrRefInstrIndex(unsigned InstrIdx)
Definition: MachineOperand.h:715
llvm::Value::printAsOperand
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:4778
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::MCCFIInstruction::OpEscape
@ OpEscape
Definition: MCDwarf.h:492
llvm::CmpInst::isIntPredicate
bool isIntPredicate() const
Definition: InstrTypes.h:826
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:59
llvm::MachineOperand::MO_CImmediate
@ MO_CImmediate
Immediate >64bit operand.
Definition: MachineOperand.h:53
llvm::printRegClassOrBank
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Definition: TargetRegisterInfo.cpp:175
llvm::MachineMemOperand::MOTargetFlag3
@ MOTargetFlag3
Definition: MachineMemOperand.h:152
llvm::MachineOperand::setIsDef
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Definition: MachineOperand.cpp:102
llvm::ArrayRef< int >
llvm::MCCFIInstruction::getAddressSpace
unsigned getAddressSpace() const
Definition: MCDwarf.h:659
llvm::MCCFIInstruction::OpRememberState
@ OpRememberState
Definition: MCDwarf.h:483
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:568
llvm::HexagonInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
Definition: HexagonInstrInfo.cpp:2065
llvm::MachinePointerInfo::V
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Definition: MachineMemOperand.h:41
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MCCFIInstruction::getValues
StringRef getValues() const
Definition: MCDwarf.h:672
llvm::MachineOperand::ChangeToES
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Definition: MachineOperand.cpp:178
llvm::Offset
@ Offset
Definition: DWP.cpp:406
llvm::TargetRegisterInfo::composeSubRegIndices
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Definition: TargetRegisterInfo.h:662
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:527
uint32_t
llvm::MachineOperand::setIsRenamable
void setIsRenamable(bool Val=true)
Definition: MachineOperand.cpp:137
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:55
llvm::MCCFIInstruction::OpLLVMDefAspaceCfa
@ OpLLVMDefAspaceCfa
Definition: MCDwarf.h:486
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachinePointerInfo::AddrSpace
unsigned AddrSpace
Definition: MachineMemOperand.h:46
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:381
llvm::FoldingSetNodeID
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:318
llvm::MachineOperand::MO_IntrinsicID
@ MO_IntrinsicID
Intrinsic ID for ISel.
Definition: MachineOperand.h:68
llvm::MachineRegisterInfo::removeRegOperandFromUseList
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
Definition: MachineRegisterInfo.cpp:304
llvm::format
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
llvm::DataLayout::getAllocaAddrSpace
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:283
llvm::MachineOperand::setIndex
void setIndex(int Idx)
Definition: MachineOperand.h:704
llvm::TargetIntrinsicInfo::getName
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition: MachineOperand.cpp:1019
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:371
FoldingSet.h
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1762
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::PseudoSourceValueManager::getJumpTable
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
Definition: PseudoSourceValue.cpp:118
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::PseudoSourceValue::GOT
@ GOT
Definition: PseudoSourceValue.h:39
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition: MachineMemOperand.h:289
llvm::BlockAddress::getFunction
Function * getFunction() const
Definition: Constants.h:903
llvm::MachineOperand::printTargetFlags
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
Definition: MachineOperand.cpp:560
llvm::MachineOperand::ChangeToGA
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
Definition: MachineOperand.cpp:191
llvm::MachineRegisterInfo::addRegOperandToUseList
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
Definition: MachineRegisterInfo.cpp:265
llvm::AAMDNodes::NoAlias
MDNode * NoAlias
The tag specifying the noalias scope.
Definition: Metadata.h:677
getTargetFlagName
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
Definition: MachineOperand.cpp:463
llvm::PseudoSourceValueManager::getFixedStack
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot.
Definition: PseudoSourceValue.cpp:123
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:354
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:235
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:60
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:573
llvm::MachineOperand::getCFIIndex
unsigned getCFIIndex() const
Definition: MachineOperand.h:604
llvm::PseudoSourceValue::Stack
@ Stack
Definition: PseudoSourceValue.h:38
llvm::MachineMemOperand::refineAlignment
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
Definition: MachineOperand.cpp:1106
llvm::MCCFIInstruction::OpRegister
@ OpRegister
Definition: MCDwarf.h:495
llvm::AAMDNodes::TBAA
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:668
llvm::hash_value
hash_code hash_value(const FixedPointSemantics &Val)
Definition: APFixedPoint.h:128
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:452
llvm::MachineInstr::IgnoreBundle
@ IgnoreBundle
Definition: MachineInstr.h:809
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:28
isValid
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
Definition: RustDemangle.cpp:184
Instructions.h
Other
std::optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1260
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1044
llvm::hash_combine
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:608
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:634
TargetIntrinsicInfo.h
getTargetMMOFlagName
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
Definition: MachineOperand.cpp:526
llvm::MachineOperand::ChangeToDbgInstrRef
void ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx, unsigned TargetFlags=0)
Replace this operand with an Instruction Reference.
Definition: MachineOperand.cpp:239
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:56
llvm::toIRString
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
Definition: AtomicOrdering.h:81
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:292
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:437
llvm::MachineOperand::getRegLiveOut
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
Definition: MachineOperand.h:667
ModuleSlotTracker.h
llvm::SmallVectorImpl< StringRef >
llvm::MachineMemOperand::getFailureOrdering
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
Definition: MachineMemOperand.h:276
MachineOperand.h
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1149
llvm::MachineOperand::substPhysReg
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Definition: MachineOperand.cpp:88
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::AllocaInst
an instruction to allocate memory on the stack
Definition: Instructions.h:58
llvm::MachineOperand::MO_RegisterMask
@ MO_RegisterMask
Mask of preserved registers.
Definition: MachineOperand.h:63
printIRBlockReference
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
Definition: MachineOperand.cpp:486
llvm::cl::desc
Definition: CommandLine.h:411
llvm::MachineMemOperand::isNonTemporal
bool isNonTemporal() const
Definition: MachineMemOperand.h:290
llvm::TargetRegisterInfo::getSubRegIndexName
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition: TargetRegisterInfo.h:370
llvm::MachineMemOperand::getRanges
const MDNode * getRanges() const
Return the range tag for the memory reference.
Definition: MachineMemOperand.h:260
llvm::MCCFIInstruction::OpNegateRAState
@ OpNegateRAState
Definition: MCDwarf.h:497
llvm::MIRFormatter::printCustomPseudoSourceValue
virtual void printCustomPseudoSourceValue(raw_ostream &OS, ModuleSlotTracker &MST, const PseudoSourceValue &PSV) const
Implement target specific printing of target custom pseudo source value.
Definition: MIRFormatter.h:56
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::LLT::isValid
constexpr bool isValid() const
Definition: LowLevelTypeImpl.h:121
llvm::MachineOperand::MO_DbgInstrRef
@ MO_DbgInstrRef
Integer indices referring to an instruction+operand.
Definition: MachineOperand.h:71
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1057
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:219
TargetRegisterInfo.h
llvm::MCCFIInstruction::OpRestoreState
@ OpRestoreState
Definition: MCDwarf.h:484
llvm::PseudoSourceValueManager::getConstantPool
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
Definition: PseudoSourceValue.cpp:114
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::AtomicOrdering::NotAtomic
@ NotAtomic
llvm::isDereferenceableAndAlignedPointer
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition: Loads.cpp:201
llvm::MachineOperand::isIdenticalTo
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Definition: MachineOperand.cpp:301
llvm::MCCFIInstruction::getLabel
MCSymbol * getLabel() const
Definition: MCDwarf.h:643
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:212
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:39
llvm::hash_code
An opaque object representing a hash code.
Definition: Hashing.h:74
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:57
llvm::MachineFrameInfo::getObjectAllocation
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
Definition: MachineFrameInfo.h:510
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::MachineOperand::setOffset
void setOffset(int64_t Offset)
Definition: MachineOperand.h:696
printSyncScope
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
Definition: MachineOperand.cpp:509