LLVM 18.0.0git
MachineOperand.cpp
Go to the documentation of this file.
1//===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file Methods common to all machine operands.
10//
11//===----------------------------------------------------------------------===//
12
16#include "llvm/Analysis/Loads.h"
23#include "llvm/Config/llvm-config.h"
24#include "llvm/IR/Constants.h"
28#include "llvm/MC/MCDwarf.h"
31#include <optional>
32
33using namespace llvm;
34
35static cl::opt<int>
36 PrintRegMaskNumRegs("print-regmask-num-regs",
37 cl::desc("Number of registers to limit to when "
38 "printing regmask operands in IR dumps. "
39 "unlimited = -1"),
40 cl::init(32), cl::Hidden);
41
43 if (const MachineInstr *MI = MO.getParent())
44 if (const MachineBasicBlock *MBB = MI->getParent())
45 if (const MachineFunction *MF = MBB->getParent())
46 return MF;
47 return nullptr;
48}
49
51 return const_cast<MachineFunction *>(
52 getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
53}
54
56 assert(getParent() && "Operand does not belong to any instruction!");
57 return getParent()->getOperandNo(this);
58}
59
61 if (getReg() == Reg)
62 return; // No change.
63
64 // Clear the IsRenamable bit to keep it conservatively correct.
65 IsRenamable = false;
66
67 // Otherwise, we have to change the register. If this operand is embedded
68 // into a machine function, we need to update the old and new register's
69 // use/def lists.
70 if (MachineFunction *MF = getMFIfAvailable(*this)) {
71 MachineRegisterInfo &MRI = MF->getRegInfo();
72 MRI.removeRegOperandFromUseList(this);
73 SmallContents.RegNo = Reg;
74 MRI.addRegOperandToUseList(this);
75 return;
76 }
77
78 // Otherwise, just change the register, no problem. :)
79 SmallContents.RegNo = Reg;
80}
81
82void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
83 const TargetRegisterInfo &TRI) {
84 assert(Reg.isVirtual());
85 if (SubIdx && getSubReg())
86 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
87 setReg(Reg);
88 if (SubIdx)
89 setSubReg(SubIdx);
90}
91
94 if (getSubReg()) {
95 Reg = TRI.getSubReg(Reg, getSubReg());
96 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
97 // That won't happen in legal code.
98 setSubReg(0);
99 if (isDef())
100 setIsUndef(false);
101 }
102 setReg(Reg);
103}
104
105/// Change a def to a use, or a use to a def.
107 assert(isReg() && "Wrong MachineOperand accessor");
108 assert((!Val || !isDebug()) && "Marking a debug operation as def");
109 if (IsDef == Val)
110 return;
111 assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
112 // MRI may keep uses and defs in different list positions.
113 if (MachineFunction *MF = getMFIfAvailable(*this)) {
114 MachineRegisterInfo &MRI = MF->getRegInfo();
115 MRI.removeRegOperandFromUseList(this);
116 IsDef = Val;
117 MRI.addRegOperandToUseList(this);
118 return;
119 }
120 IsDef = Val;
121}
122
124 assert(isReg() && "Wrong MachineOperand accessor");
125 assert(getReg().isPhysical() &&
126 "isRenamable should only be checked on physical registers");
127 if (!IsRenamable)
128 return false;
129
130 const MachineInstr *MI = getParent();
131 if (!MI)
132 return true;
133
134 if (isDef())
135 return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
136
137 assert(isUse() && "Reg is not def or use");
138 return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
139}
140
142 assert(isReg() && "Wrong MachineOperand accessor");
143 assert(getReg().isPhysical() &&
144 "setIsRenamable should only be called on physical registers");
145 IsRenamable = Val;
146}
147
148// If this operand is currently a register operand, and if this is in a
149// function, deregister the operand from the register's use/def list.
150void MachineOperand::removeRegFromUses() {
151 if (!isReg() || !isOnRegUseList())
152 return;
153
154 if (MachineFunction *MF = getMFIfAvailable(*this))
155 MF->getRegInfo().removeRegOperandFromUseList(this);
156}
157
158/// ChangeToImmediate - Replace this operand with a new immediate operand of
159/// the specified value. If an operand is known to be an immediate already,
160/// the setImm method should be used.
161void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
162 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
163
164 removeRegFromUses();
165
166 OpKind = MO_Immediate;
167 Contents.ImmVal = ImmVal;
168 setTargetFlags(TargetFlags);
169}
170
172 unsigned TargetFlags) {
173 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
174
175 removeRegFromUses();
176
177 OpKind = MO_FPImmediate;
178 Contents.CFP = FPImm;
179 setTargetFlags(TargetFlags);
180}
181
182void MachineOperand::ChangeToES(const char *SymName,
183 unsigned TargetFlags) {
184 assert((!isReg() || !isTied()) &&
185 "Cannot change a tied operand into an external symbol");
186
187 removeRegFromUses();
188
189 OpKind = MO_ExternalSymbol;
190 Contents.OffsetedInfo.Val.SymbolName = SymName;
191 setOffset(0); // Offset is always 0.
192 setTargetFlags(TargetFlags);
193}
194
196 unsigned TargetFlags) {
197 assert((!isReg() || !isTied()) &&
198 "Cannot change a tied operand into a global address");
199
200 removeRegFromUses();
201
202 OpKind = MO_GlobalAddress;
203 Contents.OffsetedInfo.Val.GV = GV;
205 setTargetFlags(TargetFlags);
206}
207
208void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
209 assert((!isReg() || !isTied()) &&
210 "Cannot change a tied operand into an MCSymbol");
211
212 removeRegFromUses();
213
214 OpKind = MO_MCSymbol;
215 Contents.Sym = Sym;
216 setTargetFlags(TargetFlags);
217}
218
219void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
220 assert((!isReg() || !isTied()) &&
221 "Cannot change a tied operand into a FrameIndex");
222
223 removeRegFromUses();
224
225 OpKind = MO_FrameIndex;
226 setIndex(Idx);
227 setTargetFlags(TargetFlags);
228}
229
231 unsigned TargetFlags) {
232 assert((!isReg() || !isTied()) &&
233 "Cannot change a tied operand into a FrameIndex");
234
235 removeRegFromUses();
236
237 OpKind = MO_TargetIndex;
238 setIndex(Idx);
240 setTargetFlags(TargetFlags);
241}
242
243void MachineOperand::ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx,
244 unsigned TargetFlags) {
245 assert((!isReg() || !isTied()) &&
246 "Cannot change a tied operand into a DbgInstrRef");
247
248 removeRegFromUses();
249
250 OpKind = MO_DbgInstrRef;
251 setInstrRefInstrIndex(InstrIdx);
252 setInstrRefOpIndex(OpIdx);
253 setTargetFlags(TargetFlags);
254}
255
256/// ChangeToRegister - Replace this operand with a new register operand of
257/// the specified value. If an operand is known to be an register already,
258/// the setReg method should be used.
259void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
260 bool isKill, bool isDead, bool isUndef,
261 bool isDebug) {
262 MachineRegisterInfo *RegInfo = nullptr;
263 if (MachineFunction *MF = getMFIfAvailable(*this))
264 RegInfo = &MF->getRegInfo();
265 // If this operand is already a register operand, remove it from the
266 // register's use/def lists.
267 bool WasReg = isReg();
268 if (RegInfo && WasReg)
269 RegInfo->removeRegOperandFromUseList(this);
270
271 // Ensure debug instructions set debug flag on register uses.
272 const MachineInstr *MI = getParent();
273 if (!isDef && MI && MI->isDebugInstr())
274 isDebug = true;
275
276 // Change this to a register and set the reg#.
277 assert(!(isDead && !isDef) && "Dead flag on non-def");
278 assert(!(isKill && isDef) && "Kill flag on def");
279 OpKind = MO_Register;
280 SmallContents.RegNo = Reg;
281 SubReg_TargetFlags = 0;
282 IsDef = isDef;
283 IsImp = isImp;
284 IsDeadOrKill = isKill | isDead;
285 IsRenamable = false;
286 IsUndef = isUndef;
287 IsInternalRead = false;
288 IsEarlyClobber = false;
289 IsDebug = isDebug;
290 // Ensure isOnRegUseList() returns false.
291 Contents.Reg.Prev = nullptr;
292 // Preserve the tie when the operand was already a register.
293 if (!WasReg)
294 TiedTo = 0;
295
296 // If this operand is embedded in a function, add the operand to the
297 // register's use/def list.
298 if (RegInfo)
299 RegInfo->addRegOperandToUseList(this);
300}
301
302/// isIdenticalTo - Return true if this operand is identical to the specified
303/// operand. Note that this should stay in sync with the hash_value overload
304/// below.
306 if (getType() != Other.getType() ||
307 getTargetFlags() != Other.getTargetFlags())
308 return false;
309
310 switch (getType()) {
312 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
313 getSubReg() == Other.getSubReg();
315 return getImm() == Other.getImm();
317 return getCImm() == Other.getCImm();
319 return getFPImm() == Other.getFPImm();
321 return getMBB() == Other.getMBB();
323 return getIndex() == Other.getIndex();
326 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
328 return getIndex() == Other.getIndex();
330 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
332 return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
333 getOffset() == Other.getOffset();
335 return getBlockAddress() == Other.getBlockAddress() &&
336 getOffset() == Other.getOffset();
339 // Shallow compare of the two RegMasks
340 const uint32_t *RegMask = getRegMask();
341 const uint32_t *OtherRegMask = Other.getRegMask();
342 if (RegMask == OtherRegMask)
343 return true;
344
345 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
346 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
347 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
348 // Deep compare of the two RegMasks
349 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
350 }
351 // We don't know the size of the RegMask, so we can't deep compare the two
352 // reg masks.
353 return false;
354 }
356 return getMCSymbol() == Other.getMCSymbol();
358 return getInstrRefInstrIndex() == Other.getInstrRefInstrIndex() &&
359 getInstrRefOpIndex() == Other.getInstrRefOpIndex();
361 return getCFIIndex() == Other.getCFIIndex();
363 return getMetadata() == Other.getMetadata();
365 return getIntrinsicID() == Other.getIntrinsicID();
367 return getPredicate() == Other.getPredicate();
369 return getShuffleMask() == Other.getShuffleMask();
370 }
371 llvm_unreachable("Invalid machine operand type");
372}
373
374// Note: this must stay exactly in sync with isIdenticalTo above.
376 switch (MO.getType()) {
378 // Register operands don't have target flags.
379 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
381 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
383 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
385 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
387 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
389 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
392 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
393 MO.getOffset());
395 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
397 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
400 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
401 MO.getOffset());
403 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
404 MO.getOffset());
407 if (const MachineFunction *MF = getMFIfAvailable(MO)) {
408 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
409 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
410 const uint32_t *RegMask = MO.getRegMask();
411 std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize);
412 return hash_combine(MO.getType(), MO.getTargetFlags(),
413 stable_hash_combine_array(RegMaskHashes.data(),
414 RegMaskHashes.size()));
415 }
416
417 assert(0 && "MachineOperand not associated with any MachineFunction");
418 return hash_combine(MO.getType(), MO.getTargetFlags());
419 }
421 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
423 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
425 return hash_combine(MO.getType(), MO.getTargetFlags(),
428 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
430 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
432 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
434 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
435 }
436 llvm_unreachable("Invalid machine operand type");
437}
438
439// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
440// it.
441static void tryToGetTargetInfo(const MachineOperand &MO,
442 const TargetRegisterInfo *&TRI,
443 const TargetIntrinsicInfo *&IntrinsicInfo) {
444 if (const MachineFunction *MF = getMFIfAvailable(MO)) {
445 TRI = MF->getSubtarget().getRegisterInfo();
446 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
447 }
448}
449
450static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
451 const auto *TII = MF.getSubtarget().getInstrInfo();
452 assert(TII && "expected instruction info");
453 auto Indices = TII->getSerializableTargetIndices();
454 auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
455 return I.first == Index;
456 });
457 if (Found != Indices.end())
458 return Found->second;
459 return nullptr;
460}
461
463 const MachineFunction *MF = getMFIfAvailable(*this);
464 return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
465}
466
467static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
469 for (const auto &I : Flags) {
470 if (I.first == TF) {
471 return I.second;
472 }
473 }
474 return nullptr;
475}
476
477static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
478 const TargetRegisterInfo *TRI) {
479 if (!TRI) {
480 OS << "%dwarfreg." << DwarfReg;
481 return;
482 }
483
484 if (std::optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
485 OS << printReg(*Reg, TRI);
486 else
487 OS << "<badreg>";
488}
489
491 ModuleSlotTracker &MST) {
492 OS << "%ir-block.";
493 if (BB.hasName()) {
495 return;
496 }
497 std::optional<int> Slot;
498 if (const Function *F = BB.getParent()) {
499 if (F == MST.getCurrentFunction()) {
500 Slot = MST.getLocalSlot(&BB);
501 } else if (const Module *M = F->getParent()) {
502 ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
503 CustomMST.incorporateFunction(*F);
504 Slot = CustomMST.getLocalSlot(&BB);
505 }
506 }
507 if (Slot)
509 else
510 OS << "<unknown>";
511}
512
513static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
514 SyncScope::ID SSID,
516 switch (SSID) {
518 break;
519 default:
520 if (SSNs.empty())
522
523 OS << "syncscope(\"";
524 printEscapedString(SSNs[SSID], OS);
525 OS << "\") ";
526 break;
527 }
528}
529
530static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
531 unsigned TMMOFlag) {
532 auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
533 for (const auto &I : Flags) {
534 if (I.first == TMMOFlag) {
535 return I.second;
536 }
537 }
538 return nullptr;
539}
540
541static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
542 const MachineFrameInfo *MFI) {
544 if (MFI) {
545 IsFixed = MFI->isFixedObjectIndex(FrameIndex);
546 if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
547 if (Alloca->hasName())
548 Name = Alloca->getName();
549 if (IsFixed)
550 FrameIndex -= MFI->getObjectIndexBegin();
551 }
553}
554
556 const TargetRegisterInfo *TRI) {
557 OS << "%subreg.";
558 if (TRI && Index != 0 && Index < TRI->getNumSubRegIndices())
559 OS << TRI->getSubRegIndexName(Index);
560 else
561 OS << Index;
562}
563
565 const MachineOperand &Op) {
566 if (!Op.getTargetFlags())
567 return;
569 if (!MF)
570 return;
571
572 const auto *TII = MF->getSubtarget().getInstrInfo();
573 assert(TII && "expected instruction info");
574 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
575 OS << "target-flags(";
576 const bool HasDirectFlags = Flags.first;
577 const bool HasBitmaskFlags = Flags.second;
578 if (!HasDirectFlags && !HasBitmaskFlags) {
579 OS << "<unknown>) ";
580 return;
581 }
582 if (HasDirectFlags) {
583 if (const auto *Name = getTargetFlagName(TII, Flags.first))
584 OS << Name;
585 else
586 OS << "<unknown target flag>";
587 }
588 if (!HasBitmaskFlags) {
589 OS << ") ";
590 return;
591 }
592 bool IsCommaNeeded = HasDirectFlags;
593 unsigned BitMask = Flags.second;
595 for (const auto &Mask : BitMasks) {
596 // Check if the flag's bitmask has the bits of the current mask set.
597 if ((BitMask & Mask.first) == Mask.first) {
598 if (IsCommaNeeded)
599 OS << ", ";
600 IsCommaNeeded = true;
601 OS << Mask.second;
602 // Clear the bits which were serialized from the flag's bitmask.
603 BitMask &= ~(Mask.first);
604 }
605 }
606 if (BitMask) {
607 // When the resulting flag's bitmask isn't zero, we know that we didn't
608 // serialize all of the bit flags.
609 if (IsCommaNeeded)
610 OS << ", ";
611 OS << "<unknown bitmask target flag>";
612 }
613 OS << ") ";
614}
615
617 OS << "<mcsymbol " << Sym << ">";
618}
619
621 unsigned FrameIndex,
622 bool IsFixed, StringRef Name) {
623 if (IsFixed) {
624 OS << "%fixed-stack." << FrameIndex;
625 return;
626 }
627
628 OS << "%stack." << FrameIndex;
629 if (!Name.empty())
630 OS << '.' << Name;
631}
632
634 if (Offset == 0)
635 return;
636 if (Offset < 0) {
637 OS << " - " << -Offset;
638 return;
639 }
640 OS << " + " << Offset;
641}
642
644 if (Slot == -1)
645 OS << "<badref>";
646 else
647 OS << Slot;
648}
649
650static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
651 const TargetRegisterInfo *TRI) {
652 switch (CFI.getOperation()) {
654 OS << "same_value ";
655 if (MCSymbol *Label = CFI.getLabel())
658 break;
660 OS << "remember_state ";
661 if (MCSymbol *Label = CFI.getLabel())
663 break;
665 OS << "restore_state ";
666 if (MCSymbol *Label = CFI.getLabel())
668 break;
670 OS << "offset ";
671 if (MCSymbol *Label = CFI.getLabel())
674 OS << ", " << CFI.getOffset();
675 break;
677 OS << "def_cfa_register ";
678 if (MCSymbol *Label = CFI.getLabel())
681 break;
683 OS << "def_cfa_offset ";
684 if (MCSymbol *Label = CFI.getLabel())
686 OS << CFI.getOffset();
687 break;
689 OS << "def_cfa ";
690 if (MCSymbol *Label = CFI.getLabel())
693 OS << ", " << CFI.getOffset();
694 break;
696 OS << "llvm_def_aspace_cfa ";
697 if (MCSymbol *Label = CFI.getLabel())
700 OS << ", " << CFI.getOffset();
701 OS << ", " << CFI.getAddressSpace();
702 break;
704 OS << "rel_offset ";
705 if (MCSymbol *Label = CFI.getLabel())
708 OS << ", " << CFI.getOffset();
709 break;
711 OS << "adjust_cfa_offset ";
712 if (MCSymbol *Label = CFI.getLabel())
714 OS << CFI.getOffset();
715 break;
717 OS << "restore ";
718 if (MCSymbol *Label = CFI.getLabel())
721 break;
723 OS << "escape ";
724 if (MCSymbol *Label = CFI.getLabel())
726 if (!CFI.getValues().empty()) {
727 size_t e = CFI.getValues().size() - 1;
728 for (size_t i = 0; i < e; ++i)
729 OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
730 OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
731 }
732 break;
733 }
735 OS << "undefined ";
736 if (MCSymbol *Label = CFI.getLabel())
739 break;
741 OS << "register ";
742 if (MCSymbol *Label = CFI.getLabel())
745 OS << ", ";
747 break;
749 OS << "window_save ";
750 if (MCSymbol *Label = CFI.getLabel())
752 break;
754 OS << "negate_ra_sign_state ";
755 if (MCSymbol *Label = CFI.getLabel())
757 break;
758 default:
759 // TODO: Print the other CFI Operations.
760 OS << "<unserializable cfi directive>";
761 break;
762 }
763}
764
766 const TargetIntrinsicInfo *IntrinsicInfo) const {
767 print(OS, LLT{}, TRI, IntrinsicInfo);
768}
769
771 const TargetRegisterInfo *TRI,
772 const TargetIntrinsicInfo *IntrinsicInfo) const {
773 tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
774 ModuleSlotTracker DummyMST(nullptr);
775 print(OS, DummyMST, TypeToPrint, std::nullopt, /*PrintDef=*/false,
776 /*IsStandalone=*/true,
777 /*ShouldPrintRegisterTies=*/true,
778 /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
779}
780
782 LLT TypeToPrint, std::optional<unsigned> OpIdx,
783 bool PrintDef, bool IsStandalone,
784 bool ShouldPrintRegisterTies,
785 unsigned TiedOperandIdx,
786 const TargetRegisterInfo *TRI,
787 const TargetIntrinsicInfo *IntrinsicInfo) const {
788 printTargetFlags(OS, *this);
789 switch (getType()) {
791 Register Reg = getReg();
792 if (isImplicit())
793 OS << (isDef() ? "implicit-def " : "implicit ");
794 else if (PrintDef && isDef())
795 // Print the 'def' flag only when the operand is defined after '='.
796 OS << "def ";
797 if (isInternalRead())
798 OS << "internal ";
799 if (isDead())
800 OS << "dead ";
801 if (isKill())
802 OS << "killed ";
803 if (isUndef())
804 OS << "undef ";
805 if (isEarlyClobber())
806 OS << "early-clobber ";
807 if (getReg().isPhysical() && isRenamable())
808 OS << "renamable ";
809 // isDebug() is exactly true for register operands of a DBG_VALUE. So we
810 // simply infer it when parsing and do not need to print it.
811
812 const MachineRegisterInfo *MRI = nullptr;
813 if (Reg.isVirtual()) {
814 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
815 MRI = &MF->getRegInfo();
816 }
817 }
818
819 OS << printReg(Reg, TRI, 0, MRI);
820 // Print the sub register.
821 if (unsigned SubReg = getSubReg()) {
822 if (TRI)
823 OS << '.' << TRI->getSubRegIndexName(SubReg);
824 else
825 OS << ".subreg" << SubReg;
826 }
827 // Print the register class / bank.
828 if (Reg.isVirtual()) {
829 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
830 const MachineRegisterInfo &MRI = MF->getRegInfo();
831 if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
832 OS << ':';
833 OS << printRegClassOrBank(Reg, MRI, TRI);
834 }
835 }
836 }
837 // Print ties.
838 if (ShouldPrintRegisterTies && isTied() && !isDef())
839 OS << "(tied-def " << TiedOperandIdx << ")";
840 // Print types.
841 if (TypeToPrint.isValid())
842 OS << '(' << TypeToPrint << ')';
843 break;
844 }
846 const MIRFormatter *Formatter = nullptr;
847 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
848 const auto *TII = MF->getSubtarget().getInstrInfo();
849 assert(TII && "expected instruction info");
850 Formatter = TII->getMIRFormatter();
851 }
852 if (Formatter)
853 Formatter->printImm(OS, *getParent(), OpIdx, getImm());
854 else
855 OS << getImm();
856 break;
857 }
859 getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
860 break;
862 getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
863 break;
866 break;
868 int FrameIndex = getIndex();
869 bool IsFixed = false;
870 const MachineFrameInfo *MFI = nullptr;
871 if (const MachineFunction *MF = getMFIfAvailable(*this))
872 MFI = &MF->getFrameInfo();
873 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
874 break;
875 }
877 OS << "%const." << getIndex();
879 break;
881 OS << "target-index(";
882 const char *Name = "<unknown>";
883 if (const MachineFunction *MF = getMFIfAvailable(*this))
884 if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
885 Name = TargetIndexName;
886 OS << Name << ')';
888 break;
889 }
892 break;
894 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
896 break;
899 OS << '&';
900 if (Name.empty()) {
901 OS << "\"\"";
902 } else {
904 }
906 break;
907 }
909 OS << "blockaddress(";
910 getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
911 MST);
912 OS << ", ";
913 printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
914 OS << ')';
916 break;
917 }
919 OS << "<regmask";
920 if (TRI) {
921 unsigned NumRegsInMask = 0;
922 unsigned NumRegsEmitted = 0;
923 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
924 unsigned MaskWord = i / 32;
925 unsigned MaskBit = i % 32;
926 if (getRegMask()[MaskWord] & (1 << MaskBit)) {
927 if (PrintRegMaskNumRegs < 0 ||
928 NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
929 OS << " " << printReg(i, TRI);
930 NumRegsEmitted++;
931 }
932 NumRegsInMask++;
933 }
934 }
935 if (NumRegsEmitted != NumRegsInMask)
936 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
937 } else {
938 OS << " ...";
939 }
940 OS << ">";
941 break;
942 }
944 const uint32_t *RegMask = getRegLiveOut();
945 OS << "liveout(";
946 if (!TRI) {
947 OS << "<unknown>";
948 } else {
949 bool IsCommaNeeded = false;
950 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
951 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
952 if (IsCommaNeeded)
953 OS << ", ";
954 OS << printReg(Reg, TRI);
955 IsCommaNeeded = true;
956 }
957 }
958 }
959 OS << ")";
960 break;
961 }
964 break;
967 break;
969 OS << "dbg-instr-ref(" << getInstrRefInstrIndex() << ", "
970 << getInstrRefOpIndex() << ')';
971 break;
972 }
974 if (const MachineFunction *MF = getMFIfAvailable(*this))
975 printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
976 else
977 OS << "<cfi directive>";
978 break;
979 }
982 if (ID < Intrinsic::num_intrinsics)
983 OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
984 else if (IntrinsicInfo)
985 OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
986 else
987 OS << "intrinsic(" << ID << ')';
988 break;
989 }
991 auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
992 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
993 << Pred << ')';
994 break;
995 }
997 OS << "shufflemask(";
999 StringRef Separator;
1000 for (int Elt : Mask) {
1001 if (Elt == -1)
1002 OS << Separator << "undef";
1003 else
1004 OS << Separator << Elt;
1005 Separator = ", ";
1006 }
1007
1008 OS << ')';
1009 break;
1010 }
1011}
1012
1013#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1014LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
1015#endif
1016
1017//===----------------------------------------------------------------------===//
1018// MachineMemOperand Implementation
1019//===----------------------------------------------------------------------===//
1020
1021/// getAddrSpace - Return the LLVM IR address space number that this pointer
1022/// points into.
1024
1025/// isDereferenceable - Return true if V is always dereferenceable for
1026/// Offset + Size byte.
1028 const DataLayout &DL) const {
1029 if (!isa<const Value *>(V))
1030 return false;
1031
1032 const Value *BasePtr = cast<const Value *>(V);
1033 if (BasePtr == nullptr)
1034 return false;
1035
1037 BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
1038}
1039
1040/// getConstantPool - Return a MachinePointerInfo record that refers to the
1041/// constant pool.
1044}
1045
1046/// getFixedStack - Return a MachinePointerInfo record that refers to the
1047/// the specified FrameIndex.
1049 int FI, int64_t Offset) {
1051}
1052
1055}
1056
1059}
1060
1062 int64_t Offset, uint8_t ID) {
1064}
1065
1068}
1069
1071 LLT type, Align a, const AAMDNodes &AAInfo,
1072 const MDNode *Ranges, SyncScope::ID SSID,
1073 AtomicOrdering Ordering,
1074 AtomicOrdering FailureOrdering)
1075 : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1076 AAInfo(AAInfo), Ranges(Ranges) {
1077 assert((PtrInfo.V.isNull() || isa<const PseudoSourceValue *>(PtrInfo.V) ||
1078 isa<PointerType>(cast<const Value *>(PtrInfo.V)->getType())) &&
1079 "invalid pointer value");
1080 assert((isLoad() || isStore()) && "Not a load/store!");
1081
1082 AtomicInfo.SSID = static_cast<unsigned>(SSID);
1083 assert(getSyncScopeID() == SSID && "Value truncated");
1084 AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1085 assert(getSuccessOrdering() == Ordering && "Value truncated");
1086 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1087 assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1088}
1089
1091 uint64_t s, Align a,
1092 const AAMDNodes &AAInfo,
1093 const MDNode *Ranges, SyncScope::ID SSID,
1094 AtomicOrdering Ordering,
1095 AtomicOrdering FailureOrdering)
1096 : MachineMemOperand(ptrinfo, f,
1097 s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
1098 AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1099
1101 // The Value and Offset may differ due to CSE. But the flags and size
1102 // should be the same.
1103 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1104 assert((MMO->getSize() == ~UINT64_C(0) || getSize() == ~UINT64_C(0) ||
1105 MMO->getSize() == getSize()) &&
1106 "Size mismatch!");
1107
1108 if (MMO->getBaseAlign() >= getBaseAlign()) {
1109 // Update the alignment value.
1110 BaseAlign = MMO->getBaseAlign();
1111 // Also update the base and offset, because the new alignment may
1112 // not be applicable with the old ones.
1113 PtrInfo = MMO->PtrInfo;
1114 }
1115}
1116
1117/// getAlign - Return the minimum known alignment in bytes of the
1118/// actual memory reference.
1121}
1122
1125 const LLVMContext &Context,
1126 const MachineFrameInfo *MFI,
1127 const TargetInstrInfo *TII) const {
1128 OS << '(';
1129 if (isVolatile())
1130 OS << "volatile ";
1131 if (isNonTemporal())
1132 OS << "non-temporal ";
1133 if (isDereferenceable())
1134 OS << "dereferenceable ";
1135 if (isInvariant())
1136 OS << "invariant ";
1137 if (TII) {
1140 << "\" ";
1143 << "\" ";
1146 << "\" ";
1147 } else {
1149 OS << "\"MOTargetFlag1\" ";
1151 OS << "\"MOTargetFlag2\" ";
1153 OS << "\"MOTargetFlag3\" ";
1154 }
1155
1156 assert((isLoad() || isStore()) &&
1157 "machine memory operand must be a load or store (or both)");
1158 if (isLoad())
1159 OS << "load ";
1160 if (isStore())
1161 OS << "store ";
1162
1164
1166 OS << toIRString(getSuccessOrdering()) << ' ';
1168 OS << toIRString(getFailureOrdering()) << ' ';
1169
1170 if (getMemoryType().isValid())
1171 OS << '(' << getMemoryType() << ')';
1172 else
1173 OS << "unknown-size";
1174
1175 if (const Value *Val = getValue()) {
1176 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1177 MIRFormatter::printIRValue(OS, *Val, MST);
1178 } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1179 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1180 assert(PVal && "Expected a pseudo source value");
1181 switch (PVal->kind()) {
1183 OS << "stack";
1184 break;
1186 OS << "got";
1187 break;
1189 OS << "jump-table";
1190 break;
1192 OS << "constant-pool";
1193 break;
1195 int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1196 bool IsFixed = true;
1197 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1198 break;
1199 }
1201 OS << "call-entry ";
1202 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1203 OS, /*PrintType=*/false, MST);
1204 break;
1206 OS << "call-entry &";
1208 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1209 break;
1210 default: {
1211 const MIRFormatter *Formatter = TII->getMIRFormatter();
1212 // FIXME: This is not necessarily the correct MIR serialization format for
1213 // a custom pseudo source value, but at least it allows
1214 // MIR printing to work on a target with custom pseudo source
1215 // values.
1216 OS << "custom \"";
1217 Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1218 OS << '\"';
1219 break;
1220 }
1221 }
1222 } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1223 OS << ((isLoad() && isStore()) ? " on "
1224 : isLoad() ? " from "
1225 : " into ")
1226 << "unknown-address";
1227 }
1229 if (getSize() > 0 && getAlign() != getSize())
1230 OS << ", align " << getAlign().value();
1231 if (getAlign() != getBaseAlign())
1232 OS << ", basealign " << getBaseAlign().value();
1233 auto AAInfo = getAAInfo();
1234 if (AAInfo.TBAA) {
1235 OS << ", !tbaa ";
1236 AAInfo.TBAA->printAsOperand(OS, MST);
1237 }
1238 if (AAInfo.Scope) {
1239 OS << ", !alias.scope ";
1240 AAInfo.Scope->printAsOperand(OS, MST);
1241 }
1242 if (AAInfo.NoAlias) {
1243 OS << ", !noalias ";
1244 AAInfo.NoAlias->printAsOperand(OS, MST);
1245 }
1246 if (getRanges()) {
1247 OS << ", !range ";
1248 getRanges()->printAsOperand(OS, MST);
1249 }
1250 // FIXME: Implement addrspace printing/parsing in MIR.
1251 // For now, print this even though parsing it is not available in MIR.
1252 if (unsigned AS = getAddrSpace())
1253 OS << ", addrspace " << AS;
1254
1255 OS << ')';
1256}
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:510
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
std::string Name
uint64_t Size
Symbol * Sym
Definition: ELF_riscv.cpp:477
const HexagonInstrInfo * TII
static bool isDebug()
static bool isUndef(ArrayRef< int > Mask)
IRTranslator LLVM IR MI
This file contains an interface for creating legacy passes to print out IR in various granularities.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
unsigned const TargetRegisterInfo * TRI
LLVMContext & Context
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file contains some functions that are useful when dealing with strings.
static constexpr uint32_t RegMask
Definition: aarch32.h:221
Class for arbitrary precision integers.
Definition: APInt.h:76
an instruction to allocate memory on the stack
Definition: Instructions.h:58
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:213
Function * getFunction() const
Definition: Constants.h:902
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:748
bool isIntPredicate() const
Definition: InstrTypes.h:856
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:260
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:276
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
constexpr bool isValid() const
Definition: LowLevelType.h:137
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
MCSymbol * getLabel() const
Definition: MCDwarf.h:659
unsigned getAddressSpace() const
Definition: MCDwarf.h:675
unsigned getRegister2() const
Definition: MCDwarf.h:670
unsigned getRegister() const
Definition: MCDwarf.h:661
int getOffset() const
Definition: MCDwarf.h:680
OpType getOperation() const
Definition: MCDwarf.h:658
StringRef getValues() const
Definition: MCDwarf.h:688
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
Metadata node.
Definition: Metadata.h:1037
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:32
virtual void printImm(raw_ostream &OS, const MachineInstr &MI, std::optional< unsigned > OpIdx, int64_t Imm) const
Implement target specific printing for machine operand immediate value, so that we can have more mean...
Definition: MIRFormatter.h:43
virtual void printCustomPseudoSourceValue(raw_ostream &OS, ModuleSlotTracker &MST, const PseudoSourceValue &PSV) const
Implement target specific printing of target custom pseudo source value.
Definition: MIRFormatter.h:60
static void printIRValue(raw_ostream &OS, const Value &V, ModuleSlotTracker &MST)
Helper functions to print IR value as MIR serialization format which will be useful for target specif...
Definition: MIRPrinter.cpp:961
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
int getObjectIndexBegin() const
Return the minimum frame object index.
PseudoSourceValueManager & getPSVManager() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:749
A description of a memory reference used in the backend.
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
const PseudoSourceValue * getPseudoValue() const
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
LLT getMemoryType() const
Return the memory type of the memory reference.
unsigned getAddrSpace() const
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
const MDNode * getRanges() const
Return the range tag for the memory reference.
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
uint64_t getSize() const
Return the size in bytes of the memory reference.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
const void * getOpaqueValue() const
Flags
Flags values. These may be or'd together.
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
Flags getFlags() const
Return the raw flags of the source value,.
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
const Value * getValue() const
Return the base address of the memory access.
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
unsigned getInstrRefOpIndex() const
void setInstrRefInstrIndex(unsigned InstrIdx)
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
const GlobalValue * getGlobal() const
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
void setInstrRefOpIndex(unsigned OpIdx)
const ConstantInt * getCImm() const
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
int64_t getImm() const
unsigned getInstrRefInstrIndex() const
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
bool isImplicit() const
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
void setIsRenamable(bool Val=true)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const MDNode * getMetadata() const
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
void setReg(Register Reg)
Change the register this operand corresponds to.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
unsigned getCFIIndex() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
void ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx, unsigned TargetFlags=0)
Replace this operand with an Instruction Reference.
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
const BlockAddress * getBlockAddress() const
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
void setOffset(int64_t Offset)
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
unsigned getTargetFlags() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
void setIsUndef(bool Val=true)
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
Intrinsic::ID getIntrinsicID() const
bool isInternalRead() const
void setTargetFlags(unsigned F)
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void setIndex(int Idx)
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
const ConstantFP * getFPImm() const
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
unsigned getPredicate() const
MCSymbol * getMCSymbol() const
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_Predicate
Generic predicate for ISel.
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
@ MO_CImmediate
Immediate >64bit operand.
@ MO_BlockAddress
Address of a basic block.
@ MO_DbgInstrRef
Integer indices referring to an instruction+operand.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_IntrinsicID
Intrinsic ID for ISel.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
@ MO_TargetIndex
Target-dependent index+offset operand.
@ MO_Metadata
Metadata reference (for debug info)
@ MO_FPImmediate
Floating-point immediate operand.
@ MO_RegisterLiveOut
Mask of live-out registers.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:5021
Manage lifetime of a slot tracker for printing IR.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:906
const Function * getCurrentFunction() const
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:892
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:142
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot.
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like).
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function,...
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
bool empty() const
Definition: SmallVector.h:94
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
Definition: Value.h:74
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:4915
bool hasName() const
Definition: Value.h:261
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:309
An opaque object representing a hash code.
Definition: Hashing.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
Definition: Function.cpp:1005
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:57
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
hash_code hash_value(const FixedPointSemantics &Val)
Definition: APFixedPoint.h:128
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition: Loads.cpp:199
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
stable_hash stable_hash_combine_array(const stable_hash *P, size_t C)
Definition: StableHashing.h:92
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:125
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ Other
Any other memory.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1753
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:212
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:613
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:376
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:738
MDNode * Scope
The tag for alias scope specification (used with noalias).
Definition: Metadata.h:761
MDNode * TBAA
The tag for type-based alias analysis.
Definition: Metadata.h:755
MDNode * NoAlias
The tag specifying the noalias scope.
Definition: Metadata.h:764
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
int64_t Offset
Offset - This is an offset from the base Value*.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.