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24 #include "llvm/Config/llvm-config.h"
38 cl::desc(
"Number of registers to limit to when "
39 "printing regmask operands in IR dumps. "
69 SmallContents.RegNo =
Reg;
75 SmallContents.RegNo =
Reg;
103 assert(
isReg() &&
"Wrong MachineOperand accessor");
104 assert((!Val || !
isDebug()) &&
"Marking a debug operation as def");
107 assert(!IsDeadOrKill &&
"Changing def/use with dead/kill set not supported");
120 assert(
isReg() &&
"Wrong MachineOperand accessor");
122 "isRenamable should only be checked on physical registers");
138 assert(
isReg() &&
"Wrong MachineOperand accessor");
140 "setIsRenamable should only be called on physical registers");
146 void MachineOperand::removeRegFromUses() {
147 if (!
isReg() || !isOnRegUseList())
151 MF->getRegInfo().removeRegOperandFromUseList(
this);
163 Contents.ImmVal = ImmVal;
168 unsigned TargetFlags) {
174 Contents.CFP = FPImm;
179 unsigned TargetFlags) {
181 "Cannot change a tied operand into an external symbol");
186 Contents.OffsetedInfo.Val.SymbolName = SymName;
192 unsigned TargetFlags) {
194 "Cannot change a tied operand into a global address");
199 Contents.OffsetedInfo.Val.GV = GV;
206 "Cannot change a tied operand into an MCSymbol");
217 "Cannot change a tied operand into a FrameIndex");
227 unsigned TargetFlags) {
229 "Cannot change a tied operand into a FrameIndex");
240 unsigned TargetFlags) {
242 "Cannot change a tied operand into a DbgInstrRef");
256 bool isKill,
bool isDead,
bool isUndef,
260 RegInfo = &MF->getRegInfo();
263 bool WasReg =
isReg();
264 if (RegInfo && WasReg)
276 SmallContents.RegNo =
Reg;
277 SubReg_TargetFlags = 0;
283 IsInternalRead =
false;
284 IsEarlyClobber =
false;
287 Contents.Reg.Prev =
nullptr;
338 if (RegMask == OtherRegMask)
345 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
407 std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize);
410 RegMaskHashes.size()));
413 assert(0 &&
"MachineOperand not associated with any MachineFunction");
441 TRI = MF->getSubtarget().getRegisterInfo();
442 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
448 assert(
TII &&
"expected instruction info");
449 auto Indices =
TII->getSerializableTargetIndices();
450 auto Found =
find_if(Indices, [&](
const std::pair<int, const char *> &
I) {
453 if (Found != Indices.end())
454 return Found->second;
465 for (
const auto &
I : Flags) {
476 OS <<
"%dwarfreg." << DwarfReg;
493 std::optional<int> Slot;
497 }
else if (
const Module *
M =
F->getParent()) {
519 OS <<
"syncscope(\"";
520 printEscapedString(SSNs[SSID], OS);
528 auto Flags =
TII.getSerializableMachineMemOperandTargetFlags();
529 for (
const auto &
I : Flags) {
530 if (
I.first == TMMOFlag) {
543 if (Alloca->hasName())
544 Name = Alloca->getName();
562 if (!
Op.getTargetFlags())
569 assert(
TII &&
"expected instruction info");
571 OS <<
"target-flags(";
572 const bool HasDirectFlags = Flags.first;
573 const bool HasBitmaskFlags = Flags.second;
574 if (!HasDirectFlags && !HasBitmaskFlags) {
578 if (HasDirectFlags) {
582 OS <<
"<unknown target flag>";
584 if (!HasBitmaskFlags) {
588 bool IsCommaNeeded = HasDirectFlags;
589 unsigned BitMask = Flags.second;
591 for (
const auto &
Mask : BitMasks) {
593 if ((BitMask &
Mask.first) ==
Mask.first) {
596 IsCommaNeeded =
true;
599 BitMask &= ~(
Mask.first);
607 OS <<
"<unknown bitmask target flag>";
613 OS <<
"<mcsymbol " << Sym <<
">";
656 OS <<
"remember_state ";
661 OS <<
"restore_state ";
673 OS <<
"def_cfa_register ";
679 OS <<
"def_cfa_offset ";
692 OS <<
"llvm_def_aspace_cfa ";
707 OS <<
"adjust_cfa_offset ";
724 for (
size_t i = 0;
i <
e; ++
i)
745 OS <<
"window_save ";
750 OS <<
"negate_ra_sign_state ";
756 OS <<
"<unserializable cfi directive>";
771 print(OS, DummyMST, TypeToPrint, std::nullopt,
false,
774 0,
TRI, IntrinsicInfo);
778 LLT TypeToPrint, std::optional<unsigned> OpIdx,
779 bool PrintDef,
bool IsStandalone,
780 bool ShouldPrintRegisterTies,
781 unsigned TiedOperandIdx,
789 OS << (
isDef() ?
"implicit-def " :
"implicit ");
790 else if (PrintDef &&
isDef())
802 OS <<
"early-clobber ";
809 if (
Reg.isVirtual()) {
811 MRI = &MF->getRegInfo();
821 OS <<
".subreg" <<
SubReg;
824 if (
Reg.isVirtual()) {
834 if (ShouldPrintRegisterTies &&
isTied() && !
isDef())
835 OS <<
"(tied-def " << TiedOperandIdx <<
")";
838 OS <<
'(' << TypeToPrint <<
')';
844 const auto *
TII = MF->getSubtarget().getInstrInfo();
845 assert(
TII &&
"expected instruction info");
846 Formatter =
TII->getMIRFormatter();
865 bool IsFixed =
false;
868 MFI = &MF->getFrameInfo();
877 OS <<
"target-index(";
878 const char *Name =
"<unknown>";
881 Name = TargetIndexName;
905 OS <<
"blockaddress(";
917 unsigned NumRegsInMask = 0;
918 unsigned NumRegsEmitted = 0;
920 unsigned MaskWord =
i / 32;
921 unsigned MaskBit =
i % 32;
922 if (
getRegMask()[MaskWord] & (1 << MaskBit)) {
931 if (NumRegsEmitted != NumRegsInMask)
932 OS <<
" and " << (NumRegsInMask - NumRegsEmitted) <<
" more...";
945 bool IsCommaNeeded =
false;
947 if (RegMask[
Reg / 32] & (1U << (
Reg % 32))) {
951 IsCommaNeeded =
true;
973 OS <<
"<cfi directive>";
978 if (
ID < Intrinsic::num_intrinsics)
980 else if (IntrinsicInfo)
981 OS <<
"intrinsic(@" << IntrinsicInfo->
getName(
ID) <<
')';
983 OS <<
"intrinsic(" <<
ID <<
')';
993 OS <<
"shufflemask(";
996 for (
int Elt :
Mask) {
998 OS << Separator <<
"undef";
1000 OS << Separator << Elt;
1009 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1029 if (BasePtr ==
nullptr)
1045 int FI, int64_t
Offset) {
1072 AAInfo(AAInfo), Ranges(Ranges) {
1075 "invalid pointer value");
1078 AtomicInfo.SSID =
static_cast<unsigned>(SSID);
1080 AtomicInfo.Ordering =
static_cast<unsigned>(Ordering);
1082 AtomicInfo.FailureOrdering =
static_cast<unsigned>(FailureOrdering);
1093 s == ~UINT64_C(0) ?
LLT() :
LLT::scalar(8 *
s),
a,
1094 AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1119 PtrInfo = MMO->PtrInfo;
1138 OS <<
"non-temporal ";
1140 OS <<
"dereferenceable ";
1155 OS <<
"\"MOTargetFlag1\" ";
1157 OS <<
"\"MOTargetFlag2\" ";
1159 OS <<
"\"MOTargetFlag3\" ";
1163 "machine memory operand must be a load or store (or both)");
1179 OS <<
"unknown-size";
1186 assert(PVal &&
"Expected a pseudo source value");
1187 switch (PVal->kind()) {
1198 OS <<
"constant-pool";
1201 int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1202 bool IsFixed =
true;
1207 OS <<
"call-entry ";
1208 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1212 OS <<
"call-entry &";
1214 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1232 <<
"unknown-address";
1245 OS <<
", !alias.scope ";
1249 OS <<
", !noalias ";
1259 OS <<
", addrspace " << AS;
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI)
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
@ MO_BlockAddress
Address of a basic block.
const PseudoSourceValue * getGOT()
Return a pseudo source value referencing the global offset table (or something the like).
@ MO_Immediate
Immediate operand.
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
This is an optimization pass for GlobalISel generic memory operations.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
static void tryToGetTargetInfo(const MachineOperand &MO, const TargetRegisterInfo *&TRI, const TargetIntrinsicInfo *&IntrinsicInfo)
A parsed version of the target data layout string in and methods for querying it.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
const GlobalValue * getGlobal() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
@ MO_RegisterLiveOut
Mask of live-out registers.
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
virtual const TargetInstrInfo * getInstrInfo() const
static const MachineFunction * getMFIfAvailable(const MachineOperand &MO)
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
Print a stack object reference.
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Print an IRSlotNumber.
stable_hash stable_hash_combine_array(const stable_hash *P, size_t C)
Intrinsic::ID getIntrinsicID() const
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
const BlockAddress * getBlockAddress() const
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
const Function * getCurrentFunction() const
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Reg
All possible values of the reg field in the ModR/M byte.
@ System
Synchronized with respect to all concurrently executing threads.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
const void * getOpaqueValue() const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
A description of a memory reference used in the backend.
@ MO_CFIIndex
MCCFIInstruction index.
const char * getTargetIndexName() const
getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name...
PseudoSourceValueManager & getPSVManager() const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
void getSyncScopeNames(SmallVectorImpl< StringRef > &SSNs) const
getSyncScopeNames - Populates client supplied SmallVector with synchronization scope names registered...
void ChangeToTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Replace this operand with a target index.
void incorporateFunction(const Function &F)
Incorporate the given function.
const PseudoSourceValue * getStack()
Return a pseudo source value referencing the area below the stack frame of a function,...
void ChangeToFrameIndex(int Idx, unsigned TargetFlags=0)
Replace this operand with a frame index.
static StringRef getPredicateName(Predicate P)
MDNode * Scope
The tag for alias scope specification (used with noalias).
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
int64_t getOffset() const
Return the offset from the symbol in this operand.
Manage lifetime of a slot tracker for printing IR.
unsigned const TargetRegisterInfo * TRI
T get() const
Returns the value of the specified pointer type.
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
MCSymbol * getMCSymbol() const
@ MO_Register
Register operand.
LLVM Basic Block Representation.
bool is() const
Test if the Union currently holds the type matching T.
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
static bool isUndef(ArrayRef< int > Mask)
TargetIntrinsicInfo - Interface to description of machine instruction set.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
int64_t Offset
Offset - This is an offset from the base Value*.
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
@ MO_GlobalAddress
Address of a global value.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
unsigned getAddrSpace() const
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
static unsigned getRegMaskSize(unsigned NumRegs)
Returns number of elements needed for a regmask array.
const Value * getValue() const
Return the base address of the memory access.
(vector float) vec_cmpeq(*A, *B) C
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void setSubReg(unsigned subReg)
@ MO_FrameIndex
Abstract Stack Frame Index.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
const HexagonInstrInfo * TII
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
MachineOperand class - Representation of each machine instruction operand.
unsigned getInstrRefInstrIndex() const
This class implements an extremely fast bulk output stream that can only output to a stream.
ConstantFP - Floating Point Values [float, double].
void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
OpType getOperation() const
Printable printJumpTableEntryReference(unsigned Idx)
Prints a jump table entry reference.
void setTargetFlags(unsigned F)
Special value supplied for machine level alias analysis.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
This struct is a compact representation of a valid (non-zero power of two) alignment.
int getObjectIndexBegin() const
Return the minimum frame object index.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachinePointerInfo(const Value *v, int64_t offset=0, uint8_t ID=0)
unsigned getRegister() const
static void printOperandOffset(raw_ostream &OS, int64_t Offset)
Print the offset with explicit +/- signs.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
const MDNode * getMetadata() const
constexpr bool empty() const
empty - Check if the string is empty.
@ ExternalSymbolCallEntry
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ MO_Metadata
Metadata reference (for debug info)
void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags=0)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference and DH registers in an instruction requiring REX prefix divb and mulb both produce results in AH If isel emits a CopyFromReg which gets turned into a movb and that can be allocated a r8b r15b To get around isel emits a CopyFromReg from AX and then right shift it down by and truncate it It s not pretty but it works We need some register allocation magic to make the hack go which would often require a callee saved register Callees usually need to keep this value live for most of their body so it doesn t add a significant burden on them We currently implement this in however this is suboptimal because it means that it would be quite awkward to implement the optimization for callers A better implementation would be to relax the LLVM IR rules for sret arguments to allow a function with an sret argument to have a non void return type
unsigned getInstrRefOpIndex() const
void setInstrRefOpIndex(unsigned OpIdx)
unsigned getTargetFlags() const
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const ConstantInt * getCImm() const
Representation of each machine instruction.
bool isDereferenceable() const
multiplies can be turned into SHL s
This class contains a discriminated union of information about pointers in memory operands,...
This is an important class for using LLVM in a threaded context.
@ MO_Predicate
Generic predicate for ISel.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
initializer< Ty > init(const Ty &Val)
std::optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const ConstantFP * getFPImm() const
unsigned getPredicate() const
unsigned getRegister2() const
Flags
Flags values. These may be or'd together.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isEarlyClobber() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
ArrayRef< int > getShuffleMask() const
@ MO_TargetIndex
Target-dependent index+offset operand.
static cl::opt< int > PrintRegMaskNumRegs("print-regmask-num-regs", cl::desc("Number of registers to limit to when " "printing regmask operands in IR dumps. " "unlimited = -1"), cl::init(32), cl::Hidden)
LLT getMemoryType() const
Return the memory type of the memory reference.
@ MO_FPImmediate
Floating-point immediate operand.
static void printFrameIndex(raw_ostream &OS, int FrameIndex, bool IsFixed, const MachineFrameInfo *MFI)
Register getReg() const
getReg - Returns the register number.
A Module instance is used to store all the information related to an LLVM module.
void setInstrRefInstrIndex(unsigned InstrIdx)
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Class for arbitrary precision integers.
bool isIntPredicate() const
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
@ MO_CImmediate
Immediate >64bit operand.
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
unsigned getAddressSpace() const
MachineBasicBlock * getMBB() const
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
StringRef - Represent a constant reference to a string, i.e.
StringRef getValues() const
void ChangeToES(const char *SymName, unsigned TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Type * getType() const
All values are typed, get the type of this value.
void setIsUndef(bool Val=true)
void setIsRenamable(bool Val=true)
@ MO_MachineBasicBlock
MachineBasicBlock reference.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
@ MO_IntrinsicID
Intrinsic ID for ISel.
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
unsigned getAllocaAddrSpace() const
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
const PseudoSourceValue * getJumpTable()
Return a pseudo source value referencing a jump table.
constexpr size_t size() const
size - Get the string size.
Function * getFunction() const
static void printTargetFlags(raw_ostream &OS, const MachineOperand &Op)
Print operand target flags.
void ChangeToGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
ChangeToGA - Replace this operand with a new global address operand.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.
MDNode * NoAlias
The tag specifying the noalias scope.
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
const PseudoSourceValue * getFixedStack(int FI)
Return a pseudo source value referencing a fixed stack frame entry, e.g., a spill slot.
uint64_t value() const
This is a hole in the type system and should not be abused.
uint64_t getSize() const
Return the size in bytes of the memory reference.
@ MO_ExternalSymbol
Name of external global symbol.
unsigned getCFIIndex() const
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
MDNode * TBAA
The tag for type-based alias analysis.
hash_code hash_value(const FixedPointSemantics &Val)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
std::optional< std::vector< StOtherPiece > > Other
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
const char * getSymbolName() const
static const char * getTargetMMOFlagName(const TargetInstrInfo &TII, unsigned TMMOFlag)
void ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx, unsigned TargetFlags=0)
Replace this operand with an Instruction Reference.
void setReg(Register Reg)
Change the register this operand corresponds to.
const char * toIRString(AtomicOrdering ao)
String used by LLVM IR to represent atomic ordering.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
bool isInternalRead() const
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
an instruction to allocate memory on the stack
@ MO_RegisterMask
Mask of preserved registers.
static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, ModuleSlotTracker &MST)
bool isNonTemporal() const
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
const MDNode * getRanges() const
Return the range tag for the memory reference.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
constexpr bool isValid() const
@ MO_DbgInstrRef
Integer indices referring to an instruction+operand.
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
LLVM Value Representation.
Flags getFlags() const
Return the raw flags of the source value,.
const PseudoSourceValue * getConstantPool()
Return a pseudo source value referencing the constant pool.
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
MCSymbol * getLabel() const
Wrapper class representing physical registers. Should be passed by value.
const PseudoSourceValue * getPseudoValue() const
An opaque object representing a hash code.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
void setOffset(int64_t Offset)
static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, SyncScope::ID SSID, SmallVectorImpl< StringRef > &SSNs)