#include "Target/Hexagon/HexagonInstrInfo.h"

Inheritance diagram for llvm::HexagonInstrInfo:

Public Member Functions
	HexagonInstrInfo (HexagonSubtarget &ST)

Register	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
	TargetInstrInfo overrides.

Register	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
	If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

bool	hasLoadFromStackSlot (const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
	Check if the instruction or the bundle of instructions has load from stack slots.

bool	hasStoreToStackSlot (const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
	Check if the instruction or the bundle of instructions has store to stack slots.

bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
	Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.

unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
	Remove the branching code at the end of the specific MBB.

unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
	Insert branch code into the end of the specified MachineBasicBlock.

std::unique_ptr< PipelinerLoopInfo >	analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
	Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

bool	isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
	Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.

bool	isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const override
	Second variant of isProfitableToIfCvt.

bool	isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
	Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion.

void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
	Emit instructions to copy a pair of physical registers.

void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, Register VReg) const override
	Store the specified register of the given register class to the specified stack frame index.

void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, Register VReg) const override
	Load the specified register of the given register class from the specified stack frame index.

bool	expandPostRAPseudo (MachineInstr &MI) const override
	This function is called for all pseudo instructions that remain after register allocation.

bool	getMemOperandsWithOffsetWidth (const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
	Get the base register and byte offset of a load/store instr.

bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
	Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.

void	insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
	Insert a noop into the instruction stream at the specified point.

bool	isPredicated (const MachineInstr &MI) const override
	Returns true if the instruction is already predicated.

bool	isPostIncrement (const MachineInstr &MI) const override
	Return true for post-incremented instructions.

bool	PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
	Convert the instruction into a predicated instruction.

bool	SubsumesPredicate (ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
	Returns true if the first specified predicate subsumes the second, e.g.

bool	ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
	If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.

bool	isPredicable (const MachineInstr &MI) const override
	Return true if the specified instruction can be predicated.

bool	isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
	Test if the given instruction should be considered a scheduling boundary.

unsigned	getInlineAsmLength (const char Str, const MCAsmInfo &MAI, const TargetSubtargetInfo STI=nullptr) const override
	Measure the specified inline asm to determine an approximation of its length.

ScheduleHazardRecognizer *	CreateTargetPostRAHazardRecognizer (const InstrItineraryData II, const ScheduleDAG DAG) const override
	Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation.

bool	analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
	For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

unsigned	getInstrLatency (const InstrItineraryData ItinData, const MachineInstr &MI, unsigned PredCost=nullptr) const override
	Compute the instruction latency of a given instruction.

DFAPacketizer *	CreateTargetScheduleState (const TargetSubtargetInfo &STI) const override
	Create machine specific model for scheduling.

bool	areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override

bool	getBaseAndOffsetPosition (const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
	For instructions with a base and offset, return the position of the base register and offset operands.

bool	getIncrementValue (const MachineInstr &MI, int &Value) const override
	If the instruction is an increment of a constant value, return the amount.

std::optional< unsigned >	getOperandLatency (const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
	getOperandLatency - Compute and return the use operand latency of a given pair of def and use.

std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
	Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied.

ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
	Return an array that contains the direct target flag values and their names.

ArrayRef< std::pair< unsigned, const char * > >	getSerializableBitmaskMachineOperandTargetFlags () const override
	Return an array that contains the bitmask target flag values and their names.

bool	isTailCall (const MachineInstr &MI) const override

bool	isAsCheapAsAMove (const MachineInstr &MI) const override

bool	shouldSink (const MachineInstr &MI) const override

Register	createVR (MachineFunction *MF, MVT VT) const
	HexagonInstrInfo specifics.

MachineInstr *	findLoopInstr (MachineBasicBlock BB, unsigned EndLoopOp, MachineBasicBlock TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
	Find the hardware loop instruction used to set-up the specified loop.

bool	isAbsoluteSet (const MachineInstr &MI) const

bool	isAccumulator (const MachineInstr &MI) const

bool	isAddrModeWithOffset (const MachineInstr &MI) const

bool	isBaseImmOffset (const MachineInstr &MI) const

bool	isComplex (const MachineInstr &MI) const

bool	isCompoundBranchInstr (const MachineInstr &MI) const

bool	isConstExtended (const MachineInstr &MI) const

bool	isDeallocRet (const MachineInstr &MI) const

bool	isDependent (const MachineInstr &ProdMI, const MachineInstr &ConsMI) const

bool	isDotCurInst (const MachineInstr &MI) const

bool	isDotNewInst (const MachineInstr &MI) const

bool	isDuplexPair (const MachineInstr &MIa, const MachineInstr &MIb) const
	Symmetrical. See if these two instructions are fit for duplex pair.

bool	isEndLoopN (unsigned Opcode) const

bool	isExpr (unsigned OpType) const

bool	isExtendable (const MachineInstr &MI) const

bool	isExtended (const MachineInstr &MI) const

bool	isFloat (const MachineInstr &MI) const

bool	isHVXMemWithAIndirect (const MachineInstr &I, const MachineInstr &J) const

bool	isIndirectCall (const MachineInstr &MI) const

bool	isIndirectL4Return (const MachineInstr &MI) const

bool	isJumpR (const MachineInstr &MI) const

bool	isJumpWithinBranchRange (const MachineInstr &MI, unsigned offset) const

bool	isLateSourceInstr (const MachineInstr &MI) const

bool	isLoopN (const MachineInstr &MI) const

bool	isMemOp (const MachineInstr &MI) const

bool	isNewValue (const MachineInstr &MI) const

bool	isNewValue (unsigned Opcode) const

bool	isNewValueInst (const MachineInstr &MI) const

bool	isNewValueJump (const MachineInstr &MI) const

bool	isNewValueJump (unsigned Opcode) const

bool	isNewValueStore (const MachineInstr &MI) const

bool	isNewValueStore (unsigned Opcode) const

bool	isOperandExtended (const MachineInstr &MI, unsigned OperandNum) const

bool	isPredicatedNew (const MachineInstr &MI) const

bool	isPredicatedNew (unsigned Opcode) const

bool	isPredicatedTrue (const MachineInstr &MI) const

bool	isPredicatedTrue (unsigned Opcode) const

bool	isPredicated (unsigned Opcode) const

bool	isPredicateLate (unsigned Opcode) const

bool	isPredictedTaken (unsigned Opcode) const

bool	isPureSlot0 (const MachineInstr &MI) const

bool	isRestrictNoSlot1Store (const MachineInstr &MI) const

bool	isSaveCalleeSavedRegsCall (const MachineInstr &MI) const

bool	isSignExtendingLoad (const MachineInstr &MI) const

bool	isSolo (const MachineInstr &MI) const

bool	isSpillPredRegOp (const MachineInstr &MI) const

bool	isTC1 (const MachineInstr &MI) const

bool	isTC2 (const MachineInstr &MI) const

bool	isTC2Early (const MachineInstr &MI) const

bool	isTC4x (const MachineInstr &MI) const

bool	isToBeScheduledASAP (const MachineInstr &MI1, const MachineInstr &MI2) const

bool	isHVXVec (const MachineInstr &MI) const

bool	isValidAutoIncImm (const EVT VT, const int Offset) const

bool	isValidOffset (unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend=true) const

bool	isVecAcc (const MachineInstr &MI) const

bool	isVecALU (const MachineInstr &MI) const

bool	isVecUsableNextPacket (const MachineInstr &ProdMI, const MachineInstr &ConsMI) const

bool	isZeroExtendingLoad (const MachineInstr &MI) const

bool	addLatencyToSchedule (const MachineInstr &MI1, const MachineInstr &MI2) const

bool	canExecuteInBundle (const MachineInstr &First, const MachineInstr &Second) const
	Can these instructions execute at the same time in a bundle.

bool	doesNotReturn (const MachineInstr &CallMI) const

bool	hasEHLabel (const MachineBasicBlock *B) const

bool	hasNonExtEquivalent (const MachineInstr &MI) const

bool	hasPseudoInstrPair (const MachineInstr &MI) const

bool	hasUncondBranch (const MachineBasicBlock *B) const

bool	mayBeCurLoad (const MachineInstr &MI) const

bool	mayBeNewStore (const MachineInstr &MI) const

bool	producesStall (const MachineInstr &ProdMI, const MachineInstr &ConsMI) const

bool	producesStall (const MachineInstr &MI, MachineBasicBlock::const_instr_iterator MII) const

bool	predCanBeUsedAsDotNew (const MachineInstr &MI, Register PredReg) const

bool	PredOpcodeHasJMP_c (unsigned Opcode) const

bool	predOpcodeHasNot (ArrayRef< MachineOperand > Cond) const

unsigned	getAddrMode (const MachineInstr &MI) const

MachineOperand *	getBaseAndOffset (const MachineInstr &MI, int64_t &Offset, LocationSize &AccessSize) const

SmallVector< MachineInstr *, 2 >	getBranchingInstrs (MachineBasicBlock &MBB) const

unsigned	getCExtOpNum (const MachineInstr &MI) const

HexagonII::CompoundGroup	getCompoundCandidateGroup (const MachineInstr &MI) const

unsigned	getCompoundOpcode (const MachineInstr &GA, const MachineInstr &GB) const

int	getDuplexOpcode (const MachineInstr &MI, bool ForBigCore=true) const

int	getCondOpcode (int Opc, bool sense) const

int	getDotCurOp (const MachineInstr &MI) const

int	getNonDotCurOp (const MachineInstr &MI) const

int	getDotNewOp (const MachineInstr &MI) const

int	getDotNewPredJumpOp (const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const

int	getDotNewPredOp (const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const

int	getDotOldOp (const MachineInstr &MI) const

HexagonII::SubInstructionGroup	getDuplexCandidateGroup (const MachineInstr &MI) const

short	getEquivalentHWInstr (const MachineInstr &MI) const

unsigned	getInstrTimingClassLatency (const InstrItineraryData *ItinData, const MachineInstr &MI) const

bool	getInvertedPredSense (SmallVectorImpl< MachineOperand > &Cond) const

unsigned	getInvertedPredicatedOpcode (const int Opc) const

int	getMaxValue (const MachineInstr &MI) const

unsigned	getMemAccessSize (const MachineInstr &MI) const

int	getMinValue (const MachineInstr &MI) const

short	getNonExtOpcode (const MachineInstr &MI) const

bool	getPredReg (ArrayRef< MachineOperand > Cond, Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const

short	getPseudoInstrPair (const MachineInstr &MI) const

short	getRegForm (const MachineInstr &MI) const

unsigned	getSize (const MachineInstr &MI) const

uint64_t	getType (const MachineInstr &MI) const

InstrStage::FuncUnits	getUnits (const MachineInstr &MI) const

MachineBasicBlock::instr_iterator	expandVGatherPseudo (MachineInstr &MI) const

unsigned	nonDbgBBSize (const MachineBasicBlock *BB) const
	getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Class information, if available.

unsigned	nonDbgBundleSize (MachineBasicBlock::const_iterator BundleHead) const

void	immediateExtend (MachineInstr &MI) const
	immediateExtend - Changes the instruction in place to one using an immediate extender.

bool	invertAndChangeJumpTarget (MachineInstr &MI, MachineBasicBlock *NewTarget) const

void	genAllInsnTimingClasses (MachineFunction &MF) const

bool	reversePredSense (MachineInstr &MI) const

unsigned	reversePrediction (unsigned Opcode) const

bool	validateBranchCond (const ArrayRef< MachineOperand > &Cond) const

void	setBundleNoShuf (MachineBasicBlock::instr_iterator MIB) const

bool	getBundleNoShuf (const MachineInstr &MIB) const

void	changeDuplexOpcode (MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const

void	translateInstrsForDup (MachineFunction &MF, bool ToBigInstrs=true) const

void	translateInstrsForDup (MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const

short	changeAddrMode_abs_io (short Opc) const

short	changeAddrMode_io_abs (short Opc) const

short	changeAddrMode_io_pi (short Opc) const

short	changeAddrMode_io_rr (short Opc) const

short	changeAddrMode_pi_io (short Opc) const

short	changeAddrMode_rr_io (short Opc) const

short	changeAddrMode_rr_ur (short Opc) const

short	changeAddrMode_ur_rr (short Opc) const

short	changeAddrMode_abs_io (const MachineInstr &MI) const

short	changeAddrMode_io_abs (const MachineInstr &MI) const

short	changeAddrMode_io_rr (const MachineInstr &MI) const

short	changeAddrMode_rr_io (const MachineInstr &MI) const

short	changeAddrMode_rr_ur (const MachineInstr &MI) const

short	changeAddrMode_ur_rr (const MachineInstr &MI) const

MCInst	getNop () const override

Detailed Description

Definition at line 38 of file HexagonInstrInfo.h.

Constructor & Destructor Documentation

◆ HexagonInstrInfo()

HexagonInstrInfo::HexagonInstrInfo ( HexagonSubtarget & ST )

explicit

Definition at line 119 of file HexagonInstrInfo.cpp.

Member Function Documentation

◆ addLatencyToSchedule()

bool HexagonInstrInfo::addLatencyToSchedule	(	const MachineInstr &	MI1,
		const MachineInstr &	MI2
	)		const

Definition at line 3062 of file HexagonInstrInfo.cpp.

References isHVXVec(), and isVecUsableNextPacket().

◆ analyzeBranch()

bool HexagonInstrInfo::analyzeBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *&	TBB,
		MachineBasicBlock *&	FBB,
		SmallVectorImpl< MachineOperand > &	Cond,
		bool	AllowModify
	)		const

override

Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.

This function can analyze one/two way branching only and should (mostly) be called by target independent side.

it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:

If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null.
If this block ends with only an unconditional branch, it sets TBB to be the destination block.
If this block ends with a conditional branch and it falls through to a successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
If this block ends with a conditional branch followed by an unconditional branch, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.

Note that removeBranch and insertBranch must be implemented to support cases where this method returns success.

If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).

First entry is always the opcode of the branching instruction, except when the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a BB with only unconditional jump. Subsequent entries depend upon the opcode, e.g. Jump_c p will have Cond[0] = Jump_c Cond[1] = p HW-loop ENDLOOP: Cond[0] = ENDLOOP Cond[1] = MBB New value jump: Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 – specific opcode Cond[1] = R Cond[2] = Imm

Definition at line 433 of file HexagonInstrInfo.cpp.

References Cond, llvm::MachineOperand::CreateImm(), llvm::dbgs(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), isEndLoopN(), llvm::MachineBasicBlock::isLayoutSuccessor(), llvm::MachineOperand::isMBB(), isNewValueJump(), LLVM_DEBUG, MBB, PredOpcodeHasJMP_c(), llvm::printMBBReference(), and TBB.

Referenced by llvm::MachineBasicBlock::canSplitCriticalEdge(), createDedicatedExit(), FixTail(), getBBFallenThrough(), llvm::MachineBasicBlock::getFallThrough(), INITIALIZE_PASS(), insertBranch(), isAnalyzableBB(), jumpTableHasOtherUses(), llvm::PeelSingleBlockLoop(), updateBranches(), and llvm::MachineBasicBlock::updateTerminator().

◆ analyzeCompare()

bool HexagonInstrInfo::analyzeCompare	(	const MachineInstr &	MI,
		Register &	SrcReg,
		Register &	SrcReg2,
		int64_t &	Mask,
		int64_t &	Value
	)		const

override

For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 1879 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::isImm(), and MI.

◆ analyzeLoopForPipelining()

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > HexagonInstrInfo::analyzeLoopForPipelining ( MachineBasicBlock * LoopBB ) const

override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.

Definition at line 803 of file HexagonInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::MachineBasicBlock::getFirstTerminator(), I, and isEndLoopN().

◆ areMemAccessesTriviallyDisjoint()

bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint	(	const MachineInstr &	MIa,
		const MachineInstr &	MIb
	)		const

override

Definition at line 1985 of file HexagonInstrInfo.cpp.

References getBaseAndOffsetPosition(), llvm::MachineOperand::getImm(), getMemAccessSize(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isImm(), isMemOp(), isPostIncrement(), and llvm::MachineInstr::mayLoad().

Referenced by llvm::MachineInstr::mayAlias().

◆ canExecuteInBundle()

bool HexagonInstrInfo::canExecuteInBundle	(	const MachineInstr &	First,
		const MachineInstr &	Second
	)		const

Can these instructions execute at the same time in a bundle.

Definition at line 3084 of file HexagonInstrInfo.cpp.

References DisableNVSchedule, llvm::First, llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), mayBeNewStore(), and llvm::MachineInstr::mayStore().

Referenced by llvm::HexagonSubtarget::adjustSchedDependency().

◆ changeAddrMode_abs_io() [1/2]

short llvm::HexagonInstrInfo::changeAddrMode_abs_io ( const MachineInstr & MI ) const

inline

Definition at line 515 of file HexagonInstrInfo.h.

References changeAddrMode_abs_io(), and MI.

◆ changeAddrMode_abs_io() [2/2]

short HexagonInstrInfo::changeAddrMode_abs_io ( short Opc ) const

Definition at line 4737 of file HexagonInstrInfo.cpp.

Referenced by changeAddrMode_abs_io().

◆ changeAddrMode_io_abs() [1/2]

short llvm::HexagonInstrInfo::changeAddrMode_io_abs ( const MachineInstr & MI ) const

inline

Definition at line 518 of file HexagonInstrInfo.h.

References changeAddrMode_io_abs(), and MI.

◆ changeAddrMode_io_abs() [2/2]

short HexagonInstrInfo::changeAddrMode_io_abs ( short Opc ) const

Definition at line 4741 of file HexagonInstrInfo.cpp.

Referenced by changeAddrMode_io_abs().

◆ changeAddrMode_io_pi()

short HexagonInstrInfo::changeAddrMode_io_pi ( short Opc ) const

Definition at line 4745 of file HexagonInstrInfo.cpp.

◆ changeAddrMode_io_rr() [1/2]

short llvm::HexagonInstrInfo::changeAddrMode_io_rr ( const MachineInstr & MI ) const

inline

Definition at line 521 of file HexagonInstrInfo.h.

References changeAddrMode_io_rr(), and MI.

◆ changeAddrMode_io_rr() [2/2]

short HexagonInstrInfo::changeAddrMode_io_rr ( short Opc ) const

Definition at line 4749 of file HexagonInstrInfo.cpp.

Referenced by changeAddrMode_io_rr().

◆ changeAddrMode_pi_io()

short HexagonInstrInfo::changeAddrMode_pi_io ( short Opc ) const

Definition at line 4753 of file HexagonInstrInfo.cpp.

◆ changeAddrMode_rr_io() [1/2]

short llvm::HexagonInstrInfo::changeAddrMode_rr_io ( const MachineInstr & MI ) const

inline

Definition at line 524 of file HexagonInstrInfo.h.

References changeAddrMode_rr_io(), and MI.

◆ changeAddrMode_rr_io() [2/2]

short HexagonInstrInfo::changeAddrMode_rr_io ( short Opc ) const

Definition at line 4757 of file HexagonInstrInfo.cpp.

Referenced by changeAddrMode_rr_io().

◆ changeAddrMode_rr_ur() [1/2]

short llvm::HexagonInstrInfo::changeAddrMode_rr_ur ( const MachineInstr & MI ) const

inline

Definition at line 527 of file HexagonInstrInfo.h.

References changeAddrMode_rr_ur(), and MI.

◆ changeAddrMode_rr_ur() [2/2]

short HexagonInstrInfo::changeAddrMode_rr_ur ( short Opc ) const

Definition at line 4761 of file HexagonInstrInfo.cpp.

Referenced by changeAddrMode_rr_ur().

◆ changeAddrMode_ur_rr() [1/2]

short llvm::HexagonInstrInfo::changeAddrMode_ur_rr ( const MachineInstr & MI ) const

inline

Definition at line 530 of file HexagonInstrInfo.h.

References changeAddrMode_ur_rr(), and MI.

◆ changeAddrMode_ur_rr() [2/2]

short HexagonInstrInfo::changeAddrMode_ur_rr ( short Opc ) const

Definition at line 4765 of file HexagonInstrInfo.cpp.

Referenced by changeAddrMode_ur_rr().

◆ changeDuplexOpcode()

void HexagonInstrInfo::changeDuplexOpcode	(	MachineBasicBlock::instr_iterator	MII,
		bool	ToBigInstrs
	)		const

Definition at line 4450 of file HexagonInstrInfo.cpp.

References llvm::get(), getDuplexCandidateGroup(), and getDuplexOpcode().

Referenced by translateInstrsForDup().

◆ ClobbersPredicate()

bool HexagonInstrInfo::ClobbersPredicate	(	MachineInstr &	MI,
		std::vector< MachineOperand > &	Pred,
		bool	SkipDead
	)		const

override

If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.

Definition at line 1729 of file HexagonInstrInfo.cpp.

References llvm::HexagonSubtarget::getRegisterInfo(), and MI.

◆ copyPhysReg()

void HexagonInstrInfo::copyPhysReg	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		MCRegister	DestReg,
		MCRegister	SrcReg,
		bool	KillSrc,
		bool	RenamableDest = `false`,
		bool	RenamableSrc = `false`
	)		const

override

Emit instructions to copy a pair of physical registers.

This function should support copies within any legal register class as well as any cross-class copies created during instruction selection.

The source and destination registers may overlap, which may require a careful implementation when multiple copy instructions are required for large registers. See for example the ARM target.

Definition at line 854 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::LivePhysRegs::contains(), contains(), llvm::dbgs(), DL, llvm::get(), llvm::getKillRegState(), getLiveInRegsAt(), llvm::HexagonSubtarget::getRegisterInfo(), llvm::getUndefRegState(), I, llvm_unreachable, MBB, llvm::printMBBReference(), and llvm::printReg().

Referenced by llvm::AArch64FrameLowering::emitPrologue(), expandPostRAPseudo(), INITIALIZE_PASS(), llvm::Mips16RegisterInfo::saveScavengerRegister(), and tryOptimizeLEAtoMOV().

◆ CreateTargetPostRAHazardRecognizer()

ScheduleHazardRecognizer * HexagonInstrInfo::CreateTargetPostRAHazardRecognizer	(	const InstrItineraryData *	II,
		const ScheduleDAG *	DAG
	)		const

override

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation.

Definition at line 1868 of file HexagonInstrInfo.cpp.

References llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer(), II, and UseDFAHazardRec.

Referenced by INITIALIZE_PASS().

◆ CreateTargetScheduleState()

DFAPacketizer * HexagonInstrInfo::CreateTargetScheduleState ( const TargetSubtargetInfo & STI ) const

override

Create machine specific model for scheduling.

Definition at line 1975 of file HexagonInstrInfo.cpp.

References llvm::TargetSubtargetInfo::getInstrItineraryData(), and II.

◆ createVR()

Register HexagonInstrInfo::createVR	(	MachineFunction *	MF,
		MVT	VT
	)		const

HexagonInstrInfo specifics.

Definition at line 2100 of file HexagonInstrInfo.cpp.

References llvm::MachineFunction::getRegInfo(), llvm_unreachable, and MRI.

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > HexagonInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned TF ) const

override

Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied.

Definition at line 2066 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::MO_Bitmasks.

Referenced by llvm::MachineOperand::printTargetFlags().

◆ doesNotReturn()

bool HexagonInstrInfo::doesNotReturn ( const MachineInstr & CallMI ) const

Definition at line 3109 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by isSchedulingBoundary().

◆ expandPostRAPseudo()

bool HexagonInstrInfo::expandPostRAPseudo ( MachineInstr & MI ) const

override

This function is called for all pseudo instructions that remain after register allocation.

expandPostRAPseudo - This function is called for all pseudo instructions that remain after register allocation.

Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.

Definition at line 1051 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::all_of(), assert(), llvm::LivePhysRegs::available(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), copyPhysReg(), llvm::MachineFunction::createExternalSymbolName(), DL, llvm::MachineBasicBlock::erase(), llvm::get(), llvm::HexagonRegisterInfo::getFrameRegister(), llvm::MachineOperand::getImm(), llvm::GlobalVariable::getInitializer(), llvm::getKillRegState(), getLiveInRegsAt(), getLiveOutRegsAt(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::SrcOp::getReg(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::HexagonSubtarget::getRegisterInfo(), llvm::getRegState(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getTarget(), llvm::getUndefRegState(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::RegState::InternalRead, isConstant(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), llvm::RegState::Kill, mayAlias(), MBB, MBBI, MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOVolatile, MRI, llvm::Offset, OS, and llvm::RegState::Undef.

◆ expandVGatherPseudo()

MachineBasicBlock::instr_iterator HexagonInstrInfo::expandVGatherPseudo ( MachineInstr & MI ) const

Definition at line 1545 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::erase(), llvm::First, llvm::get(), MBB, and MI.

◆ findLoopInstr()

MachineInstr * HexagonInstrInfo::findLoopInstr	(	MachineBasicBlock *	BB,
		unsigned	EndLoopOp,
		MachineBasicBlock *	TargetBB,
		SmallPtrSet< MachineBasicBlock *, 8 > &	Visited
	)		const

Find the hardware loop instruction used to set-up the specified loop.

On Hexagon, we have two instructions used to set-up the hardware loop (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions to indicate the end of a loop.

Definition at line 196 of file HexagonInstrInfo.cpp.

References findLoopInstr(), I, llvm::SmallPtrSetImpl< PtrType >::insert(), PB(), llvm::MachineBasicBlock::predecessors(), and llvm::reverse().

Referenced by analyzeLoopForPipelining(), findLoopInstr(), and insertBranch().

◆ genAllInsnTimingClasses()

void HexagonInstrInfo::genAllInsnTimingClasses ( MachineFunction & MF ) const

Definition at line 4675 of file HexagonInstrInfo.cpp.

References A, B, llvm::MachineFunction::begin(), llvm::BuildMI(), llvm::dbgs(), DL, llvm::MachineInstr::eraseFromParent(), llvm::get(), llvm::MachineInstr::getDesc(), getName(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::getSchedClass(), I, and LLVM_DEBUG.

◆ getAddrMode()

unsigned HexagonInstrInfo::getAddrMode ( const MachineInstr & MI ) const

Definition at line 3280 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::AddrModeMask, llvm::HexagonII::AddrModePos, F, and MI.

Referenced by llvm::HexagonSubtarget::BankConflictMutation::apply(), getBaseAndOffset(), getNonExtOpcode(), hasNonExtEquivalent(), isAbsoluteSet(), isBaseImmOffset(), and isPostIncrement().

◆ getBaseAndOffset()

MachineOperand * HexagonInstrInfo::getBaseAndOffset	(	const MachineInstr &	MI,
		int64_t &	Offset,
		LocationSize &	AccessSize
	)		const

Definition at line 3290 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), getBaseAndOffsetPosition(), llvm::MachineOperand::getImm(), getMemAccessSize(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), isMemOp(), isPostIncrement(), MI, and llvm::Offset.

Referenced by llvm::HexagonSubtarget::BankConflictMutation::apply(), and getMemOperandsWithOffsetWidth().

◆ getBaseAndOffsetPosition()

bool HexagonInstrInfo::getBaseAndOffsetPosition	(	const MachineInstr &	MI,
		unsigned &	BasePos,
		unsigned &	OffsetPos
	)		const

override

For instructions with a base and offset, return the position of the base register and offset operands.

Return the position of the base and offset operands for this instruction.

Definition at line 3322 of file HexagonInstrInfo.cpp.

References isAddrModeWithOffset(), isMemOp(), isPostIncrement(), isPredicated(), and MI.

Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), getIncrementValue(), INITIALIZE_PASS(), and isLoadStoreThatCanHandleDisplacement().

◆ getBranchingInstrs()

SmallVector< MachineInstr *, 2 > HexagonInstrInfo::getBranchingInstrs ( MachineBasicBlock & MBB ) const

Definition at line 3359 of file HexagonInstrInfo.cpp.

References I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), MBB, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getBundleNoShuf()

bool HexagonInstrInfo::getBundleNoShuf ( const MachineInstr & MIB ) const

Definition at line 4730 of file HexagonInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::isBundle(), and llvm::MachineOperand::isImm().

◆ getCExtOpNum()

unsigned HexagonInstrInfo::getCExtOpNum ( const MachineInstr & MI ) const

Definition at line 3417 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::ExtendableOpMask, llvm::HexagonII::ExtendableOpPos, F, and MI.

Referenced by immediateExtend(), and isConstExtended().

◆ getCompoundCandidateGroup()

HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup ( const MachineInstr & MI ) const

Definition at line 3424 of file HexagonInstrInfo.cpp.

References contains(), llvm::HexagonII::HCG_A, llvm::HexagonII::HCG_B, llvm::HexagonII::HCG_C, llvm::HexagonII::HCG_None, isIntRegForSubInst(), and MI.

Referenced by getCompoundOpcode().

◆ getCompoundOpcode()

unsigned HexagonInstrInfo::getCompoundOpcode	(	const MachineInstr &	GA,
		const MachineInstr &	GB
	)		const

Definition at line 3512 of file HexagonInstrInfo.cpp.

References assert(), getCompoundCandidateGroup(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::HexagonII::HCG_A, llvm::HexagonII::HCG_B, llvm::MachineOperand::isImm(), and llvm::MachineInstr::readsRegister().

◆ getCondOpcode()

int HexagonInstrInfo::getCondOpcode	(	int	Opc,
		bool	sense
	)		const

Definition at line 3596 of file HexagonInstrInfo.cpp.

References llvm_unreachable.

Referenced by PredicateInstruction().

◆ getDotCurOp()

int HexagonInstrInfo::getDotCurOp ( const MachineInstr & MI ) const

Definition at line 3608 of file HexagonInstrInfo.cpp.

References llvm_unreachable, and MI.

◆ getDotNewOp()

int HexagonInstrInfo::getDotNewOp ( const MachineInstr & MI ) const

Definition at line 3729 of file HexagonInstrInfo.cpp.

References MI, and llvm::report_fatal_error().

Referenced by llvm::HexagonHazardRecognizer::EmitInstruction(), and llvm::HexagonHazardRecognizer::getHazardType().

◆ getDotNewPredJumpOp()

int HexagonInstrInfo::getDotNewPredJumpOp	(	const MachineInstr &	MI,
		const MachineBranchProbabilityInfo *	MBPI
	)		const

Definition at line 3770 of file HexagonInstrInfo.cpp.

References assert(), B, llvm::MachineBranchProbabilityInfo::getEdgeProbability(), llvm::MachineOperand::getMBB(), I, llvm::MachineOperand::isMBB(), llvm_unreachable, and MI.

Referenced by getDotNewPredOp().

◆ getDotNewPredOp()

int HexagonInstrInfo::getDotNewPredOp	(	const MachineInstr &	MI,
		const MachineBranchProbabilityInfo *	MBPI
	)		const

Definition at line 3856 of file HexagonInstrInfo.cpp.

References getDotNewPredJumpOp(), and MI.

◆ getDotOldOp()

int HexagonInstrInfo::getDotOldOp ( const MachineInstr & MI ) const

Definition at line 3871 of file HexagonInstrInfo.cpp.

References assert(), llvm::HexagonSubtarget::hasV60Ops(), isNewValueStore(), isPredicated(), isPredicatedNew(), and MI.

◆ getDuplexCandidateGroup()

HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup ( const MachineInstr & MI ) const

Definition at line 3922 of file HexagonInstrInfo.cpp.

References contains(), llvm::HexagonSubtarget::getRegisterInfo(), llvm::HexagonRegisterInfo::getStackRegister(), llvm::HexagonII::HSIG_A, llvm::HexagonII::HSIG_L1, llvm::HexagonII::HSIG_L2, llvm::HexagonII::HSIG_None, llvm::HexagonII::HSIG_S1, llvm::HexagonII::HSIG_S2, isDblRegForSubInst(), isIntRegForSubInst(), and MI.

Referenced by changeDuplexOpcode(), and isDuplexPair().

◆ getDuplexOpcode()

int HexagonInstrInfo::getDuplexOpcode	(	const MachineInstr &	MI,
		bool	ForBigCore = `true`
	)		const

Definition at line 3539 of file HexagonInstrInfo.cpp.

References MI.

Referenced by changeDuplexOpcode().

◆ getEquivalentHWInstr()

short HexagonInstrInfo::getEquivalentHWInstr ( const MachineInstr & MI ) const

Definition at line 4302 of file HexagonInstrInfo.cpp.

References MI.

◆ getIncrementValue()

bool HexagonInstrInfo::getIncrementValue	(	const MachineInstr &	MI,
		int &	Value
	)		const

override

If the instruction is an increment of a constant value, return the amount.

Definition at line 2043 of file HexagonInstrInfo.cpp.

References getBaseAndOffsetPosition(), llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), isPostIncrement(), and MI.

◆ getInlineAsmLength()

unsigned HexagonInstrInfo::getInlineAsmLength	(	const char *	Str,
		const MCAsmInfo &	MAI,
		const TargetSubtargetInfo *	STI = `nullptr`
	)		const

override

Measure the specified inline asm to determine an approximation of its length.

Comments (which run till the next SeparatorString or newline) do not count as an instruction. Any other non-whitespace text is considered an instruction, with multiple instructions separated by SeparatorString or newlines. Variable-length instructions are not handled here; this function may be overloaded in the target code to do that. Hexagon counts the number of ##'s and adjust for that many constant exenders.

Definition at line 1840 of file HexagonInstrInfo.cpp.

References llvm::StringRef::count(), llvm::StringRef::data(), llvm::MCAsmInfo::getCommentString(), llvm::MCAsmInfo::getMaxInstLength(), llvm::MCAsmInfo::getSeparatorString(), llvm::Length, and llvm::StringRef::size().

Referenced by llvm::MSP430InstrInfo::getInstSizeInBytes(), and getSize().

◆ getInstrLatency()

unsigned HexagonInstrInfo::getInstrLatency	(	const InstrItineraryData *	ItinData,
		const MachineInstr &	MI,
		unsigned *	PredCost = `nullptr`
	)		const

override

Compute the instruction latency of a given instruction.

If the instruction has higher cost when predicated, it's returned via PredCost.

Definition at line 1969 of file HexagonInstrInfo.cpp.

References getInstrTimingClassLatency(), and MI.

Referenced by getInstrTimingClassLatency().

◆ getInstrTimingClassLatency()

unsigned HexagonInstrInfo::getInstrTimingClassLatency	(	const InstrItineraryData *	ItinData,
		const MachineInstr &	MI
	)		const

Definition at line 4306 of file HexagonInstrInfo.cpp.

References getInstrLatency(), llvm::InstrItineraryData::getStageLatency(), and MI.

Referenced by getInstrLatency().

◆ getInvertedPredicatedOpcode()

unsigned HexagonInstrInfo::getInvertedPredicatedOpcode ( const int Opc ) const

Definition at line 4379 of file HexagonInstrInfo.cpp.

References isPredicatedTrue(), and llvm_unreachable.

Referenced by getInvertedPredSense(), invertAndChangeJumpTarget(), reverseBranchCondition(), and reversePredSense().

◆ getInvertedPredSense()

bool HexagonInstrInfo::getInvertedPredSense ( SmallVectorImpl< MachineOperand > & Cond ) const

Definition at line 4370 of file HexagonInstrInfo.cpp.

References Cond, and getInvertedPredicatedOpcode().

◆ getMaxValue()

int HexagonInstrInfo::getMaxValue ( const MachineInstr & MI ) const

Definition at line 4390 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::ExtentBitsMask, llvm::HexagonII::ExtentBitsPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F, isSigned(), and MI.

Referenced by isConstExtended().

◆ getMemAccessSize()

unsigned HexagonInstrInfo::getMemAccessSize ( const MachineInstr & MI ) const

Definition at line 4487 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::DoubleWordAccess, F, llvm::HexagonSubtarget::getRegisterInfo(), llvm::HexagonII::HVXVectorAccess, llvm_unreachable, MI, and Size.

Referenced by areMemAccessesTriviallyDisjoint(), and getBaseAndOffset().

◆ getMemOperandsWithOffsetWidth()

bool HexagonInstrInfo::getMemOperandsWithOffsetWidth	(	const MachineInstr &	LdSt,
		SmallVectorImpl< const MachineOperand * > &	BaseOps,
		int64_t &	Offset,
		bool &	OffsetIsScalable,
		LocationSize &	Width,
		const TargetRegisterInfo *	TRI
	)		const

override

Get the base register and byte offset of a load/store instr.

Definition at line 3071 of file HexagonInstrInfo.cpp.

References getBaseAndOffset(), llvm::MachineOperand::isReg(), llvm::Offset, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getMinValue()

int HexagonInstrInfo::getMinValue ( const MachineInstr & MI ) const

Definition at line 4510 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::ExtentBitsMask, llvm::HexagonII::ExtentBitsPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F, isSigned(), and MI.

Referenced by isConstExtended().

◆ getNonDotCurOp()

int HexagonInstrInfo::getNonDotCurOp ( const MachineInstr & MI ) const

Definition at line 3628 of file HexagonInstrInfo.cpp.

References llvm_unreachable, and MI.

◆ getNonExtOpcode()

short HexagonInstrInfo::getNonExtOpcode ( const MachineInstr & MI ) const

Definition at line 4524 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::Absolute, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), and MI.

◆ getNop()

MCInst HexagonInstrInfo::getNop ( ) const

override

Definition at line 4769 of file HexagonInstrInfo.cpp.

References llvm::MCInstBuilder::addImm(), and llvm::MCInstBuilder::addInst().

◆ getOperandLatency()

std::optional< unsigned > HexagonInstrInfo::getOperandLatency	(	const InstrItineraryData *	ItinData,
		const MachineInstr &	DefMI,
		unsigned	DefIdx,
		const MachineInstr &	UseMI,
		unsigned	UseIdx
	)		const

override

getOperandLatency - Compute and return the use operand latency of a given pair of def and use.

In most cases, the static scheduling itinerary was enough to determine the operand latency. But it may not be possible for instructions with variable number of defs / uses.

This is a raw interface to the itinerary that may be directly overriden by a target. Use computeOperandLatency to get the best estimate of latency.

Definition at line 4326 of file HexagonInstrInfo.cpp.

References DefMI, llvm::TargetInstrInfo::getOperandLatency(), llvm::MachineOperand::getReg(), llvm::HexagonSubtarget::getRegisterInfo(), Idx, llvm::MachineOperand::isImplicit(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::Latency, and UseMI.

Referenced by llvm::HexagonSubtarget::adjustSchedDependency().

◆ getPredReg()

bool HexagonInstrInfo::getPredReg	(	ArrayRef< MachineOperand >	Cond,
		Register &	PredReg,
		unsigned &	PredRegPos,
		unsigned &	PredRegFlags
	)		const

Definition at line 4548 of file HexagonInstrInfo.cpp.

References assert(), Cond, llvm::dbgs(), llvm::RegState::Implicit, isNewValueJump(), isUndef(), LLVM_DEBUG, and llvm::RegState::Undef.

Referenced by PredicateInstruction().

◆ getPseudoInstrPair()

short HexagonInstrInfo::getPseudoInstrPair ( const MachineInstr & MI ) const

Definition at line 4568 of file HexagonInstrInfo.cpp.

References MI.

◆ getRegForm()

short HexagonInstrInfo::getRegForm ( const MachineInstr & MI ) const

Definition at line 4572 of file HexagonInstrInfo.cpp.

References MI.

◆ getSerializableBitmaskMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const

override

Return an array that contains the bitmask target flag values and their names.

MIR Serialization is able to serialize only the target flags that are defined by this method.

Definition at line 2091 of file HexagonInstrInfo.cpp.

Referenced by llvm::MachineOperand::printTargetFlags().

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const

override

Return an array that contains the direct target flag values and their names.

MIR Serialization is able to serialize only the target flags that are defined by this method.

Definition at line 2072 of file HexagonInstrInfo.cpp.

Referenced by getTargetFlagName().

◆ getSize()

unsigned HexagonInstrInfo::getSize ( const MachineInstr & MI ) const

Definition at line 4580 of file HexagonInstrInfo.cpp.

References assert(), BranchRelaxAsmLarge, getInlineAsmLength(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getTarget(), HEXAGON_INSTR_SIZE, isConstExtended(), isExtended(), isReg(), MBB, MI, and Size.

◆ getType()

uint64_t HexagonInstrInfo::getType ( const MachineInstr & MI ) const

Definition at line 4614 of file HexagonInstrInfo.cpp.

References F, MI, llvm::HexagonII::TypeMask, and llvm::HexagonII::TypePos.

Referenced by cannotCoexistAsymm(), llvm::InstCombinerImpl::foldSelectOpOp(), isCompoundBranchInstr(), isHVXVec(), and isLateSourceInstr().

◆ getUnits()

InstrStage::FuncUnits HexagonInstrInfo::getUnits ( const MachineInstr & MI ) const

Definition at line 4619 of file HexagonInstrInfo.cpp.

References llvm::HexagonSubtarget::getInstrItineraryData(), llvm::InstrStage::getUnits(), II, and MI.

Referenced by isPureSlot0().

◆ hasEHLabel()

bool HexagonInstrInfo::hasEHLabel ( const MachineBasicBlock * B ) const

Definition at line 3114 of file HexagonInstrInfo.cpp.

References B, and I.

◆ hasLoadFromStackSlot()

bool HexagonInstrInfo::hasLoadFromStackSlot	(	const MachineInstr &	MI,
		SmallVectorImpl< const MachineMemOperand * > &	Accesses
	)		const

override

Check if the instruction or the bundle of instructions has load from stack slots.

This function checks if the instruction or bundle of instructions has load from stack slot and returns frameindex and machine memory operand of that instruction if true.

Return the frameindex and machine memory operand if true.

Definition at line 385 of file HexagonInstrInfo.cpp.

References llvm::TargetInstrInfo::hasLoadFromStackSlot(), llvm::MachineBasicBlock::instr_end(), MBB, and MI.

Referenced by llvm::MachineInstr::getFoldedRestoreSize().

◆ hasNonExtEquivalent()

bool HexagonInstrInfo::hasNonExtEquivalent ( const MachineInstr & MI ) const

Definition at line 3123 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::Absolute, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), and MI.

◆ hasPseudoInstrPair()

bool HexagonInstrInfo::hasPseudoInstrPair ( const MachineInstr & MI ) const

Definition at line 3158 of file HexagonInstrInfo.cpp.

References MI.

◆ hasStoreToStackSlot()

bool HexagonInstrInfo::hasStoreToStackSlot	(	const MachineInstr &	MI,
		SmallVectorImpl< const MachineMemOperand * > &	Accesses
	)		const

override

Check if the instruction or the bundle of instructions has store to stack slots.

This function checks if the instruction or bundle of instructions has store to stack slot and returns frameindex and machine memory operand of that instruction if true.

Return the frameindex and machine memory operand if true.

Definition at line 403 of file HexagonInstrInfo.cpp.

References llvm::TargetInstrInfo::hasStoreToStackSlot(), llvm::MachineBasicBlock::instr_end(), MBB, and MI.

Referenced by llvm::MachineInstr::getFoldedSpillSize().

◆ hasUncondBranch()

bool HexagonInstrInfo::hasUncondBranch ( const MachineBasicBlock * B ) const

Definition at line 3163 of file HexagonInstrInfo.cpp.

References B, and I.

◆ immediateExtend()

void HexagonInstrInfo::immediateExtend ( MachineInstr & MI ) const

immediateExtend - Changes the instruction in place to one using an immediate extender.

Definition at line 4641 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::addTargetFlag(), assert(), getCExtOpNum(), llvm::HexagonII::HMOTF_ConstExtended, isConstExtended(), isExtendable(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isMBB(), and MI.

◆ insertBranch()

unsigned HexagonInstrInfo::insertBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *	TBB,
		MachineBasicBlock *	FBB,
		ArrayRef< MachineOperand >	Cond,
		const DebugLoc &	DL,
		int *	BytesAdded = `nullptr`
	)		const

override

Insert branch code into the end of the specified MachineBasicBlock.

The operands to this method are the same as those returned by analyzeBranch. This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions inserted.

It is also invoked by tail merging to add unconditional branches in cases where analyzeBranch doesn't apply because there was no original branch to analyze. At least this much must be implemented, else tail merging needs to be disabled.

Definition at line 626 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), analyzeBranch(), assert(), llvm::BuildMI(), Cond, llvm::dbgs(), DL, llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::get(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getReg(), getReg(), llvm::getUndefRegState(), insertBranch(), isEndLoopN(), isImm(), isNewValueJump(), isPredicated(), isReg(), llvm::MachineOperand::isUndef(), isUndef(), LLVM_DEBUG, llvm_unreachable, MBB, llvm::printMBBReference(), removeBranch(), reverseBranchCondition(), TBB, and validateBranchCond().

Referenced by createDedicatedExit(), FixTail(), insertBranch(), InsertUncondBranch(), llvm::PeelSingleBlockLoop(), llvm::MachineBasicBlock::SplitCriticalEdge(), splitEdge(), and llvm::MachineBasicBlock::updateTerminator().

◆ insertNoop()

void HexagonInstrInfo::insertNoop	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI
	)		const

override

Insert a noop into the instruction stream at the specified point.

Definition at line 1648 of file HexagonInstrInfo.cpp.

References llvm::BuildMI(), DL, llvm::get(), MBB, and MI.

◆ invertAndChangeJumpTarget()

bool HexagonInstrInfo::invertAndChangeJumpTarget	(	MachineInstr &	MI,
		MachineBasicBlock *	NewTarget
	)		const

Definition at line 4654 of file HexagonInstrInfo.cpp.

References assert(), llvm::dbgs(), llvm::Pass::dump(), EnableBranchPrediction, llvm::get(), getInvertedPredicatedOpcode(), isPredicatedNew(), LLVM_DEBUG, MI, llvm::printMBBReference(), and reversePrediction().

◆ isAbsoluteSet()

bool HexagonInstrInfo::isAbsoluteSet ( const MachineInstr & MI ) const

Definition at line 2117 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::AbsoluteSet, getAddrMode(), and MI.

◆ isAccumulator()

bool HexagonInstrInfo::isAccumulator ( const MachineInstr & MI ) const

Definition at line 2121 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::AccumulatorMask, llvm::HexagonII::AccumulatorPos, F, and MI.

Referenced by isVecAcc().

◆ isAddrModeWithOffset()

bool HexagonInstrInfo::isAddrModeWithOffset ( const MachineInstr & MI ) const

Definition at line 4404 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::AddrModeMask, llvm::HexagonII::AddrModePos, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, llvm::HexagonII::BaseRegOffset, F, and MI.

Referenced by getBaseAndOffsetPosition().

◆ isAsCheapAsAMove()

bool HexagonInstrInfo::isAsCheapAsAMove ( const MachineInstr & MI ) const

override

Definition at line 153 of file HexagonInstrInfo.cpp.

References MI.

◆ isBaseImmOffset()

bool HexagonInstrInfo::isBaseImmOffset ( const MachineInstr & MI ) const

Definition at line 2126 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::BaseImmOffset, getAddrMode(), and MI.

◆ isComplex()

bool HexagonInstrInfo::isComplex ( const MachineInstr & MI ) const

Definition at line 2130 of file HexagonInstrInfo.cpp.

References isMemOp(), isTC1(), isTC2Early(), and MI.

◆ isCompoundBranchInstr()

bool HexagonInstrInfo::isCompoundBranchInstr ( const MachineInstr & MI ) const

Definition at line 2139 of file HexagonInstrInfo.cpp.

References getType(), MI, and llvm::HexagonII::TypeCJ.

◆ isConstExtended()

bool HexagonInstrInfo::isConstExtended ( const MachineInstr & MI ) const

◆ isDeallocRet()

bool HexagonInstrInfo::isDeallocRet ( const MachineInstr & MI ) const

Definition at line 2194 of file HexagonInstrInfo.cpp.

References MI.

◆ isDependent()

bool HexagonInstrInfo::isDependent	(	const MachineInstr &	ProdMI,
		const MachineInstr &	ConsMI
	)		const

Definition at line 2209 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::HexagonSubtarget::getRegisterInfo(), llvm::is_contained(), and parseOperands().

Referenced by producesStall().

◆ isDotCurInst()

bool HexagonInstrInfo::isDotCurInst ( const MachineInstr & MI ) const

Definition at line 2240 of file HexagonInstrInfo.cpp.

References MI.

◆ isDotNewInst()

bool HexagonInstrInfo::isDotNewInst ( const MachineInstr & MI ) const

Definition at line 2251 of file HexagonInstrInfo.cpp.

References isNewValueInst(), isPredicated(), isPredicatedNew(), and MI.

◆ isDuplexPair()

bool HexagonInstrInfo::isDuplexPair	(	const MachineInstr &	MIa,
		const MachineInstr &	MIb
	)		const

Symmetrical. See if these two instructions are fit for duplex pair.

Definition at line 2259 of file HexagonInstrInfo.cpp.

References getDuplexCandidateGroup(), and isDuplexPairMatch().

◆ isEndLoopN()

bool HexagonInstrInfo::isEndLoopN ( unsigned Opcode ) const

Definition at line 2266 of file HexagonInstrInfo.cpp.

Referenced by analyzeBranch(), analyzeLoopForPipelining(), insertBranch(), PredicateInstruction(), and reverseBranchCondition().

◆ isExpr()

bool HexagonInstrInfo::isExpr ( unsigned OpType ) const

Definition at line 2271 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::MO_BlockAddress, llvm::MachineOperand::MO_ConstantPoolIndex, llvm::MachineOperand::MO_ExternalSymbol, llvm::MachineOperand::MO_GlobalAddress, llvm::MachineOperand::MO_JumpTableIndex, and llvm::MachineOperand::MO_MachineBasicBlock.

◆ isExtendable()

bool HexagonInstrInfo::isExtendable ( const MachineInstr & MI ) const

Definition at line 2285 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::ExtendableMask, llvm::HexagonII::ExtendablePos, F, MI, and llvm::MCInstrDesc::TSFlags.

Referenced by immediateExtend(), and isConstExtended().

◆ isExtended()

bool HexagonInstrInfo::isExtended ( const MachineInstr & MI ) const

Definition at line 2307 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::ExtendedMask, llvm::HexagonII::ExtendedPos, F, llvm::HexagonII::HMOTF_ConstExtended, and MI.

Referenced by getSize(), and isConstExtended().

◆ isFloat()

bool HexagonInstrInfo::isFloat ( const MachineInstr & MI ) const

Definition at line 2320 of file HexagonInstrInfo.cpp.

References F, llvm::HexagonII::FPMask, llvm::HexagonII::FPPos, llvm::get(), and MI.

Referenced by shouldSink().

◆ isHVXMemWithAIndirect()

bool HexagonInstrInfo::isHVXMemWithAIndirect	(	const MachineInstr &	I,
		const MachineInstr &	J
	)		const

Definition at line 2327 of file HexagonInstrInfo.cpp.

References I, isHVXVec(), llvm::MachineInstr::isIndirectBranch(), isIndirectCall(), and isIndirectL4Return().

Referenced by cannotCoexistAsymm().

◆ isHVXVec()

bool HexagonInstrInfo::isHVXVec ( const MachineInstr & MI ) const

Definition at line 2704 of file HexagonInstrInfo.cpp.

References getType(), MI, llvm::HexagonII::TypeCVI_FIRST, and llvm::HexagonII::TypeCVI_LAST.

Referenced by addLatencyToSchedule(), llvm::HexagonHazardRecognizer::EmitInstruction(), isHVXMemWithAIndirect(), isVecAcc(), and producesStall().

◆ isIndirectCall()

bool HexagonInstrInfo::isIndirectCall ( const MachineInstr & MI ) const

Definition at line 2336 of file HexagonInstrInfo.cpp.

References MI.

Referenced by isHVXMemWithAIndirect().

◆ isIndirectL4Return()

bool HexagonInstrInfo::isIndirectL4Return ( const MachineInstr & MI ) const

Definition at line 2347 of file HexagonInstrInfo.cpp.

References MI.

Referenced by isHVXMemWithAIndirect().

◆ isJumpR()

bool HexagonInstrInfo::isJumpR ( const MachineInstr & MI ) const

Definition at line 2361 of file HexagonInstrInfo.cpp.

References MI.

◆ isJumpWithinBranchRange()

bool HexagonInstrInfo::isJumpWithinBranchRange	(	const MachineInstr &	MI,
		unsigned	offset
	)		const

Definition at line 2379 of file HexagonInstrInfo.cpp.

References isNewValueJump(), and MI.

◆ isLateSourceInstr()

bool HexagonInstrInfo::isLateSourceInstr ( const MachineInstr & MI ) const

Definition at line 2421 of file HexagonInstrInfo.cpp.

References getType(), MI, and llvm::HexagonII::TypeCVI_VX_LATE.

Referenced by isVecUsableNextPacket().

◆ isLoadFromStackSlot()

Register HexagonInstrInfo::isLoadFromStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

override

TargetInstrInfo overrides.

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.

If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Definition at line 287 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and MI.

Referenced by MatchingStackOffset(), and llvm::SIFrameLowering::processFunctionBeforeFrameFinalized().

◆ isLoopN()

bool HexagonInstrInfo::isLoopN ( const MachineInstr & MI ) const

Definition at line 2427 of file HexagonInstrInfo.cpp.

References MI.

◆ isMemOp()

bool HexagonInstrInfo::isMemOp ( const MachineInstr & MI ) const

Definition at line 2439 of file HexagonInstrInfo.cpp.

References MI.

Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), getBaseAndOffsetPosition(), and isComplex().

◆ isNewValue() [1/2]

bool HexagonInstrInfo::isNewValue ( const MachineInstr & MI ) const

Definition at line 2471 of file HexagonInstrInfo.cpp.

References F, MI, llvm::HexagonII::NewValueMask, and llvm::HexagonII::NewValuePos.

Referenced by isNewValueJump(), and isPredictedTaken().

◆ isNewValue() [2/2]

bool HexagonInstrInfo::isNewValue ( unsigned Opcode ) const

Definition at line 2476 of file HexagonInstrInfo.cpp.

References F, llvm::get(), llvm::HexagonII::NewValueMask, and llvm::HexagonII::NewValuePos.

◆ isNewValueInst()

bool HexagonInstrInfo::isNewValueInst ( const MachineInstr & MI ) const

Definition at line 2481 of file HexagonInstrInfo.cpp.

References isNewValueJump(), isNewValueStore(), and MI.

Referenced by isDotNewInst().

◆ isNewValueJump() [1/2]

bool HexagonInstrInfo::isNewValueJump ( const MachineInstr & MI ) const

Definition at line 2485 of file HexagonInstrInfo.cpp.

References isNewValue(), and MI.

Referenced by analyzeBranch(), getPredReg(), insertBranch(), isJumpWithinBranchRange(), isNewValueInst(), and PredicateInstruction().

◆ isNewValueJump() [2/2]

bool HexagonInstrInfo::isNewValueJump ( unsigned Opcode ) const

Definition at line 2489 of file HexagonInstrInfo.cpp.

References llvm::get(), isNewValue(), and isPredicated().

◆ isNewValueStore() [1/2]

bool HexagonInstrInfo::isNewValueStore ( const MachineInstr & MI ) const

Definition at line 2493 of file HexagonInstrInfo.cpp.

References F, MI, llvm::HexagonII::NVStoreMask, and llvm::HexagonII::NVStorePos.

Referenced by cannotCoexistAsymm(), getDotOldOp(), and isNewValueInst().

◆ isNewValueStore() [2/2]

bool HexagonInstrInfo::isNewValueStore ( unsigned Opcode ) const

Definition at line 2498 of file HexagonInstrInfo.cpp.

References F, llvm::get(), llvm::HexagonII::NVStoreMask, and llvm::HexagonII::NVStorePos.

◆ isOperandExtended()

bool HexagonInstrInfo::isOperandExtended	(	const MachineInstr &	MI,
		unsigned	OperandNum
	)		const

Definition at line 2504 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::ExtendableOpMask, llvm::HexagonII::ExtendableOpPos, F, and MI.

◆ isPostIncrement()

bool HexagonInstrInfo::isPostIncrement ( const MachineInstr & MI ) const

override

Return true for post-incremented instructions.

Definition at line 1654 of file HexagonInstrInfo.cpp.

References getAddrMode(), MI, and llvm::HexagonII::PostInc.

Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), getBaseAndOffsetPosition(), getIncrementValue(), and getPostIncrementOperand().

◆ isPredicable()

bool HexagonInstrInfo::isPredicable ( const MachineInstr & MI ) const

override

Return true if the specified instruction can be predicated.

By default, this returns true for every instruction with a PredicateOperand.

Definition at line 1756 of file HexagonInstrInfo.cpp.

References llvm::HexagonSubtarget::hasV62Ops(), isTailCall(), MI, and llvm::HexagonSubtarget::usePredicatedCalls().

Referenced by PredicateInstruction().

◆ isPredicated() [1/2]

bool HexagonInstrInfo::isPredicated ( const MachineInstr & MI ) const

override

Returns true if the instruction is already predicated.

Definition at line 1666 of file HexagonInstrInfo.cpp.

References F, MI, llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.

Referenced by findHoistingInsertPosAndDeps(), getBaseAndOffsetPosition(), getDotOldOp(), llvm::MachineBasicBlock::getFallThrough(), getPredicatedRegister(), getPredicateSense(), insertBranch(), isDotNewInst(), isNewValueJump(), isPredicatedNew(), and predOpcodeHasNot().

◆ isPredicated() [2/2]

bool HexagonInstrInfo::isPredicated ( unsigned Opcode ) const

Definition at line 2537 of file HexagonInstrInfo.cpp.

References F, llvm::get(), llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.

◆ isPredicatedNew() [1/2]

bool HexagonInstrInfo::isPredicatedNew ( const MachineInstr & MI ) const

Definition at line 2511 of file HexagonInstrInfo.cpp.

References assert(), F, isPredicated(), MI, llvm::HexagonII::PredicatedNewMask, and llvm::HexagonII::PredicatedNewPos.

Referenced by getDotOldOp(), invertAndChangeJumpTarget(), isDotNewInst(), and isPredictedTaken().

◆ isPredicatedNew() [2/2]

bool HexagonInstrInfo::isPredicatedNew ( unsigned Opcode ) const

Definition at line 2517 of file HexagonInstrInfo.cpp.

References assert(), F, llvm::get(), isPredicated(), llvm::HexagonII::PredicatedNewMask, and llvm::HexagonII::PredicatedNewPos.

◆ isPredicatedTrue() [1/2]

bool HexagonInstrInfo::isPredicatedTrue ( const MachineInstr & MI ) const

Definition at line 2523 of file HexagonInstrInfo.cpp.

References F, MI, llvm::HexagonII::PredicatedFalseMask, and llvm::HexagonII::PredicatedFalsePos.

Referenced by getInvertedPredicatedOpcode(), getPredicateSense(), and predOpcodeHasNot().

◆ isPredicatedTrue() [2/2]

bool HexagonInstrInfo::isPredicatedTrue ( unsigned Opcode ) const

Definition at line 2529 of file HexagonInstrInfo.cpp.

References assert(), F, llvm::get(), llvm::HexagonII::PredicatedFalseMask, llvm::HexagonII::PredicatedFalsePos, llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.

◆ isPredicateLate()

bool HexagonInstrInfo::isPredicateLate ( unsigned Opcode ) const

Definition at line 2542 of file HexagonInstrInfo.cpp.

References F, llvm::get(), llvm::HexagonII::PredicateLateMask, and llvm::HexagonII::PredicateLatePos.

◆ isPredictedTaken()

bool HexagonInstrInfo::isPredictedTaken ( unsigned Opcode ) const

Definition at line 2547 of file HexagonInstrInfo.cpp.

References assert(), F, llvm::get(), isBranch(), isNewValue(), isPredicatedNew(), llvm::HexagonII::TakenMask, and llvm::HexagonII::TakenPos.

Referenced by reversePrediction().

◆ isProfitableToDupForIfCvt()

bool HexagonInstrInfo::isProfitableToDupForIfCvt	(	MachineBasicBlock &	MBB,
		unsigned	NumCycles,
		BranchProbability	Probability
	)		const

override

Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion.

The probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.

Definition at line 830 of file HexagonInstrInfo.cpp.

◆ isProfitableToIfCvt() [1/2]

bool HexagonInstrInfo::isProfitableToIfCvt	(	MachineBasicBlock &	MBB,
		unsigned	NumCycles,
		unsigned	ExtraPredCycles,
		BranchProbability	Probability
	)		const

override

Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.

Definition at line 817 of file HexagonInstrInfo.cpp.

References MBB, and nonDbgBBSize().

◆ isProfitableToIfCvt() [2/2]

bool HexagonInstrInfo::isProfitableToIfCvt	(	MachineBasicBlock &	TMBB,
		unsigned	NumTCycles,
		unsigned	ExtraTCycles,
		MachineBasicBlock &	FMBB,
		unsigned	NumFCycles,
		unsigned	ExtraFCycles,
		BranchProbability	Probability
	)		const

override

Second variant of isProfitableToIfCvt.

This one checks for the case where two basic blocks from true and false path of a if-then-else (diamond) are predicated on mutally exclusive predicates, where the probability of the true path being taken is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.

Definition at line 823 of file HexagonInstrInfo.cpp.

References nonDbgBBSize().

◆ isPureSlot0()

bool HexagonInstrInfo::isPureSlot0 ( const MachineInstr & MI ) const

Definition at line 4432 of file HexagonInstrInfo.cpp.

References getUnits(), llvm::HexagonFUnits::isSlot0Only(), and MI.

Referenced by cannotCoexistAsymm().

◆ isRestrictNoSlot1Store()

bool HexagonInstrInfo::isRestrictNoSlot1Store ( const MachineInstr & MI ) const

Definition at line 4444 of file HexagonInstrInfo.cpp.

References F, MI, llvm::HexagonII::RestrictNoSlot1StoreMask, and llvm::HexagonII::RestrictNoSlot1StorePos.

Referenced by cannotCoexistAsymm().

◆ isSaveCalleeSavedRegsCall()

bool HexagonInstrInfo::isSaveCalleeSavedRegsCall ( const MachineInstr & MI ) const

Definition at line 2554 of file HexagonInstrInfo.cpp.

References MI.

◆ isSchedulingBoundary()

bool HexagonInstrInfo::isSchedulingBoundary	(	const MachineInstr &	MI,
		const MachineBasicBlock *	MBB,
		const MachineFunction &	MF
	)		const

override

Test if the given instruction should be considered a scheduling boundary.

This primarily includes labels and terminators.

Definition at line 1792 of file HexagonInstrInfo.cpp.

References doesNotReturn(), I, MBB, MI, ScheduleInlineAsm, and llvm::MachineBasicBlock::successors().

Referenced by hoistAndMergeSGPRInits(), and isSchedBoundary().

◆ isSignExtendingLoad()

bool HexagonInstrInfo::isSignExtendingLoad ( const MachineInstr & MI ) const

Definition at line 2561 of file HexagonInstrInfo.cpp.

References MI.

◆ isSolo()

bool HexagonInstrInfo::isSolo ( const MachineInstr & MI ) const

Definition at line 2639 of file HexagonInstrInfo.cpp.

References F, MI, llvm::HexagonII::SoloMask, and llvm::HexagonII::SoloPos.

◆ isSpillPredRegOp()

bool HexagonInstrInfo::isSpillPredRegOp ( const MachineInstr & MI ) const

Definition at line 2644 of file HexagonInstrInfo.cpp.

References MI.

◆ isStoreToStackSlot()

Register HexagonInstrInfo::isStoreToStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

override

If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.

If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Definition at line 335 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and MI.

Referenced by llvm::SIFrameLowering::processFunctionBeforeFrameFinalized().

◆ isTailCall()

bool HexagonInstrInfo::isTailCall ( const MachineInstr & MI ) const

override

Definition at line 2654 of file HexagonInstrInfo.cpp.

References MI.

Referenced by llvm::DwarfDebug::beginInstruction(), llvm::findSplitPointForStackProtector(), getBBAddrMapMetadata(), isLibCallInTailPosition(), and isPredicable().

◆ isTC1()

bool HexagonInstrInfo::isTC1 ( const MachineInstr & MI ) const

Definition at line 2665 of file HexagonInstrInfo.cpp.

References llvm::is_TC1(), and MI.

Referenced by isComplex().

◆ isTC2()

bool HexagonInstrInfo::isTC2 ( const MachineInstr & MI ) const

Definition at line 2670 of file HexagonInstrInfo.cpp.

References llvm::is_TC2(), and MI.

◆ isTC2Early()

bool HexagonInstrInfo::isTC2Early ( const MachineInstr & MI ) const

Definition at line 2675 of file HexagonInstrInfo.cpp.

References llvm::is_TC2early(), and MI.

Referenced by isComplex().

◆ isTC4x()

bool HexagonInstrInfo::isTC4x ( const MachineInstr & MI ) const

Definition at line 2680 of file HexagonInstrInfo.cpp.

References llvm::is_TC4x(), and MI.

◆ isToBeScheduledASAP()

bool HexagonInstrInfo::isToBeScheduledASAP	(	const MachineInstr &	MI1,
		const MachineInstr &	MI2
	)		const

Definition at line 2686 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isReg(), mayBeCurLoad(), mayBeNewStore(), and N.

Referenced by llvm::HexagonSubtarget::adjustSchedDependency().

◆ isValidAutoIncImm()

bool HexagonInstrInfo::isValidAutoIncImm	(	const EVT	VT,
		const int	Offset
	)		const

Definition at line 2710 of file HexagonInstrInfo.cpp.

References llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm_unreachable, llvm::Offset, llvm::MVT::SimpleTy, and Size.

Referenced by llvm::HexagonTargetLowering::getPostIndexedAddressParts(), and llvm::HexagonDAGToDAGISel::SelectIndexedStore().

◆ isValidOffset()

bool HexagonInstrInfo::isValidOffset	(	unsigned	Opcode,
		int	Offset,
		const TargetRegisterInfo *	TRI,
		bool	Extend = `true`
	)		const

◆ isVecAcc()

bool HexagonInstrInfo::isVecAcc ( const MachineInstr & MI ) const

Definition at line 2957 of file HexagonInstrInfo.cpp.

References isAccumulator(), isHVXVec(), and MI.

Referenced by isVecUsableNextPacket().

◆ isVecALU()

bool HexagonInstrInfo::isVecALU ( const MachineInstr & MI ) const

Definition at line 2961 of file HexagonInstrInfo.cpp.

References F, llvm::get(), MI, llvm::HexagonII::TypeCVI_VA, llvm::HexagonII::TypeCVI_VA_DV, llvm::HexagonII::TypeMask, and llvm::HexagonII::TypePos.

Referenced by isVecUsableNextPacket().

◆ isVecUsableNextPacket()

bool HexagonInstrInfo::isVecUsableNextPacket	(	const MachineInstr &	ProdMI,
		const MachineInstr &	ConsMI
	)		const

Definition at line 2969 of file HexagonInstrInfo.cpp.

References EnableACCForwarding, EnableALUForwarding, isLateSourceInstr(), isVecAcc(), isVecALU(), and mayBeNewStore().

Referenced by addLatencyToSchedule(), and producesStall().

◆ isZeroExtendingLoad()

bool HexagonInstrInfo::isZeroExtendingLoad ( const MachineInstr & MI ) const

Definition at line 2983 of file HexagonInstrInfo.cpp.

References MI.

◆ loadRegFromStackSlot()

void HexagonInstrInfo::loadRegFromStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		Register	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI,
		Register	VReg
	)		const

override

Load the specified register of the given register class from the specified stack frame index.

The load instruction is to be added to the given machine basic block before the specified machine instruction.

Definition at line 1005 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), I, llvm_unreachable, MBB, and llvm::MachineMemOperand::MOLoad.

Referenced by emitBuildPairF64Pseudo(), llvm::MipsSEFrameLowering::emitEpilogue(), insertCSRRestores(), llvm::SystemZELFFrameLowering::restoreCalleeSavedRegisters(), llvm::SystemZXPLINKFrameLowering::restoreCalleeSavedRegisters(), llvm::CSKYFrameLowering::restoreCalleeSavedRegisters(), llvm::PPCFrameLowering::restoreCalleeSavedRegisters(), llvm::RISCVFrameLowering::restoreCalleeSavedRegisters(), and llvm::XCoreFrameLowering::restoreCalleeSavedRegisters().

◆ mayBeCurLoad()

bool HexagonInstrInfo::mayBeCurLoad ( const MachineInstr & MI ) const

Definition at line 3175 of file HexagonInstrInfo.cpp.

References F, llvm::HexagonSubtarget::hasV60Ops(), llvm::HexagonII::mayCVLoadMask, llvm::HexagonII::mayCVLoadPos, and MI.

Referenced by llvm::HexagonHazardRecognizer::EmitInstruction(), and isToBeScheduledASAP().

◆ mayBeNewStore()

bool HexagonInstrInfo::mayBeNewStore ( const MachineInstr & MI ) const

Definition at line 3182 of file HexagonInstrInfo.cpp.

References F, llvm::HexagonII::mayNVStoreMask, llvm::HexagonII::mayNVStorePos, MI, and llvm::HexagonSubtarget::useNewValueStores().

Referenced by canExecuteInBundle(), llvm::HexagonHazardRecognizer::EmitInstruction(), isToBeScheduledASAP(), and isVecUsableNextPacket().

◆ nonDbgBBSize()

unsigned HexagonInstrInfo::nonDbgBBSize ( const MachineBasicBlock * BB ) const

getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Class information, if available.

Definition at line 4627 of file HexagonInstrInfo.cpp.

References llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), and nonDbgMICount().

Referenced by isProfitableToIfCvt().

◆ nonDbgBundleSize()

unsigned HexagonInstrInfo::nonDbgBundleSize ( MachineBasicBlock::const_iterator BundleHead ) const

Definition at line 4631 of file HexagonInstrInfo.cpp.

References assert(), llvm::getBundleEnd(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getInstrIterator(), and nonDbgMICount().

◆ predCanBeUsedAsDotNew()

bool HexagonInstrInfo::predCanBeUsedAsDotNew	(	const MachineInstr &	MI,
		Register	PredReg
	)		const

Definition at line 3228 of file HexagonInstrInfo.cpp.

References MI.

◆ PredicateInstruction()

bool HexagonInstrInfo::PredicateInstruction	(	MachineInstr &	MI,
		ArrayRef< MachineOperand >	Cond
	)		const

override

Convert the instruction into a predicated instruction.

It returns true if the operation was successful.

Definition at line 1671 of file HexagonInstrInfo.cpp.

References assert(), B, llvm::BuildMI(), Cond, llvm::dbgs(), DL, llvm::Pass::dump(), llvm::get(), getCondOpcode(), getPredReg(), isEndLoopN(), isNewValueJump(), isPredicable(), LLVM_DEBUG, MI, MRI, and predOpcodeHasNot().

◆ PredOpcodeHasJMP_c()

bool HexagonInstrInfo::PredOpcodeHasJMP_c ( unsigned Opcode ) const

Definition at line 3263 of file HexagonInstrInfo.cpp.

Referenced by analyzeBranch().

◆ predOpcodeHasNot()

bool HexagonInstrInfo::predOpcodeHasNot ( ArrayRef< MachineOperand > Cond ) const

Definition at line 3274 of file HexagonInstrInfo.cpp.

References Cond, isPredicated(), and isPredicatedTrue().

Referenced by PredicateInstruction().

◆ producesStall() [1/2]

bool HexagonInstrInfo::producesStall	(	const MachineInstr &	MI,
		MachineBasicBlock::const_instr_iterator	MII
	)		const

Definition at line 3208 of file HexagonInstrInfo.cpp.

References isHVXVec(), MI, and producesStall().

◆ producesStall() [2/2]

bool HexagonInstrInfo::producesStall	(	const MachineInstr &	ProdMI,
		const MachineInstr &	ConsMI
	)		const

Definition at line 3190 of file HexagonInstrInfo.cpp.

References isDependent(), isHVXVec(), and isVecUsableNextPacket().

Referenced by producesStall().

◆ removeBranch()

unsigned HexagonInstrInfo::removeBranch	(	MachineBasicBlock &	MBB,
		int *	BytesRemoved = `nullptr`
	)		const

override

Remove the branching code at the end of the specific MBB.

This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions that were removed.

Definition at line 603 of file HexagonInstrInfo.cpp.

References assert(), llvm::MachineBasicBlock::back(), llvm::MachineBasicBlock::begin(), llvm::dbgs(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), I, LLVM_DEBUG, llvm_unreachable, MBB, and llvm::printMBBReference().

Referenced by createDedicatedExit(), FixTail(), insertBranch(), llvm::PeelSingleBlockLoop(), and llvm::MachineBasicBlock::updateTerminator().

◆ reverseBranchCondition()

bool HexagonInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > & Cond ) const

override

Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.

Definition at line 1633 of file HexagonInstrInfo.cpp.

References assert(), Cond, llvm::get(), getInvertedPredicatedOpcode(), isBranch(), isEndLoopN(), and isImm().

Referenced by FixTail(), insertBranch(), and llvm::MachineBasicBlock::updateTerminator().

◆ reversePrediction()

unsigned HexagonInstrInfo::reversePrediction ( unsigned Opcode ) const

Definition at line 4704 of file HexagonInstrInfo.cpp.

References assert(), and isPredictedTaken().

Referenced by invertAndChangeJumpTarget().

◆ reversePredSense()

bool HexagonInstrInfo::reversePredSense ( MachineInstr & MI ) const

Definition at line 4697 of file HexagonInstrInfo.cpp.

References llvm::dbgs(), llvm::Pass::dump(), llvm::get(), getInvertedPredicatedOpcode(), LLVM_DEBUG, and MI.

◆ setBundleNoShuf()

void HexagonInstrInfo::setBundleNoShuf ( MachineBasicBlock::instr_iterator MIB ) const

Definition at line 4720 of file HexagonInstrInfo.cpp.

References assert(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::setImm().

◆ shouldSink()

bool HexagonInstrInfo::shouldSink ( const MachineInstr & MI ) const

override

Definition at line 184 of file HexagonInstrInfo.cpp.

References isFloat(), and MI.

◆ storeRegToStackSlot()

void HexagonInstrInfo::storeRegToStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		Register	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI,
		Register	VReg
	)		const

override

Store the specified register of the given register class to the specified stack frame index.

The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.

Definition at line 957 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), I, llvm_unreachable, MBB, and llvm::MachineMemOperand::MOStore.

◆ SubsumesPredicate()

bool HexagonInstrInfo::SubsumesPredicate	(	ArrayRef< MachineOperand >	Pred1,
		ArrayRef< MachineOperand >	Pred2
	)		const

override

Returns true if the first specified predicate subsumes the second, e.g.

GE subsumes GT.

Definition at line 1723 of file HexagonInstrInfo.cpp.

◆ translateInstrsForDup() [1/2]

void HexagonInstrInfo::translateInstrsForDup	(	MachineBasicBlock::instr_iterator	MII,
		bool	ToBigInstrs
	)		const

Definition at line 4478 of file HexagonInstrInfo.cpp.

References changeDuplexOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineBasicBlock::instr_end(), and MBB.

◆ translateInstrsForDup() [2/2]

void HexagonInstrInfo::translateInstrsForDup	(	MachineFunction &	MF,
		bool	ToBigInstrs = `true`
	)		const

Definition at line 4468 of file HexagonInstrInfo.cpp.

References changeDuplexOpcode(), and End.

◆ validateBranchCond()

bool HexagonInstrInfo::validateBranchCond ( const ArrayRef< MachineOperand > & Cond ) const

Definition at line 4715 of file HexagonInstrInfo.cpp.

References Cond.

Referenced by insertBranch().

The documentation for this class was generated from the following files:

lib/Target/Hexagon/HexagonInstrInfo.h
lib/Target/Hexagon/HexagonInstrInfo.cpp

Public Member Functions

Detailed Description

Constructor & Destructor Documentation

◆ HexagonInstrInfo()

Member Function Documentation

◆ addLatencyToSchedule()

◆ analyzeBranch()

◆ analyzeCompare()

◆ analyzeLoopForPipelining()

◆ areMemAccessesTriviallyDisjoint()

◆ canExecuteInBundle()

◆ changeAddrMode_abs_io() [1/2]

◆ changeAddrMode_abs_io() [2/2]

◆ changeAddrMode_io_abs() [1/2]

◆ changeAddrMode_io_abs() [2/2]

◆ changeAddrMode_io_pi()

◆ changeAddrMode_io_rr() [1/2]

◆ changeAddrMode_io_rr() [2/2]

◆ changeAddrMode_pi_io()

◆ changeAddrMode_rr_io() [1/2]

◆ changeAddrMode_rr_io() [2/2]

◆ changeAddrMode_rr_ur() [1/2]

◆ changeAddrMode_rr_ur() [2/2]

◆ changeAddrMode_ur_rr() [1/2]

◆ changeAddrMode_ur_rr() [2/2]

◆ changeDuplexOpcode()

◆ ClobbersPredicate()

◆ copyPhysReg()

◆ CreateTargetPostRAHazardRecognizer()

◆ CreateTargetScheduleState()

◆ createVR()

◆ decomposeMachineOperandsTargetFlags()

◆ doesNotReturn()

◆ expandPostRAPseudo()

◆ expandVGatherPseudo()

◆ findLoopInstr()

◆ genAllInsnTimingClasses()

◆ getAddrMode()

◆ getBaseAndOffset()

◆ getBaseAndOffsetPosition()

◆ getBranchingInstrs()

◆ getBundleNoShuf()

◆ getCExtOpNum()

◆ getCompoundCandidateGroup()

◆ getCompoundOpcode()

◆ getCondOpcode()

◆ getDotCurOp()

◆ getDotNewOp()

◆ getDotNewPredJumpOp()

◆ getDotNewPredOp()

◆ getDotOldOp()

◆ getDuplexCandidateGroup()

◆ getDuplexOpcode()

◆ getEquivalentHWInstr()

◆ getIncrementValue()

◆ getInlineAsmLength()

◆ getInstrLatency()

◆ getInstrTimingClassLatency()

◆ getInvertedPredicatedOpcode()

◆ getInvertedPredSense()

◆ getMaxValue()

◆ getMemAccessSize()

◆ getMemOperandsWithOffsetWidth()

◆ getMinValue()

◆ getNonDotCurOp()

◆ getNonExtOpcode()

◆ getNop()

◆ getOperandLatency()

◆ getPredReg()

◆ getPseudoInstrPair()

◆ getRegForm()

◆ getSerializableBitmaskMachineOperandTargetFlags()

◆ getSerializableDirectMachineOperandTargetFlags()

◆ getSize()

◆ getType()

◆ getUnits()

◆ hasEHLabel()

◆ hasLoadFromStackSlot()

◆ hasNonExtEquivalent()

◆ hasPseudoInstrPair()