LLVM 18.0.0git
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#include "Target/Hexagon/HexagonInstrInfo.h"
Definition at line 38 of file HexagonInstrInfo.h.
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explicit |
Definition at line 121 of file HexagonInstrInfo.cpp.
bool HexagonInstrInfo::addLatencyToSchedule | ( | const MachineInstr & | MI1, |
const MachineInstr & | MI2 | ||
) | const |
Definition at line 3034 of file HexagonInstrInfo.cpp.
References isHVXVec(), and isVecUsableNextPacket().
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Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.
This function can analyze one/two way branching only and should (mostly) be called by target independent side.
it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:
Note that removeBranch and insertBranch must be implemented to support cases where this method returns success.
If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).
First entry is always the opcode of the branching instruction, except when the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a BB with only unconditional jump. Subsequent entries depend upon the opcode, e.g. Jump_c p will have Cond[0] = Jump_c Cond[1] = p HW-loop ENDLOOP: Cond[0] = ENDLOOP Cond[1] = MBB New value jump: Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 – specific opcode Cond[1] = R Cond[2] = Imm
Definition at line 435 of file HexagonInstrInfo.cpp.
References Cond, llvm::MachineOperand::CreateImm(), llvm::dbgs(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), isEndLoopN(), llvm::MachineBasicBlock::isLayoutSuccessor(), llvm::MachineOperand::isMBB(), isNewValueJump(), LLVM_DEBUG, MBB, PredOpcodeHasJMP_c(), llvm::printMBBReference(), and TBB.
Referenced by llvm::MachineBasicBlock::canSplitCriticalEdge(), FixTail(), getBBFallenThrough(), llvm::MachineBasicBlock::getFallThrough(), INITIALIZE_PASS(), insertBranch(), isAnalyzableBB(), jumpTableHasOtherUses(), llvm::PeelSingleBlockLoop(), updateBranches(), and llvm::MachineBasicBlock::updateTerminator().
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For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
For a comparison instruction, return the source registers in SrcReg
and SrcReg2
if having two register operands, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 1879 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::isImm(), and MI.
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Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.
Definition at line 805 of file HexagonInstrInfo.cpp.
References llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::MachineBasicBlock::getFirstTerminator(), I, and isEndLoopN().
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Definition at line 1985 of file HexagonInstrInfo.cpp.
References getBaseAndOffsetPosition(), llvm::MachineOperand::getImm(), getMemAccessSize(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineOperand::isImm(), isMemOp(), isPostIncrement(), and llvm::MachineInstr::mayLoad().
Referenced by llvm::MachineInstr::mayAlias().
bool HexagonInstrInfo::canExecuteInBundle | ( | const MachineInstr & | First, |
const MachineInstr & | Second | ||
) | const |
Can these instructions execute at the same time in a bundle.
Definition at line 3056 of file HexagonInstrInfo.cpp.
References DisableNVSchedule, llvm::First, llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), mayBeNewStore(), and llvm::MachineInstr::mayStore().
Referenced by llvm::HexagonSubtarget::adjustSchedDependency().
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Definition at line 514 of file HexagonInstrInfo.h.
References changeAddrMode_abs_io(), and MI.
short HexagonInstrInfo::changeAddrMode_abs_io | ( | short | Opc | ) | const |
Definition at line 4709 of file HexagonInstrInfo.cpp.
Referenced by changeAddrMode_abs_io().
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Definition at line 517 of file HexagonInstrInfo.h.
References changeAddrMode_io_abs(), and MI.
short HexagonInstrInfo::changeAddrMode_io_abs | ( | short | Opc | ) | const |
Definition at line 4713 of file HexagonInstrInfo.cpp.
Referenced by changeAddrMode_io_abs().
short HexagonInstrInfo::changeAddrMode_io_pi | ( | short | Opc | ) | const |
Definition at line 4717 of file HexagonInstrInfo.cpp.
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Definition at line 520 of file HexagonInstrInfo.h.
References changeAddrMode_io_rr(), and MI.
short HexagonInstrInfo::changeAddrMode_io_rr | ( | short | Opc | ) | const |
Definition at line 4721 of file HexagonInstrInfo.cpp.
Referenced by changeAddrMode_io_rr().
short HexagonInstrInfo::changeAddrMode_pi_io | ( | short | Opc | ) | const |
Definition at line 4725 of file HexagonInstrInfo.cpp.
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Definition at line 523 of file HexagonInstrInfo.h.
References changeAddrMode_rr_io(), and MI.
short HexagonInstrInfo::changeAddrMode_rr_io | ( | short | Opc | ) | const |
Definition at line 4729 of file HexagonInstrInfo.cpp.
Referenced by changeAddrMode_rr_io().
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Definition at line 526 of file HexagonInstrInfo.h.
References changeAddrMode_rr_ur(), and MI.
short HexagonInstrInfo::changeAddrMode_rr_ur | ( | short | Opc | ) | const |
Definition at line 4733 of file HexagonInstrInfo.cpp.
Referenced by changeAddrMode_rr_ur().
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Definition at line 529 of file HexagonInstrInfo.h.
References changeAddrMode_ur_rr(), and MI.
short HexagonInstrInfo::changeAddrMode_ur_rr | ( | short | Opc | ) | const |
Definition at line 4737 of file HexagonInstrInfo.cpp.
Referenced by changeAddrMode_ur_rr().
void HexagonInstrInfo::changeDuplexOpcode | ( | MachineBasicBlock::instr_iterator | MII, |
bool | ToBigInstrs | ||
) | const |
Definition at line 4422 of file HexagonInstrInfo.cpp.
References llvm::get(), getDuplexCandidateGroup(), getDuplexOpcode(), and Opcode.
Referenced by translateInstrsForDup().
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If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.
Definition at line 1729 of file HexagonInstrInfo.cpp.
References llvm::HexagonSubtarget::getRegisterInfo(), and MI.
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Emit instructions to copy a pair of physical registers.
This function should support copies within any legal register class as well as any cross-class copies created during instruction selection.
The source and destination registers may overlap, which may require a careful implementation when multiple copy instructions are required for large registers. See for example the ARM target.
Definition at line 856 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::LivePhysRegs::contains(), contains(), llvm::dbgs(), DL, llvm::get(), llvm::getKillRegState(), getLiveInRegsAt(), llvm::HexagonSubtarget::getRegisterInfo(), llvm::getUndefRegState(), I, llvm_unreachable, MBB, llvm::printMBBReference(), and llvm::printReg().
Referenced by llvm::AArch64FrameLowering::emitPrologue(), expandPostRAPseudo(), INITIALIZE_PASS(), llvm::Mips16RegisterInfo::saveScavengerRegister(), and tryOptimizeLEAtoMOV().
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Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation.
Definition at line 1868 of file HexagonInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer(), and UseDFAHazardRec.
Referenced by INITIALIZE_PASS().
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Create machine specific model for scheduling.
Definition at line 1975 of file HexagonInstrInfo.cpp.
References llvm::TargetSubtargetInfo::getInstrItineraryData().
Register HexagonInstrInfo::createVR | ( | MachineFunction * | MF, |
MVT | VT | ||
) | const |
HexagonInstrInfo specifics.
Definition at line 2100 of file HexagonInstrInfo.cpp.
References llvm::MachineFunction::getRegInfo(), llvm_unreachable, and MRI.
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Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied.
Definition at line 2066 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::MO_Bitmasks.
Referenced by llvm::MachineOperand::printTargetFlags().
bool HexagonInstrInfo::doesNotReturn | ( | const MachineInstr & | CallMI | ) | const |
Definition at line 3081 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by isSchedulingBoundary().
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This function is called for all pseudo instructions that remain after register allocation.
expandPostRAPseudo - This function is called for all pseudo instructions that remain after register allocation.
Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.
Definition at line 1051 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::all_of(), assert(), llvm::LivePhysRegs::available(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), copyPhysReg(), llvm::MachineFunction::createExternalSymbolName(), DL, llvm::MachineBasicBlock::erase(), llvm::get(), llvm::HexagonRegisterInfo::getFrameRegister(), llvm::MachineOperand::getImm(), llvm::GlobalVariable::getInitializer(), llvm::getKillRegState(), getLiveInRegsAt(), getLiveOutRegsAt(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::SrcOp::getReg(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::HexagonSubtarget::getRegisterInfo(), llvm::getRegState(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getTarget(), llvm::getUndefRegState(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::RegState::InternalRead, isConstant(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), llvm::RegState::Kill, mayAlias(), MBB, MBBI, MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOVolatile, MRI, llvm::Offset, OS, TM, and llvm::RegState::Undef.
MachineBasicBlock::instr_iterator HexagonInstrInfo::expandVGatherPseudo | ( | MachineInstr & | MI | ) | const |
Definition at line 1545 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::erase(), llvm::First, llvm::get(), MBB, and MI.
MachineInstr * HexagonInstrInfo::findLoopInstr | ( | MachineBasicBlock * | BB, |
unsigned | EndLoopOp, | ||
MachineBasicBlock * | TargetBB, | ||
SmallPtrSet< MachineBasicBlock *, 8 > & | Visited | ||
) | const |
Find the hardware loop instruction used to set-up the specified loop.
On Hexagon, we have two instructions used to set-up the hardware loop (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions to indicate the end of a loop.
Definition at line 198 of file HexagonInstrInfo.cpp.
References findLoopInstr(), I, llvm::SmallPtrSetImpl< PtrType >::insert(), PB(), llvm::MachineBasicBlock::predecessors(), and llvm::reverse().
Referenced by analyzeLoopForPipelining(), findLoopInstr(), and insertBranch().
void HexagonInstrInfo::genAllInsnTimingClasses | ( | MachineFunction & | MF | ) | const |
Definition at line 4647 of file HexagonInstrInfo.cpp.
References A, B, llvm::MachineFunction::begin(), llvm::BuildMI(), llvm::dbgs(), DL, llvm::MachineInstr::eraseFromParent(), llvm::get(), llvm::MachineInstr::getDesc(), getName(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::getSchedClass(), I, and LLVM_DEBUG.
unsigned HexagonInstrInfo::getAddrMode | ( | const MachineInstr & | MI | ) | const |
Definition at line 3252 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AddrModeMask, llvm::HexagonII::AddrModePos, F, and MI.
Referenced by llvm::HexagonSubtarget::BankConflictMutation::apply(), getBaseAndOffset(), getNonExtOpcode(), hasNonExtEquivalent(), isAbsoluteSet(), isBaseImmOffset(), and isPostIncrement().
MachineOperand * HexagonInstrInfo::getBaseAndOffset | ( | const MachineInstr & | MI, |
int64_t & | Offset, | ||
unsigned & | AccessSize | ||
) | const |
Definition at line 3261 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), getBaseAndOffsetPosition(), llvm::MachineOperand::getImm(), getMemAccessSize(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), isMemOp(), isPostIncrement(), MI, and llvm::Offset.
Referenced by llvm::HexagonSubtarget::BankConflictMutation::apply(), and getMemOperandsWithOffsetWidth().
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For instructions with a base and offset, return the position of the base register and offset operands.
Return the position of the base and offset operands for this instruction.
Definition at line 3294 of file HexagonInstrInfo.cpp.
References isAddrModeWithOffset(), isMemOp(), isPostIncrement(), isPredicated(), and MI.
Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), getIncrementValue(), and isLoadStoreThatCanHandleDisplacement().
SmallVector< MachineInstr *, 2 > HexagonInstrInfo::getBranchingInstrs | ( | MachineBasicBlock & | MBB | ) | const |
Definition at line 3331 of file HexagonInstrInfo.cpp.
References I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), MBB, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
bool HexagonInstrInfo::getBundleNoShuf | ( | const MachineInstr & | MIB | ) | const |
Definition at line 4702 of file HexagonInstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::isBundle(), and llvm::MachineOperand::isImm().
unsigned HexagonInstrInfo::getCExtOpNum | ( | const MachineInstr & | MI | ) | const |
Definition at line 3389 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendableOpMask, llvm::HexagonII::ExtendableOpPos, F, and MI.
Referenced by immediateExtend(), and isConstExtended().
HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup | ( | const MachineInstr & | MI | ) | const |
Definition at line 3396 of file HexagonInstrInfo.cpp.
References contains(), llvm::HexagonII::HCG_A, llvm::HexagonII::HCG_B, llvm::HexagonII::HCG_C, llvm::HexagonII::HCG_None, isIntRegForSubInst(), and MI.
Referenced by getCompoundOpcode().
unsigned HexagonInstrInfo::getCompoundOpcode | ( | const MachineInstr & | GA, |
const MachineInstr & | GB | ||
) | const |
Definition at line 3484 of file HexagonInstrInfo.cpp.
References assert(), getCompoundCandidateGroup(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::HexagonII::HCG_A, llvm::HexagonII::HCG_B, llvm::MachineOperand::isImm(), and llvm::MachineInstr::readsRegister().
int HexagonInstrInfo::getCondOpcode | ( | int | Opc, |
bool | sense | ||
) | const |
Definition at line 3568 of file HexagonInstrInfo.cpp.
References llvm_unreachable.
Referenced by PredicateInstruction().
int HexagonInstrInfo::getDotCurOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3580 of file HexagonInstrInfo.cpp.
References llvm_unreachable, and MI.
int HexagonInstrInfo::getDotNewOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3701 of file HexagonInstrInfo.cpp.
References MI, and llvm::report_fatal_error().
Referenced by llvm::HexagonHazardRecognizer::EmitInstruction(), and llvm::HexagonHazardRecognizer::getHazardType().
int HexagonInstrInfo::getDotNewPredJumpOp | ( | const MachineInstr & | MI, |
const MachineBranchProbabilityInfo * | MBPI | ||
) | const |
Definition at line 3742 of file HexagonInstrInfo.cpp.
References assert(), B, llvm::MachineBranchProbabilityInfo::getEdgeProbability(), llvm::MachineOperand::getMBB(), I, llvm::MachineOperand::isMBB(), llvm_unreachable, and MI.
Referenced by getDotNewPredOp().
int HexagonInstrInfo::getDotNewPredOp | ( | const MachineInstr & | MI, |
const MachineBranchProbabilityInfo * | MBPI | ||
) | const |
Definition at line 3828 of file HexagonInstrInfo.cpp.
References getDotNewPredJumpOp(), and MI.
int HexagonInstrInfo::getDotOldOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3843 of file HexagonInstrInfo.cpp.
References assert(), llvm::HexagonSubtarget::hasV60Ops(), isNewValueStore(), isPredicated(), isPredicatedNew(), and MI.
HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup | ( | const MachineInstr & | MI | ) | const |
Definition at line 3894 of file HexagonInstrInfo.cpp.
References contains(), llvm::HexagonSubtarget::getRegisterInfo(), llvm::HexagonRegisterInfo::getStackRegister(), llvm::HexagonII::HSIG_A, llvm::HexagonII::HSIG_L1, llvm::HexagonII::HSIG_L2, llvm::HexagonII::HSIG_None, llvm::HexagonII::HSIG_S1, llvm::HexagonII::HSIG_S2, isDblRegForSubInst(), isIntRegForSubInst(), and MI.
Referenced by changeDuplexOpcode(), and isDuplexPair().
int HexagonInstrInfo::getDuplexOpcode | ( | const MachineInstr & | MI, |
bool | ForBigCore = true |
||
) | const |
Definition at line 3511 of file HexagonInstrInfo.cpp.
References MI.
Referenced by changeDuplexOpcode().
short HexagonInstrInfo::getEquivalentHWInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 4274 of file HexagonInstrInfo.cpp.
References MI.
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If the instruction is an increment of a constant value, return the amount.
Definition at line 2043 of file HexagonInstrInfo.cpp.
References getBaseAndOffsetPosition(), llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), isPostIncrement(), and MI.
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Measure the specified inline asm to determine an approximation of its length.
Comments (which run till the next SeparatorString or newline) do not count as an instruction. Any other non-whitespace text is considered an instruction, with multiple instructions separated by SeparatorString or newlines. Variable-length instructions are not handled here; this function may be overloaded in the target code to do that. Hexagon counts the number of ##'s and adjust for that many constant exenders.
Definition at line 1840 of file HexagonInstrInfo.cpp.
References llvm::StringRef::count(), llvm::StringRef::data(), llvm::MCAsmInfo::getCommentString(), llvm::MCAsmInfo::getMaxInstLength(), llvm::MCAsmInfo::getSeparatorString(), llvm::Length, and llvm::StringRef::size().
Referenced by llvm::MSP430InstrInfo::getInstSizeInBytes(), and getSize().
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Compute the instruction latency of a given instruction.
If the instruction has higher cost when predicated, it's returned via PredCost.
Definition at line 1969 of file HexagonInstrInfo.cpp.
References getInstrTimingClassLatency(), and MI.
Referenced by getInstrTimingClassLatency().
unsigned HexagonInstrInfo::getInstrTimingClassLatency | ( | const InstrItineraryData * | ItinData, |
const MachineInstr & | MI | ||
) | const |
Definition at line 4278 of file HexagonInstrInfo.cpp.
References getInstrLatency(), llvm::InstrItineraryData::getStageLatency(), and MI.
Referenced by getInstrLatency().
Definition at line 4351 of file HexagonInstrInfo.cpp.
References isPredicatedTrue(), and llvm_unreachable.
Referenced by getInvertedPredSense(), invertAndChangeJumpTarget(), reverseBranchCondition(), and reversePredSense().
bool HexagonInstrInfo::getInvertedPredSense | ( | SmallVectorImpl< MachineOperand > & | Cond | ) | const |
Definition at line 4342 of file HexagonInstrInfo.cpp.
References Cond, and getInvertedPredicatedOpcode().
int HexagonInstrInfo::getMaxValue | ( | const MachineInstr & | MI | ) | const |
Definition at line 4362 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtentBitsMask, llvm::HexagonII::ExtentBitsPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F, isSigned(), and MI.
Referenced by isConstExtended().
unsigned HexagonInstrInfo::getMemAccessSize | ( | const MachineInstr & | MI | ) | const |
Definition at line 4459 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::DoubleWordAccess, F, llvm::HexagonSubtarget::getRegisterInfo(), llvm::HexagonII::HVXVectorAccess, llvm_unreachable, MI, and Size.
Referenced by areMemAccessesTriviallyDisjoint(), and getBaseAndOffset().
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Get the base register and byte offset of a load/store instr.
Definition at line 3043 of file HexagonInstrInfo.cpp.
References getBaseAndOffset(), llvm::MachineOperand::isReg(), llvm::Offset, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
int HexagonInstrInfo::getMinValue | ( | const MachineInstr & | MI | ) | const |
Definition at line 4482 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtentBitsMask, llvm::HexagonII::ExtentBitsPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F, isSigned(), and MI.
Referenced by isConstExtended().
int HexagonInstrInfo::getNonDotCurOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3600 of file HexagonInstrInfo.cpp.
References llvm_unreachable, and MI.
short HexagonInstrInfo::getNonExtOpcode | ( | const MachineInstr & | MI | ) | const |
Definition at line 4496 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::Absolute, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), and MI.
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Definition at line 4741 of file HexagonInstrInfo.cpp.
References llvm::MCInstBuilder::addImm(), and llvm::MCInstBuilder::addInst().
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getOperandLatency - Compute and return the use operand latency of a given pair of def and use.
In most cases, the static scheduling itinerary was enough to determine the operand latency. But it may not be possible for instructions with variable number of defs / uses.
This is a raw interface to the itinerary that may be directly overriden by a target. Use computeOperandLatency to get the best estimate of latency.
Definition at line 4298 of file HexagonInstrInfo.cpp.
References DefMI, llvm::TargetInstrInfo::getOperandLatency(), llvm::MachineOperand::getReg(), llvm::HexagonSubtarget::getRegisterInfo(), Idx, llvm::MachineOperand::isImplicit(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::Latency, and UseMI.
Referenced by llvm::HexagonSubtarget::adjustSchedDependency().
bool HexagonInstrInfo::getPredReg | ( | ArrayRef< MachineOperand > | Cond, |
Register & | PredReg, | ||
unsigned & | PredRegPos, | ||
unsigned & | PredRegFlags | ||
) | const |
Definition at line 4520 of file HexagonInstrInfo.cpp.
References assert(), Cond, llvm::dbgs(), llvm::RegState::Implicit, isNewValueJump(), isUndef(), LLVM_DEBUG, and llvm::RegState::Undef.
Referenced by PredicateInstruction().
short HexagonInstrInfo::getPseudoInstrPair | ( | const MachineInstr & | MI | ) | const |
Definition at line 4540 of file HexagonInstrInfo.cpp.
References MI.
short HexagonInstrInfo::getRegForm | ( | const MachineInstr & | MI | ) | const |
Definition at line 4544 of file HexagonInstrInfo.cpp.
References MI.
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Return an array that contains the bitmask target flag values and their names.
MIR Serialization is able to serialize only the target flags that are defined by this method.
Definition at line 2091 of file HexagonInstrInfo.cpp.
Referenced by llvm::MachineOperand::printTargetFlags().
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Return an array that contains the direct target flag values and their names.
MIR Serialization is able to serialize only the target flags that are defined by this method.
Definition at line 2072 of file HexagonInstrInfo.cpp.
Referenced by getTargetFlagName().
unsigned HexagonInstrInfo::getSize | ( | const MachineInstr & | MI | ) | const |
Definition at line 4552 of file HexagonInstrInfo.cpp.
References assert(), BranchRelaxAsmLarge, getInlineAsmLength(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getTarget(), HEXAGON_INSTR_SIZE, isConstExtended(), isExtended(), isReg(), MBB, MI, and Size.
uint64_t HexagonInstrInfo::getType | ( | const MachineInstr & | MI | ) | const |
Definition at line 4586 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::TypeMask, and llvm::HexagonII::TypePos.
Referenced by cannotCoexistAsymm(), llvm::InstCombinerImpl::foldSelectOpOp(), isCompoundBranchInstr(), isHVXVec(), and isLateSourceInstr().
InstrStage::FuncUnits HexagonInstrInfo::getUnits | ( | const MachineInstr & | MI | ) | const |
Definition at line 4591 of file HexagonInstrInfo.cpp.
References llvm::InstrItineraryData::beginStage(), llvm::HexagonSubtarget::getInstrItineraryData(), llvm::InstrStage::getUnits(), and MI.
Referenced by isPureSlot0().
bool HexagonInstrInfo::hasEHLabel | ( | const MachineBasicBlock * | B | ) | const |
Definition at line 3086 of file HexagonInstrInfo.cpp.
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Check if the instruction or the bundle of instructions has load from stack slots.
This function checks if the instruction or bundle of instructions has load from stack slot and returns frameindex and machine memory operand of that instruction if true.
Return the frameindex and machine memory operand if true.
Definition at line 387 of file HexagonInstrInfo.cpp.
References llvm::TargetInstrInfo::hasLoadFromStackSlot(), llvm::MachineBasicBlock::instr_end(), MBB, and MI.
Referenced by llvm::MachineInstr::getFoldedRestoreSize().
bool HexagonInstrInfo::hasNonExtEquivalent | ( | const MachineInstr & | MI | ) | const |
Definition at line 3095 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::Absolute, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), and MI.
bool HexagonInstrInfo::hasPseudoInstrPair | ( | const MachineInstr & | MI | ) | const |
Definition at line 3130 of file HexagonInstrInfo.cpp.
References MI.
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Check if the instruction or the bundle of instructions has store to stack slots.
This function checks if the instruction or bundle of instructions has store to stack slot and returns frameindex and machine memory operand of that instruction if true.
Return the frameindex and machine memory operand if true.
Definition at line 405 of file HexagonInstrInfo.cpp.
References llvm::TargetInstrInfo::hasStoreToStackSlot(), llvm::MachineBasicBlock::instr_end(), MBB, and MI.
Referenced by llvm::MachineInstr::getFoldedSpillSize().
bool HexagonInstrInfo::hasUncondBranch | ( | const MachineBasicBlock * | B | ) | const |
Definition at line 3135 of file HexagonInstrInfo.cpp.
void HexagonInstrInfo::immediateExtend | ( | MachineInstr & | MI | ) | const |
immediateExtend - Changes the instruction in place to one using an immediate extender.
Definition at line 4613 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::addTargetFlag(), assert(), getCExtOpNum(), llvm::HexagonII::HMOTF_ConstExtended, isConstExtended(), isExtendable(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isMBB(), and MI.
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Insert branch code into the end of the specified MachineBasicBlock.
The operands to this method are the same as those returned by analyzeBranch. This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions inserted.
It is also invoked by tail merging to add unconditional branches in cases where analyzeBranch doesn't apply because there was no original branch to analyze. At least this much must be implemented, else tail merging needs to be disabled.
Definition at line 628 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), analyzeBranch(), assert(), llvm::BuildMI(), Cond, llvm::dbgs(), DL, llvm::MachineBasicBlock::end(), findLoopInstr(), llvm::get(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getReg(), getReg(), llvm::getUndefRegState(), insertBranch(), isEndLoopN(), isImm(), isNewValueJump(), isPredicated(), isReg(), llvm::MachineOperand::isUndef(), isUndef(), LLVM_DEBUG, llvm_unreachable, MBB, llvm::printMBBReference(), removeBranch(), reverseBranchCondition(), TBB, and validateBranchCond().
Referenced by FixTail(), insertBranch(), InsertUncondBranch(), llvm::PeelSingleBlockLoop(), llvm::MachineBasicBlock::SplitCriticalEdge(), splitEdge(), and llvm::MachineBasicBlock::updateTerminator().
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Insert a noop into the instruction stream at the specified point.
Definition at line 1648 of file HexagonInstrInfo.cpp.
References llvm::BuildMI(), DL, llvm::get(), MBB, and MI.
bool HexagonInstrInfo::invertAndChangeJumpTarget | ( | MachineInstr & | MI, |
MachineBasicBlock * | NewTarget | ||
) | const |
Definition at line 4626 of file HexagonInstrInfo.cpp.
References assert(), llvm::dbgs(), llvm::Pass::dump(), EnableBranchPrediction, llvm::get(), getInvertedPredicatedOpcode(), isPredicatedNew(), LLVM_DEBUG, MI, llvm::printMBBReference(), and reversePrediction().
bool HexagonInstrInfo::isAbsoluteSet | ( | const MachineInstr & | MI | ) | const |
Definition at line 2117 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AbsoluteSet, getAddrMode(), and MI.
bool HexagonInstrInfo::isAccumulator | ( | const MachineInstr & | MI | ) | const |
Definition at line 2121 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AccumulatorMask, llvm::HexagonII::AccumulatorPos, F, and MI.
Referenced by isVecAcc().
bool HexagonInstrInfo::isAddrModeWithOffset | ( | const MachineInstr & | MI | ) | const |
Definition at line 4376 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AddrModeMask, llvm::HexagonII::AddrModePos, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, llvm::HexagonII::BaseRegOffset, F, and MI.
Referenced by getBaseAndOffsetPosition().
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Definition at line 155 of file HexagonInstrInfo.cpp.
References MI.
bool HexagonInstrInfo::isBaseImmOffset | ( | const MachineInstr & | MI | ) | const |
Definition at line 2126 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::BaseImmOffset, getAddrMode(), and MI.
bool HexagonInstrInfo::isComplex | ( | const MachineInstr & | MI | ) | const |
Definition at line 2130 of file HexagonInstrInfo.cpp.
References isMemOp(), isTC1(), isTC2Early(), and MI.
bool HexagonInstrInfo::isCompoundBranchInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 2139 of file HexagonInstrInfo.cpp.
References getType(), MI, and llvm::HexagonII::TypeCJ.
bool HexagonInstrInfo::isConstExtended | ( | const MachineInstr & | MI | ) | const |
Definition at line 2145 of file HexagonInstrInfo.cpp.
References assert(), llvm::HexagonII::ExtendableMask, llvm::HexagonII::ExtendablePos, llvm::HexagonII::ExtendedMask, llvm::HexagonII::ExtendedPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F, getCExtOpNum(), llvm::MachineOperand::getImm(), getMaxValue(), getMinValue(), llvm::MachineOperand::getTargetFlags(), llvm::HexagonII::HMOTF_ConstExtended, llvm::MachineOperand::isBlockAddress(), llvm::MachineOperand::isCPI(), isExtendable(), isExtended(), llvm::MachineOperand::isFPImm(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isJTI(), llvm::MachineOperand::isMBB(), llvm::MachineOperand::isSymbol(), and MI.
Referenced by getSize(), and immediateExtend().
bool HexagonInstrInfo::isDeallocRet | ( | const MachineInstr & | MI | ) | const |
Definition at line 2194 of file HexagonInstrInfo.cpp.
References MI.
bool HexagonInstrInfo::isDependent | ( | const MachineInstr & | ProdMI, |
const MachineInstr & | ConsMI | ||
) | const |
Definition at line 2209 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::HexagonSubtarget::getRegisterInfo(), llvm::is_contained(), and parseOperands().
Referenced by producesStall().
bool HexagonInstrInfo::isDotCurInst | ( | const MachineInstr & | MI | ) | const |
Definition at line 2240 of file HexagonInstrInfo.cpp.
References MI.
bool HexagonInstrInfo::isDotNewInst | ( | const MachineInstr & | MI | ) | const |
Definition at line 2251 of file HexagonInstrInfo.cpp.
References isNewValueInst(), isPredicated(), isPredicatedNew(), and MI.
bool HexagonInstrInfo::isDuplexPair | ( | const MachineInstr & | MIa, |
const MachineInstr & | MIb | ||
) | const |
Symmetrical. See if these two instructions are fit for duplex pair.
Definition at line 2259 of file HexagonInstrInfo.cpp.
References getDuplexCandidateGroup(), and isDuplexPairMatch().
Definition at line 2266 of file HexagonInstrInfo.cpp.
References Opcode.
Referenced by analyzeBranch(), analyzeLoopForPipelining(), insertBranch(), PredicateInstruction(), and reverseBranchCondition().
Definition at line 2271 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::MO_BlockAddress, llvm::MachineOperand::MO_ConstantPoolIndex, llvm::MachineOperand::MO_ExternalSymbol, llvm::MachineOperand::MO_GlobalAddress, llvm::MachineOperand::MO_JumpTableIndex, and llvm::MachineOperand::MO_MachineBasicBlock.
bool HexagonInstrInfo::isExtendable | ( | const MachineInstr & | MI | ) | const |
Definition at line 2285 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendableMask, llvm::HexagonII::ExtendablePos, F, MI, and llvm::MCInstrDesc::TSFlags.
Referenced by immediateExtend(), and isConstExtended().
bool HexagonInstrInfo::isExtended | ( | const MachineInstr & | MI | ) | const |
Definition at line 2307 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendedMask, llvm::HexagonII::ExtendedPos, F, llvm::HexagonII::HMOTF_ConstExtended, and MI.
Referenced by getSize(), and isConstExtended().
bool HexagonInstrInfo::isFloat | ( | const MachineInstr & | MI | ) | const |
Definition at line 2320 of file HexagonInstrInfo.cpp.
References F, llvm::HexagonII::FPMask, llvm::HexagonII::FPPos, llvm::get(), MI, and Opcode.
Referenced by shouldSink().
bool HexagonInstrInfo::isHVXMemWithAIndirect | ( | const MachineInstr & | I, |
const MachineInstr & | J | ||
) | const |
Definition at line 2327 of file HexagonInstrInfo.cpp.
References I, isHVXVec(), llvm::MachineInstr::isIndirectBranch(), isIndirectCall(), and isIndirectL4Return().
Referenced by cannotCoexistAsymm().
bool HexagonInstrInfo::isHVXVec | ( | const MachineInstr & | MI | ) | const |
Definition at line 2704 of file HexagonInstrInfo.cpp.
References getType(), MI, llvm::HexagonII::TypeCVI_FIRST, and llvm::HexagonII::TypeCVI_LAST.
Referenced by addLatencyToSchedule(), llvm::HexagonHazardRecognizer::EmitInstruction(), isHVXMemWithAIndirect(), isVecAcc(), and producesStall().
bool HexagonInstrInfo::isIndirectCall | ( | const MachineInstr & | MI | ) | const |
Definition at line 2336 of file HexagonInstrInfo.cpp.
References MI.
Referenced by isHVXMemWithAIndirect().
bool HexagonInstrInfo::isIndirectL4Return | ( | const MachineInstr & | MI | ) | const |
Definition at line 2347 of file HexagonInstrInfo.cpp.
References MI.
Referenced by isHVXMemWithAIndirect().
bool HexagonInstrInfo::isJumpR | ( | const MachineInstr & | MI | ) | const |
Definition at line 2361 of file HexagonInstrInfo.cpp.
References MI.
bool HexagonInstrInfo::isJumpWithinBranchRange | ( | const MachineInstr & | MI, |
unsigned | offset | ||
) | const |
Definition at line 2379 of file HexagonInstrInfo.cpp.
References isNewValueJump(), and MI.
bool HexagonInstrInfo::isLateSourceInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 2421 of file HexagonInstrInfo.cpp.
References getType(), MI, and llvm::HexagonII::TypeCVI_VX_LATE.
Referenced by isVecUsableNextPacket().
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TargetInstrInfo overrides.
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.
If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
Definition at line 289 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and MI.
Referenced by MatchingStackOffset(), and llvm::SIFrameLowering::processFunctionBeforeFrameFinalized().
bool HexagonInstrInfo::isLoopN | ( | const MachineInstr & | MI | ) | const |
Definition at line 2427 of file HexagonInstrInfo.cpp.
bool HexagonInstrInfo::isMemOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 2439 of file HexagonInstrInfo.cpp.
References MI.
Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), getBaseAndOffsetPosition(), and isComplex().
bool HexagonInstrInfo::isNewValue | ( | const MachineInstr & | MI | ) | const |
Definition at line 2471 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::NewValueMask, and llvm::HexagonII::NewValuePos.
Referenced by isNewValueJump(), and isPredictedTaken().
Definition at line 2476 of file HexagonInstrInfo.cpp.
References F, llvm::get(), llvm::HexagonII::NewValueMask, llvm::HexagonII::NewValuePos, and Opcode.
bool HexagonInstrInfo::isNewValueInst | ( | const MachineInstr & | MI | ) | const |
Definition at line 2481 of file HexagonInstrInfo.cpp.
References isNewValueJump(), isNewValueStore(), and MI.
Referenced by isDotNewInst().
bool HexagonInstrInfo::isNewValueJump | ( | const MachineInstr & | MI | ) | const |
Definition at line 2485 of file HexagonInstrInfo.cpp.
References isNewValue(), and MI.
Referenced by analyzeBranch(), getPredReg(), insertBranch(), isJumpWithinBranchRange(), isNewValueInst(), and PredicateInstruction().
Definition at line 2489 of file HexagonInstrInfo.cpp.
References llvm::get(), isNewValue(), isPredicated(), and Opcode.
bool HexagonInstrInfo::isNewValueStore | ( | const MachineInstr & | MI | ) | const |
Definition at line 2493 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::NVStoreMask, and llvm::HexagonII::NVStorePos.
Referenced by cannotCoexistAsymm(), getDotOldOp(), and isNewValueInst().
Definition at line 2498 of file HexagonInstrInfo.cpp.
References F, llvm::get(), llvm::HexagonII::NVStoreMask, llvm::HexagonII::NVStorePos, and Opcode.
bool HexagonInstrInfo::isOperandExtended | ( | const MachineInstr & | MI, |
unsigned | OperandNum | ||
) | const |
Definition at line 2504 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendableOpMask, llvm::HexagonII::ExtendableOpPos, F, and MI.
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Return true for post-incremented instructions.
Definition at line 1654 of file HexagonInstrInfo.cpp.
References getAddrMode(), MI, and llvm::HexagonII::PostInc.
Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), getBaseAndOffsetPosition(), getIncrementValue(), and getPostIncrementOperand().
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Return true if the specified instruction can be predicated.
By default, this returns true for every instruction with a PredicateOperand.
Definition at line 1756 of file HexagonInstrInfo.cpp.
References llvm::HexagonSubtarget::hasV62Ops(), isTailCall(), MI, and llvm::HexagonSubtarget::usePredicatedCalls().
Referenced by PredicateInstruction().
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Returns true if the instruction is already predicated.
Definition at line 1666 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.
Referenced by findHoistingInsertPosAndDeps(), getBaseAndOffsetPosition(), getDotOldOp(), llvm::MachineBasicBlock::getFallThrough(), getPredicatedRegister(), getPredicateSense(), insertBranch(), isDotNewInst(), isNewValueJump(), isPredicatedNew(), and predOpcodeHasNot().
Definition at line 2537 of file HexagonInstrInfo.cpp.
References F, llvm::get(), Opcode, llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.
bool HexagonInstrInfo::isPredicatedNew | ( | const MachineInstr & | MI | ) | const |
Definition at line 2511 of file HexagonInstrInfo.cpp.
References assert(), F, isPredicated(), MI, llvm::HexagonII::PredicatedNewMask, and llvm::HexagonII::PredicatedNewPos.
Referenced by getDotOldOp(), invertAndChangeJumpTarget(), isDotNewInst(), and isPredictedTaken().
Definition at line 2517 of file HexagonInstrInfo.cpp.
References assert(), F, llvm::get(), isPredicated(), Opcode, llvm::HexagonII::PredicatedNewMask, and llvm::HexagonII::PredicatedNewPos.
bool HexagonInstrInfo::isPredicatedTrue | ( | const MachineInstr & | MI | ) | const |
Definition at line 2523 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::PredicatedFalseMask, and llvm::HexagonII::PredicatedFalsePos.
Referenced by getInvertedPredicatedOpcode(), getPredicateSense(), and predOpcodeHasNot().
Definition at line 2529 of file HexagonInstrInfo.cpp.
References assert(), F, llvm::get(), Opcode, llvm::HexagonII::PredicatedFalseMask, llvm::HexagonII::PredicatedFalsePos, llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.
Definition at line 2542 of file HexagonInstrInfo.cpp.
References F, llvm::get(), Opcode, llvm::HexagonII::PredicateLateMask, and llvm::HexagonII::PredicateLatePos.
Definition at line 2547 of file HexagonInstrInfo.cpp.
References assert(), F, llvm::get(), isBranch(), isNewValue(), isPredicatedNew(), Opcode, llvm::HexagonII::TakenMask, and llvm::HexagonII::TakenPos.
Referenced by reversePrediction().
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Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion.
The probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 832 of file HexagonInstrInfo.cpp.
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Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 819 of file HexagonInstrInfo.cpp.
References MBB, and nonDbgBBSize().
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Second variant of isProfitableToIfCvt.
This one checks for the case where two basic blocks from true and false path of a if-then-else (diamond) are predicated on mutally exclusive predicates, where the probability of the true path being taken is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 825 of file HexagonInstrInfo.cpp.
References nonDbgBBSize().
bool HexagonInstrInfo::isPureSlot0 | ( | const MachineInstr & | MI | ) | const |
Definition at line 4404 of file HexagonInstrInfo.cpp.
References getUnits(), llvm::HexagonFUnits::isSlot0Only(), and MI.
Referenced by cannotCoexistAsymm().
bool HexagonInstrInfo::isRestrictNoSlot1Store | ( | const MachineInstr & | MI | ) | const |
Definition at line 4416 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::RestrictNoSlot1StoreMask, and llvm::HexagonII::RestrictNoSlot1StorePos.
Referenced by cannotCoexistAsymm().
bool HexagonInstrInfo::isSaveCalleeSavedRegsCall | ( | const MachineInstr & | MI | ) | const |
Definition at line 2554 of file HexagonInstrInfo.cpp.
References MI.
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Test if the given instruction should be considered a scheduling boundary.
This primarily includes labels and terminators.
Definition at line 1792 of file HexagonInstrInfo.cpp.
References doesNotReturn(), I, MBB, MI, ScheduleInlineAsm, and llvm::MachineBasicBlock::successors().
Referenced by hoistAndMergeSGPRInits(), and isSchedBoundary().
bool HexagonInstrInfo::isSignExtendingLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 2561 of file HexagonInstrInfo.cpp.
References MI.
bool HexagonInstrInfo::isSolo | ( | const MachineInstr & | MI | ) | const |
Definition at line 2639 of file HexagonInstrInfo.cpp.
References F, MI, llvm::HexagonII::SoloMask, and llvm::HexagonII::SoloPos.
bool HexagonInstrInfo::isSpillPredRegOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 2644 of file HexagonInstrInfo.cpp.
References MI.
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If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.
If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.
Definition at line 337 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and MI.
Referenced by llvm::SIFrameLowering::processFunctionBeforeFrameFinalized().
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Definition at line 2654 of file HexagonInstrInfo.cpp.
References MI.
Referenced by llvm::DwarfDebug::beginInstruction(), llvm::findSplitPointForStackProtector(), getBBAddrMapMetadata(), isLibCallInTailPosition(), and isPredicable().
bool HexagonInstrInfo::isTC1 | ( | const MachineInstr & | MI | ) | const |
Definition at line 2665 of file HexagonInstrInfo.cpp.
References llvm::is_TC1(), and MI.
Referenced by isComplex().
bool HexagonInstrInfo::isTC2 | ( | const MachineInstr & | MI | ) | const |
Definition at line 2670 of file HexagonInstrInfo.cpp.
References llvm::is_TC2(), and MI.
bool HexagonInstrInfo::isTC2Early | ( | const MachineInstr & | MI | ) | const |
Definition at line 2675 of file HexagonInstrInfo.cpp.
References llvm::is_TC2early(), and MI.
Referenced by isComplex().
bool HexagonInstrInfo::isTC4x | ( | const MachineInstr & | MI | ) | const |
Definition at line 2680 of file HexagonInstrInfo.cpp.
References llvm::is_TC4x(), and MI.
bool HexagonInstrInfo::isToBeScheduledASAP | ( | const MachineInstr & | MI1, |
const MachineInstr & | MI2 | ||
) | const |
Definition at line 2686 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isReg(), mayBeCurLoad(), mayBeNewStore(), and N.
Referenced by llvm::HexagonSubtarget::adjustSchedDependency().
Definition at line 2710 of file HexagonInstrInfo.cpp.
References llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm_unreachable, llvm::Offset, llvm::MVT::SimpleTy, and Size.
Referenced by llvm::HexagonTargetLowering::getPostIndexedAddressParts(), and llvm::HexagonDAGToDAGISel::SelectIndexedStore().
bool HexagonInstrInfo::isValidOffset | ( | unsigned | Opcode, |
int | Offset, | ||
const TargetRegisterInfo * | TRI, | ||
bool | Extend = true |
||
) | const |
Definition at line 2747 of file HexagonInstrInfo.cpp.
References assert(), llvm::dbgs(), getName(), Hexagon_ADDI_OFFSET_MAX, Hexagon_ADDI_OFFSET_MIN, Hexagon_MEMB_OFFSET_MAX, Hexagon_MEMB_OFFSET_MIN, Hexagon_MEMD_OFFSET_MAX, Hexagon_MEMD_OFFSET_MIN, Hexagon_MEMH_OFFSET_MAX, Hexagon_MEMH_OFFSET_MIN, Hexagon_MEMW_OFFSET_MAX, Hexagon_MEMW_OFFSET_MIN, llvm::isPowerOf2_32(), llvm_unreachable, llvm::Log2_32(), llvm::Offset, Opcode, and TRI.
bool HexagonInstrInfo::isVecAcc | ( | const MachineInstr & | MI | ) | const |
Definition at line 2929 of file HexagonInstrInfo.cpp.
References isAccumulator(), isHVXVec(), and MI.
Referenced by isVecUsableNextPacket().
bool HexagonInstrInfo::isVecALU | ( | const MachineInstr & | MI | ) | const |
Definition at line 2933 of file HexagonInstrInfo.cpp.
References F, llvm::get(), MI, llvm::HexagonII::TypeCVI_VA, llvm::HexagonII::TypeCVI_VA_DV, llvm::HexagonII::TypeMask, and llvm::HexagonII::TypePos.
Referenced by isVecUsableNextPacket().
bool HexagonInstrInfo::isVecUsableNextPacket | ( | const MachineInstr & | ProdMI, |
const MachineInstr & | ConsMI | ||
) | const |
Definition at line 2941 of file HexagonInstrInfo.cpp.
References EnableACCForwarding, EnableALUForwarding, isLateSourceInstr(), isVecAcc(), isVecALU(), and mayBeNewStore().
Referenced by addLatencyToSchedule(), and producesStall().
bool HexagonInstrInfo::isZeroExtendingLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 2955 of file HexagonInstrInfo.cpp.
References MI.
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override |
Load the specified register of the given register class from the specified stack frame index.
The load instruction is to be added to the given machine basic block before the specified machine instruction.
Definition at line 1005 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), I, llvm_unreachable, MBB, and llvm::MachineMemOperand::MOLoad.
Referenced by emitBuildPairF64Pseudo(), llvm::MipsSEFrameLowering::emitEpilogue(), insertCSRRestores(), llvm::SystemZELFFrameLowering::restoreCalleeSavedRegisters(), llvm::SystemZXPLINKFrameLowering::restoreCalleeSavedRegisters(), llvm::CSKYFrameLowering::restoreCalleeSavedRegisters(), llvm::PPCFrameLowering::restoreCalleeSavedRegisters(), llvm::RISCVFrameLowering::restoreCalleeSavedRegisters(), and llvm::XCoreFrameLowering::restoreCalleeSavedRegisters().
bool HexagonInstrInfo::mayBeCurLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 3147 of file HexagonInstrInfo.cpp.
References F, llvm::HexagonSubtarget::hasV60Ops(), llvm::HexagonII::mayCVLoadMask, llvm::HexagonII::mayCVLoadPos, and MI.
Referenced by llvm::HexagonHazardRecognizer::EmitInstruction(), and isToBeScheduledASAP().
bool HexagonInstrInfo::mayBeNewStore | ( | const MachineInstr & | MI | ) | const |
Definition at line 3154 of file HexagonInstrInfo.cpp.
References F, llvm::HexagonII::mayNVStoreMask, llvm::HexagonII::mayNVStorePos, MI, and llvm::HexagonSubtarget::useNewValueStores().
Referenced by canExecuteInBundle(), llvm::HexagonHazardRecognizer::EmitInstruction(), isToBeScheduledASAP(), and isVecUsableNextPacket().
unsigned HexagonInstrInfo::nonDbgBBSize | ( | const MachineBasicBlock * | BB | ) | const |
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Class information, if available.
Definition at line 4599 of file HexagonInstrInfo.cpp.
References llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), and nonDbgMICount().
Referenced by isProfitableToIfCvt().
unsigned HexagonInstrInfo::nonDbgBundleSize | ( | MachineBasicBlock::const_iterator | BundleHead | ) | const |
Definition at line 4603 of file HexagonInstrInfo.cpp.
References assert(), llvm::getBundleEnd(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getInstrIterator(), and nonDbgMICount().
bool HexagonInstrInfo::predCanBeUsedAsDotNew | ( | const MachineInstr & | MI, |
Register | PredReg | ||
) | const |
Definition at line 3200 of file HexagonInstrInfo.cpp.
References MI.
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override |
Convert the instruction into a predicated instruction.
It returns true if the operation was successful.
Definition at line 1671 of file HexagonInstrInfo.cpp.
References assert(), B, llvm::BuildMI(), Cond, llvm::dbgs(), DL, llvm::Pass::dump(), llvm::get(), getCondOpcode(), getPredReg(), isEndLoopN(), isNewValueJump(), isPredicable(), LLVM_DEBUG, MI, MRI, and predOpcodeHasNot().
Definition at line 3235 of file HexagonInstrInfo.cpp.
References Opcode.
Referenced by analyzeBranch().
bool HexagonInstrInfo::predOpcodeHasNot | ( | ArrayRef< MachineOperand > | Cond | ) | const |
Definition at line 3246 of file HexagonInstrInfo.cpp.
References Cond, isPredicated(), and isPredicatedTrue().
Referenced by PredicateInstruction().
bool HexagonInstrInfo::producesStall | ( | const MachineInstr & | MI, |
MachineBasicBlock::const_instr_iterator | MII | ||
) | const |
Definition at line 3180 of file HexagonInstrInfo.cpp.
References isHVXVec(), MI, and producesStall().
bool HexagonInstrInfo::producesStall | ( | const MachineInstr & | ProdMI, |
const MachineInstr & | ConsMI | ||
) | const |
Definition at line 3162 of file HexagonInstrInfo.cpp.
References isDependent(), isHVXVec(), and isVecUsableNextPacket().
Referenced by producesStall().
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override |
Remove the branching code at the end of the specific MBB.
This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions that were removed.
Definition at line 605 of file HexagonInstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::back(), llvm::MachineBasicBlock::begin(), llvm::dbgs(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), I, LLVM_DEBUG, llvm_unreachable, MBB, and llvm::printMBBReference().
Referenced by FixTail(), insertBranch(), llvm::PeelSingleBlockLoop(), and llvm::MachineBasicBlock::updateTerminator().
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override |
Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.
Definition at line 1633 of file HexagonInstrInfo.cpp.
References assert(), Cond, llvm::get(), getInvertedPredicatedOpcode(), isBranch(), isEndLoopN(), and isImm().
Referenced by FixTail(), insertBranch(), and llvm::MachineBasicBlock::updateTerminator().
Definition at line 4676 of file HexagonInstrInfo.cpp.
References assert(), isPredictedTaken(), and Opcode.
Referenced by invertAndChangeJumpTarget().
bool HexagonInstrInfo::reversePredSense | ( | MachineInstr & | MI | ) | const |
Definition at line 4669 of file HexagonInstrInfo.cpp.
References llvm::dbgs(), llvm::Pass::dump(), llvm::get(), getInvertedPredicatedOpcode(), LLVM_DEBUG, and MI.
void HexagonInstrInfo::setBundleNoShuf | ( | MachineBasicBlock::instr_iterator | MIB | ) | const |
Definition at line 4692 of file HexagonInstrInfo.cpp.
References assert(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::getImm(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::setImm().
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Definition at line 186 of file HexagonInstrInfo.cpp.
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Store the specified register of the given register class to the specified stack frame index.
The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.
Definition at line 957 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), I, llvm_unreachable, MBB, and llvm::MachineMemOperand::MOStore.
Referenced by llvm::MipsSEFrameLowering::emitPrologue(), emitSplitF64Pseudo(), insertCSRSaves(), llvm::SystemZELFFrameLowering::spillCalleeSavedRegisters(), llvm::SystemZXPLINKFrameLowering::spillCalleeSavedRegisters(), llvm::CSKYFrameLowering::spillCalleeSavedRegisters(), llvm::LoongArchFrameLowering::spillCalleeSavedRegisters(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), llvm::PPCFrameLowering::spillCalleeSavedRegisters(), llvm::RISCVFrameLowering::spillCalleeSavedRegisters(), and llvm::XCoreFrameLowering::spillCalleeSavedRegisters().
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Returns true if the first specified predicate subsumes the second, e.g.
GE subsumes GT.
Definition at line 1723 of file HexagonInstrInfo.cpp.
void HexagonInstrInfo::translateInstrsForDup | ( | MachineBasicBlock::instr_iterator | MII, |
bool | ToBigInstrs | ||
) | const |
Definition at line 4450 of file HexagonInstrInfo.cpp.
References changeDuplexOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineBasicBlock::instr_end(), and MBB.
void HexagonInstrInfo::translateInstrsForDup | ( | MachineFunction & | MF, |
bool | ToBigInstrs = true |
||
) | const |
Definition at line 4440 of file HexagonInstrInfo.cpp.
References changeDuplexOpcode(), and End.
bool HexagonInstrInfo::validateBranchCond | ( | const ArrayRef< MachineOperand > & | Cond | ) | const |
Definition at line 4687 of file HexagonInstrInfo.cpp.
References Cond.
Referenced by insertBranch().