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HexagonVLIWPacketizer.cpp
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1 //===- HexagonPacketizer.cpp - VLIW packetizer ----------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements a simple VLIW packetizer using DFA. The packetizer works on
10 // machine basic blocks. For each instruction I in BB, the packetizer consults
11 // the DFA to see if machine resources are available to execute I. If so, the
12 // packetizer checks if I depends on any instruction J in the current packet.
13 // If no dependency is found, I is added to current packet and machine resource
14 // is marked as taken. If any dependency is found, a target API call is made to
15 // prune the dependence.
16 //
17 //===----------------------------------------------------------------------===//
18 
19 #include "HexagonVLIWPacketizer.h"
20 #include "Hexagon.h"
21 #include "HexagonInstrInfo.h"
22 #include "HexagonRegisterInfo.h"
23 #include "HexagonSubtarget.h"
24 #include "llvm/ADT/BitVector.h"
25 #include "llvm/ADT/DenseSet.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/StringExtras.h"
42 #include "llvm/IR/DebugLoc.h"
43 #include "llvm/MC/MCInstrDesc.h"
44 #include "llvm/Pass.h"
46 #include "llvm/Support/Debug.h"
49 #include <cassert>
50 #include <cstdint>
51 #include <iterator>
52 
53 using namespace llvm;
54 
55 #define DEBUG_TYPE "packets"
56 
57 static cl::opt<bool> DisablePacketizer("disable-packetizer", cl::Hidden,
58  cl::ZeroOrMore, cl::init(false),
59  cl::desc("Disable Hexagon packetizer pass"));
60 
61 static cl::opt<bool> Slot1Store("slot1-store-slot0-load", cl::Hidden,
62  cl::ZeroOrMore, cl::init(true),
63  cl::desc("Allow slot1 store and slot0 load"));
64 
65 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
67  cl::desc("Allow non-solo packetization of volatile memory references"));
68 
69 static cl::opt<bool> EnableGenAllInsnClass("enable-gen-insn", cl::init(false),
70  cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"));
71 
72 static cl::opt<bool> DisableVecDblNVStores("disable-vecdbl-nv-stores",
74  cl::desc("Disable vector double new-value-stores"));
75 
77 
78 namespace llvm {
79 
82 
83 } // end namespace llvm
84 
85 namespace {
86 
87  class HexagonPacketizer : public MachineFunctionPass {
88  public:
89  static char ID;
90 
91  HexagonPacketizer(bool Min = false)
92  : MachineFunctionPass(ID), Minimal(Min) {}
93 
94  void getAnalysisUsage(AnalysisUsage &AU) const override {
95  AU.setPreservesCFG();
103  }
104 
105  StringRef getPassName() const override { return "Hexagon Packetizer"; }
106  bool runOnMachineFunction(MachineFunction &Fn) override;
107 
108  MachineFunctionProperties getRequiredProperties() const override {
111  }
112 
113  private:
114  const HexagonInstrInfo *HII;
115  const HexagonRegisterInfo *HRI;
116  const bool Minimal;
117  };
118 
119 } // end anonymous namespace
120 
121 char HexagonPacketizer::ID = 0;
122 
123 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "hexagon-packetizer",
124  "Hexagon Packetizer", false, false)
129 INITIALIZE_PASS_END(HexagonPacketizer, "hexagon-packetizer",
130  "Hexagon Packetizer", false, false)
131 
133  MachineLoopInfo &MLI, AliasAnalysis *AA,
134  const MachineBranchProbabilityInfo *MBPI, bool Minimal)
135  : VLIWPacketizerList(MF, MLI, AA), MBPI(MBPI), MLI(&MLI),
136  Minimal(Minimal) {
137  HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
138  HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
139 
140  addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
141  addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
142  addMutation(std::make_unique<HexagonSubtarget::BankConflictMutation>());
143 }
144 
145 // Check if FirstI modifies a register that SecondI reads.
146 static bool hasWriteToReadDep(const MachineInstr &FirstI,
147  const MachineInstr &SecondI,
148  const TargetRegisterInfo *TRI) {
149  for (auto &MO : FirstI.operands()) {
150  if (!MO.isReg() || !MO.isDef())
151  continue;
152  Register R = MO.getReg();
153  if (SecondI.readsRegister(R, TRI))
154  return true;
155  }
156  return false;
157 }
158 
159 
161  MachineBasicBlock::iterator BundleIt, bool Before) {
163  if (Before)
164  InsertPt = BundleIt.getInstrIterator();
165  else
166  InsertPt = std::next(BundleIt).getInstrIterator();
167 
168  MachineBasicBlock &B = *MI.getParent();
169  // The instruction should at least be bundled with the preceding instruction
170  // (there will always be one, i.e. BUNDLE, if nothing else).
172  if (MI.isBundledWithSucc()) {
175  } else {
176  // If it's not bundled with the successor (i.e. it is the last one
177  // in the bundle), then we can simply unbundle it from the predecessor,
178  // which will take care of updating the predecessor's flag.
179  MI.unbundleFromPred();
180  }
181  B.splice(InsertPt, &B, MI.getIterator());
182 
183  // Get the size of the bundle without asserting.
186  unsigned Size = 0;
187  for (++I; I != E && I->isBundledWithPred(); ++I)
188  ++Size;
189 
190  // If there are still two or more instructions, then there is nothing
191  // else to be done.
192  if (Size > 1)
193  return BundleIt;
194 
195  // Otherwise, extract the single instruction out and delete the bundle.
196  MachineBasicBlock::iterator NextIt = std::next(BundleIt);
197  MachineInstr &SingleI = *BundleIt->getNextNode();
198  SingleI.unbundleFromPred();
199  assert(!SingleI.isBundledWithSucc());
200  BundleIt->eraseFromParent();
201  return NextIt;
202 }
203 
204 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
205  auto &HST = MF.getSubtarget<HexagonSubtarget>();
206  HII = HST.getInstrInfo();
207  HRI = HST.getRegisterInfo();
208  auto &MLI = getAnalysis<MachineLoopInfo>();
209  auto *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
210  auto *MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
211 
213  HII->genAllInsnTimingClasses(MF);
214 
215  // Instantiate the packetizer.
216  bool MinOnly = Minimal || DisablePacketizer || !HST.usePackets() ||
217  skipFunction(MF.getFunction());
218  HexagonPacketizerList Packetizer(MF, MLI, AA, MBPI, MinOnly);
219 
220  // DFA state table should not be empty.
221  assert(Packetizer.getResourceTracker() && "Empty DFA table!");
222 
223  // Loop over all basic blocks and remove KILL pseudo-instructions
224  // These instructions confuse the dependence analysis. Consider:
225  // D0 = ... (Insn 0)
226  // R0 = KILL R0, D0 (Insn 1)
227  // R0 = ... (Insn 2)
228  // Here, Insn 1 will result in the dependence graph not emitting an output
229  // dependence between Insn 0 and Insn 2. This can lead to incorrect
230  // packetization
231  for (MachineBasicBlock &MB : MF) {
232  auto End = MB.end();
233  auto MI = MB.begin();
234  while (MI != End) {
235  auto NextI = std::next(MI);
236  if (MI->isKill()) {
237  MB.erase(MI);
238  End = MB.end();
239  }
240  MI = NextI;
241  }
242  }
243 
244  // Loop over all of the basic blocks.
245  for (auto &MB : MF) {
246  auto Begin = MB.begin(), End = MB.end();
247  while (Begin != End) {
248  // Find the first non-boundary starting from the end of the last
249  // scheduling region.
250  MachineBasicBlock::iterator RB = Begin;
251  while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF))
252  ++RB;
253  // Find the first boundary starting from the beginning of the new
254  // region.
256  while (RE != End && !HII->isSchedulingBoundary(*RE, &MB, MF))
257  ++RE;
258  // Add the scheduling boundary if it's not block end.
259  if (RE != End)
260  ++RE;
261  // If RB == End, then RE == End.
262  if (RB != End)
263  Packetizer.PacketizeMIs(&MB, RB, RE);
264 
265  Begin = RE;
266  }
267  }
268 
269  Packetizer.unpacketizeSoloInstrs(MF);
270  return true;
271 }
272 
273 // Reserve resources for a constant extender. Trigger an assertion if the
274 // reservation fails.
276  if (!tryAllocateResourcesForConstExt(true))
277  llvm_unreachable("Resources not available");
278 }
279 
281  return tryAllocateResourcesForConstExt(false);
282 }
283 
284 // Allocate resources (i.e. 4 bytes) for constant extender. If succeeded,
285 // return true, otherwise, return false.
287  auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
288  bool Avail = ResourceTracker->canReserveResources(*ExtMI);
289  if (Reserve && Avail)
290  ResourceTracker->reserveResources(*ExtMI);
291  MF.DeleteMachineInstr(ExtMI);
292  return Avail;
293 }
294 
296  SDep::Kind DepType, unsigned DepReg) {
297  // Check for LR dependence.
298  if (DepReg == HRI->getRARegister())
299  return true;
300 
301  if (HII->isDeallocRet(MI))
302  if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister())
303  return true;
304 
305  // Call-like instructions can be packetized with preceding instructions
306  // that define registers implicitly used or modified by the call. Explicit
307  // uses are still prohibited, as in the case of indirect calls:
308  // r0 = ...
309  // J2_jumpr r0
310  if (DepType == SDep::Data) {
311  for (const MachineOperand MO : MI.operands())
312  if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit())
313  return true;
314  }
315 
316  return false;
317 }
318 
319 static bool isRegDependence(const SDep::Kind DepType) {
320  return DepType == SDep::Data || DepType == SDep::Anti ||
321  DepType == SDep::Output;
322 }
323 
324 static bool isDirectJump(const MachineInstr &MI) {
325  return MI.getOpcode() == Hexagon::J2_jump;
326 }
327 
328 static bool isSchedBarrier(const MachineInstr &MI) {
329  switch (MI.getOpcode()) {
330  case Hexagon::Y2_barrier:
331  return true;
332  }
333  return false;
334 }
335 
336 static bool isControlFlow(const MachineInstr &MI) {
337  return MI.getDesc().isTerminator() || MI.getDesc().isCall();
338 }
339 
340 /// Returns true if the instruction modifies a callee-saved register.
342  const TargetRegisterInfo *TRI) {
343  const MachineFunction &MF = *MI.getParent()->getParent();
344  for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
345  if (MI.modifiesRegister(*CSR, TRI))
346  return true;
347  return false;
348 }
349 
350 // Returns true if an instruction can be promoted to .new predicate or
351 // new-value store.
353  const TargetRegisterClass *NewRC) {
354  // Vector stores can be predicated, and can be new-value stores, but
355  // they cannot be predicated on a .new predicate value.
356  if (NewRC == &Hexagon::PredRegsRegClass) {
357  if (HII->isHVXVec(MI) && MI.mayStore())
358  return false;
359  return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0;
360  }
361  // If the class is not PredRegs, it could only apply to new-value stores.
362  return HII->mayBeNewStore(MI);
363 }
364 
365 // Promote an instructiont to its .cur form.
366 // At this time, we have already made a call to canPromoteToDotCur and made
367 // sure that it can *indeed* be promoted.
370  const TargetRegisterClass* RC) {
371  assert(DepType == SDep::Data);
372  int CurOpcode = HII->getDotCurOp(MI);
373  MI.setDesc(HII->get(CurOpcode));
374  return true;
375 }
376 
378  MachineInstr *MI = nullptr;
379  for (auto BI : CurrentPacketMIs) {
380  LLVM_DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););
381  if (HII->isDotCurInst(*BI)) {
382  MI = BI;
383  continue;
384  }
385  if (MI) {
386  for (auto &MO : BI->operands())
387  if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
388  return;
389  }
390  }
391  if (!MI)
392  return;
393  // We did not find a use of the CUR, so de-cur it.
394  MI->setDesc(HII->get(HII->getNonDotCurOp(*MI)));
395  LLVM_DEBUG(dbgs() << "Demoted CUR "; MI->dump(););
396 }
397 
398 // Check to see if an instruction can be dot cur.
400  const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
401  const TargetRegisterClass *RC) {
402  if (!HII->isHVXVec(MI))
403  return false;
404  if (!HII->isHVXVec(*MII))
405  return false;
406 
407  // Already a dot new instruction.
408  if (HII->isDotCurInst(MI) && !HII->mayBeCurLoad(MI))
409  return false;
410 
411  if (!HII->mayBeCurLoad(MI))
412  return false;
413 
414  // The "cur value" cannot come from inline asm.
415  if (PacketSU->getInstr()->isInlineAsm())
416  return false;
417 
418  // Make sure candidate instruction uses cur.
419  LLVM_DEBUG(dbgs() << "Can we DOT Cur Vector MI\n"; MI.dump();
420  dbgs() << "in packet\n";);
421  MachineInstr &MJ = *MII;
422  LLVM_DEBUG({
423  dbgs() << "Checking CUR against ";
424  MJ.dump();
425  });
426  Register DestReg = MI.getOperand(0).getReg();
427  bool FoundMatch = false;
428  for (auto &MO : MJ.operands())
429  if (MO.isReg() && MO.getReg() == DestReg)
430  FoundMatch = true;
431  if (!FoundMatch)
432  return false;
433 
434  // Check for existing uses of a vector register within the packet which
435  // would be affected by converting a vector load into .cur formt.
436  for (auto BI : CurrentPacketMIs) {
437  LLVM_DEBUG(dbgs() << "packet has "; BI->dump(););
438  if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
439  return false;
440  }
441 
442  LLVM_DEBUG(dbgs() << "Can Dot CUR MI\n"; MI.dump(););
443  // We can convert the opcode into a .cur.
444  return true;
445 }
446 
447 // Promote an instruction to its .new form. At this time, we have already
448 // made a call to canPromoteToDotNew and made sure that it can *indeed* be
449 // promoted.
452  const TargetRegisterClass* RC) {
453  assert(DepType == SDep::Data);
454  int NewOpcode;
455  if (RC == &Hexagon::PredRegsRegClass)
456  NewOpcode = HII->getDotNewPredOp(MI, MBPI);
457  else
458  NewOpcode = HII->getDotNewOp(MI);
459  MI.setDesc(HII->get(NewOpcode));
460  return true;
461 }
462 
464  int NewOpcode = HII->getDotOldOp(MI);
465  MI.setDesc(HII->get(NewOpcode));
466  return true;
467 }
468 
470  unsigned Opc = MI.getOpcode();
471  switch (Opc) {
472  case Hexagon::S2_storerd_io:
473  case Hexagon::S2_storeri_io:
474  case Hexagon::S2_storerh_io:
475  case Hexagon::S2_storerb_io:
476  break;
477  default:
478  llvm_unreachable("Unexpected instruction");
479  }
480  unsigned FrameSize = MF.getFrameInfo().getStackSize();
481  MachineOperand &Off = MI.getOperand(1);
482  int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE);
483  if (HII->isValidOffset(Opc, NewOff, HRI)) {
484  Off.setImm(NewOff);
485  return true;
486  }
487  return false;
488 }
489 
491  unsigned Opc = MI.getOpcode();
492  switch (Opc) {
493  case Hexagon::S2_storerd_io:
494  case Hexagon::S2_storeri_io:
495  case Hexagon::S2_storerh_io:
496  case Hexagon::S2_storerb_io:
497  break;
498  default:
499  llvm_unreachable("Unexpected instruction");
500  }
501  unsigned FrameSize = MF.getFrameInfo().getStackSize();
502  MachineOperand &Off = MI.getOperand(1);
503  Off.setImm(Off.getImm() + FrameSize + HEXAGON_LRFP_SIZE);
504 }
505 
506 /// Return true if we can update the offset in MI so that MI and MJ
507 /// can be packetized together.
509  assert(SUI->getInstr() && SUJ->getInstr());
510  MachineInstr &MI = *SUI->getInstr();
511  MachineInstr &MJ = *SUJ->getInstr();
512 
513  unsigned BPI, OPI;
514  if (!HII->getBaseAndOffsetPosition(MI, BPI, OPI))
515  return false;
516  unsigned BPJ, OPJ;
517  if (!HII->getBaseAndOffsetPosition(MJ, BPJ, OPJ))
518  return false;
519  Register Reg = MI.getOperand(BPI).getReg();
520  if (Reg != MJ.getOperand(BPJ).getReg())
521  return false;
522  // Make sure that the dependences do not restrict adding MI to the packet.
523  // That is, ignore anti dependences, and make sure the only data dependence
524  // involves the specific register.
525  for (const auto &PI : SUI->Preds)
526  if (PI.getKind() != SDep::Anti &&
527  (PI.getKind() != SDep::Data || PI.getReg() != Reg))
528  return false;
529  int Incr;
530  if (!HII->getIncrementValue(MJ, Incr))
531  return false;
532 
533  int64_t Offset = MI.getOperand(OPI).getImm();
534  if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI))
535  return false;
536 
537  MI.getOperand(OPI).setImm(Offset + Incr);
538  ChangedOffset = Offset;
539  return true;
540 }
541 
542 /// Undo the changed offset. This is needed if the instruction cannot be
543 /// added to the current packet due to a different instruction.
545  unsigned BP, OP;
546  if (!HII->getBaseAndOffsetPosition(MI, BP, OP))
547  llvm_unreachable("Unable to find base and offset operands.");
548  MI.getOperand(OP).setImm(ChangedOffset);
549 }
550 
555 };
556 
557 /// Returns true if an instruction is predicated on p0 and false if it's
558 /// predicated on !p0.
560  const HexagonInstrInfo *HII) {
561  if (!HII->isPredicated(MI))
562  return PK_Unknown;
563  if (HII->isPredicatedTrue(MI))
564  return PK_True;
565  return PK_False;
566 }
567 
569  const HexagonInstrInfo *HII) {
570  assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
571 #ifndef NDEBUG
572  // Post Increment means duplicates. Use dense map to find duplicates in the
573  // list. Caution: Densemap initializes with the minimum of 64 buckets,
574  // whereas there are at most 5 operands in the post increment.
575  DenseSet<unsigned> DefRegsSet;
576  for (auto &MO : MI.operands())
577  if (MO.isReg() && MO.isDef())
578  DefRegsSet.insert(MO.getReg());
579 
580  for (auto &MO : MI.operands())
581  if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
582  return MO;
583 #else
584  if (MI.mayLoad()) {
585  const MachineOperand &Op1 = MI.getOperand(1);
586  // The 2nd operand is always the post increment operand in load.
587  assert(Op1.isReg() && "Post increment operand has be to a register.");
588  return Op1;
589  }
590  if (MI.getDesc().mayStore()) {
591  const MachineOperand &Op0 = MI.getOperand(0);
592  // The 1st operand is always the post increment operand in store.
593  assert(Op0.isReg() && "Post increment operand has be to a register.");
594  return Op0;
595  }
596 #endif
597  // we should never come here.
598  llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
599 }
600 
601 // Get the value being stored.
603  // value being stored is always the last operand.
604  return MI.getOperand(MI.getNumOperands()-1);
605 }
606 
607 static bool isLoadAbsSet(const MachineInstr &MI) {
608  unsigned Opc = MI.getOpcode();
609  switch (Opc) {
610  case Hexagon::L4_loadrd_ap:
611  case Hexagon::L4_loadrb_ap:
612  case Hexagon::L4_loadrh_ap:
613  case Hexagon::L4_loadrub_ap:
614  case Hexagon::L4_loadruh_ap:
615  case Hexagon::L4_loadri_ap:
616  return true;
617  }
618  return false;
619 }
620 
622  assert(isLoadAbsSet(MI));
623  return MI.getOperand(1);
624 }
625 
626 // Can be new value store?
627 // Following restrictions are to be respected in convert a store into
628 // a new value store.
629 // 1. If an instruction uses auto-increment, its address register cannot
630 // be a new-value register. Arch Spec 5.4.2.1
631 // 2. If an instruction uses absolute-set addressing mode, its address
632 // register cannot be a new-value register. Arch Spec 5.4.2.1.
633 // 3. If an instruction produces a 64-bit result, its registers cannot be used
634 // as new-value registers. Arch Spec 5.4.2.2.
635 // 4. If the instruction that sets the new-value register is conditional, then
636 // the instruction that uses the new-value register must also be conditional,
637 // and both must always have their predicates evaluate identically.
638 // Arch Spec 5.4.2.3.
639 // 5. There is an implied restriction that a packet cannot have another store,
640 // if there is a new value store in the packet. Corollary: if there is
641 // already a store in a packet, there can not be a new value store.
642 // Arch Spec: 3.4.4.2
644  const MachineInstr &PacketMI, unsigned DepReg) {
645  // Make sure we are looking at the store, that can be promoted.
646  if (!HII->mayBeNewStore(MI))
647  return false;
648 
649  // Make sure there is dependency and can be new value'd.
650  const MachineOperand &Val = getStoreValueOperand(MI);
651  if (Val.isReg() && Val.getReg() != DepReg)
652  return false;
653 
654  const MCInstrDesc& MCID = PacketMI.getDesc();
655 
656  // First operand is always the result.
657  const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
658  // Double regs can not feed into new value store: PRM section: 5.4.2.2.
659  if (PacketRC == &Hexagon::DoubleRegsRegClass)
660  return false;
661 
662  // New-value stores are of class NV (slot 0), dual stores require class ST
663  // in slot 0 (PRM 5.5).
664  for (auto I : CurrentPacketMIs) {
665  SUnit *PacketSU = MIToSUnit.find(I)->second;
666  if (PacketSU->getInstr()->mayStore())
667  return false;
668  }
669 
670  // Make sure it's NOT the post increment register that we are going to
671  // new value.
672  if (HII->isPostIncrement(MI) &&
673  getPostIncrementOperand(MI, HII).getReg() == DepReg) {
674  return false;
675  }
676 
677  if (HII->isPostIncrement(PacketMI) && PacketMI.mayLoad() &&
678  getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
679  // If source is post_inc, or absolute-set addressing, it can not feed
680  // into new value store
681  // r3 = memw(r2++#4)
682  // memw(r30 + #-1404) = r2.new -> can not be new value store
683  // arch spec section: 5.4.2.1.
684  return false;
685  }
686 
687  if (isLoadAbsSet(PacketMI) && getAbsSetOperand(PacketMI).getReg() == DepReg)
688  return false;
689 
690  // If the source that feeds the store is predicated, new value store must
691  // also be predicated.
692  if (HII->isPredicated(PacketMI)) {
693  if (!HII->isPredicated(MI))
694  return false;
695 
696  // Check to make sure that they both will have their predicates
697  // evaluate identically.
698  unsigned predRegNumSrc = 0;
699  unsigned predRegNumDst = 0;
700  const TargetRegisterClass* predRegClass = nullptr;
701 
702  // Get predicate register used in the source instruction.
703  for (auto &MO : PacketMI.operands()) {
704  if (!MO.isReg())
705  continue;
706  predRegNumSrc = MO.getReg();
707  predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);
708  if (predRegClass == &Hexagon::PredRegsRegClass)
709  break;
710  }
711  assert((predRegClass == &Hexagon::PredRegsRegClass) &&
712  "predicate register not found in a predicated PacketMI instruction");
713 
714  // Get predicate register used in new-value store instruction.
715  for (auto &MO : MI.operands()) {
716  if (!MO.isReg())
717  continue;
718  predRegNumDst = MO.getReg();
719  predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst);
720  if (predRegClass == &Hexagon::PredRegsRegClass)
721  break;
722  }
723  assert((predRegClass == &Hexagon::PredRegsRegClass) &&
724  "predicate register not found in a predicated MI instruction");
725 
726  // New-value register producer and user (store) need to satisfy these
727  // constraints:
728  // 1) Both instructions should be predicated on the same register.
729  // 2) If producer of the new-value register is .new predicated then store
730  // should also be .new predicated and if producer is not .new predicated
731  // then store should not be .new predicated.
732  // 3) Both new-value register producer and user should have same predicate
733  // sense, i.e, either both should be negated or both should be non-negated.
734  if (predRegNumDst != predRegNumSrc ||
735  HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
736  getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII))
737  return false;
738  }
739 
740  // Make sure that other than the new-value register no other store instruction
741  // register has been modified in the same packet. Predicate registers can be
742  // modified by they should not be modified between the producer and the store
743  // instruction as it will make them both conditional on different values.
744  // We already know this to be true for all the instructions before and
745  // including PacketMI. Howerver, we need to perform the check for the
746  // remaining instructions in the packet.
747 
748  unsigned StartCheck = 0;
749 
750  for (auto I : CurrentPacketMIs) {
751  SUnit *TempSU = MIToSUnit.find(I)->second;
752  MachineInstr &TempMI = *TempSU->getInstr();
753 
754  // Following condition is true for all the instructions until PacketMI is
755  // reached (StartCheck is set to 0 before the for loop).
756  // StartCheck flag is 1 for all the instructions after PacketMI.
757  if (&TempMI != &PacketMI && !StartCheck) // Start processing only after
758  continue; // encountering PacketMI.
759 
760  StartCheck = 1;
761  if (&TempMI == &PacketMI) // We don't want to check PacketMI for dependence.
762  continue;
763 
764  for (auto &MO : MI.operands())
765  if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
766  return false;
767  }
768 
769  // Make sure that for non-POST_INC stores:
770  // 1. The only use of reg is DepReg and no other registers.
771  // This handles base+index registers.
772  // The following store can not be dot new.
773  // Eg. r0 = add(r0, #3)
774  // memw(r1+r0<<#2) = r0
775  if (!HII->isPostIncrement(MI)) {
776  for (unsigned opNum = 0; opNum < MI.getNumOperands()-1; opNum++) {
777  const MachineOperand &MO = MI.getOperand(opNum);
778  if (MO.isReg() && MO.getReg() == DepReg)
779  return false;
780  }
781  }
782 
783  // If data definition is because of implicit definition of the register,
784  // do not newify the store. Eg.
785  // %r9 = ZXTH %r12, implicit %d6, implicit-def %r12
786  // S2_storerh_io %r8, 2, killed %r12; mem:ST2[%scevgep343]
787  for (auto &MO : PacketMI.operands()) {
788  if (MO.isRegMask() && MO.clobbersPhysReg(DepReg))
789  return false;
790  if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())
791  continue;
792  Register R = MO.getReg();
793  if (R == DepReg || HRI->isSuperRegister(DepReg, R))
794  return false;
795  }
796 
797  // Handle imp-use of super reg case. There is a target independent side
798  // change that should prevent this situation but I am handling it for
799  // just-in-case. For example, we cannot newify R2 in the following case:
800  // %r3 = A2_tfrsi 0;
801  // S2_storeri_io killed %r0, 0, killed %r2, implicit killed %d1;
802  for (auto &MO : MI.operands()) {
803  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
804  return false;
805  }
806 
807  // Can be dot new store.
808  return true;
809 }
810 
811 // Can this MI to promoted to either new value store or new value jump.
813  const SUnit *PacketSU, unsigned DepReg,
815  if (!HII->mayBeNewStore(MI))
816  return false;
817 
818  // Check to see the store can be new value'ed.
819  MachineInstr &PacketMI = *PacketSU->getInstr();
820  if (canPromoteToNewValueStore(MI, PacketMI, DepReg))
821  return true;
822 
823  // Check to see the compare/jump can be new value'ed.
824  // This is done as a pass on its own. Don't need to check it here.
825  return false;
826 }
827 
828 static bool isImplicitDependency(const MachineInstr &I, bool CheckDef,
829  unsigned DepReg) {
830  for (auto &MO : I.operands()) {
831  if (CheckDef && MO.isRegMask() && MO.clobbersPhysReg(DepReg))
832  return true;
833  if (!MO.isReg() || MO.getReg() != DepReg || !MO.isImplicit())
834  continue;
835  if (CheckDef == MO.isDef())
836  return true;
837  }
838  return false;
839 }
840 
841 // Check to see if an instruction can be dot new.
843  const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
844  const TargetRegisterClass* RC) {
845  // Already a dot new instruction.
846  if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI))
847  return false;
848 
849  if (!isNewifiable(MI, RC))
850  return false;
851 
852  const MachineInstr &PI = *PacketSU->getInstr();
853 
854  // The "new value" cannot come from inline asm.
855  if (PI.isInlineAsm())
856  return false;
857 
858  // IMPLICIT_DEFs won't materialize as real instructions, so .new makes no
859  // sense.
860  if (PI.isImplicitDef())
861  return false;
862 
863  // If dependency is trough an implicitly defined register, we should not
864  // newify the use.
865  if (isImplicitDependency(PI, true, DepReg) ||
866  isImplicitDependency(MI, false, DepReg))
867  return false;
868 
869  const MCInstrDesc& MCID = PI.getDesc();
870  const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
871  if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass)
872  return false;
873 
874  // predicate .new
875  if (RC == &Hexagon::PredRegsRegClass)
876  return HII->predCanBeUsedAsDotNew(PI, DepReg);
877 
878  if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
879  return false;
880 
881  // Create a dot new machine instruction to see if resources can be
882  // allocated. If not, bail out now.
883  int NewOpcode = HII->getDotNewOp(MI);
884  const MCInstrDesc &D = HII->get(NewOpcode);
885  MachineInstr *NewMI = MF.CreateMachineInstr(D, DebugLoc());
886  bool ResourcesAvailable = ResourceTracker->canReserveResources(*NewMI);
887  MF.DeleteMachineInstr(NewMI);
888  if (!ResourcesAvailable)
889  return false;
890 
891  // New Value Store only. New Value Jump generated as a separate pass.
892  if (!canPromoteToNewValue(MI, PacketSU, DepReg, MII))
893  return false;
894 
895  return true;
896 }
897 
898 // Go through the packet instructions and search for an anti dependency between
899 // them and DepReg from MI. Consider this case:
900 // Trying to add
901 // a) %r1 = TFRI_cdNotPt %p3, 2
902 // to this packet:
903 // {
904 // b) %p0 = C2_or killed %p3, killed %p0
905 // c) %p3 = C2_tfrrp %r23
906 // d) %r1 = C2_cmovenewit %p3, 4
907 // }
908 // The P3 from a) and d) will be complements after
909 // a)'s P3 is converted to .new form
910 // Anti-dep between c) and b) is irrelevant for this case
912  unsigned DepReg) {
913  SUnit *PacketSUDep = MIToSUnit.find(&MI)->second;
914 
915  for (auto I : CurrentPacketMIs) {
916  // We only care for dependencies to predicated instructions
917  if (!HII->isPredicated(*I))
918  continue;
919 
920  // Scheduling Unit for current insn in the packet
921  SUnit *PacketSU = MIToSUnit.find(I)->second;
922 
923  // Look at dependencies between current members of the packet and
924  // predicate defining instruction MI. Make sure that dependency is
925  // on the exact register we care about.
926  if (PacketSU->isSucc(PacketSUDep)) {
927  for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
928  auto &Dep = PacketSU->Succs[i];
929  if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti &&
930  Dep.getReg() == DepReg)
931  return true;
932  }
933  }
934  }
935 
936  return false;
937 }
938 
939 /// Gets the predicate register of a predicated instruction.
941  const HexagonInstrInfo *QII) {
942  /// We use the following rule: The first predicate register that is a use is
943  /// the predicate register of a predicated instruction.
944  assert(QII->isPredicated(MI) && "Must be predicated instruction");
945 
946  for (auto &Op : MI.operands()) {
947  if (Op.isReg() && Op.getReg() && Op.isUse() &&
948  Hexagon::PredRegsRegClass.contains(Op.getReg()))
949  return Op.getReg();
950  }
951 
952  llvm_unreachable("Unknown instruction operand layout");
953  return 0;
954 }
955 
956 // Given two predicated instructions, this function detects whether
957 // the predicates are complements.
959  MachineInstr &MI2) {
960  // If we don't know the predicate sense of the instructions bail out early, we
961  // need it later.
962  if (getPredicateSense(MI1, HII) == PK_Unknown ||
963  getPredicateSense(MI2, HII) == PK_Unknown)
964  return false;
965 
966  // Scheduling unit for candidate.
967  SUnit *SU = MIToSUnit[&MI1];
968 
969  // One corner case deals with the following scenario:
970  // Trying to add
971  // a) %r24 = A2_tfrt %p0, %r25
972  // to this packet:
973  // {
974  // b) %r25 = A2_tfrf %p0, %r24
975  // c) %p0 = C2_cmpeqi %r26, 1
976  // }
977  //
978  // On general check a) and b) are complements, but presence of c) will
979  // convert a) to .new form, and then it is not a complement.
980  // We attempt to detect it by analyzing existing dependencies in the packet.
981 
982  // Analyze relationships between all existing members of the packet.
983  // Look for Anti dependecy on the same predicate reg as used in the
984  // candidate.
985  for (auto I : CurrentPacketMIs) {
986  // Scheduling Unit for current insn in the packet.
987  SUnit *PacketSU = MIToSUnit.find(I)->second;
988 
989  // If this instruction in the packet is succeeded by the candidate...
990  if (PacketSU->isSucc(SU)) {
991  for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
992  auto Dep = PacketSU->Succs[i];
993  // The corner case exist when there is true data dependency between
994  // candidate and one of current packet members, this dep is on
995  // predicate reg, and there already exist anti dep on the same pred in
996  // the packet.
997  if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data &&
998  Hexagon::PredRegsRegClass.contains(Dep.getReg())) {
999  // Here I know that I is predicate setting instruction with true
1000  // data dep to candidate on the register we care about - c) in the
1001  // above example. Now I need to see if there is an anti dependency
1002  // from c) to any other instruction in the same packet on the pred
1003  // reg of interest.
1004  if (restrictingDepExistInPacket(*I, Dep.getReg()))
1005  return false;
1006  }
1007  }
1008  }
1009  }
1010 
1011  // If the above case does not apply, check regular complement condition.
1012  // Check that the predicate register is the same and that the predicate
1013  // sense is different We also need to differentiate .old vs. .new: !p0
1014  // is not complementary to p0.new.
1015  unsigned PReg1 = getPredicatedRegister(MI1, HII);
1016  unsigned PReg2 = getPredicatedRegister(MI2, HII);
1017  return PReg1 == PReg2 &&
1018  Hexagon::PredRegsRegClass.contains(PReg1) &&
1019  Hexagon::PredRegsRegClass.contains(PReg2) &&
1020  getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
1021  HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
1022 }
1023 
1024 // Initialize packetizer flags.
1026  Dependence = false;
1027  PromotedToDotNew = false;
1028  GlueToNewValueJump = false;
1029  GlueAllocframeStore = false;
1030  FoundSequentialDependence = false;
1031  ChangedOffset = INT64_MAX;
1032 }
1033 
1034 // Ignore bundling of pseudo instructions.
1036  const MachineBasicBlock *) {
1037  if (MI.isDebugInstr())
1038  return true;
1039 
1040  if (MI.isCFIInstruction())
1041  return false;
1042 
1043  // We must print out inline assembly.
1044  if (MI.isInlineAsm())
1045  return false;
1046 
1047  if (MI.isImplicitDef())
1048  return false;
1049 
1050  // We check if MI has any functional units mapped to it. If it doesn't,
1051  // we ignore the instruction.
1052  const MCInstrDesc& TID = MI.getDesc();
1053  auto *IS = ResourceTracker->getInstrItins()->beginStage(TID.getSchedClass());
1054  unsigned FuncUnits = IS->getUnits();
1055  return !FuncUnits;
1056 }
1057 
1059  // Ensure any bundles created by gather packetize remain seperate.
1060  if (MI.isBundle())
1061  return true;
1062 
1063  if (MI.isEHLabel() || MI.isCFIInstruction())
1064  return true;
1065 
1066  // Consider inline asm to not be a solo instruction by default.
1067  // Inline asm will be put in a packet temporarily, but then it will be
1068  // removed, and placed outside of the packet (before or after, depending
1069  // on dependencies). This is to reduce the impact of inline asm as a
1070  // "packet splitting" instruction.
1071  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1072  return true;
1073 
1074  if (isSchedBarrier(MI))
1075  return true;
1076 
1077  if (HII->isSolo(MI))
1078  return true;
1079 
1080  if (MI.getOpcode() == Hexagon::A2_nop)
1081  return true;
1082 
1083  return false;
1084 }
1085 
1086 // Quick check if instructions MI and MJ cannot coexist in the same packet.
1087 // Limit the tests to be "one-way", e.g. "if MI->isBranch and MJ->isInlineAsm",
1088 // but not the symmetric case: "if MJ->isBranch and MI->isInlineAsm".
1089 // For full test call this function twice:
1090 // cannotCoexistAsymm(MI, MJ) || cannotCoexistAsymm(MJ, MI)
1091 // Doing the test only one way saves the amount of code in this function,
1092 // since every test would need to be repeated with the MI and MJ reversed.
1093 static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
1094  const HexagonInstrInfo &HII) {
1095  const MachineFunction *MF = MI.getParent()->getParent();
1097  HII.isHVXMemWithAIndirect(MI, MJ))
1098  return true;
1099 
1100  // An inline asm cannot be together with a branch, because we may not be
1101  // able to remove the asm out after packetizing (i.e. if the asm must be
1102  // moved past the bundle). Similarly, two asms cannot be together to avoid
1103  // complications when determining their relative order outside of a bundle.
1104  if (MI.isInlineAsm())
1105  return MJ.isInlineAsm() || MJ.isBranch() || MJ.isBarrier() ||
1106  MJ.isCall() || MJ.isTerminator();
1107 
1108  // New-value stores cannot coexist with any other stores.
1109  if (HII.isNewValueStore(MI) && MJ.mayStore())
1110  return true;
1111 
1112  switch (MI.getOpcode()) {
1113  case Hexagon::S2_storew_locked:
1114  case Hexagon::S4_stored_locked:
1115  case Hexagon::L2_loadw_locked:
1116  case Hexagon::L4_loadd_locked:
1117  case Hexagon::Y2_dccleana:
1118  case Hexagon::Y2_dccleaninva:
1119  case Hexagon::Y2_dcinva:
1120  case Hexagon::Y2_dczeroa:
1121  case Hexagon::Y4_l2fetch:
1122  case Hexagon::Y5_l2fetch: {
1123  // These instructions can only be grouped with ALU32 or non-floating-point
1124  // XTYPE instructions. Since there is no convenient way of identifying fp
1125  // XTYPE instructions, only allow grouping with ALU32 for now.
1126  unsigned TJ = HII.getType(MJ);
1127  if (TJ != HexagonII::TypeALU32_2op &&
1128  TJ != HexagonII::TypeALU32_3op &&
1130  return true;
1131  break;
1132  }
1133  default:
1134  break;
1135  }
1136 
1137  // "False" really means that the quick check failed to determine if
1138  // I and J cannot coexist.
1139  return false;
1140 }
1141 
1142 // Full, symmetric check.
1144  const MachineInstr &MJ) {
1145  return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII);
1146 }
1147 
1149  for (auto &B : MF) {
1150  MachineBasicBlock::iterator BundleIt;
1152  for (auto I = B.instr_begin(), E = B.instr_end(); I != E; I = NextI) {
1153  NextI = std::next(I);
1154  MachineInstr &MI = *I;
1155  if (MI.isBundle())
1156  BundleIt = I;
1157  if (!MI.isInsideBundle())
1158  continue;
1159 
1160  // Decide on where to insert the instruction that we are pulling out.
1161  // Debug instructions always go before the bundle, but the placement of
1162  // INLINE_ASM depends on potential dependencies. By default, try to
1163  // put it before the bundle, but if the asm writes to a register that
1164  // other instructions in the bundle read, then we need to place it
1165  // after the bundle (to preserve the bundle semantics).
1166  bool InsertBeforeBundle;
1167  if (MI.isInlineAsm())
1168  InsertBeforeBundle = !hasWriteToReadDep(MI, *BundleIt, HRI);
1169  else if (MI.isDebugValue())
1170  InsertBeforeBundle = true;
1171  else
1172  continue;
1173 
1174  BundleIt = moveInstrOut(MI, BundleIt, InsertBeforeBundle);
1175  }
1176  }
1177 }
1178 
1179 // Check if a given instruction is of class "system".
1180 static bool isSystemInstr(const MachineInstr &MI) {
1181  unsigned Opc = MI.getOpcode();
1182  switch (Opc) {
1183  case Hexagon::Y2_barrier:
1184  case Hexagon::Y2_dcfetchbo:
1185  case Hexagon::Y4_l2fetch:
1186  case Hexagon::Y5_l2fetch:
1187  return true;
1188  }
1189  return false;
1190 }
1191 
1193  const MachineInstr &J) {
1194  // The dependence graph may not include edges between dead definitions,
1195  // so without extra checks, we could end up packetizing two instruction
1196  // defining the same (dead) register.
1197  if (I.isCall() || J.isCall())
1198  return false;
1199  if (HII->isPredicated(I) || HII->isPredicated(J))
1200  return false;
1201 
1202  BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);
1203  for (auto &MO : I.operands()) {
1204  if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1205  continue;
1206  DeadDefs[MO.getReg()] = true;
1207  }
1208 
1209  for (auto &MO : J.operands()) {
1210  if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1211  continue;
1212  Register R = MO.getReg();
1213  if (R != Hexagon::USR_OVF && DeadDefs[R])
1214  return true;
1215  }
1216  return false;
1217 }
1218 
1220  const MachineInstr &J) {
1221  // A save callee-save register function call can only be in a packet
1222  // with instructions that don't write to the callee-save registers.
1223  if ((HII->isSaveCalleeSavedRegsCall(I) &&
1224  doesModifyCalleeSavedReg(J, HRI)) ||
1225  (HII->isSaveCalleeSavedRegsCall(J) &&
1226  doesModifyCalleeSavedReg(I, HRI)))
1227  return true;
1228 
1229  // Two control flow instructions cannot go in the same packet.
1230  if (isControlFlow(I) && isControlFlow(J))
1231  return true;
1232 
1233  // \ref-manual (7.3.4) A loop setup packet in loopN or spNloop0 cannot
1234  // contain a speculative indirect jump,
1235  // a new-value compare jump or a dealloc_return.
1236  auto isBadForLoopN = [this] (const MachineInstr &MI) -> bool {
1237  if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
1238  return true;
1239  if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
1240  return true;
1241  return false;
1242  };
1243 
1244  if (HII->isLoopN(I) && isBadForLoopN(J))
1245  return true;
1246  if (HII->isLoopN(J) && isBadForLoopN(I))
1247  return true;
1248 
1249  // dealloc_return cannot appear in the same packet as a conditional or
1250  // unconditional jump.
1251  return HII->isDeallocRet(I) &&
1252  (J.isBranch() || J.isCall() || J.isBarrier());
1253 }
1254 
1256  const MachineInstr &J) {
1257  // Adding I to a packet that has J.
1258 
1259  // Regmasks are not reflected in the scheduling dependency graph, so
1260  // we need to check them manually. This code assumes that regmasks only
1261  // occur on calls, and the problematic case is when we add an instruction
1262  // defining a register R to a packet that has a call that clobbers R via
1263  // a regmask. Those cannot be packetized together, because the call will
1264  // be executed last. That's also a reson why it is ok to add a call
1265  // clobbering R to a packet that defines R.
1266 
1267  // Look for regmasks in J.
1268  for (const MachineOperand &OpJ : J.operands()) {
1269  if (!OpJ.isRegMask())
1270  continue;
1271  assert((J.isCall() || HII->isTailCall(J)) && "Regmask on a non-call");
1272  for (const MachineOperand &OpI : I.operands()) {
1273  if (OpI.isReg()) {
1274  if (OpJ.clobbersPhysReg(OpI.getReg()))
1275  return true;
1276  } else if (OpI.isRegMask()) {
1277  // Both are regmasks. Assume that they intersect.
1278  return true;
1279  }
1280  }
1281  }
1282  return false;
1283 }
1284 
1286  const MachineInstr &J) {
1287  bool SysI = isSystemInstr(I), SysJ = isSystemInstr(J);
1288  bool StoreI = I.mayStore(), StoreJ = J.mayStore();
1289  if ((SysI && StoreJ) || (SysJ && StoreI))
1290  return true;
1291 
1292  if (StoreI && StoreJ) {
1293  if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I))
1294  return true;
1295  } else {
1296  // A memop cannot be in the same packet with another memop or a store.
1297  // Two stores can be together, but here I and J cannot both be stores.
1298  bool MopStI = HII->isMemOp(I) || StoreI;
1299  bool MopStJ = HII->isMemOp(J) || StoreJ;
1300  if (MopStI && MopStJ)
1301  return true;
1302  }
1303 
1304  return (StoreJ && HII->isDeallocRet(I)) || (StoreI && HII->isDeallocRet(J));
1305 }
1306 
1307 // SUI is the current instruction that is out side of the current packet.
1308 // SUJ is the current instruction inside the current packet against which that
1309 // SUI will be packetized.
1311  assert(SUI->getInstr() && SUJ->getInstr());
1312  MachineInstr &I = *SUI->getInstr();
1313  MachineInstr &J = *SUJ->getInstr();
1314 
1315  // Clear IgnoreDepMIs when Packet starts.
1316  if (CurrentPacketMIs.size() == 1)
1317  IgnoreDepMIs.clear();
1318 
1319  MachineBasicBlock::iterator II = I.getIterator();
1320 
1321  // Solo instructions cannot go in the packet.
1322  assert(!isSoloInstruction(I) && "Unexpected solo instr!");
1323 
1324  if (cannotCoexist(I, J))
1325  return false;
1326 
1327  Dependence = hasDeadDependence(I, J) || hasControlDependence(I, J);
1328  if (Dependence)
1329  return false;
1330 
1331  // Regmasks are not accounted for in the scheduling graph, so we need
1332  // to explicitly check for dependencies caused by them. They should only
1333  // appear on calls, so it's not too pessimistic to reject all regmask
1334  // dependencies.
1335  Dependence = hasRegMaskDependence(I, J);
1336  if (Dependence)
1337  return false;
1338 
1339  // Dual-store does not allow second store, if the first store is not
1340  // in SLOT0. New value store, new value jump, dealloc_return and memop
1341  // always take SLOT0. Arch spec 3.4.4.2.
1342  Dependence = hasDualStoreDependence(I, J);
1343  if (Dependence)
1344  return false;
1345 
1346  // If an instruction feeds new value jump, glue it.
1347  MachineBasicBlock::iterator NextMII = I.getIterator();
1348  ++NextMII;
1349  if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {
1350  MachineInstr &NextMI = *NextMII;
1351 
1352  bool secondRegMatch = false;
1353  const MachineOperand &NOp0 = NextMI.getOperand(0);
1354  const MachineOperand &NOp1 = NextMI.getOperand(1);
1355 
1356  if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
1357  secondRegMatch = true;
1358 
1359  for (MachineInstr *PI : CurrentPacketMIs) {
1360  // NVJ can not be part of the dual jump - Arch Spec: section 7.8.
1361  if (PI->isCall()) {
1362  Dependence = true;
1363  break;
1364  }
1365  // Validate:
1366  // 1. Packet does not have a store in it.
1367  // 2. If the first operand of the nvj is newified, and the second
1368  // operand is also a reg, it (second reg) is not defined in
1369  // the same packet.
1370  // 3. If the second operand of the nvj is newified, (which means
1371  // first operand is also a reg), first reg is not defined in
1372  // the same packet.
1373  if (PI->getOpcode() == Hexagon::S2_allocframe || PI->mayStore() ||
1374  HII->isLoopN(*PI)) {
1375  Dependence = true;
1376  break;
1377  }
1378  // Check #2/#3.
1379  const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1;
1380  if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {
1381  Dependence = true;
1382  break;
1383  }
1384  }
1385 
1386  GlueToNewValueJump = true;
1387  if (Dependence)
1388  return false;
1389  }
1390 
1391  // There no dependency between a prolog instruction and its successor.
1392  if (!SUJ->isSucc(SUI))
1393  return true;
1394 
1395  for (unsigned i = 0; i < SUJ->Succs.size(); ++i) {
1396  if (FoundSequentialDependence)
1397  break;
1398 
1399  if (SUJ->Succs[i].getSUnit() != SUI)
1400  continue;
1401 
1402  SDep::Kind DepType = SUJ->Succs[i].getKind();
1403  // For direct calls:
1404  // Ignore register dependences for call instructions for packetization
1405  // purposes except for those due to r31 and predicate registers.
1406  //
1407  // For indirect calls:
1408  // Same as direct calls + check for true dependences to the register
1409  // used in the indirect call.
1410  //
1411  // We completely ignore Order dependences for call instructions.
1412  //
1413  // For returns:
1414  // Ignore register dependences for return instructions like jumpr,
1415  // dealloc return unless we have dependencies on the explicit uses
1416  // of the registers used by jumpr (like r31) or dealloc return
1417  // (like r29 or r30).
1418  unsigned DepReg = 0;
1419  const TargetRegisterClass *RC = nullptr;
1420  if (DepType == SDep::Data) {
1421  DepReg = SUJ->Succs[i].getReg();
1422  RC = HRI->getMinimalPhysRegClass(DepReg);
1423  }
1424 
1425  if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {
1426  if (!isRegDependence(DepType))
1427  continue;
1428  if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
1429  continue;
1430  }
1431 
1432  if (DepType == SDep::Data) {
1433  if (canPromoteToDotCur(J, SUJ, DepReg, II, RC))
1434  if (promoteToDotCur(J, DepType, II, RC))
1435  continue;
1436  }
1437 
1438  // Data dpendence ok if we have load.cur.
1439  if (DepType == SDep::Data && HII->isDotCurInst(J)) {
1440  if (HII->isHVXVec(I))
1441  continue;
1442  }
1443 
1444  // For instructions that can be promoted to dot-new, try to promote.
1445  if (DepType == SDep::Data) {
1446  if (canPromoteToDotNew(I, SUJ, DepReg, II, RC)) {
1447  if (promoteToDotNew(I, DepType, II, RC)) {
1448  PromotedToDotNew = true;
1449  if (cannotCoexist(I, J))
1450  FoundSequentialDependence = true;
1451  continue;
1452  }
1453  }
1454  if (HII->isNewValueJump(I))
1455  continue;
1456  }
1457 
1458  // For predicated instructions, if the predicates are complements then
1459  // there can be no dependence.
1460  if (HII->isPredicated(I) && HII->isPredicated(J) &&
1461  arePredicatesComplements(I, J)) {
1462  // Not always safe to do this translation.
1463  // DAG Builder attempts to reduce dependence edges using transitive
1464  // nature of dependencies. Here is an example:
1465  //
1466  // r0 = tfr_pt ... (1)
1467  // r0 = tfr_pf ... (2)
1468  // r0 = tfr_pt ... (3)
1469  //
1470  // There will be an output dependence between (1)->(2) and (2)->(3).
1471  // However, there is no dependence edge between (1)->(3). This results
1472  // in all 3 instructions going in the same packet. We ignore dependce
1473  // only once to avoid this situation.
1474  auto Itr = find(IgnoreDepMIs, &J);
1475  if (Itr != IgnoreDepMIs.end()) {
1476  Dependence = true;
1477  return false;
1478  }
1479  IgnoreDepMIs.push_back(&I);
1480  continue;
1481  }
1482 
1483  // Ignore Order dependences between unconditional direct branches
1484  // and non-control-flow instructions.
1485  if (isDirectJump(I) && !J.isBranch() && !J.isCall() &&
1486  DepType == SDep::Order)
1487  continue;
1488 
1489  // Ignore all dependences for jumps except for true and output
1490  // dependences.
1491  if (I.isConditionalBranch() && DepType != SDep::Data &&
1492  DepType != SDep::Output)
1493  continue;
1494 
1495  if (DepType == SDep::Output) {
1496  FoundSequentialDependence = true;
1497  break;
1498  }
1499 
1500  // For Order dependences:
1501  // 1. Volatile loads/stores can be packetized together, unless other
1502  // rules prevent is.
1503  // 2. Store followed by a load is not allowed.
1504  // 3. Store followed by a store is valid.
1505  // 4. Load followed by any memory operation is allowed.
1506  if (DepType == SDep::Order) {
1507  if (!PacketizeVolatiles) {
1508  bool OrdRefs = I.hasOrderedMemoryRef() || J.hasOrderedMemoryRef();
1509  if (OrdRefs) {
1510  FoundSequentialDependence = true;
1511  break;
1512  }
1513  }
1514  // J is first, I is second.
1515  bool LoadJ = J.mayLoad(), StoreJ = J.mayStore();
1516  bool LoadI = I.mayLoad(), StoreI = I.mayStore();
1517  bool NVStoreJ = HII->isNewValueStore(J);
1518  bool NVStoreI = HII->isNewValueStore(I);
1519  bool IsVecJ = HII->isHVXVec(J);
1520  bool IsVecI = HII->isHVXVec(I);
1521 
1523  ((LoadJ && StoreI && !NVStoreI) ||
1524  (StoreJ && LoadI && !NVStoreJ)) &&
1525  (J.getOpcode() != Hexagon::S2_allocframe &&
1526  I.getOpcode() != Hexagon::S2_allocframe) &&
1527  (J.getOpcode() != Hexagon::L2_deallocframe &&
1528  I.getOpcode() != Hexagon::L2_deallocframe) &&
1529  (!HII->isMemOp(J) && !HII->isMemOp(I)) && (!IsVecJ && !IsVecI))
1530  setmemShufDisabled(true);
1531  else
1532  if (StoreJ && LoadI && alias(J, I)) {
1533  FoundSequentialDependence = true;
1534  break;
1535  }
1536 
1537  if (!StoreJ)
1538  if (!LoadJ || (!LoadI && !StoreI)) {
1539  // If J is neither load nor store, assume a dependency.
1540  // If J is a load, but I is neither, also assume a dependency.
1541  FoundSequentialDependence = true;
1542  break;
1543  }
1544  // Store followed by store: not OK on V2.
1545  // Store followed by load: not OK on all.
1546  // Load followed by store: OK on all.
1547  // Load followed by load: OK on all.
1548  continue;
1549  }
1550 
1551  // Special case for ALLOCFRAME: even though there is dependency
1552  // between ALLOCFRAME and subsequent store, allow it to be packetized
1553  // in a same packet. This implies that the store is using the caller's
1554  // SP. Hence, offset needs to be updated accordingly.
1555  if (DepType == SDep::Data && J.getOpcode() == Hexagon::S2_allocframe) {
1556  unsigned Opc = I.getOpcode();
1557  switch (Opc) {
1558  case Hexagon::S2_storerd_io:
1559  case Hexagon::S2_storeri_io:
1560  case Hexagon::S2_storerh_io:
1561  case Hexagon::S2_storerb_io:
1562  if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
1563  // Since this store is to be glued with allocframe in the same
1564  // packet, it will use SP of the previous stack frame, i.e.
1565  // caller's SP. Therefore, we need to recalculate offset
1566  // according to this change.
1567  GlueAllocframeStore = useCallersSP(I);
1568  if (GlueAllocframeStore)
1569  continue;
1570  }
1571  break;
1572  default:
1573  break;
1574  }
1575  }
1576 
1577  // There are certain anti-dependencies that cannot be ignored.
1578  // Specifically:
1579  // J2_call ... implicit-def %r0 ; SUJ
1580  // R0 = ... ; SUI
1581  // Those cannot be packetized together, since the call will observe
1582  // the effect of the assignment to R0.
1583  if ((DepType == SDep::Anti || DepType == SDep::Output) && J.isCall()) {
1584  // Check if I defines any volatile register. We should also check
1585  // registers that the call may read, but these happen to be a
1586  // subset of the volatile register set.
1587  for (const MachineOperand &Op : I.operands()) {
1588  if (Op.isReg() && Op.isDef()) {
1589  Register R = Op.getReg();
1590  if (!J.readsRegister(R, HRI) && !J.modifiesRegister(R, HRI))
1591  continue;
1592  } else if (!Op.isRegMask()) {
1593  // If I has a regmask assume dependency.
1594  continue;
1595  }
1596  FoundSequentialDependence = true;
1597  break;
1598  }
1599  }
1600 
1601  // Skip over remaining anti-dependences. Two instructions that are
1602  // anti-dependent can share a packet, since in most such cases all
1603  // operands are read before any modifications take place.
1604  // The exceptions are branch and call instructions, since they are
1605  // executed after all other instructions have completed (at least
1606  // conceptually).
1607  if (DepType != SDep::Anti) {
1608  FoundSequentialDependence = true;
1609  break;
1610  }
1611  }
1612 
1613  if (FoundSequentialDependence) {
1614  Dependence = true;
1615  return false;
1616  }
1617 
1618  return true;
1619 }
1620 
1622  assert(SUI->getInstr() && SUJ->getInstr());
1623  MachineInstr &I = *SUI->getInstr();
1624  MachineInstr &J = *SUJ->getInstr();
1625 
1626  bool Coexist = !cannotCoexist(I, J);
1627 
1628  if (Coexist && !Dependence)
1629  return true;
1630 
1631  // Check if the instruction was promoted to a dot-new. If so, demote it
1632  // back into a dot-old.
1633  if (PromotedToDotNew)
1634  demoteToDotOld(I);
1635 
1636  cleanUpDotCur();
1637  // Check if the instruction (must be a store) was glued with an allocframe
1638  // instruction. If so, restore its offset to its original value, i.e. use
1639  // current SP instead of caller's SP.
1640  if (GlueAllocframeStore) {
1641  useCalleesSP(I);
1642  GlueAllocframeStore = false;
1643  }
1644 
1645  if (ChangedOffset != INT64_MAX)
1646  undoChangedOffset(I);
1647 
1648  if (GlueToNewValueJump) {
1649  // Putting I and J together would prevent the new-value jump from being
1650  // packetized with the producer. In that case I and J must be separated.
1651  GlueToNewValueJump = false;
1652  return false;
1653  }
1654 
1655  if (!Coexist)
1656  return false;
1657 
1658  if (ChangedOffset == INT64_MAX && updateOffset(SUI, SUJ)) {
1659  FoundSequentialDependence = false;
1660  Dependence = false;
1661  return true;
1662  }
1663 
1664  return false;
1665 }
1666 
1667 
1669  bool FoundLoad = false;
1670  bool FoundStore = false;
1671 
1672  for (auto MJ : CurrentPacketMIs) {
1673  unsigned Opc = MJ->getOpcode();
1674  if (Opc == Hexagon::S2_allocframe || Opc == Hexagon::L2_deallocframe)
1675  continue;
1676  if (HII->isMemOp(*MJ))
1677  continue;
1678  if (MJ->mayLoad())
1679  FoundLoad = true;
1680  if (MJ->mayStore() && !HII->isNewValueStore(*MJ))
1681  FoundStore = true;
1682  }
1683  return FoundLoad && FoundStore;
1684 }
1685 
1686 
1690  MachineBasicBlock *MBB = MI.getParent();
1691 
1692  if (CurrentPacketMIs.empty())
1693  PacketStalls = false;
1694  PacketStalls |= producesStall(MI);
1695 
1696  if (MI.isImplicitDef()) {
1697  // Add to the packet to allow subsequent instructions to be checked
1698  // properly.
1699  CurrentPacketMIs.push_back(&MI);
1700  return MII;
1701  }
1702  assert(ResourceTracker->canReserveResources(MI));
1703 
1704  bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI);
1705  bool Good = true;
1706 
1707  if (GlueToNewValueJump) {
1708  MachineInstr &NvjMI = *++MII;
1709  // We need to put both instructions in the same packet: MI and NvjMI.
1710  // Either of them can require a constant extender. Try to add both to
1711  // the current packet, and if that fails, end the packet and start a
1712  // new one.
1713  ResourceTracker->reserveResources(MI);
1714  if (ExtMI)
1715  Good = tryAllocateResourcesForConstExt(true);
1716 
1717  bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI);
1718  if (Good) {
1719  if (ResourceTracker->canReserveResources(NvjMI))
1720  ResourceTracker->reserveResources(NvjMI);
1721  else
1722  Good = false;
1723  }
1724  if (Good && ExtNvjMI)
1725  Good = tryAllocateResourcesForConstExt(true);
1726 
1727  if (!Good) {
1728  endPacket(MBB, MI);
1729  assert(ResourceTracker->canReserveResources(MI));
1730  ResourceTracker->reserveResources(MI);
1731  if (ExtMI) {
1732  assert(canReserveResourcesForConstExt());
1733  tryAllocateResourcesForConstExt(true);
1734  }
1735  assert(ResourceTracker->canReserveResources(NvjMI));
1736  ResourceTracker->reserveResources(NvjMI);
1737  if (ExtNvjMI) {
1738  assert(canReserveResourcesForConstExt());
1739  reserveResourcesForConstExt();
1740  }
1741  }
1742  CurrentPacketMIs.push_back(&MI);
1743  CurrentPacketMIs.push_back(&NvjMI);
1744  return MII;
1745  }
1746 
1747  ResourceTracker->reserveResources(MI);
1748  if (ExtMI && !tryAllocateResourcesForConstExt(true)) {
1749  endPacket(MBB, MI);
1750  if (PromotedToDotNew)
1751  demoteToDotOld(MI);
1752  if (GlueAllocframeStore) {
1753  useCalleesSP(MI);
1754  GlueAllocframeStore = false;
1755  }
1756  ResourceTracker->reserveResources(MI);
1757  reserveResourcesForConstExt();
1758  }
1759 
1760  CurrentPacketMIs.push_back(&MI);
1761  return MII;
1762 }
1763 
1766  // Replace VLIWPacketizerList::endPacket(MBB, EndMI).
1767  LLVM_DEBUG({
1768  if (!CurrentPacketMIs.empty()) {
1769  dbgs() << "Finalizing packet:\n";
1770  unsigned Idx = 0;
1771  for (MachineInstr *MI : CurrentPacketMIs) {
1772  unsigned R = ResourceTracker->getUsedResources(Idx++);
1773  dbgs() << " * [res:0x" << utohexstr(R) << "] " << *MI;
1774  }
1775  }
1776  });
1777 
1778  bool memShufDisabled = getmemShufDisabled();
1779  if (memShufDisabled && !foundLSInPacket()) {
1780  setmemShufDisabled(false);
1781  LLVM_DEBUG(dbgs() << " Not added to NoShufPacket\n");
1782  }
1783  memShufDisabled = getmemShufDisabled();
1784 
1785  OldPacketMIs.clear();
1786  for (MachineInstr *MI : CurrentPacketMIs) {
1787  MachineBasicBlock::instr_iterator NextMI = std::next(MI->getIterator());
1788  for (auto &I : make_range(HII->expandVGatherPseudo(*MI), NextMI))
1789  OldPacketMIs.push_back(&I);
1790  }
1791  CurrentPacketMIs.clear();
1792 
1793  if (OldPacketMIs.size() > 1) {
1794  MachineBasicBlock::instr_iterator FirstMI(OldPacketMIs.front());
1796  finalizeBundle(*MBB, FirstMI, LastMI);
1797  auto BundleMII = std::prev(FirstMI);
1798  if (memShufDisabled)
1799  HII->setBundleNoShuf(BundleMII);
1800 
1801  setmemShufDisabled(false);
1802  }
1803 
1804  ResourceTracker->clearResources();
1805  LLVM_DEBUG(dbgs() << "End packet\n");
1806 }
1807 
1809  if (Minimal)
1810  return false;
1811  return !producesStall(MI);
1812 }
1813 
1814 // V60 forward scheduling.
1816  // If the packet already stalls, then ignore the stall from a subsequent
1817  // instruction in the same packet.
1818  if (PacketStalls)
1819  return false;
1820 
1821  // Check whether the previous packet is in a different loop. If this is the
1822  // case, there is little point in trying to avoid a stall because that would
1823  // favor the rare case (loop entry) over the common case (loop iteration).
1824  //
1825  // TODO: We should really be able to check all the incoming edges if this is
1826  // the first packet in a basic block, so we can avoid stalls from the loop
1827  // backedge.
1828  if (!OldPacketMIs.empty()) {
1829  auto *OldBB = OldPacketMIs.front()->getParent();
1830  auto *ThisBB = I.getParent();
1831  if (MLI->getLoopFor(OldBB) != MLI->getLoopFor(ThisBB))
1832  return false;
1833  }
1834 
1835  SUnit *SUI = MIToSUnit[const_cast<MachineInstr *>(&I)];
1836 
1837  // If the latency is 0 and there is a data dependence between this
1838  // instruction and any instruction in the current packet, we disregard any
1839  // potential stalls due to the instructions in the previous packet. Most of
1840  // the instruction pairs that can go together in the same packet have 0
1841  // latency between them. The exceptions are
1842  // 1. NewValueJumps as they're generated much later and the latencies can't
1843  // be changed at that point.
1844  // 2. .cur instructions, if its consumer has a 0 latency successor (such as
1845  // .new). In this case, the latency between .cur and the consumer stays
1846  // non-zero even though we can have both .cur and .new in the same packet.
1847  // Changing the latency to 0 is not an option as it causes software pipeliner
1848  // to not pipeline in some cases.
1849 
1850  // For Example:
1851  // {
1852  // I1: v6.cur = vmem(r0++#1)
1853  // I2: v7 = valign(v6,v4,r2)
1854  // I3: vmem(r5++#1) = v7.new
1855  // }
1856  // Here I2 and I3 has 0 cycle latency, but I1 and I2 has 2.
1857 
1858  for (auto J : CurrentPacketMIs) {
1859  SUnit *SUJ = MIToSUnit[J];
1860  for (auto &Pred : SUI->Preds)
1861  if (Pred.getSUnit() == SUJ)
1862  if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) ||
1863  HII->isNewValueJump(I) || HII->isToBeScheduledASAP(*J, I))
1864  return false;
1865  }
1866 
1867  // Check if the latency is greater than one between this instruction and any
1868  // instruction in the previous packet.
1869  for (auto J : OldPacketMIs) {
1870  SUnit *SUJ = MIToSUnit[J];
1871  for (auto &Pred : SUI->Preds)
1872  if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1)
1873  return true;
1874  }
1875 
1876  return false;
1877 }
1878 
1879 //===----------------------------------------------------------------------===//
1880 // Public Constructor Functions
1881 //===----------------------------------------------------------------------===//
1882 
1884  return new HexagonPacketizer(Minimal);
1885 }
bool canPromoteToNewValueStore(const MachineInstr &MI, const MachineInstr &PacketMI, unsigned DepReg)
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static bool hasWriteToReadDep(const MachineInstr &FirstI, const MachineInstr &SecondI, const TargetRegisterInfo *TRI)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:651
instr_iterator instr_end()
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ, const HexagonInstrInfo &HII)
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool isCFIInstruction() const
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:364
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:178
static bool isImplicitDependency(const MachineInstr &I, bool CheckDef, unsigned DepReg)
unsigned Reg
bool isInlineAsm() const
bool demoteToDotOld(MachineInstr &MI)
static cl::opt< bool > PacketizeVolatiles("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references"))
void undoChangedOffset(MachineInstr &MI)
Undo the changed offset.
static cl::opt< bool > DisablePacketizer("disable-packetizer", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon packetizer pass"))
INITIALIZE_PASS_BEGIN(HexagonPacketizer, "hexagon-packetizer", "Hexagon Packetizer", false, false) INITIALIZE_PASS_END(HexagonPacketizer
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
Kind
These are the different kinds of scheduling dependencies.
Definition: ScheduleDAG.h:52
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:477
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
#define HEXAGON_LRFP_SIZE
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition: ScheduleDAG.h:256
A register anti-dependence (aka WAR).
Definition: ScheduleDAG.h:54
bool restrictingDepExistInPacket(MachineInstr &, unsigned)
bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
static cl::opt< bool > EnableGenAllInsnClass("enable-gen-insn", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"))
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
static cl::opt< bool > Slot1Store("slot1-store-slot0-load", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Allow slot1 store and slot0 load"))
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:368
bool shouldAddToPacket(const MachineInstr &MI) override
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:53
#define INT64_MAX
Definition: DataTypes.h:77
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:667
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) override
bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2)
static bool doesModifyCalleeSavedReg(const MachineInstr &MI, const TargetRegisterInfo *TRI)
Returns true if the instruction modifies a callee-saved register.
void unbundleFromPred()
Break bundle above this instruction.
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:55
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
static bool isControlFlow(const MachineInstr &MI)
bool isBundle() const
void initializeHexagonPacketizerPass(PassRegistry &)
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:352
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
hexagon Hexagon Packetizer
bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J)
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:675
static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI, MachineBasicBlock::iterator BundleIt, bool Before)
static unsigned getPredicatedRegister(MachineInstr &MI, const HexagonInstrInfo *QII)
Gets the predicate register of a predicated instruction.
static const MachineOperand & getAbsSetOperand(const MachineInstr &MI)
bool isSoloInstruction(const MachineInstr &MI) override
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:596
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:838
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
static bool isSystemInstr(const MachineInstr &MI)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:187
Represent the analysis usage information of a pass.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:313
bool isEHLabel() const
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
self_iterator getIterator()
Definition: ilist_node.h:81
static bool isRegDependence(const SDep::Kind DepType)
bool tryAllocateResourcesForConstExt(bool Reserve)
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
bool isImplicitDef() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Any other ordering dependency.
Definition: ScheduleDAG.h:56
auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1186
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
bool isDebugInstr() const
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
static const MachineOperand & getPostIncrementOperand(const MachineInstr &MI, const HexagonInstrInfo *HII)
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
bool isNewValueStore(const MachineInstr &MI) const
bool isDebugValue() const
MachineOperand class - Representation of each machine instruction operand.
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
uint64_t getType(const MachineInstr &MI) const
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
static cl::opt< bool > DisableVecDblNVStores("disable-vecdbl-nv-stores", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable vector double new-value-stores"))
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:301
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:419
static const MachineOperand & getStoreValueOperand(const MachineInstr &MI)
static bool isLoadAbsSet(const MachineInstr &MI)
static PredicateKind getPredicateSense(const MachineInstr &MI, const HexagonInstrInfo *HII)
Returns true if an instruction is predicated on p0 and false if it&#39;s predicated on !p0...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static bool isSchedBarrier(const MachineInstr &MI)
bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB &#39;Other&#39; at the position From, and insert it into this MBB right before &#39;...
bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, unsigned DepReg)
bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override
bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC)
bool updateOffset(SUnit *SUI, SUnit *SUJ)
Return true if we can update the offset in MI so that MI and MJ can be packetized together...
cl::opt< bool > ScheduleInlineAsm
#define I(x, y, z)
Definition: MD5.cpp:58
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:272
bool isPredicatedTrue(const MachineInstr &MI) const
uint32_t Size
Definition: Profile.cpp:46
bool hasControlDependence(const MachineInstr &I, const MachineInstr &J)
bool useCallersSP(MachineInstr &MI)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
hexagon packetizer
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:825
bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J)
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:285
aarch64 promote const
bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ)
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override
FunctionPass * createHexagonPacketizer(bool Minimal)
const HexagonInstrInfo * getInstrInfo() const override
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:257
void useCalleesSP(MachineInstr &MI)
bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J)
IRTranslator LLVM IR MI
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:658
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
Register getReg() const
getReg - Returns the register number.
void unpacketizeSoloInstrs(MachineFunction &MF)
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
Dependence - This class represents a dependence between two memory memory references in a function...
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII)
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool isSucc(const SUnit *N) const
Tests if node N is a successor of this node.
Definition: ScheduleDAG.h:439
#define OP(n)
Definition: regex2.h:73
static bool isDirectJump(const MachineInstr &MI)
bool producesStall(const MachineInstr &MI)
Properties which a MachineFunction may have at a given point in time.
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
std::string utohexstr(uint64_t X, bool LowerCase=false)
Definition: StringExtras.h:124