42 #define GET_REGINFO_TARGET_DESC
43 #include "HexagonGenRegisterInfo.inc"
49 cl::desc(
"Limit on instruction search range in frame index elimination"));
53 cl::desc(
"Limit on the number of reused registers in frame index "
62 return R == Hexagon::R0 || R == Hexagon::R1 || R ==
Hexagon::R2 ||
63 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
69 using namespace Hexagon;
72 R0, R1,
R2, R3,
R4, R5,
R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0
75 D0, D1, D2, D3, D4, D5, D6, D7, 0
81 V0, V1,
V2, V3,
V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
82 V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27,
86 W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
92 switch (RC->
getID()) {
93 case IntRegsRegClassID:
95 case DoubleRegsRegClassID:
97 case PredRegsRegClassID:
101 case HvxWRRegClassID:
103 case HvxQRRegClassID:
111 dbgs() <<
"Register class: " << getRegClassName(RC) <<
"\n";
120 static const MCPhysReg CalleeSavedRegsV3[] = {
121 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
122 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
123 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
128 static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
129 Hexagon::R0, Hexagon::R1,
Hexagon::R2, Hexagon::R3,
130 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
131 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
132 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
137 return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
143 return HexagonCSR_RegMask;
150 Reserved.
set(Hexagon::R29);
151 Reserved.
set(Hexagon::R30);
152 Reserved.
set(Hexagon::R31);
153 Reserved.
set(Hexagon::VTMP);
156 Reserved.
set(Hexagon::GELR);
157 Reserved.
set(Hexagon::GSR);
158 Reserved.
set(Hexagon::GOSP);
159 Reserved.
set(Hexagon::G3);
162 Reserved.
set(Hexagon::SA0);
164 Reserved.
set(Hexagon::SA1);
165 Reserved.
set(Hexagon::LC1);
166 Reserved.
set(Hexagon::P3_0);
167 Reserved.
set(Hexagon::USR);
168 Reserved.
set(Hexagon::PC);
169 Reserved.
set(Hexagon::UGP);
170 Reserved.
set(Hexagon::GP);
171 Reserved.
set(Hexagon::CS0);
172 Reserved.
set(Hexagon::CS1);
173 Reserved.
set(Hexagon::UPCYCLELO);
174 Reserved.
set(Hexagon::UPCYCLEHI);
175 Reserved.
set(Hexagon::FRAMELIMIT);
176 Reserved.
set(Hexagon::FRAMEKEY);
177 Reserved.
set(Hexagon::PKTCOUNTLO);
178 Reserved.
set(Hexagon::PKTCOUNTHI);
179 Reserved.
set(Hexagon::UTIMERLO);
180 Reserved.
set(Hexagon::UTIMERHI);
184 Reserved.
set(Hexagon::C8);
185 Reserved.
set(Hexagon::USR_OVF);
195 Reserved.
set(Hexagon::R19);
198 markSuperRegs(Reserved,
x);
204 int SPAdj,
unsigned FIOp,
206 static unsigned ReuseCount = 0;
209 assert(SPAdj == 0 &&
"Unexpected");
216 auto &HFI = *HST.getFrameLowering();
219 int FI =
MI.getOperand(FIOp).getIndex();
222 int Offset = HFI.getFrameIndexReference(MF, FI, BP).getFixed();
224 int RealOffset = Offset +
MI.getOperand(FIOp+1).getImm();
226 unsigned Opc =
MI.getOpcode();
228 case Hexagon::PS_fia:
229 MI.setDesc(HII.get(Hexagon::A2_addi));
230 MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
231 MI.removeOperand(FIOp+1);
235 MI.setDesc(HII.get(Hexagon::A2_addi));
239 if (!HII.isValidOffset(Opc, RealOffset,
this)) {
251 switch (
MI.getOpcode()) {
253 case Hexagon::PS_vloadrw_ai:
254 case Hexagon::PS_vloadrw_nt_ai:
255 case Hexagon::PS_vstorerw_ai:
256 case Hexagon::PS_vstorerw_nt_ai:
259 case Hexagon::PS_vloadrv_ai:
260 case Hexagon::PS_vloadrv_nt_ai:
261 case Hexagon::PS_vstorerv_ai:
262 case Hexagon::PS_vstorerv_nt_ai:
263 case Hexagon::V6_vL32b_ai:
264 case Hexagon::V6_vS32b_ai: {
265 unsigned HwLen = HST.getVectorLength();
266 if (RealOffset % HwLen == 0) {
267 int VecOffset = RealOffset / HwLen;
273 if (!IsPair || (VecOffset + 1) % 16 != 0) {
274 RealOffset = (VecOffset & -16) * HwLen;
275 InstOffset = (VecOffset % 16 - 8) * HwLen;
288 bool PassedCall =
false;
292 if (SearchCount == SearchRange)
297 PassedCall |= BI.
isCall();
299 if (SeenVRegs.
size() > 1)
301 if (
Op.isReg() &&
Op.getReg().isVirtual())
309 if (!Op2.isImm() || Op2.getImm() != RealOffset)
313 if (R.isPhysical()) {
314 if (Defs.available(R))
316 }
else if (R.isVirtual()) {
321 if (!PassedCall && SeenVRegs.
size() <= 1)
334 BuildMI(MB, II,
DL, HII.get(Hexagon::A2_addi), ReuseBP)
339 RealOffset = InstOffset;
342 MI.getOperand(FIOp).ChangeToRegister(BP,
false,
false,
false);
343 MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
357 if (!HST.
useHVXOps() || NewRC->
getID() != Hexagon::HvxWRRegClass.getID())
359 bool SmallSrc = SrcRC->
getID() == Hexagon::HvxVRRegClass.getID();
360 bool SmallDst = DstRC->
getID() == Hexagon::HvxVRRegClass.getID();
361 if (!SmallSrc && !SmallDst)
368 for (
SlotIndex I =
S.start.getBaseIndex(),
E =
S.end.getBaseIndex();
369 I !=
E;
I =
I.getNextIndex()) {
377 if (SmallSrc == SmallDst) {
389 unsigned SmallReg = SmallSrc ? SrcReg : DstReg;
390 unsigned LargeReg = SmallSrc ? DstReg : SrcReg;
424 static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
425 static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
426 static const unsigned WSub[] = { Hexagon::wsub_lo, Hexagon::wsub_hi };
428 switch (RC.
getID()) {
429 case Hexagon::CtrRegs64RegClassID:
430 case Hexagon::DoubleRegsRegClassID:
432 case Hexagon::HvxWRRegClassID:
434 case Hexagon::HvxVQRRegClassID:
451 unsigned Kind)
const {
452 return &Hexagon::IntRegsRegClass;