LLVM 19.0.0git
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1//==- HexagonFrameLowering.h - Define frame lowering for Hexagon -*- C++ -*-==//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
12#include "Hexagon.h"
13#include "HexagonBlockRanges.h"
15#include "llvm/ADT/STLExtras.h"
19#include <vector>
21namespace llvm {
23class BitVector;
24class HexagonInstrInfo;
25class HexagonRegisterInfo;
26class MachineFunction;
27class MachineInstr;
28class MachineRegisterInfo;
29class TargetRegisterClass;
33 // First register which could possibly hold a variable argument.
38 void
40 SmallVectorImpl<int> &ObjectsToAllocate) const override;
42 // All of the prolog/epilog functionality, including saving and restoring
43 // callee-saved registers is handled in emitPrologue. This is to have the
44 // logic for shrink-wrapping in one place.
46 override;
48 override {}
50 bool enableCalleeSaveSkip(const MachineFunction &MF) const override;
55 const TargetRegisterInfo *TRI) const override {
56 return true;
57 }
59 bool
63 const TargetRegisterInfo *TRI) const override {
64 return true;
65 }
67 bool hasReservedCallFrame(const MachineFunction &MF) const override {
68 // We always reserve call frame as a part of the initial stack allocation.
69 return true;
70 }
72 bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override {
73 // Override this function to avoid calling hasFP before CSI is set
74 // (the default implementation calls hasFP).
75 return true;
76 }
80 MachineBasicBlock::iterator I) const override;
82 RegScavenger *RS = nullptr) const override;
84 RegScavenger *RS) const override;
86 bool targetHandlesStackFrameRounding() const override {
87 return true;
88 }
91 Register &FrameReg) const override;
92 bool hasFP(const MachineFunction &MF) const override;
94 const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries)
95 const override {
96 static const SpillSlot Offsets[] = {
97 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
98 { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 },
99 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 },
100 { Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 },
101 { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 },
102 { Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 }
103 };
104 NumEntries = std::size(Offsets);
105 return Offsets;
106 }
109 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
110 const override;
112 bool needsAligna(const MachineFunction &MF) const;
113 const MachineInstr *getAlignaInstr(const MachineFunction &MF) const;
118 using CSIVect = std::vector<CalleeSavedInfo>;
120 void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
121 Register SP, unsigned CF) const;
122 void insertPrologueInBlock(MachineBasicBlock &MBB, bool PrologueStubs) const;
123 void insertEpilogueInBlock(MachineBasicBlock &MBB) const;
124 void insertAllocframe(MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator InsertPt, unsigned NumBytes) const;
126 bool insertCSRSpillsInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
127 const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
128 bool insertCSRRestoresInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
129 const HexagonRegisterInfo &HRI) const;
130 void updateEntryPaths(MachineFunction &MF, MachineBasicBlock &SaveB) const;
131 bool updateExitPaths(MachineBasicBlock &MBB, MachineBasicBlock &RestoreB,
132 BitVector &DoneT, BitVector &DoneF, BitVector &Path) const;
133 void insertCFIInstructionsAt(MachineBasicBlock &MBB,
138 SmallVectorImpl<Register> &NewRegs) const;
139 bool expandStoreInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
141 SmallVectorImpl<Register> &NewRegs) const;
142 bool expandLoadInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
144 SmallVectorImpl<Register> &NewRegs) const;
145 bool expandStoreVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
147 SmallVectorImpl<Register> &NewRegs) const;
148 bool expandLoadVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
150 SmallVectorImpl<Register> &NewRegs) const;
151 bool expandStoreVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
153 SmallVectorImpl<Register> &NewRegs) const;
154 bool expandLoadVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
156 SmallVectorImpl<Register> &NewRegs) const;
157 bool expandStoreVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
159 SmallVectorImpl<Register> &NewRegs) const;
160 bool expandLoadVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
162 SmallVectorImpl<Register> &NewRegs) const;
163 bool expandSpillMacros(MachineFunction &MF,
164 SmallVectorImpl<Register> &NewRegs) const;
169 const TargetRegisterClass *RC) const;
170 void optimizeSpillSlots(MachineFunction &MF,
171 SmallVectorImpl<Register> &VRegs) const;
173 void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
174 MachineBasicBlock *&EpilogB) const;
176 void addCalleeSaveRegistersAsImpOperand(MachineInstr *MI, const CSIVect &CSI,
177 bool IsDef, bool IsKill) const;
178 bool shouldInlineCSR(const MachineFunction &MF, const CSIVect &CSI) const;
179 bool useSpillFunction(const MachineFunction &MF, const CSIVect &CSI) const;
180 bool useRestoreFunction(const MachineFunction &MF, const CSIVect &CSI) const;
181 bool mayOverflowFrameOffset(MachineFunction &MF) const;
184} // end namespace llvm
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
basic Basic Alias true
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
This file contains some templates that are useful if you are working with the STL at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
const MachineInstr * getAlignaInstr(const MachineFunction &MF) const
void insertCFIInstructions(MachineFunction &MF) const
bool enableCalleeSaveSkip(const MachineFunction &MF) const override
Returns true if the target can safely skip saving callee-saved registers for noreturn nounwind functi...
bool targetHandlesStackFrameRounding() const override
targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack...
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override
canSimplifyCallFramePseudos - When possible, it's best to simplify the call frame pseudo ops before d...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Perform most of the PEI work here:
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void orderFrameObjects(const MachineFunction &MF, SmallVectorImpl< int > &ObjectsToAllocate) const override
Order the symbols in the local stack frame.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
bool needsAligna(const MachineFunction &MF) const
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
Information about stack frame layout on the target.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
std::map< RegisterRef, RangeList > RegToRangeMap