LLVM  13.0.0git
Classes | Macros | Functions | Variables
ARMSLSHardening.cpp File Reference
#include "ARM.h"
#include "ARMInstrInfo.h"
#include "ARMSubtarget.h"
#include "llvm/CodeGen/IndirectThunks.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/IR/DebugLoc.h"
#include <cassert>
Include dependency graph for ARMSLSHardening.cpp:

Go to the source code of this file.

Classes

struct  ThunkNameRegMode
 

Macros

#define DEBUG_TYPE   "arm-sls-hardening"
 
#define ARM_SLS_HARDENING_NAME   "ARM sls hardening pass"
 

Functions

 INITIALIZE_PASS (ARMSLSHardening, "arm-sls-hardening", ARM_SLS_HARDENING_NAME, false, false) static void insertSpeculationBarrier(const ARMSubtarget *ST
 

Variables

MachineBasicBlockMBB
 
MachineBasicBlock MachineBasicBlock::iterator MBBI
 
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
 
MachineBasicBlock MachineBasicBlock::iterator DebugLoc bool AlwaysUseISBDSB
 
static const struct ThunkNameRegMode SLSBLRThunks []
 

Macro Definition Documentation

◆ ARM_SLS_HARDENING_NAME

#define ARM_SLS_HARDENING_NAME   "ARM sls hardening pass"

Definition at line 31 of file ARMSLSHardening.cpp.

◆ DEBUG_TYPE

#define DEBUG_TYPE   "arm-sls-hardening"

Definition at line 29 of file ARMSLSHardening.cpp.

Function Documentation

◆ INITIALIZE_PASS()

INITIALIZE_PASS ( ARMSLSHardening  ,
"arm-sls-hardening ,
ARM_SLS_HARDENING_NAME  ,
false  ,
false   
) const

Variable Documentation

◆ AlwaysUseISBDSB

Definition at line 74 of file ARMSLSHardening.cpp.

◆ DL

Definition at line 73 of file ARMSLSHardening.cpp.

◆ MBB

Definition at line 71 of file ARMSLSHardening.cpp.

◆ MBBI

Definition at line 72 of file ARMSLSHardening.cpp.

◆ SLSBLRThunks

const struct ThunkNameRegMode SLSBLRThunks[]
static
Initial value:
= {
{"__llvm_slsblr_thunk_arm_r0", ARM::R0, false},
{"__llvm_slsblr_thunk_arm_r1", ARM::R1, false},
{"__llvm_slsblr_thunk_arm_r2", ARM::R2, false},
{"__llvm_slsblr_thunk_arm_r3", ARM::R3, false},
{"__llvm_slsblr_thunk_arm_r4", ARM::R4, false},
{"__llvm_slsblr_thunk_arm_r5", ARM::R5, false},
{"__llvm_slsblr_thunk_arm_r6", ARM::R6, false},
{"__llvm_slsblr_thunk_arm_r7", ARM::R7, false},
{"__llvm_slsblr_thunk_arm_r8", ARM::R8, false},
{"__llvm_slsblr_thunk_arm_r9", ARM::R9, false},
{"__llvm_slsblr_thunk_arm_r10", ARM::R10, false},
{"__llvm_slsblr_thunk_arm_r11", ARM::R11, false},
{"__llvm_slsblr_thunk_arm_sp", ARM::SP, false},
{"__llvm_slsblr_thunk_arm_pc", ARM::PC, false},
{"__llvm_slsblr_thunk_thumb_r0", ARM::R0, true},
{"__llvm_slsblr_thunk_thumb_r1", ARM::R1, true},
{"__llvm_slsblr_thunk_thumb_r2", ARM::R2, true},
{"__llvm_slsblr_thunk_thumb_r3", ARM::R3, true},
{"__llvm_slsblr_thunk_thumb_r4", ARM::R4, true},
{"__llvm_slsblr_thunk_thumb_r5", ARM::R5, true},
{"__llvm_slsblr_thunk_thumb_r6", ARM::R6, true},
{"__llvm_slsblr_thunk_thumb_r7", ARM::R7, true},
{"__llvm_slsblr_thunk_thumb_r8", ARM::R8, true},
{"__llvm_slsblr_thunk_thumb_r9", ARM::R9, true},
{"__llvm_slsblr_thunk_thumb_r10", ARM::R10, true},
{"__llvm_slsblr_thunk_thumb_r11", ARM::R11, true},
{"__llvm_slsblr_thunk_thumb_sp", ARM::SP, true},
{"__llvm_slsblr_thunk_thumb_pc", ARM::PC, true},
}
R4
#define R4(n)
R2
#define R2(n)
R6
#define R6(n)