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14 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
15 #define LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
435 class NVPTXSubtarget;
452 unsigned Intrinsic)
const override;
487 EVT VT)
const override {
494 std::pair<unsigned, const TargetRegisterClass *>
510 std::optional<std::pair<unsigned, const APInt &>> VAInfo,
511 const CallBase &CB,
unsigned UniqueCallSite)
const;
519 std::vector<SDValue> &Ops,
549 int &ExtraSteps,
bool &UseOneConst,
550 bool Reciprocal)
const override;
558 EVT)
const override {
610 SDValue PerformDAGCombine(
SDNode *
N, DAGCombinerInfo &DCI)
const override;
@ TexUnified2DU32FloatLevel
Align getFunctionParamOptimizedAlign(const Function *F, Type *ArgTy, const DataLayout &DL) const
getFunctionParamOptimizedAlign - since function arguments are passed via .param space,...
@ TexUnifiedCubeArrayS32FloatLevel
This is an optimization pass for GlobalISel generic memory operations.
@ Tld4UnifiedR2DFloatFloat
@ TexUnifiedCubeU32FloatLevel
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
@ TexUnifiedCubeFloatFloatLevel
@ TexUnified1DArrayU32Float
@ TexUnified1DFloatFloatLevel
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
@ Tex1DArrayFloatFloatLevel
@ TexUnified1DArrayS32S32
@ TexUnified2DArrayFloatS32
Align getFunctionByValParamAlign(const Function *F, Type *ArgTy, Align InitialAlign, const DataLayout &DL) const
Helper for computing alignment of a device function byval parameter.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Represents one node in the SelectionDAG.
@ TexUnified2DU32FloatGrad
@ TexUnified3DS32FloatGrad
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
@ TexUnifiedCubeArrayU32Float
@ Tex1DArrayS32FloatLevel
@ TexUnified1DArrayS32Float
The instances of the Type class are immutable: once they are created, they are never changed.
@ TexUnified2DArrayU32S32
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Function Alias Analysis Results
@ TexUnified1DArrayU32S32
@ Tex2DArrayU32FloatLevel
@ TexUnifiedCubeArrayS32Float
unsigned const TargetRegisterInfo * TRI
@ TexUnified2DS32FloatLevel
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
unsigned combineRepeatedFPDivisors() const override
Indicate whether this target prefers to combine FDIVs with the same divisor.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
@ TexUnified2DArrayS32FloatGrad
@ Tld4UnifiedB2DFloatFloat
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
@ Tex2DArrayFloatFloatLevel
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
@ TexCubeArrayS32FloatLevel
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
@ TexUnifiedCubeFloatFloat
@ TexUnifiedCubeS32FloatLevel
@ TexUnified1DFloatFloatGrad
@ TexUnified1DArrayFloatS32
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps, bool &UseOneConst, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
@ TexUnifiedCubeArrayU32FloatLevel
bool usePrecSqrtF32() const
@ TexUnified3DS32FloatLevel
Analysis containing CSE Info
This struct is a compact representation of a valid (non-zero power of two) alignment.
AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.
@ TexUnified2DFloatFloatGrad
@ TexUnified1DArrayS32FloatLevel
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ TexCubeArrayU32FloatLevel
bool isIntegerTy() const
True if this is an instance of IntegerType.
@ TexUnified1DArrayS32FloatGrad
@ TexUnified3DU32FloatLevel
@ Tld4UnifiedG2DFloatFloat
An instruction for storing to memory.
const NVPTXTargetMachine * nvTM
@ TexUnified1DArrayFloatFloatGrad
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
@ Tex2DArrayS32FloatLevel
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
This is an important class for using LLVM in a threaded context.
@ TexUnified2DArrayU32FloatLevel
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
@ TexUnified2DArrayFloatFloatGrad
@ TexUnified2DArrayS32FloatLevel
@ TexUnified2DArrayS32Float
@ TexUnifiedCubeArrayFloatFloat
@ TexUnified3DFloatFloatLevel
@ TexUnified1DArrayU32FloatLevel
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
@ TexUnified2DFloatFloatLevel
@ TexUnified1DU32FloatLevel
int getDivF32Level() const
@ Tex1DArrayU32FloatLevel
@ TexUnifiedCubeArrayFloatFloatLevel
@ TexUnified3DU32FloatGrad
bool useF32FTZ(const MachineFunction &MF) const
std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &, const SmallVectorImpl< ISD::OutputArg > &, MaybeAlign retAlignment, std::optional< std::pair< unsigned, const APInt & >> VAInfo, const CallBase &CB, unsigned UniqueCallSite) const
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
bool isVector() const
Return true if this is a vector value type.
StringRef - Represent a constant reference to a string, i.e.
@ TexUnified2DArrayFloatFloat
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ TexUnified1DArrayFloatFloatLevel
@ TexUnified1DS32FloatLevel
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ Tex1DArrayFloatFloatGrad
@ TexUnified1DArrayFloatFloat
An instruction for reading from memory.
an instruction that atomically reads a memory location, combines it with another value,...
std::vector< ArgListEntry > ArgListTy
@ TexUnified2DArrayS32S32
@ TexUnified2DArrayFloatFloatLevel
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
@ TexUnified3DFloatFloatGrad
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
@ TexUnified2DS32FloatGrad
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
@ TexUnified1DArrayU32FloatGrad
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
@ Tld4UnifiedA2DFloatFloat
@ TexUnified1DU32FloatGrad
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
@ TexUnified1DS32FloatGrad
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
bool allowUnsafeFPMath(MachineFunction &MF) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
const char LLVMTargetMachineRef TM
This class represents a function call, abstracting a target machine's calling convention.
Level
Code generation optimization level.
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.
@ TexUnified2DArrayU32FloatGrad
@ TexUnified2DArrayU32Float
bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const
@ TexCubeArrayFloatFloatLevel
@ Tex2DArrayFloatFloatGrad
NVPTXTargetLowering(const NVPTXTargetMachine &TM, const NVPTXSubtarget &STI)
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.