14 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H 15 #define LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H 435 class NVPTXSubtarget;
452 unsigned Intrinsic)
const override;
472 EVT VT)
const override {
479 std::pair<unsigned, const TargetRegisterClass *>
502 std::vector<SDValue> &Ops,
532 int &ExtraSteps,
bool &UseOneConst,
533 bool Reciprocal)
const override;
541 EVT)
const override {
579 SDValue PerformDAGCombine(
SDNode *
N, DAGCombinerInfo &DCI)
const override;
unsigned combineRepeatedFPDivisors() const override
Indicate whether this target prefers to combine FDIVs with the same divisor.
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
This class represents lattice values for constants.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
This class represents a function call, abstracting a target machine's calling convention.
Function Alias Analysis Results
bool useF32FTZ(const MachineFunction &MF) const
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type.
unsigned const TargetRegisterInfo * TRI
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isIntegerTy() const
True if this is an instance of IntegerType.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
int getDivF32Level() const
bool usePrecSqrtF32() const
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
Analysis containing CSE Info
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
The instances of the Type class are immutable: once they are created, they are never changed.
This is an important class for using LLVM in a threaded context.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
std::vector< ArgListEntry > ArgListTy
bool allowUnsafeFPMath(MachineFunction &MF) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This struct is a compact representation of a valid (non-zero power of two) alignment.
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps, bool &UseOneConst, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
NVPTXTargetLowering(const NVPTXTargetMachine &TM, const NVPTXSubtarget &STI)
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Represents one node in the SelectionDAG.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool isVector() const
Return true if this is a vector value type.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &, const SmallVectorImpl< ISD::OutputArg > &, MaybeAlign retAlignment, const CallBase &CB) const
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
StringRef - Represent a constant reference to a string, i.e.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This file describes how to lower LLVM code to machine code.
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const NVPTXTargetMachine * nvTM