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NVPTXISelLowering.h
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1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
15 #define LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H
16 
17 #include "NVPTX.h"
20 
21 namespace llvm {
22 namespace NVPTXISD {
23 enum NodeType : unsigned {
24  // Start the numbering from where ISD NodeType finishes.
61 
64  LDGV2, // LDG.v2
65  LDGV4, // LDG.v4
66  LDUV2, // LDU.v2
67  LDUV4, // LDU.v4
76  StoreParamS32, // to sext and store a <32bit value, not used currently
77  StoreParamU32, // to zext and store a <32bit value, not used currently
81 
82  // Texture intrinsics
251 
252  // Surface intrinsics
264 
276 
288 
300 
312 
324 
336 
348 
360 
372 
384 
396 
408 
420 
432 };
433 }
434 
435 class NVPTXSubtarget;
436 
437 //===--------------------------------------------------------------------===//
438 // TargetLowering Implementation
439 //===--------------------------------------------------------------------===//
441 public:
442  explicit NVPTXTargetLowering(const NVPTXTargetMachine &TM,
443  const NVPTXSubtarget &STI);
444  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
445 
447 
448  const char *getTargetNodeName(unsigned Opcode) const override;
449 
451  MachineFunction &MF,
452  unsigned Intrinsic) const override;
453 
454  /// isLegalAddressingMode - Return true if the addressing mode represented
455  /// by AM is legal for this target, for a load/store of the specified type
456  /// Used to guide target specific optimizations, like loop strength
457  /// reduction (LoopStrengthReduce.cpp) and memory optimization for
458  /// address mode (CodeGenPrepare.cpp)
459  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
460  unsigned AS,
461  Instruction *I = nullptr) const override;
462 
463  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override {
464  // Truncating 64-bit to 32-bit is free in SASS.
465  if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy())
466  return false;
467  return SrcTy->getPrimitiveSizeInBits() == 64 &&
468  DstTy->getPrimitiveSizeInBits() == 32;
469  }
470 
472  EVT VT) const override {
473  if (VT.isVector())
474  return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
475  return MVT::i1;
476  }
477 
478  ConstraintType getConstraintType(StringRef Constraint) const override;
479  std::pair<unsigned, const TargetRegisterClass *>
481  StringRef Constraint, MVT VT) const override;
482 
484  bool isVarArg,
486  const SDLoc &dl, SelectionDAG &DAG,
487  SmallVectorImpl<SDValue> &InVals) const override;
488 
489  SDValue LowerCall(CallLoweringInfo &CLI,
490  SmallVectorImpl<SDValue> &InVals) const override;
491 
492  std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &,
494  MaybeAlign retAlignment, const CallBase &CB) const;
495 
496  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
498  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
499  SelectionDAG &DAG) const override;
500 
501  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
502  std::vector<SDValue> &Ops,
503  SelectionDAG &DAG) const override;
504 
506 
507  // PTX always uses 32-bit shift amounts
508  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
509  return MVT::i32;
510  }
511 
513  getPreferredVectorAction(MVT VT) const override;
514 
515  // Get the degree of precision we want from 32-bit floating point division
516  // operations.
517  //
518  // 0 - Use ptx div.approx
519  // 1 - Use ptx.div.full (approximate, but less so than div.approx)
520  // 2 - Use IEEE-compliant div instructions, if available.
521  int getDivF32Level() const;
522 
523  // Get whether we should use a precise or approximate 32-bit floating point
524  // sqrt instruction.
525  bool usePrecSqrtF32() const;
526 
527  // Get whether we should use instructions that flush floating-point denormals
528  // to sign-preserving zero.
529  bool useF32FTZ(const MachineFunction &MF) const;
530 
532  int &ExtraSteps, bool &UseOneConst,
533  bool Reciprocal) const override;
534 
535  unsigned combineRepeatedFPDivisors() const override { return 2; }
536 
537  bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;
538  bool allowUnsafeFPMath(MachineFunction &MF) const;
539 
541  EVT) const override {
542  return true;
543  }
544 
545  bool enableAggressiveFMAFusion(EVT VT) const override { return true; }
546 
547  // The default is to transform llvm.ctlz(x, false) (where false indicates that
548  // x == 0 is not undefined behavior) into a branch that checks whether x is 0
549  // and avoids calling ctlz in that case. We have a dedicated ctlz
550  // instruction, so we say that ctlz is cheap to speculate.
551  bool isCheapToSpeculateCtlz() const override { return true; }
552 
553 private:
554  const NVPTXSubtarget &STI; // cache the subtarget here
555  SDValue getParamSymbol(SelectionDAG &DAG, int idx, EVT) const;
556 
557  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
558  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
559  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
560 
561  SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
562  SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
563  SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
564 
565  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
566  SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
567 
568  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
569  SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
570  SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
571 
572  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
573  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
574 
575  SDValue LowerSelect(SDValue Op, SelectionDAG &DAG) const;
576 
577  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
578  SelectionDAG &DAG) const override;
579  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
580 
581  Align getArgumentAlignment(SDValue Callee, const CallBase *CB, Type *Ty,
582  unsigned Idx, const DataLayout &DL) const;
583 };
584 } // namespace llvm
585 
586 #endif
unsigned combineRepeatedFPDivisors() const override
Indicate whether this target prefers to combine FDIVs with the same divisor.
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1186
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:111
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
This class represents a function call, abstracting a target machine's calling convention.
Function Alias Analysis Results
bool useF32FTZ(const MachineFunction &MF) const
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type.
unsigned const TargetRegisterInfo * TRI
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1164
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:202
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
Analysis containing CSE Info
Definition: CSEInfo.cpp:25
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const
Machine Value Type.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:122
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:298
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:35
bool allowUnsafeFPMath(MachineFunction &MF) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps, bool &UseOneConst, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:119
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:223
NVPTXTargetLowering(const NVPTXTargetMachine &TM, const NVPTXSubtarget &STI)
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1198
Represents one node in the SelectionDAG.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:74
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:146
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
#define I(x, y, z)
Definition: MD5.cpp:59
#define N
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &, const SmallVectorImpl< ISD::OutputArg > &, MaybeAlign retAlignment, const CallBase &CB) const
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This file describes how to lower LLVM code to machine code.
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const NVPTXTargetMachine * nvTM