LLVM 20.0.0git
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llvm::SelectionDAG Class Reference

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representation suitable for instruction selection. More...

#include "llvm/CodeGen/SelectionDAG.h"

Classes

struct  DAGNodeDeletedListener
 
struct  DAGNodeInsertedListener
 
struct  DAGUpdateListener
 Clients of various APIs that cause global effects on the DAG can optionally implement this interface. More...
 
class  FlagInserter
 Help to insert SDNodeFlags automatically in transforming. More...
 

Public Types

enum  OverflowKind { OFK_Never , OFK_Sometime , OFK_Always }
 Used to represent the possible overflow behavior of an operation. More...
 
using allnodes_const_iterator = ilist< SDNode >::const_iterator
 
using allnodes_iterator = ilist< SDNode >::iterator
 

Public Member Functions

 SelectionDAG (const TargetMachine &TM, CodeGenOptLevel)
 
 SelectionDAG (const SelectionDAG &)=delete
 
SelectionDAGoperator= (const SelectionDAG &)=delete
 
 ~SelectionDAG ()
 
void init (MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, UniformityInfo *UA, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin, MachineModuleInfo &MMI, FunctionVarLocs const *FnVarLocs)
 Prepare this SelectionDAG to process code in the given MachineFunction.
 
void init (MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, MachineFunctionAnalysisManager &AM, const TargetLibraryInfo *LibraryInfo, UniformityInfo *UA, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin, MachineModuleInfo &MMI, FunctionVarLocs const *FnVarLocs)
 
void setFunctionLoweringInfo (FunctionLoweringInfo *FuncInfo)
 
void clear ()
 Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
 
MachineFunctiongetMachineFunction () const
 
const PassgetPass () const
 
MachineFunctionAnalysisManagergetMFAM ()
 
CodeGenOptLevel getOptLevel () const
 
const DataLayoutgetDataLayout () const
 
const TargetMachinegetTarget () const
 
const TargetSubtargetInfogetSubtarget () const
 
template<typename STC >
const STC & getSubtarget () const
 
const TargetLoweringgetTargetLoweringInfo () const
 
const TargetLibraryInfogetLibInfo () const
 
const SelectionDAGTargetInfogetSelectionDAGInfo () const
 
const UniformityInfogetUniformityInfo () const
 
const FunctionVarLocsgetFunctionVarLocs () const
 Returns the result of the AssignmentTrackingAnalysis pass if it's available, otherwise return nullptr.
 
LLVMContextgetContext () const
 
OptimizationRemarkEmittergetORE () const
 
ProfileSummaryInfogetPSI () const
 
BlockFrequencyInfogetBFI () const
 
MachineModuleInfogetMMI () const
 
FlagInsertergetFlagInserter ()
 
void setFlagInserter (FlagInserter *FI)
 
LLVM_DUMP_METHOD void dumpDotGraph (const Twine &FileName, const Twine &Title)
 Just dump dot graph to a user-provided path and title.
 
void viewGraph (const std::string &Title)
 Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
 
void viewGraph ()
 
void clearGraphAttrs ()
 Clear all previously defined node graph attributes.
 
void setGraphAttrs (const SDNode *N, const char *Attrs)
 Set graph attributes for a node. (eg. "color=red".)
 
std::string getGraphAttrs (const SDNode *N) const
 Get graph attributes for a node.
 
void setGraphColor (const SDNode *N, const char *Color)
 Convenience for setting node color attribute.
 
void setSubgraphColor (SDNode *N, const char *Color)
 Convenience for setting subgraph color attribute.
 
allnodes_const_iterator allnodes_begin () const
 
allnodes_const_iterator allnodes_end () const
 
allnodes_iterator allnodes_begin ()
 
allnodes_iterator allnodes_end ()
 
ilist< SDNode >::size_type allnodes_size () const
 
iterator_range< allnodes_iteratorallnodes ()
 
iterator_range< allnodes_const_iteratorallnodes () const
 
const SDValuegetRoot () const
 Return the root tag of the SelectionDAG.
 
SDValue getEntryNode () const
 Return the token chain corresponding to the entry of the function.
 
const SDValuesetRoot (SDValue N)
 Set the current root tag of the SelectionDAG.
 
void VerifyDAGDivergence ()
 
void Combine (CombineLevel Level, AAResults *AA, CodeGenOptLevel OptLevel)
 This iterates over the nodes in the SelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes.
 
bool LegalizeTypes ()
 This transforms the SelectionDAG into a SelectionDAG that only uses types natively supported by the target.
 
void Legalize ()
 This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction selector, as indicated by the TargetLowering object.
 
bool LegalizeOp (SDNode *N, SmallSetVector< SDNode *, 16 > &UpdatedNodes)
 Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target instruction selector, as indicated by the TargetLowering object.
 
bool LegalizeVectors ()
 This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported by the target.
 
void RemoveDeadNodes ()
 This method deletes all unreachable nodes in the SelectionDAG.
 
void DeleteNode (SDNode *N)
 Remove the specified node from the system.
 
SDVTList getVTList (EVT VT)
 Return an SDVTList that represents the list of values specified.
 
SDVTList getVTList (EVT VT1, EVT VT2)
 
SDVTList getVTList (EVT VT1, EVT VT2, EVT VT3)
 
SDVTList getVTList (EVT VT1, EVT VT2, EVT VT3, EVT VT4)
 
SDVTList getVTList (ArrayRef< EVT > VTs)
 
SDValue getGlobalAddress (const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
 
SDValue getTargetGlobalAddress (const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
 
SDValue getFrameIndex (int FI, EVT VT, bool isTarget=false)
 
SDValue getTargetFrameIndex (int FI, EVT VT)
 
SDValue getJumpTable (int JTI, EVT VT, bool isTarget=false, unsigned TargetFlags=0)
 
SDValue getTargetJumpTable (int JTI, EVT VT, unsigned TargetFlags=0)
 
SDValue getJumpTableDebugInfo (int JTI, SDValue Chain, const SDLoc &DL)
 
SDValue getConstantPool (const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
 
SDValue getTargetConstantPool (const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
 
SDValue getConstantPool (MachineConstantPoolValue *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
 
SDValue getTargetConstantPool (MachineConstantPoolValue *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
 
SDValue getBasicBlock (MachineBasicBlock *MBB)
 
SDValue getExternalSymbol (const char *Sym, EVT VT)
 
SDValue getTargetExternalSymbol (const char *Sym, EVT VT, unsigned TargetFlags=0)
 
SDValue getMCSymbol (MCSymbol *Sym, EVT VT)
 
SDValue getValueType (EVT)
 
SDValue getRegister (unsigned Reg, EVT VT)
 
SDValue getRegisterMask (const uint32_t *RegMask)
 
SDValue getEHLabel (const SDLoc &dl, SDValue Root, MCSymbol *Label)
 
SDValue getLabelNode (unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label)
 
SDValue getBlockAddress (const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
 
SDValue getTargetBlockAddress (const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
 
SDValue getCopyToReg (SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
 
SDValue getCopyToReg (SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N, SDValue Glue)
 
SDValue getCopyToReg (SDValue Chain, const SDLoc &dl, SDValue Reg, SDValue N, SDValue Glue)
 
SDValue getCopyFromReg (SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
 
SDValue getCopyFromReg (SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT, SDValue Glue)
 
SDValue getCondCode (ISD::CondCode Cond)
 
SDValue getVectorShuffle (EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
 Return an ISD::VECTOR_SHUFFLE node.
 
SDValue getBuildVector (EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
 Return an ISD::BUILD_VECTOR node.
 
SDValue getBuildVector (EVT VT, const SDLoc &DL, ArrayRef< SDUse > Ops)
 Return an ISD::BUILD_VECTOR node.
 
SDValue getSplatBuildVector (EVT VT, const SDLoc &DL, SDValue Op)
 Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
 
SDValue getSplatVector (EVT VT, const SDLoc &DL, SDValue Op)
 
SDValue getSplat (EVT VT, const SDLoc &DL, SDValue Op)
 Returns a node representing a splat of one value into all lanes of the provided vector type.
 
SDValue getStepVector (const SDLoc &DL, EVT ResVT, const APInt &StepVal)
 Returns a vector of type ResVT whose elements contain the linear sequence <0, Step, Step * 2, Step * 3, ...>
 
SDValue getStepVector (const SDLoc &DL, EVT ResVT)
 Returns a vector of type ResVT whose elements contain the linear sequence <0, 1, 2, 3, ...>
 
SDValue getCommutedVectorShuffle (const ShuffleVectorSDNode &SV)
 Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands.
 
SDValue getFPExtendOrRound (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by truncation).
 
std::pair< SDValue, SDValuegetStrictFPExtendOrRound (SDValue Op, SDValue Chain, const SDLoc &DL, EVT VT)
 Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending or rounding (by truncation).
 
SDValue getAnyExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncating it.
 
SDValue getSExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or truncating it.
 
SDValue getZExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or truncating it.
 
SDValue getExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT, unsigned Opcode)
 Convert Op, which must be of integer type, to the integer type VT, by either any/sign/zero-extending (depending on IsAny / IsSigned) or truncating it.
 
SDValue getExtOrTrunc (bool IsSigned, SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by either sign/zero-extending (depending on IsSigned) or truncating it.
 
SDValue getBitcastedAnyExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either any-extending or truncating it.
 
SDValue getBitcastedSExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either sign-extending or truncating it.
 
SDValue getBitcastedZExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either zero-extending or truncating it.
 
SDValue getZeroExtendInReg (SDValue Op, const SDLoc &DL, EVT VT)
 Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
 
SDValue getVPZeroExtendInReg (SDValue Op, SDValue Mask, SDValue EVL, const SDLoc &DL, EVT VT)
 Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
 
SDValue getPtrExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT)
 Convert Op, which must be of integer type, to the integer type VT, by either truncating it or performing either zero or sign extension as appropriate extension for the pointer's semantics.
 
SDValue getPtrExtendInReg (SDValue Op, const SDLoc &DL, EVT VT)
 Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy value.
 
SDValue getBoolExtOrTrunc (SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT)
 Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it.
 
SDValue getNegative (SDValue Val, const SDLoc &DL, EVT VT)
 Create negative operation as (SUB 0, Val).
 
SDValue getNOT (const SDLoc &DL, SDValue Val, EVT VT)
 Create a bitwise NOT operation as (XOR Val, -1).
 
SDValue getLogicalNOT (const SDLoc &DL, SDValue Val, EVT VT)
 Create a logical NOT operation as (XOR Val, BooleanOne).
 
SDValue getVPLogicalNOT (const SDLoc &DL, SDValue Val, SDValue Mask, SDValue EVL, EVT VT)
 Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask, EVL).
 
SDValue getVPZExtOrTrunc (const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
 Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT, by performing either vector-predicated zext or truncating it.
 
SDValue getVPPtrExtOrTrunc (const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
 Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT, by either truncating it or performing either vector-predicated zero or sign extension as appropriate extension for the pointer's semantics.
 
SDValue getMemBasePlusOffset (SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
 Returns sum of the base pointer and offset.
 
SDValue getMemBasePlusOffset (SDValue Base, SDValue Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
 
SDValue getObjectPtrOffset (const SDLoc &SL, SDValue Ptr, TypeSize Offset)
 Create an add instruction with appropriate flags when used for addressing some offset of an object.
 
SDValue getObjectPtrOffset (const SDLoc &SL, SDValue Ptr, SDValue Offset)
 
SDValue getCALLSEQ_START (SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
 Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and OutSize specifies part of the frame set up prior to the sequence.
 
SDValue getCALLSEQ_END (SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
 Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
 
SDValue getCALLSEQ_END (SDValue Chain, uint64_t Size1, uint64_t Size2, SDValue Glue, const SDLoc &DL)
 
bool isUndef (unsigned Opcode, ArrayRef< SDValue > Ops)
 Return true if the result of this operation is always undefined.
 
SDValue getUNDEF (EVT VT)
 Return an UNDEF node. UNDEF does not have a useful SDLoc.
 
SDValue getVScale (const SDLoc &DL, EVT VT, APInt MulImm, bool ConstantFold=true)
 Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
 
SDValue getElementCount (const SDLoc &DL, EVT VT, ElementCount EC, bool ConstantFold=true)
 
SDValue getGLOBAL_OFFSET_TABLE (EVT VT)
 Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
 Gets or creates the specified node.
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, const SDNodeFlags Flags)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, ArrayRef< EVT > ResultTys, ArrayRef< SDValue > Ops)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, ArrayRef< SDValue > Ops)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT)
 Gets or creates the specified node.
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand, const SDNodeFlags Flags)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, const SDNodeFlags Flags)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, const SDNodeFlags Flags)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4)
 
SDValue getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5)
 
SDValue getStackArgumentTokenFactor (SDValue Chain)
 Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
 
SDValue getMemcpy (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
 
SDValue getMemmove (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
 
SDValue getMemset (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
 
SDValue getAtomicMemcpy (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
 
SDValue getAtomicMemmove (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
 
SDValue getAtomicMemset (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo)
 
SDValue getSetCC (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
 Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SDValue.
 
SDValue getSetCCVP (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Mask, SDValue EVL)
 Helper function to make it easier to build VP_SETCCs if you just have an ISD::CondCode instead of an SDValue.
 
SDValue getSelect (const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS, SDNodeFlags Flags=SDNodeFlags())
 Helper function to make it easier to build Select's if you just have operands and don't want to check for vector.
 
SDValue getSelectCC (const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
 Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an SDValue.
 
SDValue simplifySelect (SDValue Cond, SDValue TVal, SDValue FVal)
 Try to simplify a select/vselect into 1 of its operands or a constant.
 
SDValue simplifyShift (SDValue X, SDValue Y)
 Try to simplify a shift into 1 of its operands or a constant.
 
SDValue simplifyFPBinop (unsigned Opcode, SDValue X, SDValue Y, SDNodeFlags Flags)
 Try to simplify a floating-point binary operation into 1 of its operands or a constant.
 
SDValue getVAArg (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
 VAArg produces a result and token chain, and takes a pointer and a source value as input.
 
SDValue getAtomicCmpSwap (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
 Gets a node for an atomic cmpxchg op.
 
SDValue getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
 Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
 
SDValue getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO)
 Gets a node for an atomic op, produces result and chain and takes 1 operand.
 
SDValue getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTList, ArrayRef< SDValue > Ops, MachineMemOperand *MMO)
 Gets a node for an atomic op, produces result and chain and takes N operands.
 
SDValue getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
 Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
 
SDValue getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, MaybeAlign Alignment=std::nullopt, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
 
SDValue getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachineMemOperand *MMO)
 
SDValue getLifetimeNode (bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex, int64_t Size, int64_t Offset=-1)
 Creates a LifetimeSDNode that starts (IsStart==true) or ends (IsStart==false) the lifetime of the portion of FrameIndex between offsets Offset and Offset + Size.
 
SDValue getPseudoProbeNode (const SDLoc &Dl, SDValue Chain, uint64_t Guid, uint64_t Index, uint32_t Attr)
 Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing, as well as the attributes attr of the probe.
 
SDValue getMergeValues (ArrayRef< SDValue > Ops, const SDLoc &dl)
 Create a MERGE_VALUES node from the given operands.
 
SDValue getLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
 Loads are not normal binary operators: their result type is not determined by their operands, and they produce a value AND a token chain.
 
SDValue getLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO)
 
SDValue getExtLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
 
SDValue getExtLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
 
SDValue getIndexedLoad (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
 
SDValue getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
 
SDValue getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
 
SDValue getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, EVT MemVT, MachineMemOperand *MMO)
 
SDValue getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
 Helper function to build ISD::STORE nodes.
 
SDValue getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
 
SDValue getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachineMemOperand *MMO)
 
SDValue getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
 
SDValue getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
 
SDValue getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, EVT SVT, MachineMemOperand *MMO)
 
SDValue getIndexedStore (SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
 
SDValue getLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false)
 
SDValue getLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, bool IsExpanding=false)
 
SDValue getLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
 
SDValue getLoadVP (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false)
 
SDValue getLoadVP (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachineMemOperand *MMO, bool IsExpanding=false)
 
SDValue getExtLoadVP (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsExpanding=false)
 
SDValue getExtLoadVP (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
 
SDValue getIndexedLoadVP (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
 
SDValue getStoreVP (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
 
SDValue getTruncStoreVP (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsCompressing=false)
 
SDValue getTruncStoreVP (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false)
 
SDValue getIndexedStoreVP (SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
 
SDValue getStridedLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
 
SDValue getStridedLoadVP (EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, MachineMemOperand *MMO, bool IsExpanding=false)
 
SDValue getExtStridedLoadVP (ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
 
SDValue getStridedStoreVP (SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
 
SDValue getTruncStridedStoreVP (SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false)
 
SDValue getGatherVP (SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
 
SDValue getScatterVP (SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
 
SDValue getMaskedLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, ISD::LoadExtType, bool IsExpanding=false)
 
SDValue getIndexedMaskedLoad (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
 
SDValue getMaskedStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
 
SDValue getIndexedMaskedStore (SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
 
SDValue getMaskedGather (SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy)
 
SDValue getMaskedScatter (SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTruncating=false)
 
SDValue getMaskedHistogram (SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
 
SDValue getGetFPEnv (SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
 
SDValue getSetFPEnv (SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
 
SDValue getSrcValue (const Value *v)
 Construct a node to track a Value* through the backend.
 
SDValue getMDNode (const MDNode *MD)
 Return an MDNodeSDNode which holds an MDNode.
 
SDValue getBitcast (EVT VT, SDValue V)
 Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
 
SDValue getAddrSpaceCast (const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
 Return an AddrSpaceCastSDNode.
 
SDValue getFreeze (SDValue V)
 Return a freeze using the SDLoc of the value operand.
 
SDValue getAssertAlign (const SDLoc &DL, SDValue V, Align A)
 Return an AssertAlignSDNode.
 
void canonicalizeCommutativeBinop (unsigned Opcode, SDValue &N1, SDValue &N2) const
 Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite order.
 
SDValue getShiftAmountOperand (EVT LHSTy, SDValue Op)
 Return the specified value casted to the target's desired shift amount type.
 
SDValue expandVAArg (SDNode *Node)
 Expand the specified ISD::VAARG node as the Legalize pass would.
 
SDValue expandVACopy (SDNode *Node)
 Expand the specified ISD::VACOPY node as the Legalize pass would.
 
SDValue getSymbolFunctionGlobalAddress (SDValue Op, Function **TargetFunction=nullptr)
 Return a GlobalAddress of the function from the current module with name matching the given ExternalSymbol.
 
SDNodeUpdateNodeOperands (SDNode *N, SDValue Op)
 Mutate the specified node in-place to have the specified operands.
 
SDNodeUpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2)
 
SDNodeUpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3)
 
SDNodeUpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4)
 
SDNodeUpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5)
 
SDNodeUpdateNodeOperands (SDNode *N, ArrayRef< SDValue > Ops)
 
SDValue getTokenFactor (const SDLoc &DL, SmallVectorImpl< SDValue > &Vals)
 Creates a new TokenFactor containing Vals.
 
void setNodeMemRefs (MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
 Mutate the specified machine node's memory references to the provided list.
 
bool calculateDivergence (SDNode *N)
 
void updateDivergence (SDNode *N)
 
SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT)
 These are used for target selectors to mutate the specified node to have the specified return type, Target opcode, and operands.
 
SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1)
 
SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2)
 
SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3)
 
SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, ArrayRef< SDValue > Ops)
 
SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2)
 
SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, ArrayRef< SDValue > Ops)
 
SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, ArrayRef< SDValue > Ops)
 
SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2)
 
SDNodeSelectNodeTo (SDNode *N, unsigned MachineOpc, SDVTList VTs, ArrayRef< SDValue > Ops)
 
SDNodeMorphNodeTo (SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
 This mutates the specified node to have the specified return type, opcode, and operands.
 
SDNodemutateStrictFPToFP (SDNode *Node)
 Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain and dropping the metadata arguments.
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT)
 These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, ArrayRef< SDValue > Ops)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, ArrayRef< SDValue > Ops)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, ArrayRef< SDValue > Ops)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, ArrayRef< EVT > ResultTys, ArrayRef< SDValue > Ops)
 
MachineSDNodegetMachineNode (unsigned Opcode, const SDLoc &dl, SDVTList VTs, ArrayRef< SDValue > Ops)
 
SDValue getTargetExtractSubreg (int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
 A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
 
SDValue getTargetInsertSubreg (int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
 A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
 
SDNodegetNodeIfExists (unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags)
 Get the specified node if it's already available, or else return NULL.
 
SDNodegetNodeIfExists (unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops)
 getNodeIfExists - Get the specified node if it's already available, or else return NULL.
 
bool doesNodeExist (unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops)
 Check if a node exists without modifying its flags.
 
SDDbgValuegetDbgValue (DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O)
 Creates a SDDbgValue node.
 
SDDbgValuegetConstantDbgValue (DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O)
 Creates a constant SDDbgValue node.
 
SDDbgValuegetFrameIndexDbgValue (DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O)
 Creates a FrameIndex SDDbgValue node.
 
SDDbgValuegetFrameIndexDbgValue (DIVariable *Var, DIExpression *Expr, unsigned FI, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O)
 Creates a FrameIndex SDDbgValue node.
 
SDDbgValuegetVRegDbgValue (DIVariable *Var, DIExpression *Expr, unsigned VReg, bool IsIndirect, const DebugLoc &DL, unsigned O)
 Creates a VReg SDDbgValue node.
 
SDDbgValuegetDbgValueList (DIVariable *Var, DIExpression *Expr, ArrayRef< SDDbgOperand > Locs, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O, bool IsVariadic)
 Creates a SDDbgValue node from a list of locations.
 
SDDbgLabelgetDbgLabel (DILabel *Label, const DebugLoc &DL, unsigned O)
 Creates a SDDbgLabel node.
 
void transferDbgValues (SDValue From, SDValue To, unsigned OffsetInBits=0, unsigned SizeInBits=0, bool InvalidateDbg=true)
 Transfer debug values from one node to another, while optionally generating fragment expressions for split-up values.
 
void RemoveDeadNode (SDNode *N)
 Remove the specified node from the system.
 
void RemoveDeadNodes (SmallVectorImpl< SDNode * > &DeadNodes)
 This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result.
 
void ReplaceAllUsesWith (SDValue From, SDValue To)
 Modify anything using 'From' to use 'To' instead.
 
void ReplaceAllUsesWith (SDNode *From, SDNode *To)
 ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
 
void ReplaceAllUsesWith (SDNode *From, const SDValue *To)
 ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
 
void ReplaceAllUsesOfValueWith (SDValue From, SDValue To)
 Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
 
void ReplaceAllUsesOfValuesWith (const SDValue *From, const SDValue *To, unsigned Num)
 Like ReplaceAllUsesOfValueWith, but for multiple values at once.
 
SDValue makeEquivalentMemoryOrdering (SDValue OldChain, SDValue NewMemOpChain)
 If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor.
 
SDValue makeEquivalentMemoryOrdering (LoadSDNode *OldLoad, SDValue NewMemOp)
 If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor.
 
unsigned AssignTopologicalOrder ()
 Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order.
 
void RepositionNode (allnodes_iterator Position, SDNode *N)
 Move node N in the AllNodes list to be immediately before the given iterator Position.
 
void AddDbgValue (SDDbgValue *DB, bool isParameter)
 Add a dbg_value SDNode.
 
void AddDbgLabel (SDDbgLabel *DB)
 Add a dbg_label SDNode.
 
ArrayRef< SDDbgValue * > GetDbgValues (const SDNode *SD) const
 Get the debug values which reference the given SDNode.
 
bool hasDebugValues () const
 Return true if there are any SDDbgValue nodes associated with this SelectionDAG.
 
SDDbgInfo::DbgIterator DbgBegin () const
 
SDDbgInfo::DbgIterator DbgEnd () const
 
SDDbgInfo::DbgIterator ByvalParmDbgBegin () const
 
SDDbgInfo::DbgIterator ByvalParmDbgEnd () const
 
SDDbgInfo::DbgLabelIterator DbgLabelBegin () const
 
SDDbgInfo::DbgLabelIterator DbgLabelEnd () const
 
void salvageDebugInfo (SDNode &N)
 To be invoked on an SDNode that is slated to be erased.
 
void dump () const
 
Align getReducedAlign (EVT VT, bool UseABI)
 In most cases this function returns the ABI alignment for a given type, except for illegal vector types where the alignment exceeds that of the stack.
 
SDValue CreateStackTemporary (TypeSize Bytes, Align Alignment)
 Create a stack temporary based on the size in bytes and the alignment.
 
SDValue CreateStackTemporary (EVT VT, unsigned minAlign=1)
 Create a stack temporary, suitable for holding the specified value type.
 
SDValue CreateStackTemporary (EVT VT1, EVT VT2)
 Create a stack temporary suitable for holding either of the specified value types.
 
SDValue FoldSymbolOffset (unsigned Opcode, EVT VT, const GlobalAddressSDNode *GA, const SDNode *N2)
 
SDValue FoldConstantArithmetic (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SDNodeFlags Flags=SDNodeFlags())
 
SDValue foldConstantFPMath (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
 Fold floating-point operations when all operands are constants and/or undefined.
 
SDValue FoldSetCC (EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl)
 Constant fold a setcc to true or false.
 
bool SignBitIsZero (SDValue Op, unsigned Depth=0) const
 Return true if the sign bit of Op is known to be zero.
 
bool MaskedValueIsZero (SDValue Op, const APInt &Mask, unsigned Depth=0) const
 Return true if 'Op & Mask' is known to be zero.
 
bool MaskedValueIsZero (SDValue Op, const APInt &Mask, const APInt &DemandedElts, unsigned Depth=0) const
 Return true if 'Op & Mask' is known to be zero in DemandedElts.
 
bool MaskedVectorIsZero (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
 Return true if 'Op' is known to be zero in DemandedElts.
 
bool MaskedValueIsAllOnes (SDValue Op, const APInt &Mask, unsigned Depth=0) const
 Return true if '(Op & Mask) == Mask'.
 
APInt computeVectorKnownZeroElements (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
 For each demanded element of a vector, see if it is known to be zero.
 
KnownBits computeKnownBits (SDValue Op, unsigned Depth=0) const
 Determine which bits of Op are known to be either zero or one and return them in Known.
 
KnownBits computeKnownBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
 Determine which bits of Op are known to be either zero or one and return them in Known.
 
OverflowKind computeOverflowForSignedAdd (SDValue N0, SDValue N1) const
 Determine if the result of the signed addition of 2 nodes can overflow.
 
OverflowKind computeOverflowForUnsignedAdd (SDValue N0, SDValue N1) const
 Determine if the result of the unsigned addition of 2 nodes can overflow.
 
OverflowKind computeOverflowForAdd (bool IsSigned, SDValue N0, SDValue N1) const
 Determine if the result of the addition of 2 nodes can overflow.
 
bool willNotOverflowAdd (bool IsSigned, SDValue N0, SDValue N1) const
 Determine if the result of the addition of 2 nodes can never overflow.
 
OverflowKind computeOverflowForSignedSub (SDValue N0, SDValue N1) const
 Determine if the result of the signed sub of 2 nodes can overflow.
 
OverflowKind computeOverflowForUnsignedSub (SDValue N0, SDValue N1) const
 Determine if the result of the unsigned sub of 2 nodes can overflow.
 
OverflowKind computeOverflowForSub (bool IsSigned, SDValue N0, SDValue N1) const
 Determine if the result of the sub of 2 nodes can overflow.
 
bool willNotOverflowSub (bool IsSigned, SDValue N0, SDValue N1) const
 Determine if the result of the sub of 2 nodes can never overflow.
 
OverflowKind computeOverflowForSignedMul (SDValue N0, SDValue N1) const
 Determine if the result of the signed mul of 2 nodes can overflow.
 
OverflowKind computeOverflowForUnsignedMul (SDValue N0, SDValue N1) const
 Determine if the result of the unsigned mul of 2 nodes can overflow.
 
OverflowKind computeOverflowForMul (bool IsSigned, SDValue N0, SDValue N1) const
 Determine if the result of the mul of 2 nodes can overflow.
 
bool willNotOverflowMul (bool IsSigned, SDValue N0, SDValue N1) const
 Determine if the result of the mul of 2 nodes can never overflow.
 
bool isKnownToBeAPowerOfTwo (SDValue Val, unsigned Depth=0) const
 Test if the given value is known to have exactly one bit set.
 
bool isKnownToBeAPowerOfTwoFP (SDValue Val, unsigned Depth=0) const
 Test if the given fp value is known to be an integer power-of-2, either positive or negative.
 
unsigned ComputeNumSignBits (SDValue Op, unsigned Depth=0) const
 Return the number of times the sign bit of the register is replicated into the other bits.
 
unsigned ComputeNumSignBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
 Return the number of times the sign bit of the register is replicated into the other bits.
 
unsigned ComputeMaxSignificantBits (SDValue Op, unsigned Depth=0) const
 Get the upper bound on bit size for this Value Op as a signed integer.
 
unsigned ComputeMaxSignificantBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
 Get the upper bound on bit size for this Value Op as a signed integer.
 
bool isGuaranteedNotToBeUndefOrPoison (SDValue Op, bool PoisonOnly=false, unsigned Depth=0) const
 Return true if this function can prove that Op is never poison and, if PoisonOnly is false, does not have undef bits.
 
bool isGuaranteedNotToBeUndefOrPoison (SDValue Op, const APInt &DemandedElts, bool PoisonOnly=false, unsigned Depth=0) const
 Return true if this function can prove that Op is never poison and, if PoisonOnly is false, does not have undef bits.
 
bool isGuaranteedNotToBePoison (SDValue Op, unsigned Depth=0) const
 Return true if this function can prove that Op is never poison.
 
bool isGuaranteedNotToBePoison (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
 Return true if this function can prove that Op is never poison.
 
bool canCreateUndefOrPoison (SDValue Op, const APInt &DemandedElts, bool PoisonOnly=false, bool ConsiderFlags=true, unsigned Depth=0) const
 Return true if Op can create undef or poison from non-undef & non-poison operands.
 
bool canCreateUndefOrPoison (SDValue Op, bool PoisonOnly=false, bool ConsiderFlags=true, unsigned Depth=0) const
 Return true if Op can create undef or poison from non-undef & non-poison operands.
 
bool isADDLike (SDValue Op, bool NoWrap=false) const
 Return true if the specified operand is an ISD::OR or ISD::XOR node that can be treated as an ISD::ADD node.
 
bool isBaseWithConstantOffset (SDValue Op) const
 Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that is guaranteed to have the same semantics as an ADD.
 
bool isKnownNeverNaN (SDValue Op, bool SNaN=false, unsigned Depth=0) const
 Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN.
 
bool isKnownNeverSNaN (SDValue Op, unsigned Depth=0) const
 
bool isKnownNeverZeroFloat (SDValue Op) const
 Test whether the given floating point SDValue is known to never be positive or negative zero.
 
bool isKnownNeverZero (SDValue Op, unsigned Depth=0) const
 Test whether the given SDValue is known to contain non-zero value(s).
 
bool cannotBeOrderedNegativeFP (SDValue Op) const
 Test whether the given float value is known to be positive.
 
bool isEqualTo (SDValue A, SDValue B) const
 Test whether two SDValues are known to compare equal.
 
bool haveNoCommonBitsSet (SDValue A, SDValue B) const
 Return true if A and B have no common bits set.
 
bool isSplatValue (SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const
 Test whether V has a splatted value for all the demanded elements.
 
bool isSplatValue (SDValue V, bool AllowUndefs=false) const
 Test whether V has a splatted value.
 
SDValue getSplatSourceVector (SDValue V, int &SplatIndex)
 If V is a splatted value, return the source vector and its splat index.
 
SDValue getSplatValue (SDValue V, bool LegalTypes=false)
 If V is a splat vector, return its scalar source operand by extracting that element from the source vector.
 
std::optional< ConstantRangegetValidShiftAmountRange (SDValue V, const APInt &DemandedElts, unsigned Depth) const
 If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the valid constant range.
 
std::optional< uint64_tgetValidShiftAmount (SDValue V, const APInt &DemandedElts, unsigned Depth=0) const
 If a SHL/SRA/SRL node V has a uniform shift amount that is less than the element bit-width of the shift node, return it.
 
std::optional< uint64_tgetValidShiftAmount (SDValue V, unsigned Depth=0) const
 If a SHL/SRA/SRL node V has a uniform shift amount that is less than the element bit-width of the shift node, return it.
 
std::optional< uint64_tgetValidMinimumShiftAmount (SDValue V, const APInt &DemandedElts, unsigned Depth=0) const
 If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value.
 
std::optional< uint64_tgetValidMinimumShiftAmount (SDValue V, unsigned Depth=0) const
 If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value.
 
std::optional< uint64_tgetValidMaximumShiftAmount (SDValue V, const APInt &DemandedElts, unsigned Depth=0) const
 If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value.
 
std::optional< uint64_tgetValidMaximumShiftAmount (SDValue V, unsigned Depth=0) const
 If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value.
 
SDValue matchBinOpReduction (SDNode *Extract, ISD::NodeType &BinOp, ArrayRef< ISD::NodeType > CandidateBinOps, bool AllowPartials=false)
 Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract.
 
SDValue UnrollVectorOp (SDNode *N, unsigned ResNE=0)
 Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the scalars and operating on each element individually.
 
std::pair< SDValue, SDValueUnrollVectorOverflowOp (SDNode *N, unsigned ResNE=0)
 Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes.
 
bool areNonVolatileConsecutiveLoads (LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, int Dist) const
 Return true if loads are next to each other and can be merged.
 
MaybeAlign InferPtrAlign (SDValue Ptr) const
 Infer alignment of a load / store address.
 
std::pair< SDValue, SDValueSplitScalar (const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
 Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
 
std::pair< EVT, EVTGetSplitDestVTs (const EVT &VT) const
 Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces.
 
std::pair< EVT, EVTGetDependentSplitDestVTs (const EVT &VT, const EVT &EnvVT, bool *HiIsEmpty) const
 Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces.
 
std::pair< SDValue, SDValueSplitVector (const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
 Split the vector with EXTRACT_SUBVECTOR using the provided VTs and return the low/high part.
 
std::pair< SDValue, SDValueSplitVector (const SDValue &N, const SDLoc &DL)
 Split the vector with EXTRACT_SUBVECTOR and return the low/high part.
 
std::pair< SDValue, SDValueSplitEVL (SDValue N, EVT VecVT, const SDLoc &DL)
 Split the explicit vector length parameter of a VP operation.
 
std::pair< SDValue, SDValueSplitVectorOperand (const SDNode *N, unsigned OpNo)
 Split the node's operand with EXTRACT_SUBVECTOR and return the low/high part.
 
SDValue WidenVector (const SDValue &N, const SDLoc &DL)
 Widen the vector up to the next power of two using INSERT_SUBVECTOR.
 
void ExtractVectorElements (SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
 Append the extracted elements from Start to Count out of the vector Op in Args.
 
Align getEVTAlign (EVT MemoryVT) const
 Compute the default alignment value for the given type.
 
SDNodeisConstantIntBuildVectorOrConstantInt (SDValue N) const
 Test whether the given value is a constant int or similar node.
 
SDNodeisConstantFPBuildVectorOrConstantFP (SDValue N) const
 Test whether the given value is a constant FP or similar node.
 
bool isConstantValueOfAnyType (SDValue N) const
 
std::optional< boolisBoolConstant (SDValue N, bool AllowTruncation=false) const
 Check if a value \op N is a constant using the target's BooleanContent for its type.
 
void addCallSiteInfo (const SDNode *Node, CallSiteInfo &&CallInfo)
 Set CallSiteInfo to be associated with Node.
 
CallSiteInfo getCallSiteInfo (const SDNode *Node)
 Return CallSiteInfo associated with Node, or a default if none exists.
 
void addHeapAllocSite (const SDNode *Node, MDNode *MD)
 Set HeapAllocSite to be associated with Node.
 
MDNodegetHeapAllocSite (const SDNode *Node) const
 Return HeapAllocSite associated with Node, or nullptr if none exists.
 
void addPCSections (const SDNode *Node, MDNode *MD)
 Set PCSections to be associated with Node.
 
void addMMRAMetadata (const SDNode *Node, MDNode *MMRA)
 Set MMRAMetadata to be associated with Node.
 
MDNodegetPCSections (const SDNode *Node) const
 Return PCSections associated with Node, or nullptr if none exists.
 
MDNodegetMMRAMetadata (const SDNode *Node) const
 Return the MMRA MDNode associated with Node, or nullptr if none exists.
 
void addNoMergeSiteInfo (const SDNode *Node, bool NoMerge)
 Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
 
bool getNoMergeSiteInfo (const SDNode *Node) const
 Return NoMerge info associated with Node.
 
void copyExtraInfo (SDNode *From, SDNode *To)
 Copy extra info associated with one node to another.
 
DenormalMode getDenormalMode (EVT VT) const
 Return the current function's default denormal handling kind for the given floating point type.
 
bool shouldOptForSize () const
 
SDValue getNeutralElement (unsigned Opcode, const SDLoc &DL, EVT VT, SDNodeFlags Flags)
 Get the (commutative) neutral element for the given opcode, if it exists.
 
bool isSafeToSpeculativelyExecute (unsigned Opcode) const
 Some opcodes may create immediate undefined behavior when used with some values (integer division-by-zero for example).
 
bool isSafeToSpeculativelyExecuteNode (const SDNode *N) const
 Check if the provided node is save to speculatively executed given its current arguments.
 
SDValue makeStateFunctionCall (unsigned LibFunc, SDValue Ptr, SDValue InChain, const SDLoc &DLoc)
 Helper used to make a call to a library function that has one argument of pointer type.
 
SDValue getConstant (uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
 Create a ConstantSDNode wrapping a constant value.
 
SDValue getConstant (const APInt &Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
 
SDValue getAllOnesConstant (const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)
 
SDValue getConstant (const ConstantInt &Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
 
SDValue getIntPtrConstant (uint64_t Val, const SDLoc &DL, bool isTarget=false)
 
SDValue getShiftAmountConstant (uint64_t Val, EVT VT, const SDLoc &DL)
 
SDValue getShiftAmountConstant (const APInt &Val, EVT VT, const SDLoc &DL)
 
SDValue getVectorIdxConstant (uint64_t Val, const SDLoc &DL, bool isTarget=false)
 
SDValue getTargetConstant (uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
 
SDValue getTargetConstant (const APInt &Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
 
SDValue getTargetConstant (const ConstantInt &Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
 
SDValue getBoolConstant (bool V, const SDLoc &DL, EVT VT, EVT OpVT)
 Create a true or false constant of type VT using the target's BooleanContent for type OpVT.
 
SDValue getConstantFP (double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
 Create a ConstantFPSDNode wrapping a constant value.
 
SDValue getConstantFP (const APFloat &Val, const SDLoc &DL, EVT VT, bool isTarget=false)
 
SDValue getConstantFP (const ConstantFP &V, const SDLoc &DL, EVT VT, bool isTarget=false)
 
SDValue getTargetConstantFP (double Val, const SDLoc &DL, EVT VT)
 
SDValue getTargetConstantFP (const APFloat &Val, const SDLoc &DL, EVT VT)
 
SDValue getTargetConstantFP (const ConstantFP &Val, const SDLoc &DL, EVT VT)
 

Static Public Member Functions

static unsigned getOpcode_EXTEND (unsigned Opcode)
 Convert *_EXTEND_VECTOR_INREG to *_EXTEND opcode.
 
static unsigned getOpcode_EXTEND_VECTOR_INREG (unsigned Opcode)
 Convert *_EXTEND to *_EXTEND_VECTOR_INREG opcode.
 
static const fltSemanticsEVTToAPFloatSemantics (EVT VT)
 Returns an APFloat semantics tag appropriate for the given type.
 

Public Attributes

bool NewNodesMustHaveLegalTypes = false
 When true, additional steps are taken to ensure that getConstant() and similar functions return DAG nodes that have legal types.
 

Static Public Attributes

static constexpr unsigned MaxRecursionDepth = 6
 

Friends

struct DAGUpdateListener
 DAGUpdateListener is a friend so it can manipulate the listener stack.
 

Detailed Description

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representation suitable for instruction selection.

This DAG is constructed as the first step of instruction selection in order to allow implementation of machine specific optimizations and code simplifications.

The representation used by the SelectionDAG is a target-independent representation, which has some similarities to the GCC RTL representation, but is significantly more simple, powerful, and is a graph form instead of a linear form.

Definition at line 228 of file SelectionDAG.h.

Member Typedef Documentation

◆ allnodes_const_iterator

Definition at line 547 of file SelectionDAG.h.

◆ allnodes_iterator

Definition at line 552 of file SelectionDAG.h.

Member Enumeration Documentation

◆ OverflowKind

Used to represent the possible overflow behavior of an operation.

Never: the operation cannot overflow. Always: the operation will always overflow. Sometime: the operation may or may not overflow.

Enumerator
OFK_Never 
OFK_Sometime 
OFK_Always 

Definition at line 1965 of file SelectionDAG.h.

Constructor & Destructor Documentation

◆ SelectionDAG() [1/2]

SelectionDAG::SelectionDAG ( const TargetMachine TM,
CodeGenOptLevel  OL 
)
explicit

Definition at line 1324 of file SelectionDAG.cpp.

◆ SelectionDAG() [2/2]

llvm::SelectionDAG::SelectionDAG ( const SelectionDAG )
delete

◆ ~SelectionDAG()

SelectionDAG::~SelectionDAG ( )

Definition at line 1352 of file SelectionDAG.cpp.

References assert().

Member Function Documentation

◆ addCallSiteInfo()

void llvm::SelectionDAG::addCallSiteInfo ( const SDNode Node,
CallSiteInfo &&  CallInfo 
)
inline

Set CallSiteInfo to be associated with Node.

Definition at line 2329 of file SelectionDAG.h.

◆ AddDbgLabel()

void SelectionDAG::AddDbgLabel ( SDDbgLabel DB)

Add a dbg_label SDNode.

Definition at line 11826 of file SelectionDAG.cpp.

References llvm::SDDbgInfo::add().

Referenced by llvm::SelectionDAGBuilder::visitDbgInfo().

◆ AddDbgValue()

void SelectionDAG::AddDbgValue ( SDDbgValue DB,
bool  isParameter 
)

◆ addHeapAllocSite()

void llvm::SelectionDAG::addHeapAllocSite ( const SDNode Node,
MDNode MD 
)
inline

Set HeapAllocSite to be associated with Node.

Definition at line 2338 of file SelectionDAG.h.

◆ addMMRAMetadata()

void llvm::SelectionDAG::addMMRAMetadata ( const SDNode Node,
MDNode MMRA 
)
inline

Set MMRAMetadata to be associated with Node.

Definition at line 2351 of file SelectionDAG.h.

Referenced by llvm::SelectionDAGBuilder::visit().

◆ addNoMergeSiteInfo()

void llvm::SelectionDAG::addNoMergeSiteInfo ( const SDNode Node,
bool  NoMerge 
)
inline

Set NoMergeSiteInfo to be associated with Node if NoMerge is true.

Definition at line 2366 of file SelectionDAG.h.

Referenced by llvm::SystemZTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerCall().

◆ addPCSections()

void llvm::SelectionDAG::addPCSections ( const SDNode Node,
MDNode MD 
)
inline

Set PCSections to be associated with Node.

Definition at line 2347 of file SelectionDAG.h.

Referenced by llvm::SelectionDAGBuilder::visit().

◆ allnodes() [1/2]

iterator_range< allnodes_iterator > llvm::SelectionDAG::allnodes ( )
inline

◆ allnodes() [2/2]

iterator_range< allnodes_const_iterator > llvm::SelectionDAG::allnodes ( ) const
inline

Definition at line 564 of file SelectionDAG.h.

References allnodes_begin(), allnodes_end(), and llvm::make_range().

◆ allnodes_begin() [1/2]

allnodes_iterator llvm::SelectionDAG::allnodes_begin ( )
inline

Definition at line 554 of file SelectionDAG.h.

◆ allnodes_begin() [2/2]

allnodes_const_iterator llvm::SelectionDAG::allnodes_begin ( ) const
inline

◆ allnodes_end() [1/2]

allnodes_iterator llvm::SelectionDAG::allnodes_end ( )
inline

Definition at line 555 of file SelectionDAG.h.

◆ allnodes_end() [2/2]

allnodes_const_iterator llvm::SelectionDAG::allnodes_end ( ) const
inline

◆ allnodes_size()

ilist< SDNode >::size_type llvm::SelectionDAG::allnodes_size ( ) const
inline

◆ areNonVolatileConsecutiveLoads()

bool SelectionDAG::areNonVolatileConsecutiveLoads ( LoadSDNode LD,
LoadSDNode Base,
unsigned  Bytes,
int  Dist 
) const

Return true if loads are next to each other and can be merged.

Check that both are nonvolatile and if LD is loading 'Bytes' bytes from a location that is 'Dist' units away from the location that the 'Base' load is loading from.

Definition at line 12549 of file SelectionDAG.cpp.

References llvm::sampleprof::Base, llvm::EVT::getSizeInBits(), llvm::BaseIndexOffset::match(), and llvm::Offset.

Referenced by areLoadedOffsetButOtherwiseSame(), combineBVOfConsecutiveLoads(), combineINSERT_SUBVECTOR(), EltsFromConsecutiveLoads(), and lowerShuffleAsVTRUNC().

◆ AssignTopologicalOrder()

unsigned SelectionDAG::AssignTopologicalOrder ( )

Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order.

AssignTopologicalOrder - Assign a unique node id for each node in the DAG based on their topological order.

Returns the number of nodes.

It returns the maximum id and a vector of the SDNodes* in assigned order by reference.

Definition at line 11730 of file SelectionDAG.cpp.

References allnodes(), allnodes_begin(), allnodes_size(), assert(), llvm::checkForCycles(), llvm::dbgs(), llvm::SDNode::dumprFull(), llvm::ISD::EntryToken, I, llvm_unreachable, llvm::make_early_inc_range(), N, and P.

Referenced by Legalize().

◆ ByvalParmDbgBegin()

SDDbgInfo::DbgIterator llvm::SelectionDAG::ByvalParmDbgBegin ( ) const
inline

◆ ByvalParmDbgEnd()

SDDbgInfo::DbgIterator llvm::SelectionDAG::ByvalParmDbgEnd ( ) const
inline

Definition at line 1865 of file SelectionDAG.h.

References llvm::SDDbgInfo::ByvalParmDbgEnd().

Referenced by dump(), and llvm::ScheduleDAGSDNodes::EmitSchedule().

◆ calculateDivergence()

bool SelectionDAG::calculateDivergence ( SDNode N)

◆ canCreateUndefOrPoison() [1/2]

bool SelectionDAG::canCreateUndefOrPoison ( SDValue  Op,
bool  PoisonOnly = false,
bool  ConsiderFlags = true,
unsigned  Depth = 0 
) const

Return true if Op can create undef or poison from non-undef & non-poison operands.

ConsiderFlags controls whether poison producing flags on the instruction are considered. This can be used to see if the instruction could still introduce undef or poison even without poison generating flags which might be on the instruction. (i.e. could the result of Op->dropPoisonGeneratingFlags() still create poison or undef)

Definition at line 5236 of file SelectionDAG.cpp.

References canCreateUndefOrPoison(), llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), llvm::EVT::isScalableVector(), llvm::EVT::isVector(), and PoisonOnly.

◆ canCreateUndefOrPoison() [2/2]

bool SelectionDAG::canCreateUndefOrPoison ( SDValue  Op,
const APInt DemandedElts,
bool  PoisonOnly = false,
bool  ConsiderFlags = true,
unsigned  Depth = 0 
) const

Return true if Op can create undef or poison from non-undef & non-poison operands.

The DemandedElts argument limits the check to the requested vector elements.

ConsiderFlags controls whether poison producing flags on the instruction are considered. This can be used to see if the instruction could still introduce undef or poison even without poison generating flags which might be on the instruction. (i.e. could the result of Op->dropPoisonGeneratingFlags() still create poison or undef)

Definition at line 5251 of file SelectionDAG.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::ISD::BSWAP, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::TargetLowering::canCreateUndefOrPoisonForTargetNode(), computeKnownBits(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::CTPOP, llvm::Depth, llvm::enumerate(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FREEZE, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::KnownBits::getMaxValue(), getTarget(), getValidMaximumShiftAmount(), llvm::EVT::getVectorMinNumElements(), Idx, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, isGuaranteedNotToBeUndefOrPoison(), llvm::EVT::isScalableVector(), llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::TargetMachine::Options, Options, llvm::ISD::OR, llvm::ISD::PARITY, PoisonOnly, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDSAT, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SSUBSAT, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UADDSAT, llvm::APInt::uge(), llvm::APInt::ugt(), llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::USUBSAT, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZERO_EXTEND_VECTOR_INREG.

Referenced by canCreateUndefOrPoison(), and isGuaranteedNotToBeUndefOrPoison().

◆ cannotBeOrderedNegativeFP()

bool SelectionDAG::cannotBeOrderedNegativeFP ( SDValue  Op) const

Test whether the given float value is known to be positive.

+0.0, +inf and +nan are considered positive, -0.0, -inf and -nan are not.

Definition at line 5678 of file SelectionDAG.cpp.

References llvm::ISD::FABS, and llvm::isConstOrConstSplatFP().

◆ canonicalizeCommutativeBinop()

void SelectionDAG::canonicalizeCommutativeBinop ( unsigned  Opcode,
SDValue N1,
SDValue N2 
) const

Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite order.

Definition at line 6883 of file SelectionDAG.cpp.

References llvm::SDValue::getOpcode(), llvm::TargetLoweringBase::isCommutativeBinOp(), isConstantFPBuildVectorOrConstantFP(), isConstantIntBuildVectorOrConstantInt(), llvm::ISD::SPLAT_VECTOR, llvm::ISD::STEP_VECTOR, and std::swap().

Referenced by getNode().

◆ clear()

void SelectionDAG::clear ( )

Clear state and free memory necessary to make this SelectionDAG ready to process a new block.

Definition at line 1414 of file SelectionDAG.cpp.

References llvm::SDDbgInfo::clear(), getEntryNode(), and llvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Reset().

◆ clearGraphAttrs()

void SelectionDAG::clearGraphAttrs ( )

Clear all previously defined node graph attributes.

clearGraphAttrs - Clear all previously defined node graph attributes.

Intended to be used from a debugging tool (eg. gdb).

Definition at line 179 of file SelectionDAGPrinter.cpp.

References llvm::errs().

◆ Combine()

void SelectionDAG::Combine ( CombineLevel  Level,
AAResults AA,
CodeGenOptLevel  OptLevel 
)

This iterates over the nodes in the SelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes.

This is the entry point for the file.

The Level argument controls whether Combine is allowed to produce nodes and types that are illegal on the target.

This is the main entry point to this class.

Definition at line 28663 of file DAGCombiner.cpp.

◆ computeKnownBits() [1/2]

KnownBits SelectionDAG::computeKnownBits ( SDValue  Op,
const APInt DemandedElts,
unsigned  Depth = 0 
) const

Determine which bits of Op are known to be either zero or one and return them in Known.

The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements. Targets can implement the computeKnownBitsForTargetNode method in the TargetLowering class to allow target nodes to be understood.

The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements.

Definition at line 3150 of file SelectionDAG.cpp.

References llvm::ISD::ABDS, llvm::KnownBits::abds(), llvm::ISD::ABDU, llvm::KnownBits::abdu(), llvm::ISD::ABS, llvm::KnownBits::abs(), llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, llvm::KnownBits::anyext(), llvm::KnownBits::ashr(), assert(), llvm::ISD::AssertAlign, llvm::ISD::AssertZext, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_CLR, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_SWAP, llvm::ISD::AVGCEILS, llvm::KnownBits::avgCeilS(), llvm::ISD::AVGCEILU, llvm::KnownBits::avgCeilU(), llvm::ISD::AVGFLOORS, llvm::KnownBits::avgFloorS(), llvm::ISD::AVGFLOORU, llvm::KnownBits::avgFloorU(), llvm::bit_width(), llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::BitWidth, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::KnownBits::byteSwap(), llvm::CallingConv::C, llvm::APInt::clearAllBits(), llvm::APInt::clearBit(), llvm::APInt::clearLowBits(), llvm::KnownBits::computeForAddCarry(), llvm::KnownBits::computeForAddSub(), llvm::KnownBits::computeForSubBorrow(), computeKnownBits(), llvm::TargetLowering::computeKnownBitsForFrameIndex(), llvm::TargetLowering::computeKnownBitsForTargetNode(), llvm::computeKnownBitsFromRangeMetadata(), ComputeNumSignBits(), llvm::KnownBits::concat(), llvm::ISD::CONCAT_VECTORS, llvm::APInt::countl_zero(), llvm::KnownBits::countMaxLeadingZeros(), llvm::KnownBits::countMaxPopulation(), llvm::KnownBits::countMaxTrailingZeros(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::Depth, llvm::enumerate(), llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::KnownBits::extractBits(), F, llvm::ISD::FGETSIGN, llvm::ISD::FP_TO_UINT_SAT, llvm::ISD::FrameIndex, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::Constant::getAggregateElement(), llvm::getAlign(), llvm::APInt::getAllOnes(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitsSetFrom(), llvm::APInt::getBitWidth(), llvm::KnownBits::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), getDataLayout(), llvm::TargetLoweringBase::getExtendForAtomicOps(), llvm::MachineFunction::getFunction(), llvm::APInt::getHiBits(), llvm::APInt::getLowBitsSet(), getMachineFunction(), llvm::ShuffleVectorSDNode::getMask(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::APInt::getNumSignBits(), llvm::APInt::getOneBitSet(), llvm::Type::getPrimitiveSizeInBits(), llvm::EVT::getScalarSizeInBits(), llvm::Type::getScalarSizeInBits(), llvm::getShuffleDemandedElts(), llvm::EVT::getSizeInBits(), llvm::Constant::getSplatValue(), llvm::TargetLowering::getTargetConstantFromLoad(), llvm::Value::getType(), llvm::ConstantRange::getUnsignedMax(), getValidMinimumShiftAmount(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::getVScaleRange(), llvm::APInt::getZero(), I, Idx, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::APInt::insertBits(), llvm::KnownBits::insertBits(), llvm::KnownBits::intersectWith(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isConstOrConstSplat(), llvm::ISD::isEXTLoad(), llvm::EVT::isFloatingPoint(), isGuaranteedNotToBeUndefOrPoison(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::APInt::isNegative(), llvm::KnownBits::isNegative(), llvm::ISD::isNON_EXTLoad(), llvm::APInt::isNonNegative(), llvm::KnownBits::isNonNegative(), llvm::KnownBits::isNonZero(), llvm::APInt::isPowerOf2(), llvm::EVT::isScalableVector(), llvm::ISD::isSEXTLoad(), llvm::isUIntN(), llvm::KnownBits::isUnknown(), llvm::EVT::isVector(), llvm::Type::isVectorTy(), llvm::ISD::isZEXTLoad(), LHS, llvm::ISD::LOAD, llvm::Log2(), llvm::APInt::logBase2(), llvm::KnownBits::lshr(), llvm::APInt::lshrInPlace(), llvm::KnownBits::makeConstant(), llvm::KnownBits::makeNegative(), llvm::KnownBits::makeNonNegative(), MaxRecursionDepth, llvm::ISD::MERGE_VALUES, llvm::ISD::MUL, llvm::KnownBits::mul(), llvm::ISD::MULHS, llvm::KnownBits::mulhs(), llvm::ISD::MULHU, llvm::KnownBits::mulhu(), llvm::ConstantRange::multiply(), llvm::Offset, llvm::KnownBits::One, llvm::ISD::OR, llvm::ISD::PARITY, llvm::KnownBits::resetAll(), llvm::KnownBits::reverseBits(), RHS, llvm::ISD::SADDO, llvm::ISD::SADDO_CARRY, llvm::ISD::SCALAR_TO_VECTOR, llvm::APIntOps::ScaleBitMask(), llvm::ISD::SDIV, llvm::KnownBits::sdiv(), llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::APInt::setAllBits(), llvm::KnownBits::setAllZero(), llvm::APInt::setBit(), llvm::APInt::setBitsFrom(), llvm::ISD::SETCC, llvm::ISD::SETCCCARRY, llvm::APInt::setHighBits(), llvm::APInt::setLowBits(), llvm::KnownBits::sext(), llvm::KnownBits::sextInReg(), llvm::APInt::shl(), llvm::ISD::SHL, llvm::KnownBits::shl(), llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ISD::SINT_TO_FP, llvm::ArrayRef< T >::size(), llvm::APInt::sle(), llvm::ISD::SMAX, llvm::KnownBits::smax(), llvm::ISD::SMIN, llvm::KnownBits::smin(), llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::Splat, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SPLAT_VECTOR_PARTS, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::KnownBits::srem(), llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::SSUBO_CARRY, llvm::ISD::STEP_VECTOR, llvm::ISD::STRICT_FSETCC, llvm::ISD::STRICT_FSETCCS, llvm::ISD::SUB, llvm::ISD::SUBC, std::swap(), llvm::ISD::TargetFrameIndex, llvm::ConstantRange::toKnownBits(), llvm::KnownBits::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::UDIV, llvm::KnownBits::udiv(), llvm::ISD::UINT_TO_FP, llvm::ISD::UMAX, llvm::KnownBits::umax(), llvm::ISD::UMIN, llvm::KnownBits::umin(), llvm::ISD::UMUL_LOHI, llvm::APInt::umul_ov(), umul_ov(), llvm::ISD::UMULO, llvm::KnownBits::unionWith(), llvm::ISD::UREM, llvm::KnownBits::urem(), llvm::KnownBits::usub_sat(), llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::ISD::USUBSAT, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSCALE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::KnownBits::Zero, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, llvm::KnownBits::zext(), llvm::APInt::zext(), llvm::ISD::ZEXTLOAD, and llvm::KnownBits::zextOrTrunc().

◆ computeKnownBits() [2/2]

KnownBits SelectionDAG::computeKnownBits ( SDValue  Op,
unsigned  Depth = 0 
) const

Determine which bits of Op are known to be either zero or one and return them in Known.

For vectors, the known bits are those that are shared by every vector element. Targets can implement the computeKnownBitsForTargetNode method in the TargetLowering class to allow target nodes to be understood.

For vectors, the known bits are those that are shared by every vector element.

Definition at line 3135 of file SelectionDAG.cpp.

References computeKnownBits(), llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().

Referenced by adjustForRedundantAnd(), llvm::TargetLowering::BuildUDIV(), canCreateUndefOrPoison(), cannotBeIntMin(), checkDot4MulSignedness(), llvm::SelectionDAGISel::CheckOrMask(), checkZExtBool(), combineArithReduction(), combineFaddCFmul(), combineFMulcFCMulc(), combineMOVMSK(), combinePMULH(), combineScalarToVector(), combineSetCC(), combineShiftToAVG(), computeKnownBits(), computeKnownBitsBinOp(), computeKnownBitsForHorizontalOperation(), computeKnownBitsForPMADDUBSW(), computeKnownBitsForPMADDWD(), computeKnownBitsForPSADBW(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::SITargetLowering::computeKnownBitsForTargetNode(), llvm::LanaiTargetLowering::computeKnownBitsForTargetNode(), llvm::SparcTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), ComputeNumSignBits(), computeOverflowForSignedMul(), computeOverflowForSignedSub(), computeOverflowForUnsignedAdd(), computeOverflowForUnsignedMul(), computeOverflowForUnsignedSub(), detectExtMul(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandFixedPointDiv(), getPack(), getValidShiftAmountRange(), haveNoCommonBitsSet(), isBitfieldPositioningOp(), isKnownNeverZero(), isTruncateOf(), isWordAligned(), LowerAndToBT(), LowerAndToBTST(), LowerCTPOP(), LowerMUL(), llvm::SITargetLowering::lowerSET_ROUNDING(), lowerShuffleWithVPMOV(), LowerVectorAllEqual(), MaskedValueIsAllOnes(), MaskedValueIsZero(), MaskedVectorIsZero(), matchBinaryShuffle(), matchTruncateWithPACK(), narrowIndex(), llvm::AMDGPUTargetLowering::numBitsUnsigned(), performANDCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performORCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), provablyDisjointOr(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegImm34(), llvm::PPCTargetLowering::SelectAddressRegReg(), llvm::LoongArchDAGToDAGISel::selectShiftMask(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), tryBitfieldInsertOpFromOr(), and tryBitfieldInsertOpFromOrAndImm().

◆ ComputeMaxSignificantBits() [1/2]

unsigned SelectionDAG::ComputeMaxSignificantBits ( SDValue  Op,
const APInt DemandedElts,
unsigned  Depth = 0 
) const

Get the upper bound on bit size for this Value Op as a signed integer.

i.e. x == sext(trunc(x to MaxSignedBits) to bitwidth(x)). Similar to the APInt::getSignificantBits function. Helper wrapper to ComputeNumSignBits.

Definition at line 5130 of file SelectionDAG.cpp.

References ComputeNumSignBits(), and llvm::Depth.

◆ ComputeMaxSignificantBits() [2/2]

unsigned SelectionDAG::ComputeMaxSignificantBits ( SDValue  Op,
unsigned  Depth = 0 
) const

Get the upper bound on bit size for this Value Op as a signed integer.

i.e. x == sext(trunc(x to MaxSignedBits) to bitwidth(x)). Similar to the APInt::getSignificantBits function. Helper wrapper to ComputeNumSignBits.

Definition at line 5124 of file SelectionDAG.cpp.

References ComputeNumSignBits(), and llvm::Depth.

Referenced by combineConcatVectorOps(), combineMulToPMADDWD(), combinePMULH(), detectExtMul(), EmitCmp(), llvm::TargetLowering::expandMUL_LOHI(), getPack(), llvm::AMDGPUTargetLowering::numBitsSigned(), and llvm::TargetLowering::SimplifyDemandedBits().

◆ ComputeNumSignBits() [1/2]

unsigned SelectionDAG::ComputeNumSignBits ( SDValue  Op,
const APInt DemandedElts,
unsigned  Depth = 0 
) const

Return the number of times the sign bit of the register is replicated into the other bits.

We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. The DemandedElts argument allows us to only collect the minimum sign bits of the requested vector elements. Targets can implement the ComputeNumSignBitsForTarget method in the TargetLowering class to allow target nodes to be understood.

Definition at line 4458 of file SelectionDAG.cpp.

References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::AND, assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_CLR, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_SWAP, llvm::ISD::AVGCEILS, llvm::ISD::AVGFLOORS, llvm::ISD::BITCAST, llvm::BitWidth, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::CallingConv::C, llvm::APInt::clearBit(), computeKnownBits(), ComputeNumSignBits(), llvm::TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::ISD::CONCAT_VECTORS, llvm::KnownBits::countMinSignBits(), llvm::Depth, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::ISD::FP_TO_SINT_SAT, llvm::Constant::getAggregateElement(), llvm::APInt::getAllOnes(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::ConstantRange::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), llvm::getConstantRangeFromMetadata(), getDataLayout(), llvm::TargetLoweringBase::getExtendForAtomicOps(), llvm::ShuffleVectorSDNode::getMask(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::APInt::getNumSignBits(), llvm::APInt::getOneBitSet(), llvm::Type::getPrimitiveSizeInBits(), llvm::EVT::getScalarSizeInBits(), llvm::Type::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::getShuffleDemandedElts(), llvm::ConstantRange::getSignedMax(), llvm::ConstantRange::getSignedMin(), llvm::TargetLowering::getTargetConstantFromLoad(), getValidMinimumShiftAmount(), getValidShiftAmountRange(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZero(), Idx, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::APInt::insertBits(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isConstOrConstSplat(), llvm::ISD::isExtOpcode(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::KnownBits::isNonNegative(), llvm::EVT::isScalableVector(), llvm::EVT::isVector(), llvm::Type::isVectorTy(), llvm::ISD::LOAD, MaxRecursionDepth, llvm::ISD::MERGE_VALUES, llvm::ISD::MUL, llvm::ISD::NON_EXTLOAD, llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::ISD::SADDO_CARRY, llvm::APIntOps::ScaleBitMask(), llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETCCCARRY, llvm::ISD::SEXTLOAD, llvm::APInt::shl(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ConstantRange::signExtend(), llvm::ArrayRef< T >::size(), llvm::APInt::sle(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULO, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SSUBO, llvm::ISD::SSUBO_CARRY, llvm::ISD::STRICT_FSETCC, llvm::ISD::STRICT_FSETCCS, llvm::ISD::SUB, std::swap(), llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::KnownBits::Zero, llvm::ISD::ZERO_EXTEND, llvm::ConstantRange::zeroExtend(), llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, llvm::APInt::zext(), and llvm::ISD::ZEXTLOAD.

◆ ComputeNumSignBits() [2/2]

unsigned SelectionDAG::ComputeNumSignBits ( SDValue  Op,
unsigned  Depth = 0 
) const

Return the number of times the sign bit of the register is replicated into the other bits.

We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. Targets can implement the ComputeNumSignBitsForTarget method in the TargetLowering class to allow target nodes to be understood.

Definition at line 4446 of file SelectionDAG.cpp.

References ComputeNumSignBits(), llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().

Referenced by canReduceVMulWidth(), combineAnd(), combineAndMaskToShift(), combineAndnp(), combineBitOpWithPACK(), combineGatherScatter(), combineLogicBlendIntoConditionalNegate(), combineLogicBlendIntoPBLENDV(), combineMulToPMULDQ(), combinePredicateReduction(), combinePTESTCC(), combineSelect(), combineSetCCMOVMSK(), combineShiftToAVG(), combineSIntToFP(), combineVectorCompareAndMaskUnaryOp(), combineVectorPack(), combineVSelectWithAllOnesOrZeros(), computeKnownBits(), ComputeMaxSignificantBits(), ComputeNumSignBits(), computeNumSignBitsBinOp(), llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(), computeOverflowForSignedAdd(), computeOverflowForSignedMul(), computeOverflowForSignedSub(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandFixedPointDiv(), foldAddSubMasked1(), getFauxShuffleMask(), isS16(), LowerADDSAT_SUBSAT(), lowerBuildVectorOfConstants(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), LowerEXTEND_VECTOR_INREG(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerShiftByScalarImmediate(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), lowerVectorIntrinsicScalars(), LowerVSETCC(), matchBinaryShuffle(), matchShuffleWithPACK(), matchTruncateWithPACK(), matchUnaryShuffle(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), performVectorShiftCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::selectSExtBits(), llvm::LoongArchDAGToDAGISel::selectSExti32(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), and llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode().

◆ computeOverflowForAdd()

OverflowKind llvm::SelectionDAG::computeOverflowForAdd ( bool  IsSigned,
SDValue  N0,
SDValue  N1 
) const
inline

Determine if the result of the addition of 2 nodes can overflow.

Definition at line 1978 of file SelectionDAG.h.

References computeOverflowForSignedAdd(), and computeOverflowForUnsignedAdd().

Referenced by willNotOverflowAdd().

◆ computeOverflowForMul()

OverflowKind llvm::SelectionDAG::computeOverflowForMul ( bool  IsSigned,
SDValue  N0,
SDValue  N1 
) const
inline

Determine if the result of the mul of 2 nodes can overflow.

Definition at line 2014 of file SelectionDAG.h.

References computeOverflowForSignedMul(), and computeOverflowForUnsignedMul().

Referenced by willNotOverflowMul().

◆ computeOverflowForSignedAdd()

SelectionDAG::OverflowKind SelectionDAG::computeOverflowForSignedAdd ( SDValue  N0,
SDValue  N1 
) const

Determine if the result of the signed addition of 2 nodes can overflow.

Definition at line 4241 of file SelectionDAG.cpp.

References ComputeNumSignBits(), llvm::isNullConstant(), OFK_Never, and OFK_Sometime.

Referenced by computeOverflowForAdd().

◆ computeOverflowForSignedMul()

SelectionDAG::OverflowKind SelectionDAG::computeOverflowForSignedMul ( SDValue  N0,
SDValue  N1 
) const

◆ computeOverflowForSignedSub()

SelectionDAG::OverflowKind SelectionDAG::computeOverflowForSignedSub ( SDValue  N0,
SDValue  N1 
) const

Determine if the result of the signed sub of 2 nodes can overflow.

Definition at line 4279 of file SelectionDAG.cpp.

References computeKnownBits(), ComputeNumSignBits(), llvm::ConstantRange::fromKnownBits(), llvm::isNullConstant(), mapOverflowResult(), OFK_Never, and llvm::ConstantRange::signedSubMayOverflow().

Referenced by computeOverflowForSub().

◆ computeOverflowForSub()

OverflowKind llvm::SelectionDAG::computeOverflowForSub ( bool  IsSigned,
SDValue  N0,
SDValue  N1 
) const
inline

Determine if the result of the sub of 2 nodes can overflow.

Definition at line 1996 of file SelectionDAG.h.

References computeOverflowForSignedSub(), and computeOverflowForUnsignedSub().

Referenced by willNotOverflowSub().

◆ computeOverflowForUnsignedAdd()

SelectionDAG::OverflowKind SelectionDAG::computeOverflowForUnsignedAdd ( SDValue  N0,
SDValue  N1 
) const

◆ computeOverflowForUnsignedMul()

SelectionDAG::OverflowKind SelectionDAG::computeOverflowForUnsignedMul ( SDValue  N0,
SDValue  N1 
) const

Determine if the result of the unsigned mul of 2 nodes can overflow.

Definition at line 4310 of file SelectionDAG.cpp.

References computeKnownBits(), llvm::ConstantRange::fromKnownBits(), llvm::isNullConstant(), llvm::isOneConstant(), mapOverflowResult(), OFK_Never, and llvm::ConstantRange::unsignedMulMayOverflow().

Referenced by computeOverflowForMul().

◆ computeOverflowForUnsignedSub()

SelectionDAG::OverflowKind SelectionDAG::computeOverflowForUnsignedSub ( SDValue  N0,
SDValue  N1 
) const

Determine if the result of the unsigned sub of 2 nodes can overflow.

Definition at line 4297 of file SelectionDAG.cpp.

References computeKnownBits(), llvm::ConstantRange::fromKnownBits(), llvm::isNullConstant(), mapOverflowResult(), OFK_Never, and llvm::ConstantRange::unsignedSubMayOverflow().

Referenced by computeOverflowForSub().

◆ computeVectorKnownZeroElements()

APInt SelectionDAG::computeVectorKnownZeroElements ( SDValue  Op,
const APInt DemandedElts,
unsigned  Depth = 0 
) const

◆ copyExtraInfo()

void SelectionDAG::copyExtraInfo ( SDNode From,
SDNode To 
)

◆ CreateStackTemporary() [1/3]

SDValue SelectionDAG::CreateStackTemporary ( EVT  VT,
unsigned  minAlign = 1 
)

Create a stack temporary, suitable for holding the specified value type.

If minAlign is specified, the slot size will have at least that alignment.

Definition at line 2509 of file SelectionDAG.cpp.

References CreateStackTemporary(), getContext(), getDataLayout(), getPrefTypeAlign(), llvm::EVT::getStoreSize(), and llvm::EVT::getTypeForEVT().

◆ CreateStackTemporary() [2/3]

SDValue SelectionDAG::CreateStackTemporary ( EVT  VT1,
EVT  VT2 
)

◆ CreateStackTemporary() [3/3]

SDValue SelectionDAG::CreateStackTemporary ( TypeSize  Bytes,
Align  Alignment 
)

◆ DbgBegin()

SDDbgInfo::DbgIterator llvm::SelectionDAG::DbgBegin ( ) const
inline

Definition at line 1859 of file SelectionDAG.h.

References llvm::SDDbgInfo::DbgBegin().

Referenced by dump(), and llvm::ScheduleDAGSDNodes::EmitSchedule().

◆ DbgEnd()

SDDbgInfo::DbgIterator llvm::SelectionDAG::DbgEnd ( ) const
inline

Definition at line 1860 of file SelectionDAG.h.

References llvm::SDDbgInfo::DbgEnd().

Referenced by dump(), and llvm::ScheduleDAGSDNodes::EmitSchedule().

◆ DbgLabelBegin()

SDDbgInfo::DbgLabelIterator llvm::SelectionDAG::DbgLabelBegin ( ) const
inline

Definition at line 1869 of file SelectionDAG.h.

References llvm::SDDbgInfo::DbgLabelBegin().

Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().

◆ DbgLabelEnd()

SDDbgInfo::DbgLabelIterator llvm::SelectionDAG::DbgLabelEnd ( ) const
inline

Definition at line 1872 of file SelectionDAG.h.

References llvm::SDDbgInfo::DbgLabelEnd().

Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().

◆ DeleteNode()

void SelectionDAG::DeleteNode ( SDNode N)

Remove the specified node from the system.

This node must have no referrers.

Definition at line 1053 of file SelectionDAG.cpp.

References N.

Referenced by Legalize(), and llvm::SelectionDAGBuilder::LowerAsSTATEPOINT().

◆ doesNodeExist()

bool SelectionDAG::doesNodeExist ( unsigned  Opcode,
SDVTList  VTList,
ArrayRef< SDValue Ops 
)

Check if a node exists without modifying its flags.

doesNodeExist - Check if a node exists without modifying its flags.

Definition at line 10995 of file SelectionDAG.cpp.

References AddNodeIDNode(), llvm::SDVTList::NumVTs, and llvm::SDVTList::VTs.

Referenced by llvm::TargetLowering::expandIntMINMAX(), foldAndOrOfSETCC(), and llvm::TargetLowering::SimplifySetCC().

◆ dump()

LLVM_DUMP_METHOD void SelectionDAG::dump ( ) const

◆ dumpDotGraph()

LLVM_DUMP_METHOD void SelectionDAG::dumpDotGraph ( const Twine FileName,
const Twine Title 
)

Just dump dot graph to a user-provided path and title.

This doesn't open the dot viewer program and helps visualization when outside debugging session. FileName expects absolute path. If provided without any path separators then the file will be created in the current directory. Error will be emitted if the path is insane.

Definition at line 171 of file SelectionDAGPrinter.cpp.

References llvm::dumpDotGraphToFile().

◆ EVTToAPFloatSemantics()

static const fltSemantics & llvm::SelectionDAG::EVTToAPFloatSemantics ( EVT  VT)
inlinestatic

◆ expandVAArg()

SDValue SelectionDAG::expandVAArg ( SDNode Node)

◆ expandVACopy()

SDValue SelectionDAG::expandVACopy ( SDNode Node)

Expand the specified ISD::VACOPY node as the Legalize pass would.

Definition at line 2449 of file SelectionDAG.cpp.

References getDataLayout(), getLoad(), llvm::TargetLoweringBase::getPointerTy(), getStore(), getTargetLoweringInfo(), and llvm::SDValue::getValue().

Referenced by LowerVACOPY().

◆ ExtractVectorElements()

void SelectionDAG::ExtractVectorElements ( SDValue  Op,
SmallVectorImpl< SDValue > &  Args,
unsigned  Start = 0,
unsigned  Count = 0,
EVT  EltVT = EVT() 
)

◆ FoldConstantArithmetic()

SDValue SelectionDAG::FoldConstantArithmetic ( unsigned  Opcode,
const SDLoc DL,
EVT  VT,
ArrayRef< SDValue Ops,
SDNodeFlags  Flags = SDNodeFlags() 
)

Definition at line 6382 of file SelectionDAG.cpp.

References llvm::APInt::abs(), llvm::ISD::ABS, llvm::all_of(), llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BF16_TO_FP, llvm::APFloatBase::BFloat(), llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::APInt::byteSwap(), llvm::CallingConv::C, llvm::ISD::CONCAT_VECTORS, llvm::ISD::CONDCODE, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::APFloat::convert(), llvm::APFloat::convertFromAPInt(), llvm::APInt::countl_zero(), llvm::APInt::countr_zero(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, DL, EVTToAPFloatSemantics(), llvm::ISD::FABS, llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FNEG, foldConstantFPMath(), FoldSTEP_VECTOR(), FoldSymbolOffset(), FoldValue(), FoldValueWithUndef(), llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_BF16, llvm::ISD::FP_TO_FP16, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FTRUNC, getBitcast(), llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), getBuildVector(), getConstant(), getConstantFP(), getContext(), getDataLayout(), llvm::TargetLoweringBase::getExtendForContent(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getNode(), llvm::SDValue::getOpcode(), getOpcode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), getSplatVector(), getStepVector(), llvm::TargetLoweringBase::getTypeAction(), llvm::TargetLoweringBase::getTypeToTransformTo(), getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::APInt::getZero(), I, llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), llvm::APFloatBase::IEEEquad(), llvm::APFloatBase::IEEEsingle(), ignored(), llvm::TargetLoweringBase::isCommutativeBinOp(), llvm::ISD::isConstantSplatVector(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::TargetLoweringBase::isSExtCheaperThanZExt(), llvm::SDValue::isUndef(), isUndef(), llvm::EVT::isVector(), llvm::ISD::MUL, NewNodesMustHaveLegalTypes, NewSDValueDbgMsg(), llvm::APFloatBase::opInexact, llvm::APFloatBase::opInvalidOp, llvm::APFloatBase::opOK, llvm::peekThroughBitcasts(), llvm::APInt::popcount(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::BuildVectorSDNode::recastRawBits(), llvm::APInt::reverseBits(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::rmTowardNegative, llvm::APFloatBase::rmTowardPositive, llvm::APFloatBase::rmTowardZero, llvm::ISD::SETCC, llvm::APInt::sextOrTrunc(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ArrayRef< T >::size(), llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::SPLAT_VECTOR, llvm::ISD::STEP_VECTOR, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::TargetLoweringBase::TypeLegal, llvm::ISD::UINT_TO_FP, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zextOrTrunc().

Referenced by foldAddSubOfSignBit(), foldBinOpIntoSelectIfProfitable(), getNode(), getTargetVShiftByConstNode(), getTargetVShiftNode(), LowerRotate(), PromoteMaskArithmetic(), llvm::TargetLowering::SimplifyDemandedBits(), and llvm::TargetLowering::SimplifyDemandedVectorElts().

◆ foldConstantFPMath()

SDValue SelectionDAG::foldConstantFPMath ( unsigned  Opcode,
const SDLoc DL,
EVT  VT,
ArrayRef< SDValue Ops 
)

◆ FoldSetCC()

SDValue SelectionDAG::FoldSetCC ( EVT  VT,
SDValue  N1,
SDValue  N2,
ISD::CondCode  Cond,
const SDLoc dl 
)

◆ FoldSymbolOffset()

SDValue SelectionDAG::FoldSymbolOffset ( unsigned  Opcode,
EVT  VT,
const GlobalAddressSDNode GA,
const SDNode N2 
)

◆ getAddrSpaceCast()

SDValue SelectionDAG::getAddrSpaceCast ( const SDLoc dl,
EVT  VT,
SDValue  Ptr,
unsigned  SrcAS,
unsigned  DestAS 
)

◆ getAllOnesConstant()

SDValue llvm::SelectionDAG::getAllOnesConstant ( const SDLoc DL,
EVT  VT,
bool  IsTarget = false,
bool  IsOpaque = false 
)
inline

◆ getAnyExtOrTrunc()

SDValue SelectionDAG::getAnyExtOrTrunc ( SDValue  Op,
const SDLoc DL,
EVT  VT 
)

◆ getAssertAlign()

SDValue SelectionDAG::getAssertAlign ( const SDLoc DL,
SDValue  V,
Align  A 
)

◆ getAtomic() [1/3]

SDValue SelectionDAG::getAtomic ( unsigned  Opcode,
const SDLoc dl,
EVT  MemVT,
EVT  VT,
SDValue  Chain,
SDValue  Ptr,
MachineMemOperand MMO 
)

Gets a node for an atomic op, produces result and chain and takes 1 operand.

Definition at line 8714 of file SelectionDAG.cpp.

References assert(), llvm::ISD::ATOMIC_LOAD, getAtomic(), getVTList(), and Ptr.

◆ getAtomic() [2/3]

SDValue SelectionDAG::getAtomic ( unsigned  Opcode,
const SDLoc dl,
EVT  MemVT,
SDValue  Chain,
SDValue  Ptr,
SDValue  Val,
MachineMemOperand MMO 
)

◆ getAtomic() [3/3]

SDValue SelectionDAG::getAtomic ( unsigned  Opcode,
const SDLoc dl,
EVT  MemVT,
SDVTList  VTList,
ArrayRef< SDValue Ops,
MachineMemOperand MMO 
)

◆ getAtomicCmpSwap()

SDValue SelectionDAG::getAtomicCmpSwap ( unsigned  Opcode,
const SDLoc dl,
EVT  MemVT,
SDVTList  VTs,
SDValue  Chain,
SDValue  Ptr,
SDValue  Cmp,
SDValue  Swp,
MachineMemOperand MMO 
)

Gets a node for an atomic cmpxchg op.

There are two valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a chain result. ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS produces the value loaded, a success flag (initially i1), and a chain.

Definition at line 8670 of file SelectionDAG.cpp.

References assert(), llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, getAtomic(), llvm::SDValue::getValueType(), and Ptr.

◆ getAtomicMemcpy()

SDValue SelectionDAG::getAtomicMemcpy ( SDValue  Chain,
const SDLoc dl,
SDValue  Dst,
SDValue  Src,
SDValue  Size,
Type SizeTy,
unsigned  ElemSz,
bool  isTailCall,
MachinePointerInfo  DstPtrInfo,
MachinePointerInfo  SrcPtrInfo 
)

◆ getAtomicMemmove()

SDValue SelectionDAG::getAtomicMemmove ( SDValue  Chain,
const SDLoc dl,
SDValue  Dst,
SDValue  Src,
SDValue  Size,
Type SizeTy,
unsigned  ElemSz,
bool  isTailCall,
MachinePointerInfo  DstPtrInfo,
MachinePointerInfo  SrcPtrInfo 
)

◆ getAtomicMemset()

SDValue SelectionDAG::getAtomicMemset ( SDValue  Chain,
const SDLoc dl,
SDValue  Dst,
SDValue  Value,
SDValue  Size,
Type SizeTy,
unsigned  ElemSz,
bool  isTailCall,
MachinePointerInfo  DstPtrInfo 
)

◆ getBasicBlock()

SDValue SelectionDAG::getBasicBlock ( MachineBasicBlock MBB)

◆ getBFI()

BlockFrequencyInfo * llvm::SelectionDAG::getBFI ( ) const
inline

Definition at line 505 of file SelectionDAG.h.

◆ getBitcast()

SDValue SelectionDAG::getBitcast ( EVT  VT,
SDValue  V 
)

Return a bitcast using the SDLoc of the value operand, and casting to the provided type.

Use getNode to set a custom SDLoc.

Definition at line 2372 of file SelectionDAG.cpp.

References llvm::ISD::BITCAST, and getNode().

Referenced by addShuffleForVecExtend(), adjustBitcastSrcVectorSSE1(), canonicalizeBitSelect(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleVectorByLane(), canonicalizeShuffleWithOp(), combineAnd(), combineAndMaskToShift(), combineAndNotIntoANDNP(), combineAndnp(), combineAndShuffleNot(), combineArithReduction(), combineBasicSADPattern(), combineBitcast(), combineBitcastToBoolVector(), combineBitcastvxi1(), combineBitOpWithMOVMSK(), combineBitOpWithPACK(), combineBitOpWithShift(), combineBITREVERSE(), combineBlendOfPermutes(), combineBROADCAST_LOAD(), combineCastedMaskArithmetic(), combineCMP(), combineCompareEqual(), combineCONCAT_VECTORS(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineConstantPoolLoads(), combineCVTP2I_CVTTP2I(), combineCVTPH2PS(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineFMulcFCMulc(), combineFneg(), combineFP_EXTEND(), combineFP_ROUND(), combineHorizOpWithShuffle(), combineLoad(), combineLogicBlendIntoConditionalNegate(), combineLogicBlendIntoPBLENDV(), combineMinMaxReduction(), combineMOVMSK(), combineMulToPMADDWD(), combineOr(), combinePMULDQ(), combinePMULH(), combinePredicateReduction(), combinePTESTCC(), combineRedundantDWordShuffle(), combineScalarAndWithMaskSetcc(), combineScalarToVector(), combineSelect(), combineSetCCMOVMSK(), combineShuffleOfBitcast(), combineShuffleToAnyExtendVectorInreg(), combineShuffleToZeroExtendVectorInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToFPTruncExtElt(), combineTruncationShuffle(), combineVectorCompareAndMaskUnaryOp(), combineVectorHADDSUB(), combineVectorPack(), combineVectorShiftImm(), combineVectorSizedSetCCEquality(), combineVPDPBUSDPattern(), combineVSelectWithAllOnesOrZeros(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), combineXor(), constructDup(), convertIntLogicToFPLogic(), convertShiftLeftToScale(), createMMXBuildVector(), EltsFromConsecutiveLoads(), expandBitCastF128ToI128(), expandBitCastI128ToF128(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandUINT_TO_FP(), ExtractBitFromMaskVector(), FixupMMXIntrinsicTypes(), FoldConstantArithmetic(), FoldIntToFPToInt(), GeneratePerfectShuffle(), getAVX2GatherNode(), getBitcastedAnyExtOrTrunc(), getBitcastedSExtOrTrunc(), getBitcastedZExtOrTrunc(), getBuildDwordsVector(), getCanonicalConstSplat(), getConstVector(), getCopyFromPartsVector(), getCopyToPartsVector(), getDataClassTest(), getDeinterleaveViaVNSRL(), getFlagsOfCmpZeroFori1(), getMaskNode(), getMemsetValue(), llvm::X86TargetLowering::getNegatedExpression(), getOnesVector(), getPack(), getScalarMaskingNode(), getScalarValueForVectorElement(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getv64i1Argument(), getVCIXISDNodeWCHAIN(), getVectorBitwiseReduce(), getVShift(), getWideningInterleave(), getZeroVector(), llvm::TargetLowering::IncrementMemoryAddress(), isHorizontalBinOp(), IsNOT(), llvm::SystemZTargetLowering::joinRegisterPartsIntoValue(), lower128BitShuffle(), lower256BitShuffle(), lower512BitShuffle(), LowerATOMIC_STORE(), LowerAVXExtend(), LowerBITCAST(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), LowerBUILD_VECTORvXbf16(), lowerBUILD_VECTORvXf16(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorOfConstants(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::HexagonTargetLowering::LowerCall(), LowerCTPOP(), LowerEXTEND_VECTOR_INREG(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerFMINIMUM_FMAXIMUM(), llvm::SITargetLowering::LowerFormalArguments(), LowerFunnelShift(), LowerHorizontalByteSum(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), lowerLaneOp(), LowerLoad(), lowerMasksToReg(), LowerMUL(), LowerMULH(), llvm::RISCVTargetLowering::LowerOperation(), lowerRegToMasks(), llvm::HexagonTargetLowering::LowerReturn(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBitMask(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithUNPCK256(), lowerShuffleWithVPMOV(), LowerStore(), LowerTruncateVecI1(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), lowerV16F32Shuffle(), lowerV16I32Shuffle(), lowerV16I8Shuffle(), lowerV2I64Shuffle(), lowerV4F32Shuffle(), lowerV4I32Shuffle(), lowerV4I64Shuffle(), lowerV8F16Shuffle(), lowerV8F32Shuffle(), lowerV8I16GeneralSingleInputShuffle(), lowerV8I16Shuffle(), lowerV8I32Shuffle(), lowerV8I64Shuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsRotate(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVectorAllEqual(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), lowerVectorIntrinsicScalars(), LowerVSETCC(), LowervXi8MulWithUNPCK(), lowerX86FPLogicOp(), matchPERM(), narrowExtractedVectorBinOp(), narrowExtractedVectorSelect(), packImage16bitOpsToDwords(), Passv64i1ArgInRegs(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformLOADCombine(), performUzpCombine(), performVECTOR_SHUFFLECombine(), processVCIXOperands(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceBuildVecToShuffleWithZero(), reduceMaskedLoadToScalarLoad(), reduceMaskedStoreToScalarStore(), reduceVMULWidth(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), splitAndLowerShuffle(), llvm::SystemZTargetLowering::splitValueIntoRegisterParts(), takeInexpensiveLog2(), truncateVectorWithNARROW(), truncateVectorWithPACK(), tryWidenMaskForShuffle(), llvm::X86TargetLowering::visitMaskedLoad(), and llvm::X86TargetLowering::visitMaskedStore().

◆ getBitcastedAnyExtOrTrunc()

SDValue SelectionDAG::getBitcastedAnyExtOrTrunc ( SDValue  Op,
const SDLoc DL,
EVT  VT 
)

Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either any-extending or truncating it.

Definition at line 1473 of file SelectionDAG.cpp.

References assert(), DL, getAnyExtOrTrunc(), getBitcast(), llvm::EVT::getIntegerVT(), llvm::SDValue::getValueType(), llvm::EVT::isVector(), and Size.

Referenced by getDWordFromOffset(), and matchPERM().

◆ getBitcastedSExtOrTrunc()

SDValue SelectionDAG::getBitcastedSExtOrTrunc ( SDValue  Op,
const SDLoc DL,
EVT  VT 
)

Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either sign-extending or truncating it.

Definition at line 1488 of file SelectionDAG.cpp.

References assert(), DL, getBitcast(), llvm::MVT::getIntegerVT(), getSExtOrTrunc(), llvm::SDValue::getValueType(), llvm::EVT::isVector(), and Size.

◆ getBitcastedZExtOrTrunc()

SDValue SelectionDAG::getBitcastedZExtOrTrunc ( SDValue  Op,
const SDLoc DL,
EVT  VT 
)

Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either zero-extending or truncating it.

Definition at line 1503 of file SelectionDAG.cpp.

References assert(), DL, getBitcast(), llvm::MVT::getIntegerVT(), llvm::SDValue::getValueType(), getZExtOrTrunc(), llvm::EVT::isVector(), and Size.

◆ getBlockAddress()

SDValue SelectionDAG::getBlockAddress ( const BlockAddress BA,
EVT  VT,
int64_t  Offset = 0,
bool  isTarget = false,
unsigned  TargetFlags = 0 
)

◆ getBoolConstant()

SDValue SelectionDAG::getBoolConstant ( bool  V,
const SDLoc DL,
EVT  VT,
EVT  OpVT 
)

◆ getBoolExtOrTrunc()

SDValue SelectionDAG::getBoolExtOrTrunc ( SDValue  Op,
const SDLoc SL,
EVT  VT,
EVT  OpVT 
)

Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it.

Definition at line 1518 of file SelectionDAG.cpp.

References llvm::EVT::bitsLE(), llvm::TargetLoweringBase::getBooleanContents(), llvm::TargetLoweringBase::getExtendForContent(), getNode(), and llvm::ISD::TRUNCATE.

Referenced by combineCarryDiamond(), combineSelectAsExtAnd(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandUADDSUBO(), and llvm::TargetLowering::SimplifySetCC().

◆ getBuildVector() [1/2]

SDValue llvm::SelectionDAG::getBuildVector ( EVT  VT,
const SDLoc DL,
ArrayRef< SDUse Ops 
)
inline

Return an ISD::BUILD_VECTOR node.

The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.

Definition at line 853 of file SelectionDAG.h.

References llvm::ISD::BUILD_VECTOR, DL, and getNode().

◆ getBuildVector() [2/2]

SDValue llvm::SelectionDAG::getBuildVector ( EVT  VT,
const SDLoc DL,
ArrayRef< SDValue Ops 
)
inline

Return an ISD::BUILD_VECTOR node.

The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.

Definition at line 844 of file SelectionDAG.h.

References llvm::ISD::BUILD_VECTOR, DL, and getNode().

Referenced by adjustLoadValueTypeImpl(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), BuildExactSDIV(), BuildExactUDIV(), buildScalarToVector(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), combineConcatVectorOfScalars(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineShuffleOfScalars(), combineStore(), combineToExtendBoolVectorInReg(), combineX86ShuffleChain(), CompactSwizzlableVector(), convertLocVTToValVT(), convertShiftLeftToScale(), ExtendToType(), extractSubVector(), foldCONCAT_VECTORS(), FoldConstantArithmetic(), GenerateFixedLengthSVETBL(), GenerateTBL(), getBuildDwordsVector(), getBuildVectorSplat(), getConstant(), getConstVector(), getCopyFromPartsVector(), getDWordFromOffset(), getGeneralPermuteNode(), getGFNICtrlMask(), llvm::TargetLowering::getNegatedExpression(), getNode(), getStepVector(), getTargetVShiftNode(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorShuffle(), incDecVectorConstant(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorToBitOp(), LowerBuildVectorv4x32(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), lowerINT_TO_FP_vXi64(), lowerLaneOp(), lowerMSABinaryBitImmIntr(), lowerMSASplatZExt(), LowerMUL(), LowerShift(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleWithPSHUFB(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerTruncateVectorStore(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerV16I8Shuffle(), lowerV8I16Shuffle(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_VSHF(), lowerVECTOR_SHUFFLE_VSHUF(), lowerVECTOR_SHUFFLE_XVSHUF(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOPInRegLUT(), LowervXi8MulWithUNPCK(), NormalizeBuildVector(), packImage16bitOpsToDwords(), padEltsToUndef(), performBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), performConcatVectorsCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performINTRINSIC_WO_CHAINCombine(), PerformLOADCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performVSelectCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), ReorganizeVector(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeBinOpOfSplats(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::SimplifyDemandedVectorElts(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), takeInexpensiveLog2(), tryBuildVectorShuffle(), tryToConvertShuffleOfTbl2ToTbl4(), tryToFoldExtendOfConstant(), UnrollVectorOp(), UnrollVectorOverflowOp(), unrollVectorShift(), and widenVectorToPartType().

◆ getCALLSEQ_END() [1/2]

SDValue llvm::SelectionDAG::getCALLSEQ_END ( SDValue  Chain,
SDValue  Op1,
SDValue  Op2,
SDValue  InGlue,
const SDLoc DL 
)
inline

◆ getCALLSEQ_END() [2/2]

SDValue llvm::SelectionDAG::getCALLSEQ_END ( SDValue  Chain,
uint64_t  Size1,
uint64_t  Size2,
SDValue  Glue,
const SDLoc DL 
)
inline

Definition at line 1109 of file SelectionDAG.h.

References DL, getCALLSEQ_END(), and getIntPtrConstant().

◆ getCALLSEQ_START()

SDValue llvm::SelectionDAG::getCALLSEQ_START ( SDValue  Chain,
uint64_t  InSize,
uint64_t  OutSize,
const SDLoc DL 
)
inline

◆ getCallSiteInfo()

CallSiteInfo llvm::SelectionDAG::getCallSiteInfo ( const SDNode Node)
inline

◆ getCommutedVectorShuffle()

SDValue SelectionDAG::getCommutedVectorShuffle ( const ShuffleVectorSDNode SV)

Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands.

Example: shuffle A, B, <0,5,2,7> -> shuffle B, A, <4,1,6,3>

Definition at line 2257 of file SelectionDAG.cpp.

References llvm::ShuffleVectorSDNode::commuteMask(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), and getVectorShuffle().

Referenced by lowerVECTOR_SHUFFLE().

◆ getCondCode()

SDValue SelectionDAG::getCondCode ( ISD::CondCode  Cond)

◆ getConstant() [1/3]

SDValue SelectionDAG::getConstant ( const APInt Val,
const SDLoc DL,
EVT  VT,
bool  isTarget = false,
bool  isOpaque = false 
)

Definition at line 1634 of file SelectionDAG.cpp.

References DL, and getConstant().

◆ getConstant() [2/3]

SDValue SelectionDAG::getConstant ( const ConstantInt Val,
const SDLoc DL,
EVT  VT,
bool  isTarget = false,
bool  isOpaque = false 
)

◆ getConstant() [3/3]

SDValue SelectionDAG::getConstant ( uint64_t  Val,
const SDLoc DL,
EVT  VT,
bool  isTarget = false,
bool  isOpaque = false 
)

Create a ConstantSDNode wrapping a constant value.

If VT is a vector type, the constant is splatted into a BUILD_VECTOR.

If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal).

Definition at line 1625 of file SelectionDAG.cpp.

References assert(), DL, getConstant(), llvm::EVT::getScalarType(), and llvm::EVT::getSizeInBits().

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addIPMSequence(), adjustForSubtraction(), adjustForTestUnderMask(), adjustICmpTruncate(), adjustSubwordCmp(), adjustZeroCmp(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), bitcastf32Toi32(), buildCallOperands(), BuildExactSDIV(), BuildExactUDIV(), BuildIntrinsicOp(), llvm::SITargetLowering::buildRSRC(), llvm::TargetLowering::BuildSDIV(), llvm::PPCTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), canonicalizeShuffleVectorByLane(), carryFlagToValue(), checkSignTestSetCCCombine(), clampDynamicVectorIndex(), combine_CC(), combineAcrossLanesIntrinsic(), combineADC(), combineAddOfBooleanXor(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAnd(), combineAndLoadToBZHI(), combineAndnp(), CombineANDShift(), combineArithReduction(), combineAVG(), CombineBaseUpdate(), combineBitcast(), combineBitcastToBoolVector(), combineCarryDiamond(), combineCarryThroughADD(), combineCMov(), combineCMP(), combineCompareEqual(), combineCONCAT_VECTORS(), combineConcatVectorOps(), combineDeMorganOfBoolean(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFP_EXTEND(), combineGatherScatter(), combineI8TruncStore(), combineKSHIFT(), combineM68kBrCond(), combineMinMaxReduction(), combineMOVMSK(), combineMul(), combineMulSpecial(), combineMulToPMADDWD(), combineOr(), combinePMULDQ(), combinePredicateReduction(), combinePTESTCC(), combineScalarAndWithMaskSetcc(), llvm::VETargetLowering::combineSelect(), combineSelect(), llvm::VETargetLowering::combineSelectCC(), combineSelectOfTwoConstants(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToMULH(), combineStore(), combineSub(), combineSubOfBoolean(), combineSubSetcc(), combineSVEPrefetchVecBaseImmOff(), combineSVEReductionFP(), combineSVEReductionInt(), combineSVEReductionOrderedFP(), combineToExtendBoolVectorInReg(), combineTruncOfSraSext(), combineTruncSelectToSMaxUSat(), combineUADDO_CARRYDiamond(), combineV3I8LoadExt(), combineVectorCompare(), combineVectorMulToSraBitcast(), combineVectorShiftImm(), combineVectorShiftVar(), combineVectorSizedSetCCEquality(), CombineVMOVDRRCandidateWithVecOp(), combineVPMADD(), combineVSelectWithAllOnesOrZeros(), combinevXi1ConstantToInteger(), combineX86AddSub(), combineX86ShuffleChain(), constantFoldBFE(), constructDup(), constructRetValue(), ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), convertFixedMaskToScalableVector(), convertFromScalableVector(), convertShiftLeftToScale(), convertToScalableVector(), convertValVTToLocVT(), CreateCopyOfByValArgument(), createFPCmp(), createLoadLR(), createPSADBW(), createSetFPEnvNodes(), createStoreLR(), createVariablePermute(), createVPDPBUSD(), llvm::TargetLowering::CTTZTableLookup(), customLegalizeToWOp(), EltsFromConsecutiveLoads(), EmitCMP(), emitConditionalComparison(), emitConstantSizeRepmov(), emitMemMemImm(), emitMemMemReg(), emitSETCC(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrlen(), EmitTest(), Expand64BitShift(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), expandDivFix(), llvm::TargetLowering::expandDIVREMByConstant(), expandf64Toi32(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandFunnelShift(), llvm::TargetLowering::expandIntMINMAX(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandIS_FPCLASS(), expandMul(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandROT(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorSplice(), llvm::TargetLowering::expandVPBITREVERSE(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::expandVPCTLZ(), llvm::TargetLowering::expandVPCTPOP(), llvm::TargetLowering::expandVPCTTZ(), llvm::TargetLowering::expandVPCTTZElements(), expandVPFunnelShift(), ExtendToType(), extractF64Exponent(), extractShiftForRotate(), finalizeTS1AM(), foldADCToCINC(), foldAddSubBoolOfMaskedVal(), foldAndOrOfSETCC(), foldAndToUsubsat(), FoldConstantArithmetic(), foldCSELOfCSEL(), foldCSELofCTTZ(), foldExtendedSignBitTest(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldSelectOfConstantsUsingSra(), foldSelectOfCTTZOrCTLZ(), FoldSetCC(), foldSetCCWithFunnelShift(), FoldSTEP_VECTOR(), foldVSelectToSignBitSplatMask(), foldXorTruncShiftIntoCmp(), llvm::TargetLowering::forceExpandWideMUL(), genConstMult(), generateEquivalentSub(), GenerateFixedLengthSVETBL(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), llvm::MipsTargetLowering::getAddrNonPICSym64(), getAllOnesConstant(), getARMIndexedAddressParts(), getAVX512Node(), getBitTestCondition(), getBoolConstant(), getBoundedStrlen(), getBuildVectorSplat(), getCanonicalConstSplat(), getCCResult(), getConstant(), llvm::VECustomDAG::getConstant(), llvm::VECustomDAG::getConstantMask(), getConstVector(), getCopyFromParts(), llvm::RegsForValue::getCopyFromRegs(), getCSAddressAndShifts(), getDataClassTest(), getDefaultVLOps(), getDeinterleaveViaVNSRL(), getDWordFromOffset(), getElementCount(), GetExponent(), getFlagsOfCmpZeroFori1(), getGeneralPermuteNode(), getGFNICtrlMask(), llvm::AMDGPUTargetLowering::getHiHalf64(), getIntPtrConstant(), getLimitedPrecisionExp2(), llvm::AMDGPUTargetLowering::getLoHalf64(), llvm::VECustomDAG::getMaskBroadcast(), getMaskNode(), getMemBasePlusOffset(), getMemsetStringVal(), getMemsetValue(), getMVEIndexedAddressParts(), getNegatedInteger(), getNegative(), getNeutralElement(), getNode(), getPack(), getPMOVMSKB(), llvm::AVRTargetLowering::getPostIndexedAddressParts(), llvm::AVRTargetLowering::getPreIndexedAddressParts(), getPTest(), getPTrue(), getReductionSDNode(), getScaledOffsetForBitWidth(), getSETCC(), getShiftAmountConstant(), getShuffleScalarElt(), GetSignificand(), llvm::NVPTXTargetLowering::getSqrtEstimate(), getStepVector(), getSVEPredicateBitCast(), getT2IndexedAddressParts(), getTargetConstant(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getTruncatedUSUBSAT(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorBitwiseReduce(), getVectorIdxConstant(), llvm::TargetLowering::getVectorSubVecPointer(), getVPZeroExtendInReg(), getVScale(), getWideningInterleave(), getZeroExtendInReg(), getZeroVector(), getzOSCalleeAndADA(), incDecVectorConstant(), llvm::TargetLowering::IncrementMemoryAddress(), insert1BitVector(), IntCondCCodeToICC(), isBLACompatibleAddress(), isConditionalZeroOrAllOnes(), IsSingleInstrConstant(), legalizeIntrinsicImmArg(), llvm::AMDGPUTargetLowering::loadInputValue(), lower1BitShuffle(), LowerABS(), LowerADDSAT_SUBSAT(), LowerAndToBT(), LowerAndToBTST(), LowerAsSplatVectorLoad(), LowerATOMIC_FENCE(), LowerAVXExtend(), lowerBALLOTIntrinsic(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), llvm::LanaiTargetLowering::LowerBR_CC(), LowerBR_CC(), LowerBRCOND(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBUILD_VECTOR(), LowerBUILD_VECTOR_i1(), LowerBUILD_VECTORToVIDUP(), LowerBUILD_VECTORvXi1(), lowerBuildVectorOfConstants(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv16i8(), lowerBuildVectorViaPacking(), llvm::SITargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), LowerCallResult(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), LowerCONCAT_VECTORSvXi1(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::lowerCTLZResults(), LowerCTPOP(), LowerCTTZ(), lowerCttzElts(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_i1(), llvm::SparcTargetLowering::LowerF128Compare(), LowerF128Load(), LowerF128Store(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), llvm::AMDGPUTargetLowering::lowerFEXP(), LowerFGETSIGN(), LowerFLDEXP(), llvm::AMDGPUTargetLowering::LowerFLOGCommon(), LowerFMINIMUM_FMAXIMUM(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFP16_TO_FP(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), LowerFP_TO_INT_SAT(), lowerFP_TO_INT_SAT(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), LowerFunnelShift(), llvm::SITargetLowering::lowerGET_ROUNDING(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), lowerGR128ToI128(), LowerHorizontalByteSum(), lowerI128ToGR128(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), LowerINSERT_VECTOR_ELT_i1(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(), lowerINT_TO_FP_vXi64(), LowerInterruptReturn(), llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(), LowerINTRINSIC_W_CHAIN(), LowerLabelRef(), lowerLaneOp(), llvm::MipsTargetLowering::lowerLOAD(), lowerLoadF128(), lowerLoadI1(), LowerMemOpCallTo(), lowerMSABinaryBitImmIntr(), lowerMSABitClear(), lowerMSABitClearImm(), lowerMSASplatImm(), lowerMSASplatZExt(), LowerMUL(), llvm::LanaiTargetLowering::LowerMUL(), lowerMUL_LOHI32(), LowerMULH(), LowerMULO(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), lowerOverflowArithmetic(), LowerPARITY(), LowerPredicateLoad(), LowerPredicateStore(), llvm::HexagonTargetLowering::LowerPREFETCH(), LowerPREFETCH(), lowerReductionSeq(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), lowerRETURNADDR(), LowerRotate(), LowerSaturatingConditional(), lowerScalarInsert(), lowerScalarSplat(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::SITargetLowering::lowerSET_FPENV(), llvm::SITargetLowering::lowerSET_ROUNDING(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCCARRY(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsTruncBroadcast(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleToEXPAND(), lowerShuffleWithPSHUFB(), LowerSIGN_EXTEND_Mask(), LowerSMELdrStr(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), lowerStoreF128(), lowerStoreI1(), LowerSVEIntrinsicEXT(), LowerTruncatei1(), LowerTruncateVecI1(), LowerTruncateVectorStore(), llvm::HexagonTargetLowering::LowerUAddSubO(), LowerUADDSUBO_CARRY(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerUnalignedLoadRetParam(), LowerUnalignedStoreParam(), LowerUnalignedStoreRet(), lowerV16I8Shuffle(), lowerV8I16Shuffle(), llvm::VETargetLowering::lowerVAARG(), LowerVecReduce(), LowerVecReduceMinMax(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), lowerVECTOR_SHUFFLE_VREPLVEI(), lowerVECTOR_SHUFFLE_VSHUF(), lowerVECTOR_SHUFFLE_VSHUF4I(), lowerVECTOR_SHUFFLE_XVREPLVEI(), lowerVECTOR_SHUFFLEAsRotate(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorAllEqual(), lowerVectorBitClear(), lowerVectorBitClearImm(), lowerVectorBitRevImm(), lowerVectorBitSetImm(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOPInRegLUT(), lowerVectorIntrinsicScalars(), lowerVectorSplatImm(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowervXi8MulWithUNPCK(), lowerX86CmpEqZeroToCtlzSrl(), LowerXALUO(), LowerZERO_EXTEND_Mask(), llvm::SparcTargetLowering::makeAddress(), matchPERM(), MatchVectorAllEqualTest(), memsetStore(), narrowIndex(), NormalizeBuildVector(), optimizeLogicalImm(), overflowFlagToValue(), llvm::SITargetLowering::passSpecialInputs(), performAddCSelIntoCSinc(), PerformAddcSubcCombine(), PerformAddeSubeCombine(), performAddSubIntoVectorOp(), performAddUADDVCombine(), performANDCombine(), performANDORCSELCombine(), performANDSETCCCombine(), PerformARMBUILD_VECTORCombine(), PerformBFICombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), PerformCSETCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDSPShiftCombine(), performDUPCombine(), performExtBinopLoadFold(), PerformEXTRACTCombine(), PerformExtractEltCombine(), PerformExtractEltToVMOVRRD(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFlagSettingCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFP_TO_INT_SATCombine(), performFpToIntCombine(), performGlobalAddressCombine(), performINTRINSIC_WO_CHAINCombine(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), performLDNT1Combine(), PerformLongShiftCombine(), PerformMinMaxCombine(), PerformMinMaxToSatCombine(), performMulCombine(), PerformMULCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performORCombine(), PerformORCombineToBFI(), PerformPREDICATE_CASTCombine(), performScalarToVectorCombine(), performSetccAddFolding(), performSETCCCombine(), PerformShiftCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), performSHLCombine(), PerformSHLSimplify(), PerformShuffleVMOVNCombine(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performSraCombine(), performSRACombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performSRLCombine(), PerformSTORECombine(), performSUBCombine(), PerformSUBCombine(), performSubsToAndsCombine(), performSVEAndCombine(), performTBZCombine(), performTruncateCombine(), PerformTruncatingStoreCombine(), performUnpackCombine(), performUzpCombine(), PerformVCMPCombine(), PerformVCVTCombine(), PerformVDUPCombine(), performVecReduceAddCombine(), performVecReduceAddCombineWithUADDLP(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), PerformVMulVCTPCombine(), performVSelectCombine(), PerformVSELECTCombine(), PerformVSetCCToVCTPCombine(), performXORCombine(), PerformXORCombine(), prepareTS1AM(), promoteExtBeforeAdd(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReconstructShuffleWithRuntimeMask(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), refineUniformBase(), ReplaceATOMIC_LOAD_128Results(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), replaceVPICKVE2GRResults(), resolveSources(), SaturateWidenedDIVFIX(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::TargetLowering::ShrinkDemandedConstant(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::ARMTargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), simplifyShift(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), llvm::AMDGPUTargetLowering::split64BitValue(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), SplitEVL(), splitStores(), splitStoreSplat(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::AMDGPUTargetLowering::storeStackInputValue(), takeInexpensiveLog2(), llvm::ARMTargetLowering::targetShrinkDemandedConstant(), llvm::RISCVTargetLowering::targetShrinkDemandedConstant(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), transformAddImmMulImm(), transformAddShlImm(), TranslateM68kCC(), translateSetCCForBranch(), TranslateX86CC(), truncateVecElts(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), tryAdvSIMDModImmFP(), TryCombineBaseUpdate(), tryCombineMULLWithUZP1(), tryCombineShiftImm(), tryConvertSVEWideCompare(), tryDemorganOfBooleanCondition(), tryExtendDUPToExtractHigh(), tryFoldSelectIntoOp(), tryFoldToZero(), tryFormConcatFromShuffle(), tryMemPairCombine(), TryMULWIDECombine(), tryToConvertShuffleOfTbl2ToTbl4(), tryToFoldExtendOfConstant(), tryWhileWRFromOR(), UnpackFromArgumentSlot(), UnrollVectorOverflowOp(), unrollVectorShift(), valueToCarryFlag(), vectorToScalarBitmask(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::X86TargetLowering::visitMaskedLoad(), llvm::SelectionDAGBuilder::visitSwitchCase(), WidenVector(), and widenVectorOpsToi8().

◆ getConstantDbgValue()

SDDbgValue * SelectionDAG::getConstantDbgValue ( DIVariable Var,
DIExpression Expr,
const Value C,
const DebugLoc DL,
unsigned  O 
)

◆ getConstantFP() [1/3]

SDValue SelectionDAG::getConstantFP ( const APFloat Val,
const SDLoc DL,
EVT  VT,
bool  isTarget = false 
)

Definition at line 1774 of file SelectionDAG.cpp.

References DL, getConstantFP(), and getContext().

◆ getConstantFP() [2/3]

SDValue SelectionDAG::getConstantFP ( const ConstantFP V,
const SDLoc DL,
EVT  VT,
bool  isTarget = false 
)

◆ getConstantFP() [3/3]

SDValue SelectionDAG::getConstantFP ( double  Val,
const SDLoc DL,
EVT  VT,
bool  isTarget = false 
)

Create a ConstantFPSDNode wrapping a constant value.

If VT is a vector type, the constant is splatted into a BUILD_VECTOR.

If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal). The forms that take a double should only be used for simple constants that can be exactly represented in VT. No checks are made.

Definition at line 1812 of file SelectionDAG.cpp.

References llvm::APFloat::convert(), DL, EVTToAPFloatSemantics(), getConstantFP(), llvm::EVT::getScalarType(), llvm_unreachable, and llvm::APFloatBase::rmNearestTiesToEven.

Referenced by combineBitcast(), combineExtractWithShuffle(), combineFneg(), combineFP_ROUND(), combineVSelectWithAllOnesOrZeros(), EltsFromConsecutiveLoads(), expandExp(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_UINT(), expandFP_TO_UINT_SSE(), llvm::TargetLowering::expandIS_FPCLASS(), expandLog(), ExpandPowI(), llvm::TargetLowering::expandUINT_TO_FP(), FoldConstantArithmetic(), foldConstantFPMath(), getConstantFP(), getConstVector(), getF32Constant(), getInvertedVectorForFMA(), llvm::AMDGPUTargetLowering::getIsFinite(), llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(), getMemsetStringVal(), getMemsetValue(), llvm::TargetLowering::getNegatedExpression(), getNeutralElement(), getNode(), getRVVFPReductionOpAndOperands(), llvm::AMDGPUTargetLowering::getScaledLogInput(), getShuffleScalarElt(), llvm::TargetLowering::getSqrtInputTest(), llvm::TargetLowering::getSqrtResultForDenormInput(), getTargetConstantFP(), llvm::SelectionDAGBuilder::getValueImpl(), getZeroVector(), LowerFABSorFNEG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), LowerFCOPYSIGN(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::AMDGPUTargetLowering::LowerFLOG2(), llvm::AMDGPUTargetLowering::LowerFLOGCommon(), llvm::AMDGPUTargetLowering::LowerFLOGUnsafe(), LowerFMINIMUM_FMAXIMUM(), LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerShuffleAsBitMask(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i32(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performRcpCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyFPBinop(), and strictFPExtFromF16().

◆ getConstantPool() [1/2]

SDValue SelectionDAG::getConstantPool ( const Constant C,
EVT  VT,
MaybeAlign  Align = std::nullopt,
int  Offs = 0,
bool  isT = false,
unsigned  TargetFlags = 0 
)

◆ getConstantPool() [2/2]

SDValue SelectionDAG::getConstantPool ( MachineConstantPoolValue C,
EVT  VT,
MaybeAlign  Align = std::nullopt,
int  Offs = 0,
bool  isT = false,
unsigned  TargetFlags = 0 
)

◆ getContext()

LLVMContext * llvm::SelectionDAG::getContext ( ) const
inline

Definition at line 502 of file SelectionDAG.h.

Referenced by AddCombineVUZPToVPADDL(), llvm::RegsForValue::AddInlineAsmOperands(), addShuffleForVecExtend(), adjustLoadValueTypeImpl(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), BuildVectorFromScalar(), canCombineShuffleToExtendVectorInreg(), canFoldInAddressingMode(), checkIntrinsicImmArg(), CollectOpsToWiden(), combineAnd(), combineAndShuffleNot(), combineArithReduction(), combineBasicSADPattern(), combineBinOpOfExtractToReduceTree(), combineBinOpOfZExt(), combineBitcastToBoolVector(), combineBitcastvxi1(), combineBoolVectorAndTruncateStore(), combineCMP(), combineCONCAT_VECTORS(), combineConcatVectorOfCasts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFMinNumFMaxNum(), combineFP_EXTEND(), combineFP_ROUND(), combineI8TruncStore(), combineLoad(), combineMinNumMaxNumImpl(), combineOr(), combinePMULH(), combinePredicateReduction(), combineScalarAndWithMaskSetcc(), combineSelect(), combineShiftAnd1ToBitTest(), combineShiftToAVG(), combineShiftToMULH(), combineShuffleToZeroExtendVectorInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToFPTruncExtElt(), combineTruncateWithSat(), combineUIntToFP(), combineV3I8LoadExt(), combineVectorMulToSraBitcast(), CombineVMOVDRRCandidateWithVecOp(), combineVPDPBUSDPattern(), combineVSelectWithAllOnesOrZeros(), combinevXi1ConstantToInteger(), concatSubVectors(), constructRetValue(), convertIntLogicToFPLogic(), CreateStackTemporary(), llvm::TargetLowering::CTTZTableLookup(), detectPMADDUBSW(), earlyExpandDIVFIX(), EltsFromConsecutiveLoads(), llvm::SelectionDAGBuilder::EmitBranchForMergedCondition(), emitErrorAndReplaceIntrinsicResults(), emitIntrinsicErrorMessage(), emitIntrinsicWithChainErrorMessage(), emitNonHSAIntrinsicError(), emitRemovedIntrinsicError(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), errorUnsupported(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandAVG(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), expandDivFix(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), llvm::TargetLowering::expandVecReduce(), llvm::TargetLowering::expandVectorSplice(), llvm::TargetLowering::expandVPCTPOP(), llvm::TargetLowering::expandVPCTTZElements(), extractSubVector(), fail(), findMemType(), FoldConstantArithmetic(), foldExtendVectorInregToExtendOfSubvector(), foldShuffleOfConcatUndefs(), foldXorTruncShiftIntoCmp(), llvm::TargetLowering::forceExpandWideMUL(), GenerateFixedLengthSVETBL(), getAtomicMemcpy(), getAtomicMemmove(), getAtomicMemset(), getConstant(), getConstantFP(), getCopyFromParts(), getCopyFromPartsVector(), llvm::SelectionDAGBuilder::getCopyFromRegs(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::RegsForValue::getCopyToRegs(), GetDependentSplitDestVTs(), getEVTAlign(), llvm::AMDGPUTargetLowering::getIsFinite(), llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(), getMemcpy(), getMemcpyLoadsAndStores(), getMemmove(), getMemmoveLoadsAndStores(), getMemset(), getMemsetStores(), getMemsetStringVal(), getMemsetValue(), getPrefTypeAlign(), getPTest(), getReducedAlign(), getRegistersForValue(), llvm::AMDGPUTargetLowering::getScaledLogInput(), getSplatValue(), GetSplitDestVTs(), llvm::AMDGPUTargetLowering::getSplitDestVTs(), llvm::TargetLowering::getSqrtInputTest(), GetTLSADDR(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorBitwiseReduce(), llvm::TargetLowering::getVectorElementPointer(), llvm::VECustomDAG::getVectorVT(), llvm::TargetLowering::IncrementMemoryAddress(), llvm::SelectionDAGBuilder::init(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), isSaturatingMinMax(), isUpperSubvectorUndef(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), legalizeIntrinsicImmArg(), LowerADDSAT_SUBSAT(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), LowerAsSplatVectorLoad(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), lowerBitreverseShuffle(), lowerBuildVectorAsBroadcast(), llvm::SITargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SITargetLowering::LowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallSiteWithDeoptBundleImpl(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), llvm::AMDGPUTargetLowering::LowerFCEIL(), lowerFCMPIntrinsic(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFMINIMUM_FMAXIMUM(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), lowerICMPIntrinsic(), lowerLaneOp(), LowerMSCATTER(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), LowerPredicateLoad(), LowerPredicateStore(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::SITargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::SelectionDAGBuilder::LowerStatepoint(), LowerStore(), LowerSVEIntrinsicEXT(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::VETargetLowering::lowerToVVP(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), LowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), lowerVectorBitClearImm(), lowerVectorBitRevImm(), lowerVectorBitSetImm(), LowerVectorExtend(), lowerVectorSplatImm(), LowerVSETCC(), llvm::VETargetLowering::lowerVVP_LOAD_STORE(), llvm::SystemZTargetLowering::makeExternalCall(), llvm::TargetLowering::makeLibCall(), makeStateFunctionCall(), matchBinOpReduction(), matchPMADDWD(), matchPMADDWD_2(), narrowExtractedVectorBinOp(), narrowIndex(), PerformARMBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), performConcatVectorsCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performDUPCombine(), performExtBinopLoadFold(), PerformExtractFpToIntStores(), PerformInsertEltCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), performLOADCombine(), PerformMinMaxFpToSatCombine(), performMSTORECombine(), performMulVectorCmpZeroCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performSelectCombine(), performSignExtendInRegCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), performSunpkloCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), performUADDVZextCombine(), PerformUMinFpToSatCombine(), performUzpCombine(), performVecReduceAddCombine(), performVectorExtCombine(), llvm::TargetLoweringBase::promoteTargetBoolean(), promoteToConstantPool(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceVMULWidth(), ReplaceLoadVector(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), shouldTransformMulToShiftsAddsSubs(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), llvm::TargetLowering::softenSetCCOperands(), splitStores(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateVectorWithNARROW(), truncateVectorWithPACK(), tryCombineMULLWithUZP1(), tryFormConcatFromShuffle(), UnrollVectorOp(), UnrollVectorOverflowOp(), llvm::TargetLowering::verifyReturnAddressArgumentIsConstant(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), widenAbs(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), widenVec(), and WidenVector().

◆ getCopyFromReg() [1/2]

SDValue llvm::SelectionDAG::getCopyFromReg ( SDValue  Chain,
const SDLoc dl,
unsigned  Reg,
EVT  VT 
)
inline

Definition at line 815 of file SelectionDAG.h.

References llvm::ISD::CopyFromReg, getNode(), getRegister(), getVTList(), and Reg.

Referenced by llvm::AMDGPUTargetLowering::CreateLiveInRegister(), expandIntrinsicWChainHelper(), llvm::RegsForValue::getCopyFromRegs(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getFRAMEADDR(), getReadTimeStampCounter(), GetTLSADDR(), getv64i1Argument(), getzOSCalleeAndADA(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), lowerBALLOTIntrinsic(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), llvm::SITargetLowering::LowerCallResult(), llvm::HexagonTargetLowering::LowerCallResult(), LowerCallResult(), LowerCMP_SWAP(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINTRINSIC_W_CHAIN(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::LanaiTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::SITargetLowering::LowerSTACKSAVE(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), performDivRemCombine(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceZeroVectorStore(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), llvm::LoongArchDAGToDAGISel::selectShiftMask(), llvm::AMDGPUTargetLowering::storeStackInputValue(), unpack64(), unpackF64OnRV32DSoftABI(), unpackFromRegLoc(), llvm::SelectionDAGBuilder::visitBitTestCase(), and llvm::SelectionDAGBuilder::visitJumpTable().

◆ getCopyFromReg() [2/2]

SDValue llvm::SelectionDAG::getCopyFromReg ( SDValue  Chain,
const SDLoc dl,
unsigned  Reg,
EVT  VT,
SDValue  Glue 
)
inline

◆ getCopyToReg() [1/3]

SDValue llvm::SelectionDAG::getCopyToReg ( SDValue  Chain,
const SDLoc dl,
SDValue  Reg,
SDValue  N,
SDValue  Glue 
)
inline

Definition at line 807 of file SelectionDAG.h.

References llvm::ISD::CopyToReg, llvm::SDValue::getNode(), getNode(), getVTList(), N, and Reg.

◆ getCopyToReg() [2/3]

SDValue llvm::SelectionDAG::getCopyToReg ( SDValue  Chain,
const SDLoc dl,
unsigned  Reg,
SDValue  N 
)
inline

Definition at line 789 of file SelectionDAG.h.

References llvm::ISD::CopyToReg, getNode(), getRegister(), N, and Reg.

Referenced by llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(), emitRepmovs(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), expandIntrinsicWChainHelper(), llvm::RegsForValue::getCopyToRegs(), llvm::MipsTargetLowering::getOpndList(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm::SITargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallTo(), LowerCMP_SWAP(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::SITargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::XtensaTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerSETCCCARRY(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSLocalDynamicModel(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::SITargetLowering::PostISelFolding(), prepareDescriptorIndirectCall(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::Select(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::SelectionDAGBuilder::visitBitTestHeader(), and llvm::SelectionDAGBuilder::visitJumpTableHeader().

◆ getCopyToReg() [3/3]

SDValue llvm::SelectionDAG::getCopyToReg ( SDValue  Chain,
const SDLoc dl,
unsigned  Reg,
SDValue  N,
SDValue  Glue 
)
inline

◆ getDataLayout()

const DataLayout & llvm::SelectionDAG::getDataLayout ( ) const
inline

Definition at line 489 of file SelectionDAG.h.

References llvm::MachineFunction::getDataLayout().

Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), analyzeCallOperands(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), BuildExactSDIV(), BuildExactUDIV(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::buildSDIVPow2WithCMov(), llvm::TargetLowering::BuildUDIV(), canCombineShuffleToExtendVectorInreg(), canFoldInAddressingMode(), combineBVOfVecSExt(), combineConcatVectorOps(), combineFMinNumFMaxNum(), combineGatherScatter(), combineLoad(), combinePredicateReduction(), combineShiftAnd1ToBitTest(), combineShuffleToAnyExtendVectorInreg(), combineShuffleToZeroExtendVectorInReg(), combineStore(), combineTargetShuffle(), combineTruncationShuffle(), combineVSelectWithAllOnesOrZeros(), computeKnownBits(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), ComputeNumSignBits(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), createGPRPairNode(), createMMXBuildVector(), createSetFPEnvNodes(), CreateStackTemporary(), llvm::TargetLowering::CTTZTableLookup(), EltsFromConsecutiveLoads(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::X86TargetLowering::emitStackGuardXorFP(), llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::TargetLowering::expandABD(), llvm::TargetLowering::expandAddSubSat(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandCMP(), llvm::TargetLowering::expandCTLZ(), llvm::TargetLowering::expandCTPOP(), llvm::TargetLowering::expandCTTZ(), expandDivFix(), llvm::TargetLowering::expandDIVREMByConstant(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandFixedPointMul(), llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFP_ROUND(), llvm::TargetLowering::expandFP_TO_INT_SAT(), llvm::TargetLowering::expandFP_TO_SINT(), llvm::TargetLowering::expandFP_TO_UINT(), llvm::TargetLowering::expandIntMINMAX(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandMULO(), llvm::TargetLowering::expandRoundInexactToOdd(), llvm::TargetLowering::expandSADDSUBO(), llvm::TargetLowering::expandShiftParts(), llvm::TargetLowering::expandShlSat(), llvm::TargetLowering::expandUADDSUBO(), llvm::TargetLowering::expandUINT_TO_FP(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), expandVAArg(), expandVACopy(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVPBITREVERSE(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::expandVPCTLZ(), llvm::TargetLowering::expandVPCTPOP(), FoldConstantArithmetic(), foldXorTruncShiftIntoCmp(), llvm::TargetLowering::forceExpandWideMUL(), getADAEntry(), getAddressForMemoryInput(), getAtomicMemcpy(), getAtomicMemmove(), getAtomicMemset(), getAVX2GatherNode(), getConstant(), getConstantPool(), getCopyFromParts(), llvm::SelectionDAGBuilder::getCopyFromRegs(), getCopyToParts(), getEVTAlign(), GetExponent(), llvm::SelectionDAGBuilder::getFrameIndexTy(), getGatherNode(), getGlobalAddress(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), getIntPtrConstant(), llvm::AMDGPUTargetLowering::getIsFinite(), llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(), getJumpTableDebugInfo(), getLifetimeNode(), getLimitedPrecisionExp2(), getLoadStackGuard(), getMemCmpLoad(), getMemcpy(), getMemcpyLoadsAndStores(), getMemmove(), getMemmoveLoadsAndStores(), getMemset(), getMemsetStores(), getMemsetStringVal(), getNode(), llvm::TargetLowering::getPICJumpTableRelocBase(), llvm::M68kTargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::VETargetLowering::getPICJumpTableRelocBase(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), getPPCf128HiElementSelector(), getPrefetchNode(), getPrefTypeAlign(), getReducedAlign(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), llvm::AMDGPUTargetLowering::getScaledLogInput(), getScatterNode(), getShiftAmountConstant(), getShiftAmountOperand(), llvm::PPC::getSplatIdxForPPCMnemonics(), llvm::TargetLowering::getSqrtInputTest(), getSymbolFunctionGlobalAddress(), getTagSymNode(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorIdxConstant(), getzOSCalleeAndADA(), llvm::SelectionDAGBuilder::handleDebugValue(), InferPtrAlign(), llvm::SelectionDAGBuilder::init(), isBLACompatibleAddress(), isExtendedBUILD_VECTOR(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), IsPredicateKnownToFail(), isVMOVModifiedImm(), llvm::PPC::isVMRGEOShuffleMask(), llvm::PPC::isVMRGHShuffleMask(), llvm::PPC::isVMRGLShuffleMask(), llvm::PPC::isVPKUDUMShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), llvm::PPC::isVSLDOIShuffleMask(), LowerADDSAT_SUBSAT(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), llvm::HexagonTargetLowering::LowerBlockAddress(), lowerBuildVectorAsBroadcast(), llvm::NVPTXTargetLowering::LowerCall(), llvm::XtensaTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::VETargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SelectionDAGBuilder::LowerCallSiteWithPtrAuthBundle(), llvm::TargetLowering::LowerCallTo(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::LanaiTargetLowering::LowerConstantPool(), LowerCTPOP(), llvm::SelectionDAGBuilder::LowerDeoptimizeCall(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), LowerF64Op(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(), llvm::AMDGPUTargetLowering::lowerFEXP2(), llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFMINIMUM_FMAXIMUM(), LowerFNEGorFABS(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), LowerMemOpCallTo(), LowerMULO(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), LowerPredicateLoad(), LowerPredicateStore(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), LowerRETURNADDR(), llvm::SelectionDAGBuilder::LowerStatepoint(), LowerSTORE(), llvm::TargetLowering::LowerToTLSEmulatedModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), llvm::SparcTargetLowering::makeAddress(), llvm::SystemZTargetLowering::makeExternalCall(), llvm::TargetLowering::makeLibCall(), makeStateFunctionCall(), matchPERM(), narrowExtractedVectorLoad(), PerformBITCASTCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performMULCombine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), performUzpCombine(), PerformVMOVRRDCombine(), llvm::TargetLoweringBase::promoteTargetBoolean(), promoteToConstantPool(), llvm::AArch64TargetLowering::ReconstructShuffle(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), ReplaceATOMIC_LOAD_128Results(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), ReplaceLoadVector(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::RISCVDAGToDAGISel::SelectAddrRegImm(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), transformCallee(), unpackFromMemLoc(), UnrollVectorOverflowOp(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), and llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad().

◆ getDbgLabel()

SDDbgLabel * SelectionDAG::getDbgLabel ( DILabel Label,
const DebugLoc DL,
unsigned  O 
)

Creates a SDDbgLabel node.

Definition at line 11290 of file SelectionDAG.cpp.

References assert(), DL, and llvm::SDDbgInfo::getAlloc().

Referenced by llvm::SelectionDAGBuilder::visitDbgInfo().

◆ getDbgValue()

SDDbgValue * SelectionDAG::getDbgValue ( DIVariable Var,
DIExpression Expr,
SDNode N,
unsigned  R,
bool  IsIndirect,
const DebugLoc DL,
unsigned  O 
)

Creates a SDDbgValue node.

getDbgValue - Creates a SDDbgValue node.

SDNode

Definition at line 11010 of file SelectionDAG.cpp.

References assert(), DL, llvm::SDDbgOperand::fromNode(), llvm::SDDbgInfo::getAlloc(), and N.

Referenced by llvm::SelectionDAGBuilder::handleDebugDeclare().

◆ getDbgValueList()

SDDbgValue * SelectionDAG::getDbgValueList ( DIVariable Var,
DIExpression Expr,
ArrayRef< SDDbgOperand Locs,
ArrayRef< SDNode * >  Dependencies,
bool  IsIndirect,
const DebugLoc DL,
unsigned  O,
bool  IsVariadic 
)

◆ GetDbgValues()

ArrayRef< SDDbgValue * > llvm::SelectionDAG::GetDbgValues ( const SDNode SD) const
inline

Get the debug values which reference the given SDNode.

Definition at line 1850 of file SelectionDAG.h.

References llvm::SDDbgInfo::getSDDbgValues().

Referenced by ProcessSDDbgValues(), salvageDebugInfo(), and transferDbgValues().

◆ getDenormalMode()

DenormalMode llvm::SelectionDAG::getDenormalMode ( EVT  VT) const
inline

Return the current function's default denormal handling kind for the given floating point type.

Definition at line 2381 of file SelectionDAG.h.

References EVTToAPFloatSemantics(), and llvm::MachineFunction::getDenormalMode().

◆ GetDependentSplitDestVTs()

std::pair< EVT, EVT > SelectionDAG::GetDependentSplitDestVTs ( const EVT VT,
const EVT EnvVT,
bool HiIsEmpty 
) const

Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces.

GetDependentSplitDestVTs - Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces.

Sets the HisIsEmpty flag when hi type has zero storage size.

Sets the HiIsEmpty flag when hi type has zero storage size.

Definition at line 12643 of file SelectionDAG.cpp.

References assert(), getContext(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().

◆ getEHLabel()

SDValue SelectionDAG::getEHLabel ( const SDLoc dl,
SDValue  Root,
MCSymbol Label 
)

Definition at line 2297 of file SelectionDAG.cpp.

References llvm::ISD::EH_LABEL, and getLabelNode().

◆ getElementCount()

SDValue SelectionDAG::getElementCount ( const SDLoc DL,
EVT  VT,
ElementCount  EC,
bool  ConstantFold = true 
)

◆ getEntryNode()

SDValue llvm::SelectionDAG::getEntryNode ( ) const
inline

Return the token chain corresponding to the entry of the function.

Definition at line 572 of file SelectionDAG.h.

Referenced by llvm::AMDGPUTargetLowering::addTokenForArgument(), clear(), combineConcatVectorOps(), combineTargetShuffle(), copyExtraInfo(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::AMDGPUTargetLowering::CreateLiveInRegisterRaw(), llvm::TargetLowering::CTTZTableLookup(), llvm::TargetLowering::expandVECTOR_COMPRESS(), llvm::TargetLowering::expandVectorSplice(), getADAEntry(), llvm::MipsTargetLowering::getAddrLocal(), llvm::SelectionDAGBuilder::getCopyFromRegs(), getFLUSHW(), getFRAMEADDR(), getMemCmpLoad(), getStackArgumentTokenFactor(), GetTLSADDR(), llvm::SelectionDAGBuilder::getValueImpl(), getzOSCalleeAndADA(), HandleMergeInputChains(), llvm::AMDGPUTargetLowering::loadStackInputValue(), lowerBALLOTIntrinsic(), lowerBuildVectorAsBroadcast(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), lowerRETURNADDR(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCCARRY(), llvm::SelectionDAGBuilder::LowerStatepoint(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSGeneralDynamicModel64(), LowerToTLSGeneralDynamicModelX32(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerToTLSLocalDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), llvm::TargetLowering::makeLibCall(), llvm::ARMTargetLowering::PerformCMOVCombine(), performDivRemCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), llvm::SITargetLowering::PostISelFolding(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), promoteXINT_TO_FP(), llvm::SITargetLowering::ReplaceNodeResults(), replaceZeroVectorStore(), llvm::RISCVDAGToDAGISel::Select(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), llvm::LoongArchDAGToDAGISel::selectShiftMask(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getEVTAlign()

Align SelectionDAG::getEVTAlign ( EVT  MemoryVT) const

◆ getExternalSymbol()

SDValue SelectionDAG::getExternalSymbol ( const char Sym,
EVT  VT 
)

◆ getExtLoad() [1/2]

SDValue SelectionDAG::getExtLoad ( ISD::LoadExtType  ExtType,
const SDLoc dl,
EVT  VT,
SDValue  Chain,
SDValue  Ptr,
EVT  MemVT,
MachineMemOperand MMO 
)

Definition at line 8989 of file SelectionDAG.cpp.

References getLoad(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.

◆ getExtLoad() [2/2]

SDValue SelectionDAG::getExtLoad ( ISD::LoadExtType  ExtType,
const SDLoc dl,
EVT  VT,
SDValue  Chain,
SDValue  Ptr,
MachinePointerInfo  PtrInfo,
EVT  MemVT,
MaybeAlign  Alignment = MaybeAlign(),
MachineMemOperand::Flags  MMOFlags = MachineMemOperand::MONone,
const AAMDNodes AAInfo = AAMDNodes() 
)

◆ getExtLoadVP() [1/2]

SDValue SelectionDAG::getExtLoadVP ( ISD::LoadExtType  ExtType,
const SDLoc dl,
EVT  VT,
SDValue  Chain,
SDValue  Ptr,
SDValue  Mask,
SDValue  EVL,
EVT  MemVT,
MachineMemOperand MMO,
bool  IsExpanding = false 
)

Definition at line 9250 of file SelectionDAG.cpp.

References getLoadVP(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.

◆ getExtLoadVP() [2/2]

SDValue SelectionDAG::getExtLoadVP ( ISD::LoadExtType  ExtType,
const SDLoc dl,
EVT  VT,
SDValue  Chain,
SDValue  Ptr,
SDValue  Mask,
SDValue  EVL,
MachinePointerInfo  PtrInfo,
EVT  MemVT,
MaybeAlign  Alignment,
MachineMemOperand::Flags  MMOFlags,
const AAMDNodes AAInfo,
bool  IsExpanding = false 
)

Definition at line 9237 of file SelectionDAG.cpp.

References getLoadVP(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.

◆ getExtOrTrunc() [1/2]

SDValue llvm::SelectionDAG::getExtOrTrunc ( bool  IsSigned,
SDValue  Op,
const SDLoc DL,
EVT  VT 
)
inline

Convert Op, which must be of integer type, to the integer type VT, by either sign/zero-extending (depending on IsSigned) or truncating it.

Definition at line 986 of file SelectionDAG.h.

References DL, getSExtOrTrunc(), and getZExtOrTrunc().

◆ getExtOrTrunc() [2/2]

SDValue llvm::SelectionDAG::getExtOrTrunc ( SDValue  Op,
const SDLoc DL,
EVT  VT,
unsigned  Opcode 
)
inline

Convert Op, which must be of integer type, to the integer type VT, by either any/sign/zero-extending (depending on IsAny / IsSigned) or truncating it.

Definition at line 970 of file SelectionDAG.h.

References llvm::ISD::ANY_EXTEND, DL, getAnyExtOrTrunc(), getSExtOrTrunc(), getZExtOrTrunc(), llvm_unreachable, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by combineShiftToAVG(), combineShiftToMULH(), earlyExpandDIVFIX(), expandDivFix(), LowerShift(), and PerformMinMaxFpToSatCombine().

◆ getExtStridedLoadVP()

SDValue SelectionDAG::getExtStridedLoadVP ( ISD::LoadExtType  ExtType,
const SDLoc DL,
EVT  VT,
SDValue  Chain,
SDValue  Ptr,
SDValue  Stride,
SDValue  Mask,
SDValue  EVL,
EVT  MemVT,
MachineMemOperand MMO,
bool  IsExpanding = false 
)

Definition at line 9455 of file SelectionDAG.cpp.

References DL, getStridedLoadVP(), getUNDEF(), Ptr, and llvm::ISD::UNINDEXED.

◆ getFlagInserter()

FlagInserter * llvm::SelectionDAG::getFlagInserter ( )
inline

Definition at line 508 of file SelectionDAG.h.

◆ getFPExtendOrRound()

SDValue SelectionDAG::getFPExtendOrRound ( SDValue  Op,
const SDLoc DL,
EVT  VT 
)

Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by truncation).

Definition at line 1434 of file SelectionDAG.cpp.

References llvm::EVT::bitsGT(), DL, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, getIntPtrConstant(), and getNode().

Referenced by llvm::TargetLowering::expandRoundInexactToOdd(), getCopyFromPartsVector(), getNode(), llvm::RISCVTargetLowering::LowerOperation(), LowerUINT_TO_FP_i32(), and llvm::RISCVTargetLowering::PerformDAGCombine().

◆ getFrameIndex()

SDValue SelectionDAG::getFrameIndex ( int  FI,
EVT  VT,
bool  isTarget = false 
)

Definition at line 1864 of file SelectionDAG.cpp.

References AddNodeIDNode(), llvm::ISD::FrameIndex, getVTList(), N, and llvm::ISD::TargetFrameIndex.

Referenced by llvm::StatepointLoweringState::allocateStackSlot(), llvm::X86TargetLowering::BuildFILD(), CalculateTailCallArgDest(), CreateStackTemporary(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), getAddressForMemoryInput(), getLifetimeNode(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), getTargetFrameIndex(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::AMDGPUTargetLowering::loadStackInputValue(), llvm::SITargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::TargetLowering::LowerCallTo(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Op(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::XtensaTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerINTRINSIC_W_CHAIN(), lowerStatepointMetaArgs(), LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), unpack64(), unpackF64OnRV32DSoftABI(), unpackFromMemLoc(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ getFrameIndexDbgValue() [1/2]

SDDbgValue * SelectionDAG::getFrameIndexDbgValue ( DIVariable Var,
DIExpression Expr,
unsigned  FI,
ArrayRef< SDNode * >  Dependencies,
bool  IsIndirect,
const DebugLoc DL,
unsigned  O 
)

Creates a FrameIndex SDDbgValue node.

FrameIndex with dependencies.

Definition at line 11046 of file SelectionDAG.cpp.

References assert(), DL, llvm::SDDbgOperand::fromFrameIdx(), and llvm::SDDbgInfo::getAlloc().

◆ getFrameIndexDbgValue() [2/2]

SDDbgValue * SelectionDAG::getFrameIndexDbgValue ( DIVariable Var,
DIExpression Expr,
unsigned  FI,
bool  IsIndirect,
const DebugLoc DL,
unsigned  O 
)

Creates a FrameIndex SDDbgValue node.

FrameIndex.

Definition at line 11035 of file SelectionDAG.cpp.

References assert(), DL, and getFrameIndexDbgValue().

Referenced by getFrameIndexDbgValue(), and llvm::SelectionDAGBuilder::handleDebugDeclare().

◆ getFreeze()

SDValue SelectionDAG::getFreeze ( SDValue  V)

◆ getFunctionVarLocs()

const FunctionVarLocs * llvm::SelectionDAG::getFunctionVarLocs ( ) const
inline

Returns the result of the AssignmentTrackingAnalysis pass if it's available, otherwise return nullptr.

Definition at line 501 of file SelectionDAG.h.

Referenced by llvm::SelectionDAGBuilder::visitDbgInfo().

◆ getGatherVP()

SDValue SelectionDAG::getGatherVP ( SDVTList  VTs,
EVT  VT,
const SDLoc dl,
ArrayRef< SDValue Ops,
MachineMemOperand MMO,
ISD::MemIndexType  IndexType 
)

Definition at line