LLVM
15.0.0git
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This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representation suitable for instruction selection. More...
#include "llvm/CodeGen/SelectionDAG.h"
Classes | |
struct | DAGNodeDeletedListener |
struct | DAGUpdateListener |
Clients of various APIs that cause global effects on the DAG can optionally implement this interface. More... | |
class | FlagInserter |
Help to insert SDNodeFlags automatically in transforming. More... | |
Public Types | |
enum | OverflowKind { OFK_Never, OFK_Sometime, OFK_Always } |
Used to represent the possible overflow behavior of an operation. More... | |
using | allnodes_const_iterator = ilist< SDNode >::const_iterator |
using | allnodes_iterator = ilist< SDNode >::iterator |
Public Member Functions | |
SelectionDAG (const TargetMachine &TM, CodeGenOpt::Level) | |
SelectionDAG (const SelectionDAG &)=delete | |
SelectionDAG & | operator= (const SelectionDAG &)=delete |
~SelectionDAG () | |
void | init (MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, LegacyDivergenceAnalysis *Divergence, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin) |
Prepare this SelectionDAG to process code in the given MachineFunction. More... | |
void | setFunctionLoweringInfo (FunctionLoweringInfo *FuncInfo) |
void | clear () |
Clear state and free memory necessary to make this SelectionDAG ready to process a new block. More... | |
MachineFunction & | getMachineFunction () const |
const Pass * | getPass () const |
const DataLayout & | getDataLayout () const |
const TargetMachine & | getTarget () const |
const TargetSubtargetInfo & | getSubtarget () const |
const TargetLowering & | getTargetLoweringInfo () const |
const TargetLibraryInfo & | getLibInfo () const |
const SelectionDAGTargetInfo & | getSelectionDAGInfo () const |
const LegacyDivergenceAnalysis * | getDivergenceAnalysis () const |
LLVMContext * | getContext () const |
OptimizationRemarkEmitter & | getORE () const |
ProfileSummaryInfo * | getPSI () const |
BlockFrequencyInfo * | getBFI () const |
FlagInserter * | getFlagInserter () |
void | setFlagInserter (FlagInserter *FI) |
LLVM_DUMP_METHOD void | dumpDotGraph (const Twine &FileName, const Twine &Title) |
Just dump dot graph to a user-provided path and title. More... | |
void | viewGraph (const std::string &Title) |
Pop up a GraphViz/gv window with the DAG rendered using 'dot'. More... | |
void | viewGraph () |
void | clearGraphAttrs () |
Clear all previously defined node graph attributes. More... | |
void | setGraphAttrs (const SDNode *N, const char *Attrs) |
Set graph attributes for a node. (eg. "color=red".) More... | |
std::string | getGraphAttrs (const SDNode *N) const |
Get graph attributes for a node. More... | |
void | setGraphColor (const SDNode *N, const char *Color) |
Convenience for setting node color attribute. More... | |
void | setSubgraphColor (SDNode *N, const char *Color) |
Convenience for setting subgraph color attribute. More... | |
allnodes_const_iterator | allnodes_begin () const |
allnodes_const_iterator | allnodes_end () const |
allnodes_iterator | allnodes_begin () |
allnodes_iterator | allnodes_end () |
ilist< SDNode >::size_type | allnodes_size () const |
iterator_range< allnodes_iterator > | allnodes () |
iterator_range< allnodes_const_iterator > | allnodes () const |
const SDValue & | getRoot () const |
Return the root tag of the SelectionDAG. More... | |
SDValue | getEntryNode () const |
Return the token chain corresponding to the entry of the function. More... | |
const SDValue & | setRoot (SDValue N) |
Set the current root tag of the SelectionDAG. More... | |
void | VerifyDAGDivergence () |
void | Combine (CombineLevel Level, AAResults *AA, CodeGenOpt::Level OptLevel) |
This iterates over the nodes in the SelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes. More... | |
bool | LegalizeTypes () |
This transforms the SelectionDAG into a SelectionDAG that only uses types natively supported by the target. More... | |
void | Legalize () |
This transforms the SelectionDAG into a SelectionDAG that is compatible with the target instruction selector, as indicated by the TargetLowering object. More... | |
bool | LegalizeOp (SDNode *N, SmallSetVector< SDNode *, 16 > &UpdatedNodes) |
Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target instruction selector, as indicated by the TargetLowering object. More... | |
bool | LegalizeVectors () |
This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported by the target. More... | |
void | RemoveDeadNodes () |
This method deletes all unreachable nodes in the SelectionDAG. More... | |
void | DeleteNode (SDNode *N) |
Remove the specified node from the system. More... | |
SDVTList | getVTList (EVT VT) |
Return an SDVTList that represents the list of values specified. More... | |
SDVTList | getVTList (EVT VT1, EVT VT2) |
SDVTList | getVTList (EVT VT1, EVT VT2, EVT VT3) |
SDVTList | getVTList (EVT VT1, EVT VT2, EVT VT3, EVT VT4) |
SDVTList | getVTList (ArrayRef< EVT > VTs) |
SDValue | getGlobalAddress (const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0) |
SDValue | getTargetGlobalAddress (const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0) |
SDValue | getFrameIndex (int FI, EVT VT, bool isTarget=false) |
SDValue | getTargetFrameIndex (int FI, EVT VT) |
SDValue | getJumpTable (int JTI, EVT VT, bool isTarget=false, unsigned TargetFlags=0) |
SDValue | getTargetJumpTable (int JTI, EVT VT, unsigned TargetFlags=0) |
SDValue | getConstantPool (const Constant *C, EVT VT, MaybeAlign Align=None, int Offs=0, bool isT=false, unsigned TargetFlags=0) |
SDValue | getTargetConstantPool (const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0) |
SDValue | getConstantPool (MachineConstantPoolValue *C, EVT VT, MaybeAlign Align=None, int Offs=0, bool isT=false, unsigned TargetFlags=0) |
SDValue | getTargetConstantPool (MachineConstantPoolValue *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0) |
SDValue | getTargetIndex (int Index, EVT VT, int64_t Offset=0, unsigned TargetFlags=0) |
SDValue | getBasicBlock (MachineBasicBlock *MBB) |
SDValue | getExternalSymbol (const char *Sym, EVT VT) |
SDValue | getTargetExternalSymbol (const char *Sym, EVT VT, unsigned TargetFlags=0) |
SDValue | getMCSymbol (MCSymbol *Sym, EVT VT) |
SDValue | getValueType (EVT) |
SDValue | getRegister (unsigned Reg, EVT VT) |
SDValue | getRegisterMask (const uint32_t *RegMask) |
SDValue | getEHLabel (const SDLoc &dl, SDValue Root, MCSymbol *Label) |
SDValue | getLabelNode (unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label) |
SDValue | getBlockAddress (const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0) |
SDValue | getTargetBlockAddress (const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0) |
SDValue | getCopyToReg (SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N) |
SDValue | getCopyToReg (SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N, SDValue Glue) |
SDValue | getCopyToReg (SDValue Chain, const SDLoc &dl, SDValue Reg, SDValue N, SDValue Glue) |
SDValue | getCopyFromReg (SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT) |
SDValue | getCopyFromReg (SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT, SDValue Glue) |
SDValue | getCondCode (ISD::CondCode Cond) |
SDValue | getVectorShuffle (EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask) |
Return an ISD::VECTOR_SHUFFLE node. More... | |
SDValue | getBuildVector (EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops) |
Return an ISD::BUILD_VECTOR node. More... | |
SDValue | getBuildVector (EVT VT, const SDLoc &DL, ArrayRef< SDUse > Ops) |
Return an ISD::BUILD_VECTOR node. More... | |
SDValue | getSplatBuildVector (EVT VT, const SDLoc &DL, SDValue Op) |
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements. More... | |
SDValue | getSplatVector (EVT VT, const SDLoc &DL, SDValue Op) |
SDValue | getStepVector (const SDLoc &DL, EVT ResVT, APInt StepVal) |
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step, Step * 2, Step * 3, ...> More... | |
SDValue | getStepVector (const SDLoc &DL, EVT ResVT) |
Returns a vector of type ResVT whose elements contain the linear sequence <0, 1, 2, 3, ...> More... | |
SDValue | getCommutedVectorShuffle (const ShuffleVectorSDNode &SV) |
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands. More... | |
SDValue | getFPExtendOrRound (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by truncation). More... | |
std::pair< SDValue, SDValue > | getStrictFPExtendOrRound (SDValue Op, SDValue Chain, const SDLoc &DL, EVT VT) |
Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending or rounding (by truncation). More... | |
SDValue | getAnyExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncating it. More... | |
SDValue | getSExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or truncating it. More... | |
SDValue | getZExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or truncating it. More... | |
SDValue | getZeroExtendInReg (SDValue Op, const SDLoc &DL, EVT VT) |
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value. More... | |
SDValue | getPtrExtOrTrunc (SDValue Op, const SDLoc &DL, EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or performing either zero or sign extension as appropriate extension for the pointer's semantics. More... | |
SDValue | getPtrExtendInReg (SDValue Op, const SDLoc &DL, EVT VT) |
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy value. More... | |
SDValue | getBoolExtOrTrunc (SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT) |
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it. More... | |
SDValue | getNOT (const SDLoc &DL, SDValue Val, EVT VT) |
Create a bitwise NOT operation as (XOR Val, -1). More... | |
SDValue | getLogicalNOT (const SDLoc &DL, SDValue Val, EVT VT) |
Create a logical NOT operation as (XOR Val, BooleanOne). More... | |
SDValue | getVPLogicalNOT (const SDLoc &DL, SDValue Val, SDValue Mask, SDValue EVL, EVT VT) |
Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask, EVL). More... | |
SDValue | getMemBasePlusOffset (SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags()) |
Returns sum of the base pointer and offset. More... | |
SDValue | getMemBasePlusOffset (SDValue Base, SDValue Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags()) |
SDValue | getObjectPtrOffset (const SDLoc &SL, SDValue Ptr, TypeSize Offset) |
Create an add instruction with appropriate flags when used for addressing some offset of an object. More... | |
SDValue | getObjectPtrOffset (const SDLoc &SL, SDValue Ptr, SDValue Offset) |
SDValue | getCALLSEQ_START (SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL) |
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and OutSize specifies part of the frame set up prior to the sequence. More... | |
SDValue | getCALLSEQ_END (SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL) |
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd). More... | |
bool | isUndef (unsigned Opcode, ArrayRef< SDValue > Ops) |
Return true if the result of this operation is always undefined. More... | |
SDValue | getUNDEF (EVT VT) |
Return an UNDEF node. UNDEF does not have a useful SDLoc. More... | |
SDValue | getVScale (const SDLoc &DL, EVT VT, APInt MulImm) |
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'. More... | |
SDValue | getGLOBAL_OFFSET_TABLE (EVT VT) |
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc. More... | |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops) |
Gets or creates the specified node. More... | |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, const SDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, ArrayRef< EVT > ResultTys, ArrayRef< SDValue > Ops) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, ArrayRef< SDValue > Ops) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT) |
Gets or creates the specified node. More... | |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand, const SDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, const SDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, const SDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4) |
SDValue | getNode (unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) |
SDValue | getStackArgumentTokenFactor (SDValue Chain) |
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack. More... | |
SDValue | getMemcpy (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getMemmove (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getMemset (SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getAtomicMemcpy (SDValue Chain, const SDLoc &dl, SDValue Dst, unsigned DstAlign, SDValue Src, unsigned SrcAlign, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
SDValue | getAtomicMemmove (SDValue Chain, const SDLoc &dl, SDValue Dst, unsigned DstAlign, SDValue Src, unsigned SrcAlign, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) |
SDValue | getAtomicMemset (SDValue Chain, const SDLoc &dl, SDValue Dst, unsigned DstAlign, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo) |
SDValue | getSetCC (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false) |
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SDValue. More... | |
SDValue | getSetCCVP (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Mask, SDValue EVL) |
Helper function to make it easier to build VP_SETCCs if you just have an ISD::CondCode instead of an SDValue. More... | |
SDValue | getSelect (const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS) |
Helper function to make it easier to build Select's if you just have operands and don't want to check for vector. More... | |
SDValue | getSelectCC (const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond) |
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an SDValue. More... | |
SDValue | simplifySelect (SDValue Cond, SDValue TVal, SDValue FVal) |
Try to simplify a select/vselect into 1 of its operands or a constant. More... | |
SDValue | simplifyShift (SDValue X, SDValue Y) |
Try to simplify a shift into 1 of its operands or a constant. More... | |
SDValue | simplifyFPBinop (unsigned Opcode, SDValue X, SDValue Y, SDNodeFlags Flags) |
Try to simplify a floating-point binary operation into 1 of its operands or a constant. More... | |
SDValue | getVAArg (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align) |
VAArg produces a result and token chain, and takes a pointer and a source value as input. More... | |
SDValue | getAtomicCmpSwap (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO) |
Gets a node for an atomic cmpxchg op. More... | |
SDValue | getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO) |
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands. More... | |
SDValue | getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO) |
Gets a node for an atomic op, produces result and chain and takes 1 operand. More... | |
SDValue | getAtomic (unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTList, ArrayRef< SDValue > Ops, MachineMemOperand *MMO) |
Gets a node for an atomic op, produces result and chain and takes N operands. More... | |
SDValue | getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, uint64_t Size=0, const AAMDNodes &AAInfo=AAMDNodes()) |
Creates a MemIntrinsicNode that may produce a result and takes a list of operands. More... | |
SDValue | getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, MaybeAlign Alignment=None, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, uint64_t Size=0, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getMemIntrinsicNode (unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachineMemOperand *MMO) |
SDValue | getLifetimeNode (bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex, int64_t Size, int64_t Offset=-1) |
Creates a LifetimeSDNode that starts (IsStart==true ) or ends (IsStart==false ) the lifetime of the portion of FrameIndex between offsets Offset and Offset + Size . More... | |
SDValue | getPseudoProbeNode (const SDLoc &Dl, SDValue Chain, uint64_t Guid, uint64_t Index, uint32_t Attr) |
Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing, as well as the attributes attr of the probe. More... | |
SDValue | getMergeValues (ArrayRef< SDValue > Ops, const SDLoc &dl) |
Create a MERGE_VALUES node from the given operands. More... | |
SDValue | getLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr) |
Loads are not normal binary operators: their result type is not determined by their operands, and they produce a value AND a token chain. More... | |
SDValue | getLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr) |
FIXME: Remove once transition to Align is over. More... | |
SDValue | getLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO) |
SDValue | getExtLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getExtLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
FIXME: Remove once transition to Align is over. More... | |
SDValue | getExtLoad (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO) |
SDValue | getIndexedLoad (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr) |
SDValue | getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr) |
SDValue | getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr) |
FIXME: Remove once transition to Align is over. More... | |
SDValue | getLoad (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, EVT MemVT, MachineMemOperand *MMO) |
SDValue | getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
Helper function to build ISD::STORE nodes. More... | |
SDValue | getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
FIXME: Remove once transition to Align is over. More... | |
SDValue | getStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachineMemOperand *MMO) |
SDValue | getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, unsigned Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes()) |
FIXME: Remove once transition to Align is over. More... | |
SDValue | getTruncStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, EVT SVT, MachineMemOperand *MMO) |
SDValue | getIndexedStore (SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false) |
SDValue | getLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, bool IsExpanding=false) |
SDValue | getLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false) |
SDValue | getLoadVP (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false) |
SDValue | getLoadVP (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachineMemOperand *MMO, bool IsExpanding=false) |
SDValue | getExtLoadVP (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsExpanding=false) |
SDValue | getExtLoadVP (ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false) |
SDValue | getIndexedLoadVP (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getStoreVP (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false) |
SDValue | getTruncStoreVP (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsCompressing=false) |
SDValue | getTruncStoreVP (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false) |
SDValue | getIndexedStoreVP (SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getStridedLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false) |
SDValue | getStridedLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, bool IsExpanding=false) |
SDValue | getStridedLoadVP (ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false) |
SDValue | getStridedLoadVP (EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false) |
SDValue | getStridedLoadVP (EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, MachineMemOperand *MMO, bool IsExpanding=false) |
SDValue | getExtStridedLoadVP (ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsExpanding=false) |
SDValue | getExtStridedLoadVP (ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false) |
SDValue | getIndexedStridedLoadVP (SDValue OrigLoad, const SDLoc &DL, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getStridedStoreVP (SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false) |
SDValue | getTruncStridedStoreVP (SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsCompressing=false) |
SDValue | getTruncStridedStoreVP (SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false) |
SDValue | getIndexedStridedStoreVP (SDValue OrigStore, const SDLoc &DL, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getGatherVP (SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType) |
SDValue | getScatterVP (SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType) |
SDValue | getMaskedLoad (EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, ISD::LoadExtType, bool IsExpanding=false) |
SDValue | getIndexedMaskedLoad (SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getMaskedStore (SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false) |
SDValue | getIndexedMaskedStore (SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) |
SDValue | getMaskedGather (SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy) |
SDValue | getMaskedScatter (SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTruncating=false) |
SDValue | getSrcValue (const Value *v) |
Construct a node to track a Value* through the backend. More... | |
SDValue | getMDNode (const MDNode *MD) |
Return an MDNodeSDNode which holds an MDNode. More... | |
SDValue | getBitcast (EVT VT, SDValue V) |
Return a bitcast using the SDLoc of the value operand, and casting to the provided type. More... | |
SDValue | getAddrSpaceCast (const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS) |
Return an AddrSpaceCastSDNode. More... | |
SDValue | getFreeze (SDValue V) |
Return a freeze using the SDLoc of the value operand. More... | |
SDValue | getAssertAlign (const SDLoc &DL, SDValue V, Align A) |
Return an AssertAlignSDNode. More... | |
void | canonicalizeCommutativeBinop (unsigned Opcode, SDValue &N1, SDValue &N2) const |
Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite order. More... | |
SDValue | getShiftAmountOperand (EVT LHSTy, SDValue Op) |
Return the specified value casted to the target's desired shift amount type. More... | |
SDValue | expandVAArg (SDNode *Node) |
Expand the specified ISD::VAARG node as the Legalize pass would. More... | |
SDValue | expandVACopy (SDNode *Node) |
Expand the specified ISD::VACOPY node as the Legalize pass would. More... | |
SDValue | getSymbolFunctionGlobalAddress (SDValue Op, Function **TargetFunction=nullptr) |
Returs an GlobalAddress of the function from the current module with name matching the given ExternalSymbol. More... | |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op) |
Mutate the specified node in-place to have the specified operands. More... | |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2) |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) |
SDNode * | UpdateNodeOperands (SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) |
SDNode * | UpdateNodeOperands (SDNode *N, ArrayRef< SDValue > Ops) |
SDValue | getTokenFactor (const SDLoc &DL, SmallVectorImpl< SDValue > &Vals) |
Creates a new TokenFactor containing Vals . More... | |
void | setNodeMemRefs (MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs) |
Mutate the specified machine node's memory references to the provided list. More... | |
bool | calculateDivergence (SDNode *N) |
void | updateDivergence (SDNode *N) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT) |
These are used for target selectors to mutate the specified node to have the specified return type, Target opcode, and operands. More... | |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT, ArrayRef< SDValue > Ops) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, ArrayRef< SDValue > Ops) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, ArrayRef< SDValue > Ops) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) |
SDNode * | SelectNodeTo (SDNode *N, unsigned MachineOpc, SDVTList VTs, ArrayRef< SDValue > Ops) |
SDNode * | MorphNodeTo (SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops) |
This mutates the specified node to have the specified return type, opcode, and operands. More... | |
SDNode * | mutateStrictFPToFP (SDNode *Node) |
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain and dropping the metadata arguments. More... | |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT) |
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands. More... | |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT, ArrayRef< SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, ArrayRef< SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, EVT VT1, EVT VT2, EVT VT3, ArrayRef< SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, ArrayRef< EVT > ResultTys, ArrayRef< SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode, const SDLoc &dl, SDVTList VTs, ArrayRef< SDValue > Ops) |
SDValue | getTargetExtractSubreg (int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand) |
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes. More... | |
SDValue | getTargetInsertSubreg (int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg) |
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes. More... | |
SDNode * | getNodeIfExists (unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags) |
Get the specified node if it's already available, or else return NULL. More... | |
SDNode * | getNodeIfExists (unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops) |
getNodeIfExists - Get the specified node if it's already available, or else return NULL. More... | |
bool | doesNodeExist (unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops) |
Check if a node exists without modifying its flags. More... | |
SDDbgValue * | getDbgValue (DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O) |
Creates a SDDbgValue node. More... | |
SDDbgValue * | getConstantDbgValue (DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O) |
Creates a constant SDDbgValue node. More... | |
SDDbgValue * | getFrameIndexDbgValue (DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O) |
Creates a FrameIndex SDDbgValue node. More... | |
SDDbgValue * | getFrameIndexDbgValue (DIVariable *Var, DIExpression *Expr, unsigned FI, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O) |
Creates a FrameIndex SDDbgValue node. More... | |
SDDbgValue * | getVRegDbgValue (DIVariable *Var, DIExpression *Expr, unsigned VReg, bool IsIndirect, const DebugLoc &DL, unsigned O) |
Creates a VReg SDDbgValue node. More... | |
SDDbgValue * | getDbgValueList (DIVariable *Var, DIExpression *Expr, ArrayRef< SDDbgOperand > Locs, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O, bool IsVariadic) |
Creates a SDDbgValue node from a list of locations. More... | |
SDDbgLabel * | getDbgLabel (DILabel *Label, const DebugLoc &DL, unsigned O) |
Creates a SDDbgLabel node. More... | |
void | transferDbgValues (SDValue From, SDValue To, unsigned OffsetInBits=0, unsigned SizeInBits=0, bool InvalidateDbg=true) |
Transfer debug values from one node to another, while optionally generating fragment expressions for split-up values. More... | |
void | RemoveDeadNode (SDNode *N) |
Remove the specified node from the system. More... | |
void | RemoveDeadNodes (SmallVectorImpl< SDNode * > &DeadNodes) |
This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result. More... | |
void | ReplaceAllUsesWith (SDValue From, SDValue To) |
Modify anything using 'From' to use 'To' instead. More... | |
void | ReplaceAllUsesWith (SDNode *From, SDNode *To) |
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. More... | |
void | ReplaceAllUsesWith (SDNode *From, const SDValue *To) |
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. More... | |
void | ReplaceAllUsesOfValueWith (SDValue From, SDValue To) |
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone. More... | |
void | ReplaceAllUsesOfValuesWith (const SDValue *From, const SDValue *To, unsigned Num) |
Like ReplaceAllUsesOfValueWith, but for multiple values at once. More... | |
SDValue | makeEquivalentMemoryOrdering (SDValue OldChain, SDValue NewMemOpChain) |
If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor. More... | |
SDValue | makeEquivalentMemoryOrdering (LoadSDNode *OldLoad, SDValue NewMemOp) |
If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor. More... | |
unsigned | AssignTopologicalOrder () |
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order. More... | |
void | RepositionNode (allnodes_iterator Position, SDNode *N) |
Move node N in the AllNodes list to be immediately before the given iterator Position. More... | |
void | AddDbgValue (SDDbgValue *DB, bool isParameter) |
Add a dbg_value SDNode. More... | |
void | AddDbgLabel (SDDbgLabel *DB) |
Add a dbg_label SDNode. More... | |
ArrayRef< SDDbgValue * > | GetDbgValues (const SDNode *SD) const |
Get the debug values which reference the given SDNode. More... | |
bool | hasDebugValues () const |
Return true if there are any SDDbgValue nodes associated with this SelectionDAG. More... | |
SDDbgInfo::DbgIterator | DbgBegin () const |
SDDbgInfo::DbgIterator | DbgEnd () const |
SDDbgInfo::DbgIterator | ByvalParmDbgBegin () const |
SDDbgInfo::DbgIterator | ByvalParmDbgEnd () const |
SDDbgInfo::DbgLabelIterator | DbgLabelBegin () const |
SDDbgInfo::DbgLabelIterator | DbgLabelEnd () const |
void | salvageDebugInfo (SDNode &N) |
To be invoked on an SDNode that is slated to be erased. More... | |
void | useInstrRefDebugInfo (bool Flag) |
Signal whether instruction referencing variable locations are desired for this function's debug-info. More... | |
bool | getUseInstrRefDebugInfo () const |
void | dump () const |
Align | getReducedAlign (EVT VT, bool UseABI) |
In most cases this function returns the ABI alignment for a given type, except for illegal vector types where the alignment exceeds that of the stack. More... | |
SDValue | CreateStackTemporary (TypeSize Bytes, Align Alignment) |
Create a stack temporary based on the size in bytes and the alignment. More... | |
SDValue | CreateStackTemporary (EVT VT, unsigned minAlign=1) |
Create a stack temporary, suitable for holding the specified value type. More... | |
SDValue | CreateStackTemporary (EVT VT1, EVT VT2) |
Create a stack temporary suitable for holding either of the specified value types. More... | |
SDValue | FoldSymbolOffset (unsigned Opcode, EVT VT, const GlobalAddressSDNode *GA, const SDNode *N2) |
SDValue | FoldConstantArithmetic (unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops) |
SDValue | foldConstantFPMath (unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, SDValue N2) |
Fold floating-point operations with 2 operands when both operands are constants and/or undefined. More... | |
SDValue | FoldSetCC (EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl) |
Constant fold a setcc to true or false. More... | |
SDValue | GetDemandedBits (SDValue V, const APInt &DemandedBits) |
See if the specified operand can be simplified with the knowledge that only the bits specified by DemandedBits are used. More... | |
SDValue | GetDemandedBits (SDValue V, const APInt &DemandedBits, const APInt &DemandedElts) |
See if the specified operand can be simplified with the knowledge that only the bits specified by DemandedBits are used in the elements specified by DemandedElts. More... | |
bool | SignBitIsZero (SDValue Op, unsigned Depth=0) const |
Return true if the sign bit of Op is known to be zero. More... | |
bool | MaskedValueIsZero (SDValue Op, const APInt &Mask, unsigned Depth=0) const |
Return true if 'Op & Mask' is known to be zero. More... | |
bool | MaskedValueIsZero (SDValue Op, const APInt &Mask, const APInt &DemandedElts, unsigned Depth=0) const |
Return true if 'Op & Mask' is known to be zero in DemandedElts. More... | |
bool | MaskedValueIsAllOnes (SDValue Op, const APInt &Mask, unsigned Depth=0) const |
Return true if '(Op & Mask) == Mask'. More... | |
KnownBits | computeKnownBits (SDValue Op, unsigned Depth=0) const |
Determine which bits of Op are known to be either zero or one and return them in Known. More... | |
KnownBits | computeKnownBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const |
Determine which bits of Op are known to be either zero or one and return them in Known. More... | |
OverflowKind | computeOverflowKind (SDValue N0, SDValue N1) const |
Determine if the result of the addition of 2 node can overflow. More... | |
bool | isKnownToBeAPowerOfTwo (SDValue Val) const |
Test if the given value is known to have exactly one bit set. More... | |
unsigned | ComputeNumSignBits (SDValue Op, unsigned Depth=0) const |
Return the number of times the sign bit of the register is replicated into the other bits. More... | |
unsigned | ComputeNumSignBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const |
Return the number of times the sign bit of the register is replicated into the other bits. More... | |
unsigned | ComputeMaxSignificantBits (SDValue Op, unsigned Depth=0) const |
Get the upper bound on bit size for this Value Op as a signed integer. More... | |
unsigned | ComputeMaxSignificantBits (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const |
Get the upper bound on bit size for this Value Op as a signed integer. More... | |
bool | isGuaranteedNotToBeUndefOrPoison (SDValue Op, bool PoisonOnly=false, unsigned Depth=0) const |
Return true if this function can prove that Op is never poison and, if PoisonOnly is false, does not have undef bits. More... | |
bool | isGuaranteedNotToBeUndefOrPoison (SDValue Op, const APInt &DemandedElts, bool PoisonOnly=false, unsigned Depth=0) const |
Return true if this function can prove that Op is never poison and, if PoisonOnly is false, does not have undef bits. More... | |
bool | isGuaranteedNotToBePoison (SDValue Op, unsigned Depth=0) const |
Return true if this function can prove that Op is never poison. More... | |
bool | isGuaranteedNotToBePoison (SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const |
Return true if this function can prove that Op is never poison. More... | |
bool | isBaseWithConstantOffset (SDValue Op) const |
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that is guaranteed to have the same semantics as an ADD. More... | |
bool | isKnownNeverNaN (SDValue Op, bool SNaN=false, unsigned Depth=0) const |
Test whether the given SDValue is known to never be NaN. More... | |
bool | isKnownNeverSNaN (SDValue Op, unsigned Depth=0) const |
bool | isKnownNeverZeroFloat (SDValue Op) const |
Test whether the given floating point SDValue is known to never be positive or negative zero. More... | |
bool | isKnownNeverZero (SDValue Op) const |
Test whether the given SDValue is known to contain non-zero value(s). More... | |
bool | isEqualTo (SDValue A, SDValue B) const |
Test whether two SDValues are known to compare equal. More... | |
bool | haveNoCommonBitsSet (SDValue A, SDValue B) const |
Return true if A and B have no common bits set. More... | |
bool | isSplatValue (SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const |
Test whether V has a splatted value for all the demanded elements. More... | |
bool | isSplatValue (SDValue V, bool AllowUndefs=false) const |
Test whether V has a splatted value. More... | |
SDValue | getSplatSourceVector (SDValue V, int &SplatIndex) |
If V is a splatted value, return the source vector and its splat index. More... | |
SDValue | getSplatValue (SDValue V, bool LegalTypes=false) |
If V is a splat vector, return its scalar source operand by extracting that element from the source vector. More... | |
const APInt * | getValidShiftAmountConstant (SDValue V, const APInt &DemandedElts) const |
If a SHL/SRA/SRL node V has a constant or splat constant shift amount that is less than the element bit-width of the shift node, return it. More... | |
const APInt * | getValidMinimumShiftAmountConstant (SDValue V, const APInt &DemandedElts) const |
If a SHL/SRA/SRL node V has constant shift amounts that are all less than the element bit-width of the shift node, return the minimum value. More... | |
const APInt * | getValidMaximumShiftAmountConstant (SDValue V, const APInt &DemandedElts) const |
If a SHL/SRA/SRL node V has constant shift amounts that are all less than the element bit-width of the shift node, return the maximum value. More... | |
SDValue | matchBinOpReduction (SDNode *Extract, ISD::NodeType &BinOp, ArrayRef< ISD::NodeType > CandidateBinOps, bool AllowPartials=false) |
Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract. More... | |
SDValue | UnrollVectorOp (SDNode *N, unsigned ResNE=0) |
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the scalars and operating on each element individually. More... | |
std::pair< SDValue, SDValue > | UnrollVectorOverflowOp (SDNode *N, unsigned ResNE=0) |
Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes. More... | |
bool | areNonVolatileConsecutiveLoads (LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, int Dist) const |
Return true if loads are next to each other and can be merged. More... | |
MaybeAlign | InferPtrAlign (SDValue Ptr) const |
Infer alignment of a load / store address. More... | |
std::pair< EVT, EVT > | GetSplitDestVTs (const EVT &VT) const |
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces. More... | |
std::pair< EVT, EVT > | GetDependentSplitDestVTs (const EVT &VT, const EVT &EnvVT, bool *HiIsEmpty) const |
Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces. More... | |
std::pair< SDValue, SDValue > | SplitVector (const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT) |
Split the vector with EXTRACT_SUBVECTOR using the provides VTs and return the low/high part. More... | |
std::pair< SDValue, SDValue > | SplitVector (const SDValue &N, const SDLoc &DL) |
Split the vector with EXTRACT_SUBVECTOR and return the low/high part. More... | |
std::pair< SDValue, SDValue > | SplitEVL (SDValue N, EVT VecVT, const SDLoc &DL) |
Split the explicit vector length parameter of a VP operation. More... | |
std::pair< SDValue, SDValue > | SplitVectorOperand (const SDNode *N, unsigned OpNo) |
Split the node's operand with EXTRACT_SUBVECTOR and return the low/high part. More... | |
SDValue | WidenVector (const SDValue &N, const SDLoc &DL) |
Widen the vector up to the next power of two using INSERT_SUBVECTOR. More... | |
void | ExtractVectorElements (SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT()) |
Append the extracted elements from Start to Count out of the vector Op in Args. More... | |
Align | getEVTAlign (EVT MemoryVT) const |
Compute the default alignment value for the given type. More... | |
unsigned | getEVTAlignment (EVT MemoryVT) const |
Compute the default alignment value for the given type. More... | |
SDNode * | isConstantIntBuildVectorOrConstantInt (SDValue N) const |
Test whether the given value is a constant int or similar node. More... | |
SDNode * | isConstantFPBuildVectorOrConstantFP (SDValue N) const |
Test whether the given value is a constant FP or similar node. More... | |
bool | isConstantValueOfAnyType (SDValue N) const |
void | addCallSiteInfo (const SDNode *Node, CallSiteInfoImpl &&CallInfo) |
Set CallSiteInfo to be associated with Node. More... | |
CallSiteInfo | getCallSiteInfo (const SDNode *Node) |
Return CallSiteInfo associated with Node, or a default if none exists. More... | |
void | addHeapAllocSite (const SDNode *Node, MDNode *MD) |
Set HeapAllocSite to be associated with Node. More... | |
MDNode * | getHeapAllocSite (const SDNode *Node) const |
Return HeapAllocSite associated with Node, or nullptr if none exists. More... | |
void | addNoMergeSiteInfo (const SDNode *Node, bool NoMerge) |
Set NoMergeSiteInfo to be associated with Node if NoMerge is true. More... | |
bool | getNoMergeSiteInfo (const SDNode *Node) const |
Return NoMerge info associated with Node. More... | |
DenormalMode | getDenormalMode (EVT VT) const |
Return the current function's default denormal handling kind for the given floating point type. More... | |
bool | shouldOptForSize () const |
SDValue | getNeutralElement (unsigned Opcode, const SDLoc &DL, EVT VT, SDNodeFlags Flags) |
Get the (commutative) neutral element for the given opcode, if it exists. More... | |
SDValue | getConstant (uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false) |
Create a ConstantSDNode wrapping a constant value. More... | |
SDValue | getConstant (const APInt &Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false) |
SDValue | getAllOnesConstant (const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false) |
SDValue | getConstant (const ConstantInt &Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false) |
SDValue | getIntPtrConstant (uint64_t Val, const SDLoc &DL, bool isTarget=false) |
SDValue | getShiftAmountConstant (uint64_t Val, EVT VT, const SDLoc &DL, bool LegalTypes=true) |
SDValue | getVectorIdxConstant (uint64_t Val, const SDLoc &DL, bool isTarget=false) |
SDValue | getTargetConstant (uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false) |
SDValue | getTargetConstant (const APInt &Val, const SDLoc &DL, EVT VT, bool isOpaque=false) |
SDValue | getTargetConstant (const ConstantInt &Val, const SDLoc &DL, EVT VT, bool isOpaque=false) |
SDValue | getBoolConstant (bool V, const SDLoc &DL, EVT VT, EVT OpVT) |
Create a true or false constant of type VT using the target's BooleanContent for type OpVT . More... | |
SDValue | getConstantFP (double Val, const SDLoc &DL, EVT VT, bool isTarget=false) |
Create a ConstantFPSDNode wrapping a constant value. More... | |
SDValue | getConstantFP (const APFloat &Val, const SDLoc &DL, EVT VT, bool isTarget=false) |
SDValue | getConstantFP (const ConstantFP &V, const SDLoc &DL, EVT VT, bool isTarget=false) |
SDValue | getTargetConstantFP (double Val, const SDLoc &DL, EVT VT) |
SDValue | getTargetConstantFP (const APFloat &Val, const SDLoc &DL, EVT VT) |
SDValue | getTargetConstantFP (const ConstantFP &Val, const SDLoc &DL, EVT VT) |
Static Public Member Functions | |
static const fltSemantics & | EVTToAPFloatSemantics (EVT VT) |
Returns an APFloat semantics tag appropriate for the given type. More... | |
Public Attributes | |
bool | NewNodesMustHaveLegalTypes = false |
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG nodes that have legal types. More... | |
Static Public Attributes | |
static constexpr unsigned | MaxRecursionDepth = 6 |
Friends | |
struct | DAGUpdateListener |
DAGUpdateListener is a friend so it can manipulate the listener stack. More... | |
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representation suitable for instruction selection.
This DAG is constructed as the first step of instruction selection in order to allow implementation of machine specific optimizations and code simplifications.
The representation used by the SelectionDAG is a target-independent representation, which has some similarities to the GCC RTL representation, but is significantly more simple, powerful, and is a graph form instead of a linear form.
Definition at line 220 of file SelectionDAG.h.
Definition at line 503 of file SelectionDAG.h.
using llvm::SelectionDAG::allnodes_iterator = ilist<SDNode>::iterator |
Definition at line 508 of file SelectionDAG.h.
Used to represent the possible overflow behavior of an operation.
Never: the operation cannot overflow. Always: the operation will always overflow. Sometime: the operation may or may not overflow.
Enumerator | |
---|---|
OFK_Never | |
OFK_Sometime | |
OFK_Always |
Definition at line 1911 of file SelectionDAG.h.
|
explicit |
Definition at line 1231 of file SelectionDAG.cpp.
References Other.
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delete |
SelectionDAG::~SelectionDAG | ( | ) |
Definition at line 1257 of file SelectionDAG.cpp.
References assert().
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inline |
Set CallSiteInfo to be associated with Node.
Definition at line 2156 of file SelectionDAG.h.
void SelectionDAG::AddDbgLabel | ( | SDDbgLabel * | DB | ) |
Add a dbg_label SDNode.
Definition at line 10400 of file SelectionDAG.cpp.
References llvm::SDDbgInfo::add().
void SelectionDAG::AddDbgValue | ( | SDDbgValue * | DB, |
bool | isParameter | ||
) |
Add a dbg_value SDNode.
AddDbgValue - Add a dbg_value SDNode.
If SD is non-null that means the value is produced by SD.
Definition at line 10390 of file SelectionDAG.cpp.
References llvm::SDDbgInfo::add(), assert(), llvm::SDDbgInfo::getSDDbgValues(), and llvm::SDDbgValue::getSDNodes().
Referenced by llvm::SelectionDAGBuilder::addDanglingDebugInfo(), llvm::SelectionDAGBuilder::handleDebugValue(), llvm::SelectionDAGBuilder::resolveDanglingDebugInfo(), salvageDebugInfo(), llvm::SelectionDAGBuilder::salvageUnresolvedDbgValue(), and transferDbgValues().
Set HeapAllocSite to be associated with Node.
Definition at line 2166 of file SelectionDAG.h.
Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
Definition at line 2175 of file SelectionDAG.h.
Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::SystemZTargetLowering::LowerCall().
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inline |
Definition at line 517 of file SelectionDAG.h.
References allnodes_begin(), allnodes_end(), and llvm::make_range().
Referenced by AssignTopologicalOrder(), and llvm::HexagonDAGToDAGISel::PreprocessISelDAG().
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inline |
Definition at line 520 of file SelectionDAG.h.
References allnodes_begin(), allnodes_end(), and llvm::make_range().
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inline |
Definition at line 510 of file SelectionDAG.h.
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inline |
Definition at line 505 of file SelectionDAG.h.
Referenced by allnodes(), AssignTopologicalOrder(), Legalize(), llvm::RISCVDAGToDAGISel::PostprocessISelDAG(), AMDGPUDAGToDAGISel::PostprocessISelDAG(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), and AMDGPUDAGToDAGISel::PreprocessISelDAG().
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inline |
Definition at line 511 of file SelectionDAG.h.
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inline |
Definition at line 506 of file SelectionDAG.h.
Referenced by allnodes(), Legalize(), llvm::RISCVDAGToDAGISel::PostprocessISelDAG(), AMDGPUDAGToDAGISel::PostprocessISelDAG(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), and AMDGPUDAGToDAGISel::PreprocessISelDAG().
Definition at line 513 of file SelectionDAG.h.
Referenced by llvm::HexagonDAGToDAGISel::PreprocessISelDAG().
bool SelectionDAG::areNonVolatileConsecutiveLoads | ( | LoadSDNode * | LD, |
LoadSDNode * | Base, | ||
unsigned | Bytes, | ||
int | Dist | ||
) | const |
Return true if loads are next to each other and can be merged.
Check that both are nonvolatile and if LD is loading 'Bytes' bytes from a location that is 'Dist' units away from the location that the 'Base' load is loading from.
Definition at line 11053 of file SelectionDAG.cpp.
References llvm::sampleprof::Base, llvm::EVT::getSizeInBits(), llvm::ARM_MB::LD, and llvm::PatternMatch::match().
Referenced by combineINSERT_SUBVECTOR(), and EltsFromConsecutiveLoads().
unsigned SelectionDAG::AssignTopologicalOrder | ( | ) |
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order.
AssignTopologicalOrder - Assign a unique node id for each node in the DAG based on their topological order.
Returns the number of nodes.
It returns the maximum id and a vector of the SDNodes* in assigned order by reference.
Definition at line 10304 of file SelectionDAG.cpp.
References allnodes(), allnodes_begin(), assert(), llvm::checkForCycles(), llvm::make_early_inc_range(), and N.
Referenced by Legalize().
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inline |
Definition at line 1790 of file SelectionDAG.h.
References llvm::SDDbgInfo::ByvalParmDbgBegin().
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inline |
Definition at line 1793 of file SelectionDAG.h.
References llvm::SDDbgInfo::ByvalParmDbgEnd().
bool SelectionDAG::calculateDivergence | ( | SDNode * | N | ) |
Definition at line 10177 of file SelectionDAG.cpp.
References assert(), llvm::TargetLowering::isSDNodeAlwaysUniform(), llvm::TargetLowering::isSDNodeSourceOfDivergence(), N, and llvm::MVT::Other.
Referenced by updateDivergence(), and VerifyDAGDivergence().
void SelectionDAG::canonicalizeCommutativeBinop | ( | unsigned | Opcode, |
SDValue & | N1, | ||
SDValue & | N2 | ||
) | const |
Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite order.
Definition at line 5804 of file SelectionDAG.cpp.
References llvm::SDValue::getOpcode(), llvm::TargetLoweringBase::isCommutativeBinOp(), isConstantFPBuildVectorOrConstantFP(), isConstantIntBuildVectorOrConstantInt(), llvm::ISD::SPLAT_VECTOR, llvm::ISD::STEP_VECTOR, and std::swap().
Referenced by getNode().
void SelectionDAG::clear | ( | ) |
Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
Definition at line 1319 of file SelectionDAG.cpp.
References llvm::SDDbgInfo::clear(), getEntryNode(), and llvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Reset().
void SelectionDAG::clearGraphAttrs | ( | ) |
Clear all previously defined node graph attributes.
clearGraphAttrs - Clear all previously defined node graph attributes.
Intended to be used from a debugging tool (eg. gdb).
Definition at line 179 of file SelectionDAGPrinter.cpp.
References llvm::errs().
void SelectionDAG::Combine | ( | CombineLevel | Level, |
AAResults * | AA, | ||
CodeGenOpt::Level | OptLevel | ||
) |
This iterates over the nodes in the SelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes.
This is the entry point for the file.
The Level argument controls whether Combine is allowed to produce nodes and types that are illegal on the target.
This is the main entry point to this class.
Definition at line 24670 of file DAGCombiner.cpp.
KnownBits SelectionDAG::computeKnownBits | ( | SDValue | Op, |
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
Determine which bits of Op are known to be either zero or one and return them in Known.
The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements. Targets can implement the computeKnownBitsForTargetNode method in the TargetLowering class to allow target nodes to be understood.
The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements.
Definition at line 2916 of file SelectionDAG.cpp.
References llvm::KnownBits::abs(), llvm::ISD::ABS, llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDCARRY, llvm::ISD::ADDE, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, llvm::KnownBits::anyext(), llvm::KnownBits::ashr(), assert(), llvm::ISD::AssertAlign, llvm::ISD::AssertZext, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_CLR, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_SWAP, llvm::ISD::AVGCEILU, llvm::ISD::BITCAST, llvm::ISD::BITREVERSE, llvm::BitWidth, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::KnownBits::byteSwap(), llvm::APInt::clearAllBits(), llvm::APInt::clearBit(), llvm::APInt::clearLowBits(), llvm::KnownBits::commonBits(), llvm::KnownBits::computeForAddCarry(), llvm::KnownBits::computeForAddSub(), computeKnownBits(), llvm::TargetLowering::computeKnownBitsForFrameIndex(), llvm::TargetLowering::computeKnownBitsForTargetNode(), llvm::computeKnownBitsFromRangeMetadata(), llvm::ISD::CONCAT_VECTORS, llvm::KnownBits::countMaxLeadingZeros(), llvm::KnownBits::countMaxPopulation(), llvm::KnownBits::countMaxTrailingZeros(), llvm::KnownBits::countMinLeadingZeros(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::Depth, llvm::numbers::e, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::KnownBits::extractBits(), llvm::APInt::extractBits(), llvm::ISD::FGETSIGN, llvm::ISD::FP_TO_UINT_SAT, llvm::ISD::FrameIndex, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::Constant::getAggregateElement(), llvm::getAlign(), llvm::APInt::getAllOnes(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitsSetFrom(), llvm::KnownBits::getBitWidth(), llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), getDataLayout(), llvm::TargetLoweringBase::getExtendForAtomicOps(), llvm::APInt::getHiBits(), llvm::APInt::getLowBitsSet(), getMachineFunction(), llvm::ShuffleVectorSDNode::getMask(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::APInt::getNumSignBits(), llvm::APInt::getOneBitSet(), llvm::Type::getPrimitiveSizeInBits(), llvm::Type::getScalarSizeInBits(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::Constant::getSplatValue(), llvm::TargetLowering::getTargetConstantFromLoad(), llvm::Value::getType(), getValidMinimumShiftAmountConstant(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZero(), llvm::KnownBits::hasConflict(), i, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::KnownBits::insertBits(), llvm::APInt::insertBits(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isConstOrConstSplat(), llvm::EVT::isFloatingPoint(), isGuaranteedNotToBeUndefOrPoison(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::APInt::isNegative(), llvm::ISD::isNON_EXTLoad(), llvm::APInt::isNonNegative(), llvm::EVT::isScalableVector(), llvm::KnownBits::isUnknown(), llvm::EVT::isVector(), llvm::Type::isVectorTy(), llvm::ISD::isZEXTLoad(), llvm::ARM_MB::LD, LHS, LLVM_FALLTHROUGH, llvm::ISD::LOAD, llvm::Log2(), llvm::Log2_32(), llvm::KnownBits::lshr(), llvm::APInt::lshrInPlace(), M, llvm::KnownBits::makeConstant(), MaxRecursionDepth, llvm::min(), llvm::ISD::MUL, llvm::KnownBits::mul(), llvm::KnownBits::mulhs(), llvm::ISD::MULHS, llvm::KnownBits::mulhu(), llvm::ISD::MULHU, llvm::ISD::NON_EXTLOAD, llvm::KnownBits::One, llvm::ISD::OR, llvm::ISD::PARITY, llvm::KnownBits::resetAll(), llvm::KnownBits::reverseBits(), RHS, llvm::ISD::SADDO, llvm::ISD::SCALAR_TO_VECTOR, llvm::APIntOps::ScaleBitMask(), llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::APInt::setAllBits(), llvm::KnownBits::setAllZero(), llvm::APInt::setBit(), llvm::APInt::setBitsFrom(), llvm::ISD::SETCC, llvm::APInt::setHighBits(), llvm::APInt::setLowBits(), llvm::KnownBits::sext(), llvm::KnownBits::sextInReg(), llvm::KnownBits::shl(), llvm::ISD::SHL, llvm::APInt::shl(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ArrayRef< T >::size(), llvm::APInt::sle(), llvm::KnownBits::smax(), llvm::ISD::SMAX, llvm::KnownBits::smin(), llvm::ISD::SMIN, llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SREM, llvm::KnownBits::srem(), llvm::ISD::SRL, llvm::ISD::SSUBO, llvm::ISD::STRICT_FSETCC, llvm::ISD::STRICT_FSETCCS, llvm::ISD::SUB, llvm::ISD::SUBC, std::swap(), llvm::ISD::TargetFrameIndex, llvm::KnownBits::trunc(), llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UDIV, llvm::KnownBits::udiv(), llvm::KnownBits::umax(), llvm::ISD::UMAX, llvm::KnownBits::umin(), llvm::ISD::UMIN, llvm::ISD::UMUL_LOHI, llvm::ISD::UMULO, llvm::ISD::UREM, llvm::KnownBits::urem(), llvm::ISD::USUBO, llvm::ISD::USUBSAT, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::KnownBits::Zero, llvm::ISD::ZERO_EXTEND, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, llvm::KnownBits::zext(), llvm::APInt::zext(), and llvm::KnownBits::zextOrTrunc().
Determine which bits of Op are known to be either zero or one and return them in Known.
For vectors, the known bits are those that are shared by every vector element. Targets can implement the computeKnownBitsForTargetNode method in the TargetLowering class to allow target nodes to be understood.
For vectors, the known bits are those that are shared by every vector element.
Definition at line 2897 of file SelectionDAG.cpp.
References llvm::BitWidth, llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isVector().
Referenced by adjustForRedundantAnd(), llvm::SelectionDAGISel::CheckOrMask(), checkZExtBool(), combineArithReduction(), combineMOVMSK(), combinePMULH(), combineShiftToAVG(), combineVectorSignBitsTruncation(), computeKnownBits(), computeKnownBitsBinOp(), llvm::SparcTargetLowering::computeKnownBitsForTargetNode(), llvm::LanaiTargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), ComputeNumSignBits(), computeOverflowKind(), detectAVGPattern(), detectExtMul(), llvm::TargetLowering::expandFixedPointDiv(), foldMaskAndShiftToScale(), getPack(), haveNoCommonBitsSet(), isBitfieldPositioningOp(), isKnownToBeAPowerOfTwo(), isTruncateOf(), isWordAligned(), LowerAndToBT(), LowerAndToBTST(), LowerMUL(), MaskedValueIsAllOnes(), MaskedValueIsZero(), matchBinaryShuffle(), matchRotateSub(), llvm::AMDGPUTargetLowering::numBitsUnsigned(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), provablyDisjointOr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegImm34(), llvm::PPCTargetLowering::SelectAddressRegReg(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), tryBitfieldInsertOpFromOr(), and tryBitfieldInsertOpFromOrAndImm().
unsigned SelectionDAG::ComputeMaxSignificantBits | ( | SDValue | Op, |
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
Get the upper bound on bit size for this Value Op
as a signed integer.
i.e. x == sext(trunc(x to MaxSignedBits) to bitwidth(x)). Similar to the APInt::getSignificantBits function. Helper wrapper to ComputeNumSignBits.
Definition at line 4439 of file SelectionDAG.cpp.
References ComputeNumSignBits(), and llvm::Depth.
unsigned SelectionDAG::ComputeMaxSignificantBits | ( | SDValue | Op, |
unsigned | Depth = 0 |
||
) | const |
Get the upper bound on bit size for this Value Op
as a signed integer.
i.e. x == sext(trunc(x to MaxSignedBits) to bitwidth(x)). Similar to the APInt::getSignificantBits function. Helper wrapper to ComputeNumSignBits.
Definition at line 4433 of file SelectionDAG.cpp.
References ComputeNumSignBits(), and llvm::Depth.
Referenced by combineMulToPMADDWD(), combinePMULH(), detectExtMul(), EmitCmp(), getPack(), llvm::AMDGPUTargetLowering::numBitsSigned(), and llvm::TargetLowering::SimplifyDemandedBits().
unsigned SelectionDAG::ComputeNumSignBits | ( | SDValue | Op, |
const APInt & | DemandedElts, | ||
unsigned | Depth = 0 |
||
) | const |
Return the number of times the sign bit of the register is replicated into the other bits.
We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. The DemandedElts argument allows us to only collect the minimum sign bits of the requested vector elements. Targets can implement the ComputeNumSignBitsForTarget method in the TargetLowering class to allow target nodes to be understood.
Definition at line 3864 of file SelectionDAG.cpp.
References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::AND, assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_CLR, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_SWAP, llvm::ISD::BITCAST, llvm::BitWidth, llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, llvm::APInt::clearBit(), computeKnownBits(), ComputeNumSignBits(), llvm::TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::ISD::CONCAT_VECTORS, llvm::KnownBits::countMinSignBits(), llvm::Depth, llvm::numbers::e, llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::extractBits(), llvm::ISD::FP_TO_SINT_SAT, llvm::Constant::getAggregateElement(), llvm::APInt::getAllOnes(), llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), getDataLayout(), llvm::TargetLoweringBase::getExtendForAtomicOps(), llvm::ShuffleVectorSDNode::getMask(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::APInt::getNumSignBits(), llvm::APInt::getOneBitSet(), llvm::Type::getPrimitiveSizeInBits(), llvm::Type::getScalarSizeInBits(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::TargetLowering::getTargetConstantFromLoad(), getValidMaximumShiftAmountConstant(), getValidMinimumShiftAmountConstant(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZero(), i, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::APInt::insertBits(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isConstOrConstSplat(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::KnownBits::isNonNegative(), llvm::EVT::isScalableVector(), llvm::EVT::isVector(), llvm::Type::isVectorTy(), llvm::ARM_MB::LD, M, llvm::max(), MaxRecursionDepth, llvm::min(), llvm::ISD::MUL, llvm::ISD::NON_EXTLOAD, llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::APIntOps::ScaleBitMask(), llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::APInt::setBit(), llvm::ISD::SETCC, llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::APInt::shl(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, llvm::ArrayRef< T >::size(), llvm::APInt::sle(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SSUBO, llvm::ISD::STRICT_FSETCC, llvm::ISD::STRICT_FSETCCS, llvm::ISD::SUB, std::swap(), llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::ISD::XOR, llvm::KnownBits::Zero, llvm::ISD::ZERO_EXTEND, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, llvm::APInt::zext(), and llvm::ISD::ZEXTLOAD.
unsigned SelectionDAG::ComputeNumSignBits | ( | SDValue | Op, |
unsigned | Depth = 0 |
||
) | const |
Return the number of times the sign bit of the register is replicated into the other bits.
We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. Targets can implement the ComputeNumSignBitsForTarget method in the TargetLowering class to allow target nodes to be understood.
Definition at line 3851 of file SelectionDAG.cpp.
References llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), llvm::EVT::isScalableVector(), and llvm::EVT::isVector().
Referenced by canReduceVMulWidth(), combineAndMaskToShift(), combineGatherScatter(), combineLogicBlendIntoConditionalNegate(), combineLogicBlendIntoPBLENDV(), combineMUL_VLToVWMUL_VL(), combineMulToPMULDQ(), combinePredicateReduction(), combinePTESTCC(), combineSelect(), combineSetCCMOVMSK(), combineShiftToAVG(), combineSIntToFP(), combineVectorCompareAndMaskUnaryOp(), combineVectorPack(), combineVectorSignBitsTruncation(), combineVSelectWithAllOnesOrZeros(), combineVWADD_W_VL_VWSUB_W_VL(), ComputeMaxSignificantBits(), ComputeNumSignBits(), computeNumSignBitsBinOp(), llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandMUL_LOHI(), foldAddSubMasked1(), getFauxShuffleMask(), isS16(), LowerADDSAT_SUBSAT(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerTruncateVecI1(), lowerVectorIntrinsicScalars(), matchShuffleWithPACK(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), performSIGN_EXTEND_INREGCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::selectSExti32(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), and llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowKind | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the addition of 2 node can overflow.
Definition at line 3773 of file SelectionDAG.cpp.
References computeKnownBits(), llvm::APInt::getBoolValue(), llvm::KnownBits::getMaxValue(), llvm::SDValue::getOpcode(), llvm::SDValue::getResNo(), llvm::isNullConstant(), OFK_Never, OFK_Sometime, llvm::APInt::uadd_ov(), llvm::ISD::UMUL_LOHI, and llvm::KnownBits::Zero.
Create a stack temporary, suitable for holding the specified value type.
If minAlign is specified, the slot size will have at least that alignment.
Definition at line 2295 of file SelectionDAG.cpp.
References Align, CreateStackTemporary(), getContext(), getDataLayout(), getPrefTypeAlign(), llvm::EVT::getStoreSize(), llvm::EVT::getTypeForEVT(), and llvm::max().
Create a stack temporary suitable for holding either of the specified value types.
Definition at line 2302 of file SelectionDAG.cpp.
References assert(), CreateStackTemporary(), DL, getContext(), getDataLayout(), llvm::TypeSize::getKnownMinSize(), llvm::EVT::getStoreSize(), llvm::EVT::getTypeForEVT(), llvm::LinearPolySize< LeafTy >::isScalable(), and llvm::max().
Create a stack temporary based on the size in bytes and the alignment.
Definition at line 2282 of file SelectionDAG.cpp.
References llvm::MachineFrameInfo::CreateStackObject(), getDataLayout(), getFrameIndex(), llvm::TargetLoweringBase::getFrameIndexTy(), llvm::MachineFunction::getFrameInfo(), llvm::TargetSubtargetInfo::getFrameLowering(), llvm::TypeSize::getKnownMinSize(), llvm::TargetFrameLowering::getStackIDForScalableVectors(), llvm::MachineFunction::getSubtarget(), and llvm::LinearPolySize< LeafTy >::isScalable().
Referenced by CreateStackTemporary(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::RISCVTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::ARMTargetLowering::PerformMVEExtCombine(), and llvm::ARMTargetLowering::PerformMVETruncCombine().
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Definition at line 1787 of file SelectionDAG.h.
References llvm::SDDbgInfo::DbgBegin().
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Definition at line 1788 of file SelectionDAG.h.
References llvm::SDDbgInfo::DbgEnd().
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Definition at line 1797 of file SelectionDAG.h.
References llvm::SDDbgInfo::DbgLabelBegin().
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Definition at line 1800 of file SelectionDAG.h.
References llvm::SDDbgInfo::DbgLabelEnd().
void SelectionDAG::DeleteNode | ( | SDNode * | N | ) |
Remove the specified node from the system.
This node must have no referrers.
Definition at line 965 of file SelectionDAG.cpp.
References N.
Referenced by Legalize(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), and llvm::RISCVDAGToDAGISel::PreprocessISelDAG().
Check if a node exists without modifying its flags.
doesNodeExist - Check if a node exists without modifying its flags.
Definition at line 9655 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::MVT::Glue, llvm::SDVTList::NumVTs, and llvm::SDVTList::VTs.
Referenced by llvm::TargetLowering::SimplifySetCC().
LLVM_DUMP_METHOD void SelectionDAG::dump | ( | ) | const |
Definition at line 919 of file SelectionDAGDumper.cpp.
Referenced by NewSDValueDbgMsg(), llvm::HexagonDAGToDAGISel::PreprocessISelDAG(), and AMDGPUDAGToDAGISel::PreprocessISelDAG().
LLVM_DUMP_METHOD void SelectionDAG::dumpDotGraph | ( | const Twine & | FileName, |
const Twine & | Title | ||
) |
Just dump dot graph to a user-provided path and title.
This doesn't open the dot viewer program and helps visualization when outside debugging session. FileName expects absolute path. If provided without any path separators then the file will be created in the current directory. Error will be emitted if the path is insane.
Definition at line 171 of file SelectionDAGPrinter.cpp.
References llvm::dumpDotGraphToFile().
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inlinestatic |
Returns an APFloat semantics tag appropriate for the given type.
If VT is a vector type, the element semantics are returned.
Definition at line 1757 of file SelectionDAG.h.
References llvm::MVT::bf16, llvm::APFloatBase::BFloat(), llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), llvm::APFloatBase::IEEEquad(), llvm::APFloatBase::IEEEsingle(), llvm_unreachable, llvm::APFloatBase::PPCDoubleDouble(), llvm::MVT::ppcf128, llvm::MVT::SimpleTy, and llvm::APFloatBase::x87DoubleExtended().
Referenced by foldConstantFPMath(), FoldIntToFPToInt(), getConstantFP(), getDenormalMode(), getMemsetValue(), getNeutralElement(), getNode(), llvm::TargetLowering::getSqrtInputTest(), llvm::ConstantFPSDNode::isValueValidForType(), LowerFABSorFNEG(), LowerFCOPYSIGN(), lowerFROUND(), LowerFROUND(), lowerFTRUNC_FCEIL_FFLOOR(), lowerShuffleAsBitMask(), and llvm::TargetLowering::SimplifyDemandedBits().
Expand the specified ISD::VAARG
node as the Legalize pass would.
Definition at line 2206 of file SelectionDAG.cpp.
Expand the specified ISD::VACOPY
node as the Legalize pass would.
Definition at line 2240 of file SelectionDAG.cpp.
Referenced by LowerVACOPY().
void SelectionDAG::ExtractVectorElements | ( | SDValue | Op, |
SmallVectorImpl< SDValue > & | Args, | ||
unsigned | Start = 0 , |
||
unsigned | Count = 0 , |
||
EVT | EltVT = EVT() |
||
) |
Append the extracted elements from Start to Count out of the vector Op in Args.
If Count is 0, all of the elements will be extracted. The extracted elements will have type EVT if it is provided, and otherwise their type will be Op's element type.
Definition at line 11209 of file SelectionDAG.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Key::Args, llvm::numbers::e, llvm::ISD::EXTRACT_VECTOR_ELT, getNode(), llvm::EVT::getVectorElementType(), getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), and i.
Referenced by adjustLoadValueTypeImpl(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), padEltsToUndef(), UnrollVectorOverflowOp(), unrollVectorShift(), and widenVectorToPartType().
SDValue SelectionDAG::FoldConstantArithmetic | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 5482 of file SelectionDAG.cpp.
References llvm::all_of(), assert(), llvm::ISD::BITCAST, llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::ISD::BUILD_VECTOR, llvm::ISD::BUILTIN_OP_END, C1, llvm::ISD::CONCAT_VECTORS, llvm::ISD::CONDCODE, llvm::ISD::Constant, llvm::ISD::ConstantFP, DL, E, foldConstantFPMath(), FoldSymbolOffset(), FoldValue(), getBitcast(), llvm::TargetLoweringBase::getBooleanContents(), getBuildVector(), getConstant(), getContext(), getDataLayout(), llvm::TargetLoweringBase::getExtendForContent(), llvm::LinearPolySize< LeafTy >::getFixedValue(), getNode(), getOpcode(), llvm::SDValue::getOpcode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), getSplatVector(), getStepVector(), llvm::TargetLoweringBase::getTypeAction(), llvm::TargetLoweringBase::getTypeToTransformTo(), getUNDEF(), llvm::Optional< T >::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), I, llvm::MVT::i1, llvm::TargetLoweringBase::isCommutativeBinOp(), llvm::ISD::isConstantSplatVector(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isInteger(), llvm::DataLayout::isLittleEndian(), llvm::LinearPolySize< LeafTy >::isScalable(), llvm::SDValue::isUndef(), isUndef(), llvm::EVT::isVector(), llvm::ISD::MUL, NewNodesMustHaveLegalTypes, NewSDValueDbgMsg(), llvm::BitVector::none(), llvm::peekThroughBitcasts(), llvm::BuildVectorSDNode::recastRawBits(), llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ArrayRef< T >::size(), llvm::ISD::SPLAT_VECTOR, llvm::ISD::STEP_VECTOR, llvm::ISD::TRUNCATE, and llvm::TargetLoweringBase::TypeLegal.
Referenced by foldAddSubOfSignBit(), getNode(), getTargetVShiftByConstNode(), getTargetVShiftNode(), LowerRotate(), and llvm::TargetLowering::SimplifyDemandedVectorElts().
SDValue SelectionDAG::foldConstantFPMath | ( | unsigned | Opcode, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2 | ||
) |
Fold floating-point operations with 2 operands when both operands are constants and/or undefined.
Definition at line 5695 of file SelectionDAG.cpp.
References C1, DL, EVTToAPFloatSemantics(), llvm::ISD::FADD, llvm::ISD::FCOPYSIGN, llvm::ISD::FDIV, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, llvm::ISD::FMUL, llvm::ISD::FP_ROUND, llvm::ISD::FREM, llvm::ISD::FSUB, getConstantFP(), llvm::APFloat::getNaN(), getUNDEF(), llvm::ConstantFPSDNode::getValueAPF(), llvm::isConstOrConstSplatFP(), llvm::SDValue::isUndef(), LLVM_FALLTHROUGH, llvm::maximum(), llvm::maxnum(), llvm::minimum(), llvm::minnum(), and llvm::APFloatBase::rmNearestTiesToEven.
Referenced by FoldConstantArithmetic().
SDValue SelectionDAG::FoldSetCC | ( | EVT | VT, |
SDValue | N1, | ||
SDValue | N2, | ||
ISD::CondCode | Cond, | ||
const SDLoc & | dl | ||
) |
Constant fold a setcc to true or false.
Definition at line 2318 of file SelectionDAG.cpp.
References assert(), C1, llvm::APFloatBase::cmpEqual, llvm::APFloatBase::cmpGreaterThan, llvm::APFloatBase::cmpLessThan, llvm::APFloatBase::cmpUnordered, llvm::ICmpInst::compare(), Cond, getBoolConstant(), llvm::getICmpCondCode(), getSetCC(), llvm::ISD::getSetCCSwappedOperands(), llvm::EVT::getSimpleVT(), getUNDEF(), llvm::ISD::getUnorderedFlavor(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::isCondCodeLegal(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::ISD::isTrueWhenEqual(), llvm::SDValue::isUndef(), LLVM_FALLTHROUGH, llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETFALSE, llvm::ISD::SETFALSE2, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETTRUE, llvm::ISD::SETTRUE2, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.
Referenced by getNode(), and llvm::TargetLowering::SimplifySetCC().
SDValue SelectionDAG::FoldSymbolOffset | ( | unsigned | Opcode, |
EVT | VT, | ||
const GlobalAddressSDNode * | GA, | ||
const SDNode * | N2 | ||
) |
Definition at line 5437 of file SelectionDAG.cpp.
References llvm::ISD::ADD, llvm::GlobalAddressSDNode::getGlobal(), getGlobalAddress(), llvm::GlobalAddressSDNode::getOffset(), llvm::SDNode::getOpcode(), llvm::ISD::GlobalAddress, llvm::TargetLowering::isOffsetFoldingLegal(), and llvm::ISD::SUB.
Referenced by FoldConstantArithmetic().
SDValue SelectionDAG::getAddrSpaceCast | ( | const SDLoc & | dl, |
EVT | VT, | ||
SDValue | Ptr, | ||
unsigned | SrcAS, | ||
unsigned | DestAS | ||
) |
Return an AddrSpaceCastSDNode.
Definition at line 2171 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::ISD::ADDRSPACECAST, E, llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getVTList(), and N.
Referenced by combineLoad(), combineStore(), and llvm::SITargetLowering::LowerFormalArguments().
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inline |
Definition at line 634 of file SelectionDAG.h.
References DL, llvm::APInt::getAllOnes(), getConstant(), and llvm::EVT::getScalarSizeInBits().
Referenced by combineMinMaxReduction(), getBoolConstant(), getNeutralElement(), getNode(), getNOT(), getTargetVShiftNode(), isConditionalZeroOrAllOnes(), LowerADDSUBCARRY(), LowerBUILD_VECTORvXi1(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerVECTOR_SHUFFLE(), performAddCSelIntoCSinc(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifySetCC(), and simplifySetCCWithCTPOP().
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncating it.
Definition at line 1361 of file SelectionDAG.cpp.
References llvm::ISD::ANY_EXTEND, llvm::EVT::bitsGT(), DL, getNode(), and llvm::ISD::TRUNCATE.
Referenced by combineBitcast(), combineScalarToVector(), combineToExtendBoolVectorInReg(), createGPRPairNode(), createMMXBuildVector(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(), getCopyFromPartsVector(), getCopyToPartsVector(), getNode(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerFunnelShift(), LowerMUL(), LowervXi8MulWithUNPCK(), performBuildShuffleExtendCombine(), performSVESpliceCombine(), and llvm::HexagonTargetLowering::ReplaceNodeResults().
Return an AssertAlignSDNode.
Definition at line 5768 of file SelectionDAG.cpp.
References AddNodeIDNode(), Align, assert(), llvm::ISD::AssertAlign, DL, E, llvm::SDValue::getValueType(), getVTList(), llvm::EVT::isInteger(), N, and NewSDValueDbgMsg().
SDValue SelectionDAG::getAtomic | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic op, produces result and chain and takes 1 operand.
Definition at line 7459 of file SelectionDAG.cpp.
References assert(), llvm::ISD::ATOMIC_LOAD, getAtomic(), getVTList(), and llvm::MVT::Other.
SDValue SelectionDAG::getAtomic | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Val, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Definition at line 7431 of file SelectionDAG.cpp.
References assert(), llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_CLR, llvm::ISD::ATOMIC_LOAD_FADD, llvm::ISD::ATOMIC_LOAD_FSUB, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_STORE, llvm::ISD::ATOMIC_SWAP, llvm::SDValue::getValueType(), getVTList(), and llvm::MVT::Other.
Referenced by combineSetCCAtomicArith(), getAtomic(), getAtomicCmpSwap(), llvm::VETargetLowering::lowerATOMIC_SWAP(), and lowerAtomicArith().
SDValue SelectionDAG::getAtomic | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
SDVTList | VTList, | ||
ArrayRef< SDValue > | Ops, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic op, produces result and chain and takes N operands.
Definition at line 7396 of file SelectionDAG.cpp.
References AddNodeIDNode(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), and N.
SDValue SelectionDAG::getAtomicCmpSwap | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | MemVT, | ||
SDVTList | VTs, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Cmp, | ||
SDValue | Swp, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic cmpxchg op.
There are two valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a chain result. ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS produces the value loaded, a success flag (initially i1), and a chain.
Definition at line 7419 of file SelectionDAG.cpp.
References assert(), llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, getAtomic(), and llvm::SDValue::getValueType().
SDValue SelectionDAG::getAtomicMemcpy | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
unsigned | DstAlign, | ||
SDValue | Src, | ||
unsigned | SrcAlign, | ||
SDValue | Size, | ||
Type * | SizeTy, | ||
unsigned | ElemSz, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo | ||
) |
Definition at line 7152 of file SelectionDAG.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Key::Args.
SDValue SelectionDAG::getAtomicMemmove | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
unsigned | DstAlign, | ||
SDValue | Src, | ||
unsigned | SrcAlign, | ||
SDValue | Size, | ||
Type * | SizeTy, | ||
unsigned | ElemSz, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo | ||
) |
Definition at line 7255 of file SelectionDAG.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Key::Args.
SDValue SelectionDAG::getAtomicMemset | ( | SDValue | Chain, |
const SDLoc & | dl, | ||
SDValue | Dst, | ||
unsigned | DstAlign, | ||
SDValue | Value, | ||
SDValue | Size, | ||
Type * | SizeTy, | ||
unsigned | ElemSz, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo | ||
) |
Definition at line 7356 of file SelectionDAG.cpp.
References llvm::AMDGPU::HSAMD::Kernel::Key::Args.
SDValue SelectionDAG::getBasicBlock | ( | MachineBasicBlock * | MBB | ) |
Definition at line 1784 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::ISD::BasicBlock, E, getVTList(), MBB, N, llvm::None, and llvm::MVT::Other.
Referenced by AddNodeIDCustom(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), and llvm::SelectionDAGBuilder::visitSwitchCase().
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inline |
Definition at line 462 of file SelectionDAG.h.
References llvm::AMDGPUISD::BFI.
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
Use getNode to set a custom SDLoc.
Definition at line 2164 of file SelectionDAG.cpp.
References llvm::ISD::BITCAST, getNode(), and llvm::SDValue::getValueType().
Referenced by addShuffleForVecExtend(), adjustBitcastSrcVectorSSE1(), canonicalizeBitSelect(), canonicalizeLaneShuffleWithRepeatedOps(), canonicalizeShuffleMaskWithHorizOp(), canonicalizeShuffleWithBinOps(), combineAnd(), combineAndMaskToShift(), combineAndNotIntoANDNP(), combineAndnp(), combineArithReduction(), combineBasicSADPattern(), combineBitcast(), combineBitcastToBoolVector(), combineBitcastvxi1(), combineBitOpWithMOVMSK(), combineBitOpWithShift(), combineBROADCAST_LOAD(), combineCastedMaskArithmetic(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineCVTPH2PS(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineFMulcFCMulc(), combineFneg(), combineFP_EXTEND(), combineFP_ROUND(), combineHorizOpWithShuffle(), combineLoad(), combineLogicBlendIntoConditionalNegate(), combineLogicBlendIntoPBLENDV(), combineMinMaxReduction(), combineMOVMSK(), combineMulToPMADDWD(), combineOr(), combinePMULDQ(), combinePMULH(), combinePredicateReduction(), combinePTESTCC(), combineRedundantDWordShuffle(), combineScalarAndWithMaskSetcc(), combineScalarToVector(), combineSelect(), combineSetCCMOVMSK(), combineShuffleOfBitcast(), combineShuffleToVectorExtend(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToFPTruncExtElt(), combineTruncationShuffle(), combineVectorCompareAndMaskUnaryOp(), combineVectorHADDSUB(), combineVectorSizedSetCCEquality(), combineVPDPBUSDPattern(), combineVSelectWithAllOnesOrZeros(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), combineXor(), constructDup(), convertIntLogicToFPLogic(), convertShiftLeftToScale(), createMMXBuildVector(), EltsFromConsecutiveLoads(), llvm::TargetLowering::expandIS_FPCLASS(), FoldConstantArithmetic(), FoldIntToFPToInt(), GeneratePerfectShuffle(), getAVX2GatherNode(), getBuildDwordsVector(), getCanonicalConstSplat(), getConstVector(), getCopyFromPartsVector(), getCopyToPartsVector(), getMaskNode(), getMemsetValue(), llvm::X86TargetLowering::getNegatedExpression(), getOnesVector(), getPack(), getScalarMaskingNode(), getScalarValueForVectorElement(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getv64i1Argument(), getVShift(), getZeroVector(), llvm::TargetLowering::IncrementMemoryAddress(), isHorizontalBinOp(), IsNOT(), lower256BitShuffle(), lower512BitShuffle(), LowerAVXExtend(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::HexagonTargetLowering::LowerCall(), lowerCTLZ_CTTZ_ZERO_UNDEF(), LowerCTPOP(), LowerEXTEND_VECTOR_INREG(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerFunnelShift(), LowerHorizontalByteSum(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), LowerLoad(), lowerMasksToReg(), LowerMUL(), LowerMULH(), llvm::RISCVTargetLowering::LowerOperation(), lowerRegToMasks(), llvm::HexagonTargetLowering::LowerReturn(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBitMask(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithUNPCK256(), LowerStore(), LowerTruncateVecI1(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), lowerV16I32Shuffle(), lowerV16I8Shuffle(), lowerV2I64Shuffle(), lowerV4I32Shuffle(), lowerV4I64Shuffle(), lowerV8F16Shuffle(), lowerV8I16GeneralSingleInputShuffle(), lowerV8I16Shuffle(), lowerV8I32Shuffle(), lowerV8I64Shuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVectorAllZero(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), lowerVectorIntrinsicScalars(), LowerVSETCC(), LowervXi8MulWithUNPCK(), lowerX86FPLogicOp(), narrowExtractedVectorBinOp(), narrowExtractedVectorSelect(), packImage16bitOpsToDwords(), Passv64i1ArgInRegs(), performConcatVectorsCombine(), performSVESpliceCombine(), performUzpCombine(), performVECTOR_SHUFFLECombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceBuildVecToShuffleWithZero(), reduceMaskedLoadToScalarLoad(), reduceMaskedStoreToScalarStore(), reduceVMULWidth(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), splitAndLowerShuffle(), truncateVectorWithNARROW(), truncateVectorWithPACK(), and tryWidenMaskForShuffle().
SDValue SelectionDAG::getBlockAddress | ( | const BlockAddress * | BA, |
EVT | VT, | ||
int64_t | Offset = 0 , |
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bool | isTarget = false , |
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unsigned | TargetFlags = 0 |
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) |
Definition at line 2114 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::ISD::BlockAddress, E, getVTList(), N, llvm::None, and llvm::ISD::TargetBlockAddress.
Referenced by getTargetBlockAddress(), llvm::SelectionDAGBuilder::getValueImpl(), and llvm::LanaiTargetLowering::LowerBlockAddress().
Create a true or false constant of type VT
using the target's BooleanContent for type OpVT
.
Definition at line 1434 of file SelectionDAG.cpp.
References DL, getAllOnesConstant(), llvm::TargetLoweringBase::getBooleanContents(), getConstant(), llvm_unreachable, llvm::TargetLoweringBase::UndefinedBooleanContent, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.
Referenced by llvm::TargetLowering::expandIS_FPCLASS(), FoldSetCC(), getLogicalNOT(), getVPLogicalNOT(), llvm::TargetLowering::SimplifySetCC(), and UnrollVectorOverflowOp().
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it.
Definition at line 1379 of file SelectionDAG.cpp.
References llvm::EVT::bitsLE(), llvm::TargetLoweringBase::getBooleanContents(), llvm::TargetLoweringBase::getExtendForContent(), getNode(), and llvm::ISD::TRUNCATE.
Referenced by llvm::TargetLowering::SimplifySetCC().
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Return an ISD::BUILD_VECTOR node.
The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.
Definition at line 811 of file SelectionDAG.h.
References llvm::ISD::BUILD_VECTOR, DL, and getNode().
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Return an ISD::BUILD_VECTOR node.
The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.
Definition at line 802 of file SelectionDAG.h.
References llvm::ISD::BUILD_VECTOR, DL, and getNode().
Referenced by adjustLoadValueTypeImpl(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), BuildExactSDIV(), buildScalarToVector(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), combineConcatVectorOfScalars(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineShuffleOfScalars(), combineStore(), combineToExtendBoolVectorInReg(), combineX86ShuffleChain(), CompactSwizzlableVector(), convertLocVTToValVT(), convertShiftLeftToScale(), detectAVGPattern(), ExtendToType(), extractSubVector(), foldCONCAT_VECTORS(), FoldConstantArithmetic(), GenerateTBL(), getBuildDwordsVector(), getBuildVectorSplat(), getConstant(), getConstVector(), getCopyFromPartsVector(), getGeneralPermuteNode(), llvm::TargetLowering::getNegatedExpression(), getNode(), getStepVector(), getTargetVShiftNode(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorShuffle(), incDecVectorConstant(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBUILD_VECTOR(), lowerBuildVectorToBitOp(), LowerBuildVectorv4x32(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), lowerINT_TO_FP_vXi64(), lowerMSABinaryBitImmIntr(), lowerMSASplatZExt(), LowerMUL(), LowerShift(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleWithPSHUFB(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerTruncateVectorStore(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerV16I8Shuffle(), lowerV8I16Shuffle(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE_VSHF(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOPInRegLUT(), LowervXi8MulWithUNPCK(), NormalizeBuildVector(), packImage16bitOpsToDwords(), padEltsToUndef(), PerformBUILD_VECTORCombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), performVSelectCombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReorganizeVector(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeBinOpOfSplats(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::SimplifyDemandedVectorElts(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), tryBuildVectorShuffle(), tryToFoldExtendOfConstant(), UnrollVectorOp(), UnrollVectorOverflowOp(), unrollVectorShift(), and widenVectorToPartType().
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Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
CALLSEQ_END does not have a useful SDLoc.
Definition at line 952 of file SelectionDAG.h.
References llvm::ISD::CALLSEQ_END, DL, llvm::SDValue::getNode(), getNode(), getVTList(), llvm::MVT::Glue, and llvm::MVT::Other.
Referenced by llvm::VETargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), and PrepareTailCall().
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Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and OutSize specifies part of the frame set up prior to the sequence.
Definition at line 940 of file SelectionDAG.h.
References llvm::ISD::CALLSEQ_START, DL, getIntPtrConstant(), getNode(), getVTList(), llvm::MVT::Glue, and llvm::MVT::Other.
Referenced by llvm::VETargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), and llvm::VETargetLowering::lowerToTLSGeneralDynamicModel().
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Return CallSiteInfo associated with Node, or a default if none exists.
Definition at line 2160 of file SelectionDAG.h.
References llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find(), I, and move.
SDValue SelectionDAG::getCommutedVectorShuffle | ( | const ShuffleVectorSDNode & | SV | ) |
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands.
Example: shuffle A, B, <0,5,2,7> -> shuffle B, A, <4,1,6,3>
Definition at line 2051 of file SelectionDAG.cpp.
References llvm::ArrayRef< T >::begin(), llvm::ShuffleVectorSDNode::commuteMask(), llvm::ArrayRef< T >::end(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), and getVectorShuffle().
Referenced by lowerVECTOR_SHUFFLE().
SDValue SelectionDAG::getCondCode | ( | ISD::CondCode | Cond | ) |
Definition at line 1839 of file SelectionDAG.cpp.
Referenced by getSelectCC(), getSetCC(), getSetCCVP(), llvm::TargetLowering::LegalizeSetCCCondCode(), lowerBALLOTIntrinsic(), lowerFCMPIntrinsic(), lowerICMPIntrinsic(), LowerTruncatei1(), LowerVSETCC(), llvm::RISCVTargetLowering::PerformDAGCombine(), performIntrinsicCombine(), performVSelectCombine(), splitIntVSETCC(), and tryConvertSVEWideCompare().
SDValue SelectionDAG::getConstant | ( | const APInt & | Val, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false , |
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bool | isOpaque = false |
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) |
Definition at line 1458 of file SelectionDAG.cpp.
References DL, llvm::ConstantInt::get(), and getConstant().
SDValue SelectionDAG::getConstant | ( | const ConstantInt & | Val, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false , |
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bool | isOpaque = false |
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) |
Definition at line 1463 of file SelectionDAG.cpp.
References AddNodeIDNode(), llvm::append_range(), assert(), llvm::ISD::BITCAST, llvm::ISD::Constant, DL, llvm::numbers::e, llvm::APInt::extractBits(), llvm::ConstantInt::get(), llvm::ConstantInt::getBitWidth(), getBuildVector(), getConstant(), getContext(), getDataLayout(), getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), getSplatBuildVector(), getSplatVector(), llvm::TargetLoweringBase::getTypeAction(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::ConstantInt::getValue(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), getVTList(), i, isBigEndian(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::EVT::isVector(), N, NewNodesMustHaveLegalTypes, NewSDValueDbgMsg(), llvm::None, llvm::reverse(), llvm::ISD::SPLAT_VECTOR_PARTS, llvm::ISD::TargetConstant, llvm::TargetLoweringBase::TypeExpandInteger, llvm::TargetLoweringBase::TypePromoteInteger, and llvm::APInt::zextOrTrunc().
SDValue SelectionDAG::getConstant | ( | uint64_t | Val, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false , |
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bool | isOpaque = false |
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) |
Create a ConstantSDNode wrapping a constant value.
If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal).
Definition at line 1449 of file SelectionDAG.cpp.
References assert(), DL, llvm::EVT::getScalarType(), and llvm::EVT::getSizeInBits().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addIPMSequence(), adjustForSubtraction(), adjustForTestUnderMask(), adjustICmpTruncate(), adjustSubwordCmp(), adjustZeroCmp(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), bitcastf32Toi32(), buildCallOperands(), BuildExactSDIV(), BuildIntrinsicOp(), llvm::SITargetLowering::buildRSRC(), llvm::TargetLowering::BuildSDIV(), llvm::RISCVTargetLowering::BuildSDIVPow2(), llvm::PPCTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildUDIV(), carryFlagToValue(), clampDynamicVectorIndex(), combineAcrossLanesIntrinsic(), combineADC(), combineADDCARRYDiamond(), combineAddOrSubToADCOrSBB(), combineADDToADDZE(), combineAnd(), combineAndnp(), CombineANDShift(), combineArithReduction(), CombineBaseUpdate(), combineBitcast(), combineBitcastToBoolVector(), combineCarryDiamond(), combineCarryThroughADD(), combineCMov(), combineCMP(), combineCompareEqual(), combineEXTEND_VECTOR_INREG(), combineEXTRACT_SUBVECTOR(), combineExtractVectorElt(), combineFP_EXTEND(), combineGatherScatter(), combineGREVI_GORCI(), combineKSHIFT(), combineM68kBrCond(), combineMinMaxReduction(), combineMOVMSK(), combineMul(), combineMulSpecial(), combineMulToPMADDWD(), combineOr(), combineORToGORC(), combineORToGREV(), combineORToSHFL(), combinePMULDQ(), combinePredicateReduction(), combinePTESTCC(), combineROTR_ROTL_RORW_ROLW(), combineScalarAndWithMaskSetcc(), combineSelect(), combineSelectOfTwoConstants(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCMOVMSK(), combineShiftAnd1ToBitTest(), combineShiftLeft(), combineShiftOfShiftedLogic(), combineShiftRightArithmetic(), combineShiftRightLogical(), combineShiftToMULH(), combineStore(), combineSub(), combineSVEPrefetchVecBaseImmOff(), combineSVEReductionFP(), combineSVEReductionInt(), combineSVEReductionOrderedFP(), combineToExtendBoolVectorInReg(), combineVectorCompare(), combineVectorShiftImm(), combineVectorShiftVar(), combineVectorSizedSetCCEquality(), combineVectorTruncationWithPACKUS(), CombineVMOVDRRCandidateWithVecOp(), combineVPMADD(), combineVSelectWithAllOnesOrZeros(), combinevXi1ConstantToInteger(), combineX86AddSub(), combineX86ShuffleChain(), constantFoldBFE(), constructDup(), constructRetValue(), ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), convertFixedMaskToScalableVector(), convertFromScalableVector(), convertShiftLeftToScale(), convertToScalableVector(), convertValVTToLocVT(), CreateCopyOfByValArgument(), createFPCmp(), createGPRPairNode(), createLoadLR(), createPSADBW(), createStoreLR(), createVariablePermute(), createVPDPBUSD(), detectAVGPattern(), EltsFromConsecutiveLoads(), EmitCMP(), emitConditionalComparison(), emitConstantSizeRepmov(), emitMemMemImm(), emitMemMemReg(), emitSETCC(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrlen(), EmitTest(), Expand64BitShift(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandBSWAP(), expandDivFix(), expandf64Toi32(), llvm::TargetLowering::expandFixedPointDiv(), expandIntrinsicWChainHelper(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), ExtendToType(), extractF64Exponent(), extractShiftForRotate(), finalizeTS1AM(), foldADCToCINC(), foldAddSubBoolOfMaskedVal(), foldAndToUsubsat(), FoldConstantArithmetic(), foldCSELofCTTZ(), foldExtendedSignBitTest(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToBEXTR(), foldMaskedShiftToScaledMask(), foldSelectOfConstantsUsingSra(), foldSetCCWithFunnelShift(), FoldSTEP_VECTOR(), foldVSelectToSignBitSplatMask(), foldXorTruncShiftIntoCmp(), genConstMult(), generateEquivalentSub(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), llvm::MipsTargetLowering::getAddrNonPICSym64(), getAllOnesConstant(), getARMIndexedAddressParts(), getAVX512Node(), getBitTestCondition(), getBoolConstant(), getBuildVectorSplat(), getCanonicalConstSplat(), getCCResult(), llvm::VECustomDAG::getConstant(), getConstant(), llvm::VECustomDAG::getConstantMask(), getConstVector(), getCopyFromParts(), llvm::RegsForValue::getCopyFromRegs(), getDefaultVLOps(), GetDemandedBits(), GetExponent(), getGeneralPermuteNode(), llvm::AMDGPUTargetLowering::getHiHalf64(), getIntPtrConstant(), getLimitedPrecisionExp2(), llvm::AMDGPUTargetLowering::getLoHalf64(), llvm::VECustomDAG::getMaskBroadcast(), getMaskNode(), getMemBasePlusOffset(), getMemsetStringVal(), getMemsetValue(), getMVEIndexedAddressParts(), getNegatedInteger(), getNeutralElement(), getNode(), getOnesVector(), getPack(), getPMOVMSKB(), llvm::AVRTargetLowering::getPostIndexedAddressParts(), llvm::AVRTargetLowering::getPreIndexedAddressParts(), getPTest(), getReductionSDNode(), getScaledOffsetForBitWidth(), getSETCC(), getShiftAmountConstant(), getShuffleScalarElt(), GetSignificand(), llvm::NVPTXTargetLowering::getSqrtEstimate(), getStepVector(), getT2IndexedAddressParts(), getTargetConstant(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getTruncatedUSUBSAT(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorIdxConstant(), llvm::TargetLowering::getVectorSubVecPointer(), getVScale(), getZeroExtendInReg(), getZeroVector(), incDecVectorConstant(), llvm::TargetLowering::IncrementMemoryAddress(), initAccumulator(), insert1BitVector(), IntCondCCodeToICC(), isBLACompatibleAddress(), isConditionalZeroOrAllOnes(), IsSingleInstrConstant(), llvm::AMDGPUTargetLowering::loadInputValue(), lower1BitShuffle(), LowerABS(), LowerADDC_ADDE_SUBC_SUBE(), LowerADDSAT_SUBSAT(), LowerADDSUBCARRY(), LowerAndToBT(), LowerAndToBTST(), LowerAsSplatVectorLoad(), LowerATOMIC_FENCE(), lowerAtomicArith(), LowerAVXExtend(), lowerBALLOTIntrinsic(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), llvm::LanaiTargetLowering::LowerBR_CC(), LowerBR_CC(), LowerBRCOND(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBUILD_VECTOR(), LowerBUILD_VECTOR_i1(), LowerBUILD_VECTORToVIDUP(), LowerBUILD_VECTORvXi1(), LowerBuildVectorOfFPExt(), LowerBuildVectorOfFPTrunc(), LowerBuildVectorv16i8(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), LowerCallResult(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), LowerCONCAT_VECTORSvXi1(), LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), lowerCTLZ_CTTZ_ZERO_UNDEF(), LowerCTPOP(), LowerCTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_SUBVECTOR(), llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_i1(), llvm::SparcTargetLowering::LowerF128Compare(), LowerF128Load(), LowerF128Store(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), LowerFGETSIGN(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_64(), LowerFP16_TO_FP(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), lowerFP_TO_INT_SAT(), LowerFP_TO_INT_SAT(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), LowerFunnelShift(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), LowerHorizontalByteSum(), llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(), LowerINSERT_VECTOR_ELT_i1(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(), lowerINT_TO_FP_vXi64(), LowerInterruptReturn(), llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(), LowerINTRINSIC_W_CHAIN(), LowerLabelRef(), llvm::MipsTargetLowering::lowerLOAD(), lowerLoadF128(), LowerMemOpCallTo(), lowerMSABinaryBitImmIntr(), lowerMSABitClear(), lowerMSABitClearImm(), lowerMSASplatImm(), lowerMSASplatZExt(), llvm::LanaiTargetLowering::LowerMUL(), LowerMUL(), lowerMUL_LOHI32(), LowerMULH(), LowerMULO(), llvm::R600TargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperationWrapper(), LowerPARITY(), LowerPredicateLoad(), LowerPredicateStore(), llvm::HexagonTargetLowering::LowerPREFETCH(), LowerPREFETCH(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), lowerRETURNADDR(), LowerRotate(), LowerSaturatingConditional(), lowerScalarSplat(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCCARRY(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsTruncBroadcast(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleToEXPAND(), lowerShuffleWithPSHUFB(), LowerSIGN_EXTEND_Mask(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), lowerStoreF128(), LowerSVEIntrinsicEXT(), LowerTruncatei1(), LowerTruncateVecI1(), LowerTruncateVectorStore(), llvm::HexagonTargetLowering::LowerUAddSubO(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), LowerUMULO_SMULO(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerV16I8Shuffle(), lowerV8I16Shuffle(), LowerVecReduce(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorAllZero(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOPInRegLUT(), lowerVectorIntrinsicScalars(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowervXi8MulWithUNPCK(), LowerWRITE_REGISTER(), lowerX86CmpEqZeroToCtlzSrl(), LowerXALUO(), LowerZERO_EXTEND_Mask(), llvm::SparcTargetLowering::makeAddress(), matchBSwapHWordOrAndAnd(), memsetStore(), NormalizeBuildVector(), optimizeLogicalImm(), overflowFlagToValue(), llvm::SITargetLowering::passSpecialInputs(), Passv64i1ArgInRegs(), performAddCSelIntoCSinc(), PerformAddcSubcCombine(), PerformAddeSubeCombine(), performAddUADDVCombine(), PerformADDVecReduce(), performANDCombine(), performANDORCSELCombine(), PerformARMBUILD_VECTORCombine(), PerformBFICombine(), performBITREVERSECombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performConcatVectorsCombine(), PerformCSETCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::HexagonTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performDSPShiftCombine(), PerformExtractEltCombine(), PerformExtractEltToVMOVRRD(), performExtractVectorEltCombine(), llvm::AMDGPUTargetLowering::performFAbsCombine(), performFDivCombine(), performFlagSettingCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFP_TO_INT_SATCombine(), performFpToIntCombine(), performGlobalAddressCombine(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), performIntrinsicCombine(), performLDNT1Combine(), PerformLongShiftCombine(), PerformMinMaxCombine(), PerformMinMaxToSatCombine(), performMulCombine(), PerformMULCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performORCombine(), PerformORCombineToBFI(), PerformPREDICATE_CASTCombine(), performSetccAddFolding(), performSETCCCombine(), PerformShiftCombine(), llvm::AMDGPUTargetLowering::performShlCombine(), performSHLCombine(), PerformSHLSimplify(), PerformShuffleVMOVNCombine(), performSIGN_EXTEND_INREGCombine(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performSraCombine(), llvm::AMDGPUTargetLowering::performSrlCombine(), PerformSTORECombine(), PerformSUBCombine(), performSVEAndCombine(), performTBZCombine(), performTruncateCombine(), PerformTruncatingStoreCombine(), PerformVCMPCombine(), PerformVCVTCombine(), PerformVDIVCombine(), PerformVDUPCombine(), performVecReduceAddCombine(), performVecReduceAddCombineWithUADDLP(), PerformVMOVrhCombine(), PerformVMOVRRDCombine(), performVSelectCombine(), PerformVSetCCToVCTPCombine(), performXORCombine(), PerformXORCombine(), prepareTS1AM(), promoteExtBeforeAdd(), llvm::AArch64TargetLowering::ReconstructShuffle(), recoverFramePointer(), reduceBuildVecToShuffleWithZero(), ReplaceLongIntrinsic(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), SaturateWidenedDIVFIX(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::TargetLowering::ShrinkDemandedConstant(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::ARMTargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::TargetLowering::SimplifyDemandedVectorElts(), simplifyDivRem(), llvm::TargetLowering::SimplifySetCC(), simplifySetCCWithCTPOP(), simplifyShift(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), splatSplitI64WithVL(), llvm::AMDGPUTargetLowering::split64BitValue(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), SplitEVL(), splitInt128(), splitStores(), splitStoreSplat(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::AMDGPUTargetLowering::storeStackInputValue(), llvm::RISCVTargetLowering::targetShrinkDemandedConstant(), llvm::ARMTargetLowering::targetShrinkDemandedConstant(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), transformAddImmMulImm(), transformAddShlImm(), TranslateM68kCC(), translateSetCCForBranch(), TranslateX86CC(), truncateVecElts(), tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), tryAdvSIMDModImmFP(), TryCombineBaseUpdate(), tryCombineShiftImm(), tryCombineToEXTR(), tryConvertSVEWideCompare(), tryExtendDUPToExtractHigh(), tryFoldToZero(), tryFormConcatFromShuffle(), TryMULWIDECombine(), tryToFoldExtendOfConstant(), UnpackFromArgumentSlot(), UnrollVectorOverflowOp(), unrollVectorShift(), valueToCarryFlag(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSwitchCase(), WidenVector(), and WinDBZCheckDenominator().
SDDbgValue * SelectionDAG::getConstantDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
const Value * | C, | ||
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a constant SDDbgValue node.
Definition at line 9682 of file SelectionDAG.cpp.
References assert(), DL, llvm::SDDbgOperand::fromConst(), llvm::SDDbgInfo::getAlloc(), and llvm::RISCVFenceField::O.
Referenced by llvm::SelectionDAGBuilder::resolveDanglingDebugInfo(), and llvm::SelectionDAGBuilder::salvageUnresolvedDbgValue().
SDValue SelectionDAG::getConstantFP | ( | const APFloat & | Val, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false |
||
) |
Definition at line 1589 of file SelectionDAG.cpp.
References DL, llvm::ConstantFP::get(), getConstantFP(), and getContext().
SDValue SelectionDAG::getConstantFP | ( | const ConstantFP & | V, |
const SDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget = false |
||
) |
Definition at line 1594 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::ISD::ConstantFP, DL, llvm::EVT::getScalarType(), getSplatBuildVector(), getSplatVector(), getVTList(), llvm::EVT::isFloatingPoint(), llvm::EVT::isScalableVector(), llvm::EVT::isVector(), N, NewSDValueDbgMsg(), llvm::None, and llvm::ISD::TargetConstantFP.
Create a ConstantFPSDNode wrapping a constant value.
If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal). The forms that take a double should only be used for simple constants that can be exactly represented in VT. No checks are made.
Definition at line 1628 of file SelectionDAG.cpp.
References llvm::lltok::APFloat, llvm::MVT::bf16, llvm::APFloat::convert(), DL, EVTToAPFloatSemantics(), llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::EVT::getScalarType(), llvm_unreachable, llvm::MVT::ppcf128, and llvm::APFloatBase::rmNearestTiesToEven.
Referenced by combineBitcast(), combineFneg(), combineFP_ROUND(), combineVSelectWithAllOnesOrZeros(), EltsFromConsecutiveLoads(), expandExp(), expandFP_TO_UINT_SSE(), llvm::TargetLowering::expandIS_FPCLASS(), expandLog(), ExpandPowI(), foldConstantFPMath(), getConstantFP(), getConstVector(), getF32Constant(), getMemsetStringVal(), getMemsetValue(), llvm::TargetLowering::getNegatedExpression(), getNeutralElement(), getNode(), getRVVFPReductionOpAndOperands(), getShuffleScalarElt(), llvm::TargetLowering::getSqrtInputTest(), llvm::TargetLowering::getSqrtResultForDenormInput(), getTargetConstantFP(), llvm::SelectionDAGBuilder::getValueImpl(), getZeroVector(), LowerFABSorFNEG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), LowerFCOPYSIGN(), llvm::AMDGPUTargetLowering::lowerFEXP(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::AMDGPUTargetLowering::LowerFLOG(), LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND(), lowerFROUND(), LowerFROUND(), lowerFTRUNC_FCEIL_FFLOOR(), lowerShuffleAsBitMask(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i32(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), llvm::AMDGPUTargetLowering::performRcpCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::SimplifyDemandedBits(), and simplifyFPBinop().
SDValue SelectionDAG::getConstantPool | ( | const Constant * | C, |
EVT | VT, | ||
MaybeAlign | Align = None , |
||
int | Offs = 0 , |
||
bool | isT = false , |
||
unsigned | TargetFlags = 0 |
||
) |
Definition at line 1713 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::ISD::ConstantPool, E, llvm::DataLayout::getABITypeAlign(), getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), getVTList(), N, NewSDValueDbgMsg(), llvm::None, shouldOptForSize(), and llvm::ISD::TargetConstantPool.
Referenced by combineTargetShuffle(), getAddressForMemoryInput(), getTargetConstantPool(), lowerBuildVectorAsBroadcast(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), selectImmWithConstantPool(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle().
SDValue SelectionDAG::getConstantPool | ( | MachineConstantPoolValue * | C, |
EVT | VT, | ||
MaybeAlign | Align = None , |
||
int | Offs = 0 , |
||
bool | isT = false , |
||
unsigned | TargetFlags = 0 |
||
) |
Definition at line 1742 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::ISD::ConstantPool, E, getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), getVTList(), N, llvm::None, and llvm::ISD::TargetConstantPool.
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Definition at line 459 of file SelectionDAG.h.
References Context.
Referenced by AddCombineVUZPToVPADDL(), llvm::RegsForValue::AddInlineAsmOperands(), addShuffleForVecExtend(), adjustLoadValueTypeImpl(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canFoldInAddressingMode(), CollectOpsToWiden(), combineAnd(), combineArithReduction(), combineBasicSADPattern(), combineBitcastToBoolVector(), combineBitcastvxi1(), combineConcatVectorOfCasts(), combineConcatVectorOfScalars(), combineConcatVectorOps(), combineExtractVectorElt(), combineFMinNumFMaxNum(), combineFP_EXTEND(), combineFP_ROUND(), combineLoad(), combineMinNumMaxNum(), combineMulToPMADDWD(), combineOr(), combinePMULH(), combinePredicateReduction(), combineSelect(), combineShiftAnd1ToBitTest(), combineShiftToAVG(), combineShuffleToVectorExtend(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineToExtendBoolVectorInReg(), combineToFPTruncExtElt(), combineTruncateWithSat(), combineUIntToFP(), CombineVMOVDRRCandidateWithVecOp(), combineVPDPBUSDPattern(), combineVSelectWithAllOnesOrZeros(), combinevXi1ConstantToInteger(), concatSubVectors(), constructRetValue(), convertIntLogicToFPLogic(), CreateStackTemporary(), detectAVGPattern(), detectPMADDUBSW(), earlyExpandDIVFIX(), EltsFromConsecutiveLoads(), llvm::SelectionDAGBuilder::EmitBranchForMergedCondition(), emitNonHSAIntrinsicError(), emitRemovedIntrinsicError(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), errorUnsupported(), expandDivFix(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandIS_FPCLASS(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), extractSubVector(), fail(), findMemType(), FoldConstantArithmetic(), foldShuffleOfConcatUndefs(), foldXorTruncShiftIntoCmp(), getConstant(), getConstantFP(), getCopyFromParts(), getCopyFromPartsVector(), llvm::SelectionDAGBuilder::getCopyFromRegs(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::RegsForValue::getCopyToRegs(), GetDependentSplitDestVTs(), getEVTAlign(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), getMemsetStringVal(), getMemsetValue(), getPrefTypeAlign(), getPTest(), getReducedAlign(), getRegistersForValue(), getSplatValue(), llvm::AMDGPUTargetLowering::getSplitDestVTs(), GetSplitDestVTs(), llvm::TargetLowering::getSqrtInputTest(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::TargetLowering::getVectorElementPointer(), llvm::VECustomDAG::getVectorVT(), llvm::TargetLowering::IncrementMemoryAddress(), llvm::SelectionDAGBuilder::init(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), LowerADDSAT_SUBSAT(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), LowerAsSplatVectorLoad(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), lowerBuildVectorAsBroadcast(), llvm::VETargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), llvm::SelectionDAGBuilder::LowerCallSiteWithDeoptBundleImpl(), LowerCONCAT_VECTORS_i1(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), llvm::AMDGPUTargetLowering::LowerFCEIL(), lowerFCMPIntrinsic(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), lowerICMPIntrinsic(), LowerMSCATTER(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), LowerPredicateLoad(), LowerPredicateStore(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::SelectionDAGBuilder::LowerStatepoint(), LowerStore(), LowerSVEIntrinsicEXT(), llvm::TargetLowering::LowerToTLSEmulatedModel(), LowerToTLSExecModel(), llvm::VETargetLowering::lowerToVVP(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), LowerVECTOR_SHUFFLE(), LowerVectorAllZero(), LowerVectorExtend(), LowerVSETCC(), matchBinOpReduction(), matchPMADDWD(), matchPMADDWD_2(), narrowExtractedVectorBinOp(), PerformARMBUILD_VECTORCombine(), PerformBUILD_VECTORCombine(), performConcatVectorsCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformExtractFpToIntStores(), PerformInsertEltCombine(), performIntrinsicCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformMinMaxFpToSatCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), performSelectCombine(), performSignExtendInRegCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformSplittingToWideningLoad(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformSTORECombine(), performSunpkloCombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), PerformUMinFpToSatCombine(), llvm::TargetLoweringBase::promoteTargetBoolean(), promoteToConstantPool(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceVMULWidth(), ReplaceLoadVector(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::SITargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), selectImmWithConstantPool(), llvm::TargetLowering::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::TargetLowering::SimplifySetCC(), llvm::TargetLowering::softenSetCCOperands(), splitStores(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::X86TargetLowering::targetShrinkDemandedConstant(), truncateVectorWithNARROW(), truncateVectorWithPACK(), tryFormConcatFromShuffle(), UnrollVectorOp(), UnrollVectorOverflowOp(), llvm::TargetLowering::verifyReturnAddressArgumentIsConstant(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSwitchCase(), llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), widenVec(), and WidenVector().
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Definition at line 773 of file SelectionDAG.h.
References llvm::ISD::CopyFromReg, getNode(), getRegister(), getVTList(), and llvm::MVT::Other.
Referenced by llvm::AMDGPUTargetLowering::CreateLiveInRegister(), expandIntrinsicWChainHelper(), llvm::RegsForValue::getCopyFromRegs(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getFRAMEADDR(), getReadTimeStampCounter(), GetTLSADDR(), getv64i1Argument(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), lowerBALLOTIntrinsic(), llvm::VETargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), lowerCallResult(), LowerCallResult(), LowerCMP_SWAP(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), performDivRemCombine(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceZeroVectorStore(), R600DAGToDAGISel::SelectADDRVTX_READ(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::AMDGPUTargetLowering::storeStackInputValue(), unpack64(), unpackF64OnRV32DSoftABI(), unpackFromRegLoc(), llvm::SelectionDAGBuilder::visitBitTestCase(), and llvm::SelectionDAGBuilder::visitJumpTable().
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Definition at line 782 of file SelectionDAG.h.
References llvm::ISD::CopyFromReg, llvm::SDValue::getNode(), getNode(), getRegister(), getVTList(), llvm::MVT::Glue, llvm::makeArrayRef(), and llvm::MVT::Other.
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Definition at line 765 of file SelectionDAG.h.
References llvm::ISD::CopyToReg, llvm::SDValue::getNode(), getNode(), getVTList(), llvm::MVT::Glue, llvm::makeArrayRef(), N, and llvm::MVT::Other.
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Definition at line 747 of file SelectionDAG.h.
References llvm::ISD::CopyToReg, getNode(), getRegister(), N, and llvm::MVT::Other.
Referenced by emitRepmovs(), expandIntrinsicWChainHelper(), llvm::RegsForValue::getCopyToRegs(), llvm::MipsTargetLowering::getOpndList(), llvm::VETargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerCallResult(), LowerCMP_SWAP(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerSETCCCARRY(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSLocalDynamicModel(), llvm::ARMTargetLowering::PerformCMOVCombine(), prepareDescriptorIndirectCall(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::SelectionDAGBuilder::visitBitTestHeader(), and llvm::SelectionDAGBuilder::visitJumpTableHeader().
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Definition at line 756 of file SelectionDAG.h.
References llvm::ISD::CopyToReg, llvm::SDValue::getNode(), getNode(), getRegister(), getVTList(), llvm::MVT::Glue, llvm::makeArrayRef(), N, and llvm::MVT::Other.
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Definition at line 452 of file SelectionDAG.h.
References llvm::MachineFunction::getDataLayout().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), addShuffleForVecExtend(), analyzeCallOperands(), llvm::SparcTargetLowering::bitcastConstantFPToInt(), BuildExactSDIV(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canFoldInAddressingMode(), combineBVOfVecSExt(), combineConcatVectorOps(), combineFMinNumFMaxNum(), combineGatherScatter(), combineLoad(), combinePredicateReduction(), combineShiftAnd1ToBitTest(), combineShuffleToVectorExtend(), combineStore(), combineTargetShuffle(), combineTruncationShuffle(), combineVSelectWithAllOnesOrZeros(), computeKnownBits(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), ComputeNumSignBits(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), createGPRPairNode(), createMMXBuildVector(), CreateStackTemporary(), EltsFromConsecutiveLoads(), llvm::X86TargetLowering::emitStackGuardXorFP(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::TargetLowering::expandABS(), llvm::TargetLowering::expandBITREVERSE(), llvm::TargetLowering::expandBSWAP(), expandDivFix(), llvm::TargetLowering::expandFixedPointDiv(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), FoldConstantArithmetic(), foldXorTruncShiftIntoCmp(), llvm::RISCVTargetLowering::getAddr(), getAddressForMemoryInput(), getAVX2GatherNode(), getConstant(), getConstantPool(), getCopyFromParts(), llvm::SelectionDAGBuilder::getCopyFromRegs(), getCopyToParts(), getEVTAlign(), GetExponent(), llvm::SelectionDAGBuilder::getFrameIndexTy(), getGatherNode(), getGlobalAddress(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), getIntPtrConstant(), getLifetimeNode(), getLimitedPrecisionExp2(), getLoadStackGuard(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), getMemsetStringVal(), getNode(), llvm::VETargetLowering::getPICJumpTableRelocBase(), llvm::M68kTargetLowering::getPICJumpTableRelocBase(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), llvm::PPCTargetLowering::getPICJumpTableRelocBase(), llvm::TargetLowering::getPICJumpTableRelocBase(), getPPCf128HiElementSelector(), getPrefetchNode(), getPrefTypeAlign(), getReducedAlign(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), getScatterNode(), getShiftAmountConstant(), getShiftAmountOperand(), llvm::PPC::getSplatIdxForPPCMnemonics(), llvm::TargetLowering::getSqrtInputTest(), getSymbolFunctionGlobalAddress(), getTagSymNode(), getUniformBase(), llvm::SelectionDAGBuilder::getValueImpl(), getVectorIdxConstant(), llvm::SelectionDAGBuilder::handleDebugValue(), InferPtrAlign(), llvm::SelectionDAGBuilder::init(), isBLACompatibleAddress(), isExtendedBUILD_VECTOR(), llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(), llvm::TargetLoweringBase::isLoadBitCastBeneficial(), IsPredicateKnownToFail(), isVMOVModifiedImm(), llvm::PPC::isVMRGEOShuffleMask(), llvm::PPC::isVMRGHShuffleMask(), llvm::PPC::isVMRGLShuffleMask(), llvm::PPC::isVPKUDUMShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), llvm::PPC::isVSLDOIShuffleMask(), LowerADDSAT_SUBSAT(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), llvm::HexagonTargetLowering::LowerBlockAddress(), lowerBuildVectorAsBroadcast(), llvm::VETargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::TargetLowering::LowerCallTo(), llvm::LanaiTargetLowering::LowerConstantPool(), LowerCTPOP(), llvm::SelectionDAGBuilder::LowerDeoptimizeCall(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), LowerF64Op(), llvm::AMDGPUTargetLowering::LowerFCEIL(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFNEGorFABS(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(), llvm::LanaiTargetLowering::LowerGlobalAddress(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::HexagonTargetLowering::LowerGLOBALADDRESS(), llvm::NVPTXTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::LanaiTargetLowering::LowerJumpTable(), LowerMemOpCallTo(), LowerMULO(), llvm::R600TargetLowering::LowerOperation(), LowerPredicateLoad(), LowerPredicateStore(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), LowerRETURNADDR(), llvm::SelectionDAGBuilder::LowerStatepoint(), LowerSTORE(), llvm::TargetLowering::LowerToTLSEmulatedModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), llvm::SparcTargetLowering::makeAddress(), narrowExtractedVectorLoad(), PerformBITCASTCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performMULCombine(), PerformSTORECombine(), llvm::AMDGPUTargetLowering::performTruncateCombine(), PerformTruncatingStoreCombine(), PerformVMOVRRDCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::TargetLoweringBase::promoteTargetBoolean(), promoteToConstantPool(), recoverFramePointer(), ReplaceCMP_SWAP_128Results(), ReplaceCMP_SWAP_64Results(), ReplaceLoadVector(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::AVRDAGToDAGISel::selectIndexedLoad(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::PPCTargetLowering::SelectOptimalAddrMode(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::TargetLowering::SimplifySetCC(), SkipExtensionForVMULL(), llvm::TargetLowering::softenSetCCOperands(), transformCallee(), unpackFromMemLoc(), UnrollVectorOverflowOp(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), and llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad().
SDDbgLabel * SelectionDAG::getDbgLabel | ( | DILabel * | Label, |
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a SDDbgLabel node.
Definition at line 9890 of file SelectionDAG.cpp.
References assert(), DL, llvm::SDDbgInfo::getAlloc(), and llvm::RISCVFenceField::O.
SDDbgValue * SelectionDAG::getDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
SDNode * | N, | ||
unsigned | R, | ||
bool | IsIndirect, | ||
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a SDDbgValue node.
getDbgValue - Creates a SDDbgValue node.
Definition at line 9670 of file SelectionDAG.cpp.
References assert(), DL, llvm::SDDbgOperand::fromNode(), llvm::SDDbgInfo::getAlloc(), N, and llvm::RISCVFenceField::O.
SDDbgValue * SelectionDAG::getDbgValueList | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
ArrayRef< SDDbgOperand > | Locs, | ||
ArrayRef< SDNode * > | Dependencies, | ||
bool | IsIndirect, | ||
const DebugLoc & | DL, | ||
unsigned | O, | ||
bool | IsVariadic | ||
) |
Creates a SDDbgValue node from a list of locations.
Definition at line 9732 of file SelectionDAG.cpp.
References assert(), DL, llvm::SDDbgInfo::getAlloc(), and llvm::RISCVFenceField::O.
Referenced by llvm::SelectionDAGBuilder::addDanglingDebugInfo(), llvm::SelectionDAGBuilder::handleDebugValue(), salvageDebugInfo(), and transferDbgValues().
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inline |
Get the debug values which reference the given SDNode.
Definition at line 1778 of file SelectionDAG.h.
References llvm::SDDbgInfo::getSDDbgValues().
Referenced by ProcessSDDbgValues(), salvageDebugInfo(), and transferDbgValues().
See if the specified operand can be simplified with the knowledge that only the bits specified by DemandedBits are used.
If so, return the simpler operand, otherwise return a null SDValue.
(This exists alongside SimplifyDemandedBits because GetDemandedBits can simplify nodes with multiple uses more aggressively.)
TODO: really we should be making this into the DAG equivalent of SimplifyMultipleUseDemandedBits and not generate any new nodes.
Definition at line 2466 of file SelectionDAG.cpp.
References llvm::APInt::getAllOnes(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::isScalableVector(), and llvm::EVT::isVector().
Referenced by GetDemandedBits().
SDValue SelectionDAG::GetDemandedBits | ( | SDValue | V, |
const APInt & | DemandedBits, | ||
const APInt & | DemandedElts | ||
) |
See if the specified operand can be simplified with the knowledge that only the bits specified by DemandedBits are used in the elements specified by DemandedElts.
If so, return the simpler operand, otherwise return a null SDValue.
(This exists alongside SimplifyDemandedBits because GetDemandedBits can simplify nodes with multiple uses more aggressively.)
TODO: really we should be making this into the DAG equivalent of SimplifyMultipleUseDemandedBits and not generate any new nodes.
Definition at line 2483 of file SelectionDAG.cpp.
References llvm::ISD::Constant, getConstant(), GetDemandedBits(), llvm::SDValue::getNode(), getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), and llvm::ISD::SRL.
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inline |
Return the current function's default denormal handling kind for the given floating point type.
Definition at line 2187 of file SelectionDAG.h.
References EVTToAPFloatSemantics(), and llvm::MachineFunction::getDenormalMode().
std::pair< EVT, EVT > SelectionDAG::GetDependentSplitDestVTs | ( | const EVT & | VT, |
const EVT & | EnvVT, | ||
bool * | HiIsEmpty | ||
) | const |
Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces.
GetDependentSplitDestVTs - Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces.
Sets the HisIsEmpty flag when hi type has zero storage size.
Sets the HiIsEmpty flag when hi type has zero storage size.
Definition at line 11132 of file SelectionDAG.cpp.
References assert(), getContext(), llvm::LinearPolySize< LeafTy >::getKnownMinValue(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), and llvm::LinearPolySize< LeafTy >::isScalable().
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inline |
Definition at line 458 of file SelectionDAG.h.
References llvm::M68kBeads::DA.
Referenced by llvm::FunctionLoweringInfo::set().
Definition at line 2090 of file SelectionDAG.cpp.
References llvm::ISD::EH_LABEL, and getLabelNode().
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inline |
Return the token chain corresponding to the entry of the function.
Definition at line 528 of file SelectionDAG.h.
Referenced by llvm::AMDGPUTargetLowering::addTokenForArgument(), clear(), combineTargetShuffle(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::AMDGPUTargetLowering::CreateLiveInRegisterRaw(), ExpandExtIntRes_DIVREM(), llvm::MipsTargetLowering::getAddrLocal(), llvm::SelectionDAGBuilder::getCopyFromRegs(), getFLUSHW(), getFRAMEADDR(), getStackArgumentTokenFactor(), llvm::SelectionDAGBuilder::getValueImpl(), HandleMergeInputChains(), llvm::AMDGPUTargetLowering::loadStackInputValue(), lowerBALLOTIntrinsic(), lowerBuildVectorAsBroadcast(), llvm::SparcTargetLowering::LowerF128Compare(), llvm::SparcTargetLowering::LowerF128Op(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), lowerRETURNADDR(), LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCCARRY(), llvm::SelectionDAGBuilder::LowerStatepoint(), LowerToTLSExecModel(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSGeneralDynamicModel64(), LowerToTLSGeneralDynamicModelX32(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerToTLSLocalDynamicModel(), llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), llvm::TargetLowering::makeLibCall(), llvm::ARMTargetLowering::PerformCMOVCombine(), performDivRemCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), replaceZeroVectorStore(), R600DAGToDAGISel::SelectADDRVTX_READ(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectFrameIndex(), selectImmWithConstantPool(), llvm::RISCVDAGToDAGISel::selectShiftMask(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
Compute the default alignment value for the given type.
Definition at line 1222 of file SelectionDAG.cpp.
References llvm::PointerType::get(), llvm::DataLayout::getABITypeAlign(), getContext(), getDataLayout(), llvm::Type::getInt8Ty(), llvm::EVT::getTypeForEVT(), and llvm::MVT::iPTR.
Referenced by getEVTAlignment(), getLoad(), getLoadVP(), getMemIntrinsicNode(), getStore(), getStridedLoadVP(), and getTruncStore().
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inline |
Compute the default alignment value for the given type.
FIXME: Remove once transition to Align is over.
Definition at line 2138 of file SelectionDAG.h.
References getEVTAlign(), and llvm::Align::value().
Definition at line 1812 of file SelectionDAG.cpp.
References N.
Referenced by llvm::SelectionDAGBuilder::LowerDeoptimizeCall(), llvm::SparcTargetLowering::LowerF128Compare(), and llvm::SparcTargetLowering::LowerF128Op().
SDValue SelectionDAG::getExtLoad | ( | ISD::LoadExtType | ExtType, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 7734 of file SelectionDAG.cpp.
References getLoad(), getUNDEF(), llvm::SDValue::getValueType(), llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getExtLoad | ( | ISD::LoadExtType | ExtType, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
MaybeAlign | Alignment = MaybeAlign() , |
||
MachineMemOperand::Flags | MMOFlags = MachineMemOperand::MONone , |
||
const AAMDNodes & | AAInfo = AAMDNodes() |
||
) |
Definition at line 7723 of file SelectionDAG.cpp.
References getLoad(), getUNDEF(), llvm::SDValue::getValueType(), llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
Referenced by adjustSubwordCmp(), combineEXTEND_VECTOR_INREG(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), getExtLoad(), getMemcpyLoadsAndStores(), LowerPredicateLoad(), lowerVECTOR_SHUFFLE(), performFPExtendCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), PerformVMOVrhCombine(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::TargetLowering::scalarizeVectorLoad(), SkipLoadExtensionForVMULL(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), tryToFoldExtOfExtload(), tryToFoldExtOfLoad(), unpackFromMemLoc(), and llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad().
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inline |
FIXME: Remove once transition to Align is over.
Definition at line 1233 of file SelectionDAG.h.
References getExtLoad().
SDValue SelectionDAG::getExtLoadVP | ( | ISD::LoadExtType | ExtType, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding = false |
||
) |
Definition at line 7996 of file SelectionDAG.cpp.
References getLoadVP(), getUNDEF(), llvm::SDValue::getValueType(), llvm::BitmaskEnumDetail::Mask(), llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getExtLoadVP | ( | ISD::LoadExtType | ExtType, |
const SDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
MaybeAlign | Alignment, | ||
MachineMemOperand::Flags | MMOFlags, | ||
const AAMDNodes & | AAInfo, | ||
bool | IsExpanding = false |
||
) |
Definition at line 7983 of file SelectionDAG.cpp.
References getLoadVP(), getUNDEF(), llvm::SDValue::getValueType(), llvm::BitmaskEnumDetail::Mask(), llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getExtStridedLoadVP | ( | ISD::LoadExtType | ExtType, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Stride, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding = false |
||
) |
Definition at line 8247 of file SelectionDAG.cpp.
References DL, getStridedLoadVP(), getUNDEF(), llvm::SDValue::getValueType(), llvm::BitmaskEnumDetail::Mask(), llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getExtStridedLoadVP | ( | ISD::LoadExtType | ExtType, |
const SDLoc & | DL, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Stride, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
MaybeAlign | Alignment, | ||
MachineMemOperand::Flags | MMOFlags, | ||
const AAMDNodes & | AAInfo, | ||
bool | IsExpanding = false |
||
) |
Definition at line 8235 of file SelectionDAG.cpp.
References DL, getStridedLoadVP(), getUNDEF(), llvm::SDValue::getValueType(), llvm::BitmaskEnumDetail::Mask(), llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
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inline |
Definition at line 464 of file SelectionDAG.h.
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by truncation).
Definition at line 1341 of file SelectionDAG.cpp.
References llvm::EVT::bitsGT(), DL, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, getIntPtrConstant(), and getNode().
Referenced by getCopyFromPartsVector(), llvm::RISCVTargetLowering::LowerOperation(), LowerUINT_TO_FP_i32(), and llvm::RISCVTargetLowering::PerformDAGCombine().
Definition at line 1679 of file SelectionDAG.cpp.
References AddNodeIDNode(), E, llvm::ISD::FrameIndex, getVTList(), N, llvm::None, and llvm::ISD::TargetFrameIndex.
Referenced by llvm::X86TargetLowering::BuildFILD(), CalculateTailCallArgDest(), CreateStackTemporary(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), getAddressForMemoryInput(), getLifetimeNode(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), getTargetFrameIndex(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::AMDGPUTargetLowering::loadStackInputValue(), llvm::SITargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::TargetLowering::LowerCallTo(), llvm::VETargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), unpack64(), unpackF64OnRV32DSoftABI(), unpackFromMemLoc(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
SDDbgValue * SelectionDAG::getFrameIndexDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
unsigned | FI, | ||
ArrayRef< SDNode * > | Dependencies, | ||
bool | IsIndirect, | ||
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a FrameIndex SDDbgValue node.
FrameIndex with dependencies.
Definition at line 9706 of file SelectionDAG.cpp.
References assert(), DL, llvm::SDDbgOperand::fromFrameIdx(), llvm::SDDbgInfo::getAlloc(), and llvm::RISCVFenceField::O.
SDDbgValue * SelectionDAG::getFrameIndexDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
unsigned | FI, | ||
bool | IsIndirect, | ||
const DebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a FrameIndex SDDbgValue node.
FrameIndex.
Definition at line 9695 of file SelectionDAG.cpp.
References assert(), DL, and llvm::RISCVFenceField::O.
Return a freeze using the SDLoc of the value operand.
Definition at line 2192 of file SelectionDAG.cpp.
References llvm::ISD::FREEZE, getNode(), and llvm::SDValue::getValueType().
Referenced by foldSelectWithIdentityConstant(), lowerFROUND(), lowerFTRUNC_FCEIL_FFLOOR(), lowerVECTOR_SHUFFLE(), performSIGN_EXTEND_INREGCombine(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
SDValue SelectionDAG::getGatherVP | ( | SDVTList | VTs, |
EVT | VT, | ||
const SDLoc & | dl, | ||
ArrayRef< SDValue > | Ops, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexType | IndexType | ||
) |
Definition at line 8410 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::LinearPolySize< ElementCount >::isKnownGE(), N, NewSDValueDbgMsg(), and llvm::ArrayRef< T >::size().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
Definition at line 981 of file SelectionDAG.h.
References getNode(), and llvm::ISD::GLOBAL_OFFSET_TABLE.
Referenced by llvm::TargetLowering::getPICJumpTableRelocBase(), and llvm::HexagonTargetLowering::LowerGLOBALADDRESS().
SDValue SelectionDAG::getGlobalAddress | ( | const GlobalValue * | GV, |
const SDLoc & | DL, | ||
EVT | VT, | ||
int64_t | offset = 0 , |
||
bool | isTargetGA = false , |
||
unsigned | TargetFlags = 0 |
||
) |
Definition at line 1646 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::BitWidth, DL, E, getDataLayout(), llvm::DataLayout::getPointerTypeSizeInBits(), llvm::GlobalValue::getType(), getVTList(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::GlobalValue::isThreadLocal(), N, llvm::None, llvm::SignExtend64(), llvm::ISD::TargetGlobalAddress, and llvm::ISD::TargetGlobalTLSAddress.
Referenced by FoldSymbolOffset(), llvm::VETargetLowering::getPICJumpTableRelocBase(), getSymbolFunctionGlobalAddress(), getTargetGlobalAddress(), llvm::SelectionDAGBuilder::getValueImpl(), and performGlobalAddressCombine().
Get graph attributes for a node.
getGraphAttrs - Get graph attributes for a node.
(eg. "color=red".) Used from getNodeAttributes.
Definition at line 203 of file SelectionDAGPrinter.cpp.
References llvm::errs(), I, and N.
Referenced by llvm::DOTGraphTraits< SelectionDAG * >::getNodeAttributes().
Return HeapAllocSite associated with Node, or nullptr if none exists.
Definition at line 2170 of file SelectionDAG.h.
References llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find(), and I.
SDValue SelectionDAG::getIndexedLoad | ( | SDValue | OrigLoad, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 7742 of file SelectionDAG.cpp.
References assert(), llvm::sampleprof::Base, getLoad(), llvm::SDValue::getValueType(), llvm::ARM_MB::LD, llvm::MachineMemOperand::MODereferenceable, and llvm::MachineMemOperand::MOInvariant.
SDValue SelectionDAG::getIndexedLoadVP | ( | SDValue | OrigLoad, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 8005 of file SelectionDAG.cpp.
References assert(), llvm::sampleprof::Base, getLoadVP(), llvm::SDValue::getValueType(), llvm::ARM_MB::LD, llvm::MachineMemOperand::MODereferenceable, and llvm::MachineMemOperand::MOInvariant.
SDValue SelectionDAG::getIndexedMaskedLoad | ( | SDValue | OrigLoad, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 8532 of file SelectionDAG.cpp.
References assert(), llvm::sampleprof::Base, getMaskedLoad(), llvm::SDValue::getValueType(), and llvm::ARM_MB::LD.
SDValue SelectionDAG::getIndexedMaskedStore | ( | SDValue | OrigStore, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 8581 of file SelectionDAG.cpp.
References assert(), llvm::sampleprof::Base, getMaskedStore(), and llvm::ARM_MB::ST.
SDValue SelectionDAG::getIndexedStore | ( | SDValue | OrigStore, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 7875 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::sampleprof::Base, E, llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getVTList(), N, NewSDValueDbgMsg(), llvm::MVT::Other, llvm::ARM_MB::ST, and llvm::ISD::STORE.
Referenced by llvm::HexagonTargetLowering::LowerStore().
SDValue SelectionDAG::getIndexedStoreVP | ( | SDValue | OrigStore, |
const SDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 8127 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::sampleprof::Base, E, llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getVTList(), N, NewSDValueDbgMsg(), llvm::MVT::Other, and llvm::ARM_MB::ST.
SDValue SelectionDAG::getIndexedStridedLoadVP | ( | SDValue | OrigLoad, |
const SDLoc & | DL, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 8256 of file SelectionDAG.cpp.
References assert(), llvm::sampleprof::Base, DL, getStridedLoadVP(), llvm::SDValue::getValueType(), llvm::MachineMemOperand::MODereferenceable, and llvm::MachineMemOperand::MOInvariant.
SDValue SelectionDAG::getIndexedStridedStoreVP | ( | SDValue | OrigStore, |
const SDLoc & | DL, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line 8378 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::sampleprof::Base, DL, E, getVTList(), N, NewSDValueDbgMsg(), and llvm::MVT::Other.
Definition at line 1572 of file SelectionDAG.cpp.
References DL, getConstant(), getDataLayout(), and llvm::TargetLoweringBase::getPointerTy().
Referenced by buildCallOperands(), buildFromShuffleMostly(), combineArithReduction(), combineBitcast(), combineBitcastToBoolVector(), combineBVZEXTLOAD(), combineCompareEqual(), combineConcatVectorOps(), combineFP16_TO_FP(), combineFP_EXTEND(), combineFP_ROUND(), combineINSERT_SUBVECTOR(), combineMinMaxReduction(), combineSelect(), combineTargetShuffle(), combineTruncateWithSat(), CompactSwizzlableVector(), CreateCopyOfByValArgument(), detectAVGPattern(), EltsFromConsecutiveLoads(), emitConstantSizeRepmov(), emitRepmovsB(), ExtendToType(), ExtractBitFromMaskVector(), extractSubVector(), getCALLSEQ_START(), getCopyToParts(), getFPExtendOrRound(), getFRAMEADDR(), getMaskNode(), getParamsForOneTrueMaskedElt(), getScalarMaskingNode(), getShuffleHalfVectors(), getStrictFPExtendOrRound(), insert1BitVector(), insertSubVector(), lower1BitShuffle(), lower1BitShuffleAsKSHIFTR(), lowerAddSubToHorizontalOp(), LowerAVXCONCAT_VECTORS(), LowerBITCAST(), LowerBITREVERSE_XOP(), LowerBUILD_VECTORvXi1(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), llvm::VETargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS_i1(), LowerCONCAT_VECTORSvXi1(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::HexagonTargetLowering::LowerEH_RETURN(), LowerEXTRACT_SUBVECTOR(), LowerFABSorFNEG(), LowerFCOPYSIGN(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), LowerFP16_TO_FP(), LowerFP_TO_FP16(), lowerFPToIntToFP(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), lowerI128ToGR128(), LowerI64IntToFP16(), LowerI64IntToFP_AVX512DQ(), lowerINT_TO_FP_vXi64(), LowerLoad(), lowerMasksToReg(), LowerMGATHER(), LowerMLOAD(), llvm::RISCVTargetLowering::LowerOperation(), llvm::LanaiTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerSDIV(), lowerShuffleAsVTRUNCAndUnpack(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), llvm::SelectionDAGBuilder::LowerStatepoint(), LowerStore(), LowerToTLSExecModel(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerUINT_TO_FP_i32(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), LowerUMULO_SMULO(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), llvm::HexagonTargetLowering::LowerVACOPY(), LowerVACOPY(), llvm::VETargetLowering::lowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), LowerZERO_EXTEND_Mask(), matchPMADDWD_2(), llvm::PPCTargetLowering::PerformDAGCombine(), performFPExtendCombine(), performMADD_MSUBCombine(), PerformTruncatingStoreCombine(), prepareDescriptorIndirectCall(), PrepareTailCall(), ReorganizeVector(), ReplaceLoadVector(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), SplitAndExtendv16i1(), vectorizeExtractedCast(), and widenSubVector().
SDValue SelectionDAG::getJumpTable | ( | int | JTI, |
EVT | VT, | ||
bool | isTarget = false , |
||
unsigned | TargetFlags = 0 |
||
) |
Definition at line 1694 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), E, getVTList(), llvm::ISD::JumpTable, N, llvm::None, and llvm::ISD::TargetJumpTable.
Referenced by getTargetJumpTable(), and llvm::SelectionDAGBuilder::visitJumpTable().
SDValue SelectionDAG::getLabelNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
SDValue | Root, | ||
MCSymbol * | Label | ||
) |
Definition at line 2095 of file SelectionDAG.cpp.
References AddNodeIDNode(), E, llvm::SDLoc::getDebugLoc(), llvm::SDLoc::getIROrder(), getVTList(), N, and llvm::MVT::Other.
Referenced by getEHLabel().
|
inline |
Definition at line 456 of file SelectionDAG.h.
SDValue SelectionDAG::getLifetimeNode | ( | bool | IsStart, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
int | FrameIndex, | ||
int64_t | Size, | ||
int64_t | Offset = -1 |
||
) |
Creates a LifetimeSDNode that starts (IsStart==true
) or ends (IsStart==false
) the lifetime of the portion of FrameIndex
between offsets Offset
and Offset + Size
.
Definition at line 7539 of file SelectionDAG.cpp.
References AddNodeIDNode(), E, llvm::ISD::FrameIndex, getDataLayout(), llvm::SDLoc::getDebugLoc(), getFrameIndex(), llvm::SDLoc::getIROrder(), getTargetLoweringInfo(), getVTList(), llvm::ISD::LIFETIME_END, llvm::ISD::LIFETIME_START, N, NewSDValueDbgMsg(), and llvm::MVT::Other.
SDValue SelectionDAG::getLoad | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 7716 of file SelectionDAG.cpp.
References getLoad(), getUNDEF(), llvm::SDValue::getValueType(), llvm::ISD::NON_EXTLOAD, llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoad | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
MaybeAlign | Alignment = MaybeAlign() , |
||
MachineMemOperand::Flags | MMOFlags = MachineMemOperand::MONone , |
||
const AAMDNodes & | AAInfo = AAMDNodes() , |
||
const MDNode * | Ranges = nullptr |
||
) |
Loads are not normal binary operators: their result type is not determined by their operands, and they produce a value AND a token chain.
This function will set the MOLoad flag on MMOFlags, but you can set it if you want. The MOStore flag must not be set.
Definition at line 7706 of file SelectionDAG.cpp.
References getUNDEF(), llvm::SDValue::getValueType(), llvm::ISD::NON_EXTLOAD, llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
Referenced by bitcastf32Toi32(), llvm::X86TargetLowering::BuildFILD(), combineBVOfConsecutiveLoads(), combineExtractVectorElt(), combineExtractWithShuffle(), combineLoad(), combineMaskedLoadConstantMask(), combineMOVDQ2Q(), combineStore(), combineTargetShuffle(), EltsFromConsecutiveLoads(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), expandf64Toi32(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::MipsTargetLowering::getAddrGlobal(), llvm::MipsTargetLowering::getAddrGlobalLargeGOT(), llvm::MipsTargetLowering::getAddrLocal(), getExtLoad(), getFRAMEADDR(), getIndexedLoad(), getLoad(), getMemmoveLoadsAndStores(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerAsSplatVectorLoad(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallResult(), LowerF128Load(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerLoad(), LowerLoad(), lowerLoadF128(), lowerMSALoadIntr(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), lowerRETURNADDR(), LowerRETURNADDR(), lowerShuffleAsBroadcast(), LowerToTLSExecModel(), llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(), LowerUINT_TO_FP_i64(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerVECTOR_SHUFFLE(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), narrowExtractedVectorLoad(), performConcatVectorsCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performIntToFpCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), PerformSplittingMVEEXTToWideningLoad(), PerformSplittingToWideningLoad(), PerformVMOVhrCombine(), PerformVMOVRRDCombine(), prepareDescriptorIndirectCall(), reduceMaskedLoadToScalarLoad(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), llvm::TargetLowering::SimplifySetCC(), SkipLoadExtensionForVMULL(), unpack64(), unpackF64OnRV32DSoftABI(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
|
inline |
FIXME: Remove once transition to Align is over.
Definition at line 1215 of file SelectionDAG.h.
References getLoad().
SDValue SelectionDAG::getLoad | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line 7656 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), llvm::EVT::bitsLT(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), getVTList(), Indexed, llvm::EVT::isInteger(), llvm::EVT::isVector(), llvm::ISD::LOAD, N, NewSDValueDbgMsg(), llvm::ISD::NON_EXTLOAD, llvm::MVT::Other, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoad | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | MMOFlags = MachineMemOperand::MONone , |
||
const AAMDNodes & | AAInfo = AAMDNodes() , |
||
const MDNode * | Ranges = nullptr |
||
) |
Definition at line 7632 of file SelectionDAG.cpp.
References assert(), getLoad(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::MemoryLocation::getSizeOrUnknown(), llvm::EVT::getStoreSize(), llvm::SDValue::getValueType(), InferPointerInfo(), llvm::PointerUnion< PTs >::isNull(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::MVT::Other, and llvm::MachinePointerInfo::V.
|
inline |
Definition at line 1252 of file SelectionDAG.h.
References getEVTAlign(), getLoad(), and Offset.
|
inline |
SDValue SelectionDAG::getLoadVP | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding = false |
||
) |
Definition at line 7975 of file SelectionDAG.cpp.
References getLoadVP(), getUNDEF(), llvm::SDValue::getValueType(), llvm::BitmaskEnumDetail::Mask(), llvm::ISD::NON_EXTLOAD, llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoadVP | ( | EVT | VT, |
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachinePointerInfo | PtrInfo, | ||
MaybeAlign | Alignment, | ||
MachineMemOperand::Flags | MMOFlags, | ||
const AAMDNodes & | AAInfo, | ||
const MDNode * | Ranges = nullptr , |
||
bool | IsExpanding = false |
||
) |
Definition at line 7962 of file SelectionDAG.cpp.
References getLoadVP(), getUNDEF(), llvm::SDValue::getValueType(), llvm::BitmaskEnumDetail::Mask(), llvm::ISD::NON_EXTLOAD, llvm::RegState::Undef, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoadVP | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding = false |
||
) |
Definition at line 7927 of file SelectionDAG.cpp.
References AddNodeIDNode(), assert(), E, llvm::MachinePointerInfo::getAddrSpace(), llvm::SDLoc::getDebugLoc(), llvm::MachineMemOperand::getFlags(), llvm::SDLoc::getIROrder(), llvm::MachineMemOperand::getPointerInfo(), llvm::EVT::getRawBits(), llvm::SDValue::getValueType(), getVTList(), Indexed, llvm::BitmaskEnumDetail::Mask(), N, NewSDValueDbgMsg(), llvm::MVT::Other, and llvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoadVP | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
const SDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | MMOFlags, | ||
const AAMDNodes & | AAInfo, | ||
const MDNode * | Ranges = nullptr , |
||
bool | IsExpanding = false |
||
) |
Definition at line 7904 of file SelectionDAG.cpp.
References assert(), getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::MemoryLocation::getSizeOrUnknown(), llvm::EVT::getStoreSize(), llvm::SDValue::getValueType(), InferPointerInfo(), llvm::PointerUnion< PTs >::isNull(), llvm::BitmaskEnumDetail::Mask(), llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::MVT::Other, and llvm::MachinePointerInfo::V.
Referenced by getExtLoadVP(), getIndexedLoadVP(), and getLoadVP().
|
inline |
Definition at line 1344 of file SelectionDAG.h.
References getEVTAlign(), getLoadVP(), llvm::BitmaskEnumDetail::Mask(), and Offset.
Create a logical NOT operation as (XOR Val, BooleanOne).
Definition at line 1423 of file SelectionDAG.cpp.
References DL, getBoolConstant(), getNode(), and llvm::ISD::XOR.
Referenced by extractBooleanFlip(), llvm::HexagonTargetLowering::LowerAddSubCarry(), and PerformORCombine_i1().
|
inline |
Definition at line 449 of file SelectionDAG.h.
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), buildCallOperands(), llvm::X86TargetLowering::BuildFILD(), llvm::RISCVTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildSREMPow2(), CalculateTailCallSPDiff(), combineFMA(), combineFMADDSUB(), combineFMinNumFMaxNum(), combineFneg(), combineMul(), combineStore(), combineTargetShuffle(), llvm::BaseIndexOffset::computeAliasing(), computeKnownBits(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::SITargetLowering::denormalsEnabledForType(), EmitCmp(), emitConstantSizeRepmov(), emitLockedStackOp(), llvm::AArch64SelectionDAGInfo::EmitMOPS(), emitNonHSAIntrinsicError(), emitRemovedIntrinsicError(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), EmitTailCallStoreFPAndRetAddr(), EmitTailCallStoreRetAddr(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemmove(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(), EmitUnrolledSetTag(), llvm::BaseIndexOffset::equalBaseIndex(), errorUnsupported(), llvm::X86TargetLowering::expandIndirectJTBranch(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), fail(), llvm::SelectionDAGBuilder::FindMergedConditions(), fixupFuncForFI(), llvm::RISCVTargetLowering::getAddr(), getAddressForMemoryInput(), llvm::MipsTargetLowering::getAddrLocal(), getBROADCAST_LOAD(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getFRAMEADDR(), llvm::MipsTargetLowering::getGlobalReg(), getLoad(), getLoadStackGuard(), getLoadVP(), getMemcpyLoadsAndStores(), getMemIntrinsicNode(), getMemmoveLoadsAndStores(), getMemsetStores(), llvm::MipsTargetLowering::getOpndList(), llvm::VETargetLowering::getPICJumpTableRelocBase(), getRegistersForValue(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), getSPDenormModeValue(), llvm::NVPTXTargetLowering::getSqrtEstimate(), getStore(), getStridedLoadVP(), getTagSymNode(), GetTLSADDR(), getTruncStore(), getTruncStoreVP(), getTruncStridedStoreVP(), getv64i1Argument(), hasReturnsTwiceAttr(), InferPointerInfo(), InferPtrAlign(), isConsecutiveLSLoc(), llvm::HexagonTargetLowering::IsEligibleForTailCallOptimization(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), llvm::SITargetLowering::isFMADLegal(), llvm::SITargetLowering::isFPExtFoldable(), llvm::SITargetLowering::isKnownNeverNaNForTargetNode(), IsWebAssemblyLocal(), llvm::AMDGPUTargetLowering::loadStackInputValue(), LowerAsSplatVectorLoad(), lowerBuildVectorAsBroadcast(), llvm::VETargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCall(), llvm::SITargetLowering::LowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SITargetLowering::LowerCallResult(), llvm::TargetLowering::LowerCallTo(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Op(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_32(), llvm::SparcTargetLowering::LowerFormalArguments_64(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), lowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::HexagonTargetLowering::LowerINLINEASM(), LowerInterruptReturn(), LowerINTRINSIC_W_CHAIN(), llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN(), llvm::R600TargetLowering::LowerOperation(), llvm::SITargetLowering::LowerOperation(), llvm::LoongArchTargetLowering::LowerReturn(), llvm::VETargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SITargetLowering::LowerReturn(), llvm::RISCVTargetLowering::LowerReturn(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), lowerRETURNADDR(), LowerRETURNADDR(), lowerShuffleAsBroadcast(), LowerToTLSExecModel(), llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), LowerToTLSLocalDynamicModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerUINT_TO_FP_i64(), lowerUINT_TO_FP_vXi32(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::AMDGPUTargetLowering::lowerUnhandledCall(), LowerVACOPY(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), llvm::VETargetLowering::lowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), lowerVECTOR_SHUFFLE(), llvm::SparcTargetLowering::makeAddress(), llvm::VETargetLowering::makeAddress(), MarkEHGuard(), MarkEHRegistrationNode(), narrowExtractedVectorLoad(), llvm::SITargetLowering::passSpecialInputs(), PerformADDCombineWithOperands(), performBRCONDCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::ARMTargetLowering::PerformMVEExtCombine(), llvm::ARMTargetLowering::PerformMVETruncCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), promoteToConstantPool(), recoverFramePointer(), reduceVMULWidth(), llvm::X86TargetLowering::ReplaceNodeResults(), selectI64Imm(), selectImmWithConstantPool(), setAlignFlagsForFI(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), setUsesTOCBasePtr(), llvm::RISCVTargetLowering::shouldExpandShift(), llvm::AArch64TargetLowering::shouldExpandShift(), llvm::X86TargetLowering::shouldExpandShift(), shouldGenerateInlineTPLoop(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), llvm::TargetLowering::SimplifySetCC(), splitStores(), llvm::AMDGPUTargetLowering::storeStackInputValue(), StoreTailCallArgumentsToStackSlot(), transformCallee(), llvm::X86InstrInfo::unfoldMemoryOperand(), unpack64(), unpackF64OnRV32DSoftABI(), unpackFromMemLoc(), unpackFromRegLoc(), viewGraph(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
ArrayRef< EVT > | ResultTys, | ||
ArrayRef< SDValue > | Ops | ||
) |
Definition at line 9574 of file SelectionDAG.cpp.
References getMachineNode(), and getVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
const SDLoc & | dl, | ||
EVT | VT | ||
) |
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
getMachineNode - These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
Note that getMachineNode returns the resultant node. If there is already a node of the specified opcode and operands, it returns that node instead of the current one.
Definition at line 9493 of file SelectionDAG.cpp.
References getVTList(), and llvm::None.
Referenced by llvm::SITargetLowering::buildRSRC(), buildSMovImm32(), llvm::VETargetLowering::combineTRUNCATE(), llvm::SITargetLowering::copyToM0(), createGPRPairNode(), createTupleImpl(), llvm::HexagonDAGToDAGISel::DetectUseSxtw(), emitLockedStackOp(), llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(), expandIntrinsicWChainHelper(), extractSubReg(), llvm::RISCVTargetLowering::g