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VEISelLowering.cpp
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1 //===-- VEISelLowering.cpp - VE DAG Lowering Implementation ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the interfaces that VE uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "VEISelLowering.h"
15 #include "MCTargetDesc/VEMCExpr.h"
16 #include "VECustomDAG.h"
17 #include "VEInstrBuilder.h"
18 #include "VEMachineFunctionInfo.h"
19 #include "VERegisterInfo.h"
20 #include "VETargetMachine.h"
21 #include "llvm/ADT/StringSwitch.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/IRBuilder.h"
34 #include "llvm/IR/Module.h"
36 #include "llvm/Support/KnownBits.h"
37 using namespace llvm;
38 
39 #define DEBUG_TYPE "ve-lower"
40 
41 //===----------------------------------------------------------------------===//
42 // Calling Convention Implementation
43 //===----------------------------------------------------------------------===//
44 
45 #include "VEGenCallingConv.inc"
46 
48  switch (CallConv) {
49  default:
50  return RetCC_VE_C;
51  case CallingConv::Fast:
52  return RetCC_VE_Fast;
53  }
54 }
55 
56 CCAssignFn *getParamCC(CallingConv::ID CallConv, bool IsVarArg) {
57  if (IsVarArg)
58  return CC_VE2;
59  switch (CallConv) {
60  default:
61  return CC_VE_C;
62  case CallingConv::Fast:
63  return CC_VE_Fast;
64  }
65 }
66 
68  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
70  CCAssignFn *RetCC = getReturnCC(CallConv);
72  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
73  return CCInfo.CheckReturn(Outs, RetCC);
74 }
75 
78 
79 static const MVT AllMaskVTs[] = {MVT::v256i1, MVT::v512i1};
80 
82 
83 void VETargetLowering::initRegisterClasses() {
84  // Set up the register classes.
85  addRegisterClass(MVT::i32, &VE::I32RegClass);
86  addRegisterClass(MVT::i64, &VE::I64RegClass);
87  addRegisterClass(MVT::f32, &VE::F32RegClass);
88  addRegisterClass(MVT::f64, &VE::I64RegClass);
89  addRegisterClass(MVT::f128, &VE::F128RegClass);
90 
91  if (Subtarget->enableVPU()) {
92  for (MVT VecVT : AllVectorVTs)
93  addRegisterClass(VecVT, &VE::V64RegClass);
94  addRegisterClass(MVT::v256i1, &VE::VMRegClass);
95  addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
96  }
97 }
98 
99 void VETargetLowering::initSPUActions() {
100  const auto &TM = getTargetMachine();
101  /// Load & Store {
102 
103  // VE doesn't have i1 sign extending load.
104  for (MVT VT : MVT::integer_valuetypes()) {
109  }
110 
111  // VE doesn't have floating point extload/truncstore, so expand them.
112  for (MVT FPVT : MVT::fp_valuetypes()) {
113  for (MVT OtherFPVT : MVT::fp_valuetypes()) {
114  setLoadExtAction(ISD::EXTLOAD, FPVT, OtherFPVT, Expand);
115  setTruncStoreAction(FPVT, OtherFPVT, Expand);
116  }
117  }
118 
119  // VE doesn't have fp128 load/store, so expand them in custom lower.
122 
123  /// } Load & Store
124 
125  // Custom legalize address nodes into LO/HI parts.
126  MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
132 
133  /// VAARG handling {
135  // VAARG needs to be lowered to access with 8 bytes alignment.
137  // Use the default implementation.
140  /// } VAARG handling
141 
142  /// Stack {
145 
146  // Use the default implementation.
149  /// } Stack
150 
151  /// Branch {
152 
153  // VE doesn't have BRCOND
155 
156  // BR_JT is not implemented yet.
158 
159  /// } Branch
160 
161  /// Int Ops {
162  for (MVT IntVT : {MVT::i32, MVT::i64}) {
163  // VE has no REM or DIVREM operations.
168 
169  // VE has no SHL_PARTS/SRA_PARTS/SRL_PARTS operations.
173 
174  // VE has no MULHU/S or U/SMUL_LOHI operations.
175  // TODO: Use MPD instruction to implement SMUL_LOHI for i32 type.
180 
181  // VE has no CTTZ, ROTL, ROTR operations.
185 
186  // VE has 64 bits instruction which works as i64 BSWAP operation. This
187  // instruction works fine as i32 BSWAP operation with an additional
188  // parameter. Use isel patterns to lower BSWAP.
190 
191  // VE has only 64 bits instructions which work as i64 BITREVERSE/CTLZ/CTPOP
192  // operations. Use isel patterns for i64, promote for i32.
193  LegalizeAction Act = (IntVT == MVT::i32) ? Promote : Legal;
194  setOperationAction(ISD::BITREVERSE, IntVT, Act);
195  setOperationAction(ISD::CTLZ, IntVT, Act);
197  setOperationAction(ISD::CTPOP, IntVT, Act);
198 
199  // VE has only 64 bits instructions which work as i64 AND/OR/XOR operations.
200  // Use isel patterns for i64, promote for i32.
201  setOperationAction(ISD::AND, IntVT, Act);
202  setOperationAction(ISD::OR, IntVT, Act);
203  setOperationAction(ISD::XOR, IntVT, Act);
204 
205  // Legal smax and smin
208  }
209  /// } Int Ops
210 
211  /// Conversion {
212  // VE doesn't have instructions for fp<->uint, so expand them by llvm
217 
218  // fp16 not supported
219  for (MVT FPVT : MVT::fp_valuetypes()) {
222  }
223  /// } Conversion
224 
225  /// Floating-point Ops {
226  /// Note: Floating-point operations are fneg, fadd, fsub, fmul, fdiv, frem,
227  /// and fcmp.
228 
229  // VE doesn't have following floating point operations.
230  for (MVT VT : MVT::fp_valuetypes()) {
233  }
234 
235  // VE doesn't have fdiv of f128.
237 
238  for (MVT FPVT : {MVT::f32, MVT::f64}) {
239  // f32 and f64 uses ConstantFP. f128 uses ConstantPool.
241  }
242  /// } Floating-point Ops
243 
244  /// Floating-point math functions {
245 
246  // VE doesn't have following floating point math functions.
247  for (MVT VT : MVT::fp_valuetypes()) {
255  }
256 
257  // VE has single and double FMINNUM and FMAXNUM
258  for (MVT VT : {MVT::f32, MVT::f64}) {
260  }
261 
262  /// } Floating-point math functions
263 
264  /// Atomic instructions {
265 
269 
270  // Use custom inserter for ATOMIC_FENCE.
272 
273  // Other atomic instructions.
274  for (MVT VT : MVT::integer_valuetypes()) {
275  // Support i8/i16 atomic swap.
277 
278  // FIXME: Support "atmam" instructions.
283 
284  // VE doesn't have follwing instructions.
293  }
294 
295  /// } Atomic instructions
296 
297  /// SJLJ instructions {
301  if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
302  setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
303  /// } SJLJ instructions
304 
305  // Intrinsic instructions
307 }
308 
309 void VETargetLowering::initVPUActions() {
310  for (MVT LegalMaskVT : AllMaskVTs)
312 
313  for (unsigned Opc : {ISD::AND, ISD::OR, ISD::XOR})
315 
316  for (MVT LegalVecVT : AllVectorVTs) {
320  // Translate all vector instructions with legal element types to VVP_*
321  // nodes.
322  // TODO We will custom-widen into VVP_* nodes in the future. While we are
323  // buildling the infrastructure for this, we only do this for legal vector
324  // VTs.
325 #define HANDLE_VP_TO_VVP(VP_OPC, VVP_NAME) \
326  setOperationAction(ISD::VP_OPC, LegalVecVT, Custom);
327 #define ADD_VVP_OP(VVP_NAME, ISD_NAME) \
328  setOperationAction(ISD::ISD_NAME, LegalVecVT, Custom);
329  setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_LOAD, LegalVecVT, Custom);
330  setOperationAction(ISD::EXPERIMENTAL_VP_STRIDED_STORE, LegalVecVT, Custom);
331 #include "VVPNodes.def"
332  }
333 
334  for (MVT LegalPackedVT : AllPackedVTs) {
337  }
338 
339  // vNt32, vNt64 ops (legal element types)
340  for (MVT VT : MVT::vector_valuetypes()) {
341  MVT ElemVT = VT.getVectorElementType();
342  unsigned ElemBits = ElemVT.getScalarSizeInBits();
343  if (ElemBits != 32 && ElemBits != 64)
344  continue;
345 
346  for (unsigned MemOpc : {ISD::MLOAD, ISD::MSTORE, ISD::LOAD, ISD::STORE})
347  setOperationAction(MemOpc, VT, Custom);
348 
349  const ISD::NodeType IntReductionOCs[] = {
353 
354  for (unsigned IntRedOpc : IntReductionOCs)
355  setOperationAction(IntRedOpc, VT, Custom);
356  }
357 
358  // v256i1 and v512i1 ops
359  for (MVT MaskVT : AllMaskVTs) {
360  // Custom lower mask ops
363  }
364 }
365 
366 SDValue
368  bool IsVarArg,
370  const SmallVectorImpl<SDValue> &OutVals,
371  const SDLoc &DL, SelectionDAG &DAG) const {
372  // CCValAssign - represent the assignment of the return value to locations.
374 
375  // CCState - Info about the registers and stack slot.
376  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
377  *DAG.getContext());
378 
379  // Analyze return values.
380  CCInfo.AnalyzeReturn(Outs, getReturnCC(CallConv));
381 
382  SDValue Flag;
383  SmallVector<SDValue, 4> RetOps(1, Chain);
384 
385  // Copy the result values into the output registers.
386  for (unsigned i = 0; i != RVLocs.size(); ++i) {
387  CCValAssign &VA = RVLocs[i];
388  assert(VA.isRegLoc() && "Can only return in registers!");
389  assert(!VA.needsCustom() && "Unexpected custom lowering");
390  SDValue OutVal = OutVals[i];
391 
392  // Integer return values must be sign or zero extended by the callee.
393  switch (VA.getLocInfo()) {
394  case CCValAssign::Full:
395  break;
396  case CCValAssign::SExt:
397  OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
398  break;
399  case CCValAssign::ZExt:
400  OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
401  break;
402  case CCValAssign::AExt:
403  OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
404  break;
405  case CCValAssign::BCvt: {
406  // Convert a float return value to i64 with padding.
407  // 63 31 0
408  // +------+------+
409  // | float| 0 |
410  // +------+------+
411  assert(VA.getLocVT() == MVT::i64);
412  assert(VA.getValVT() == MVT::f32);
414  DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64), 0);
415  SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32);
416  OutVal = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
417  MVT::i64, Undef, OutVal, Sub_f32),
418  0);
419  break;
420  }
421  default:
422  llvm_unreachable("Unknown loc info!");
423  }
424 
425  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
426 
427  // Guarantee that all emitted copies are stuck together with flags.
428  Flag = Chain.getValue(1);
429  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
430  }
431 
432  RetOps[0] = Chain; // Update chain.
433 
434  // Add the flag if we have it.
435  if (Flag.getNode())
436  RetOps.push_back(Flag);
437 
438  return DAG.getNode(VEISD::RET_FLAG, DL, MVT::Other, RetOps);
439 }
440 
442  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
444  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
446 
447  // Get the base offset of the incoming arguments stack space.
448  unsigned ArgsBaseOffset = Subtarget->getRsaSize();
449  // Get the size of the preserved arguments area
450  unsigned ArgsPreserved = 64;
451 
452  // Analyze arguments according to CC_VE.
454  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
455  *DAG.getContext());
456  // Allocate the preserved area first.
457  CCInfo.AllocateStack(ArgsPreserved, Align(8));
458  // We already allocated the preserved area, so the stack offset computed
459  // by CC_VE would be correct now.
460  CCInfo.AnalyzeFormalArguments(Ins, getParamCC(CallConv, false));
461 
462  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
463  CCValAssign &VA = ArgLocs[i];
464  assert(!VA.needsCustom() && "Unexpected custom lowering");
465  if (VA.isRegLoc()) {
466  // This argument is passed in a register.
467  // All integer register arguments are promoted by the caller to i64.
468 
469  // Create a virtual register for the promoted live-in value.
470  Register VReg =
471  MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT()));
472  SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
473 
474  // The caller promoted the argument, so insert an Assert?ext SDNode so we
475  // won't promote the value again in this function.
476  switch (VA.getLocInfo()) {
477  case CCValAssign::SExt:
478  Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
479  DAG.getValueType(VA.getValVT()));
480  break;
481  case CCValAssign::ZExt:
482  Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
483  DAG.getValueType(VA.getValVT()));
484  break;
485  case CCValAssign::BCvt: {
486  // Extract a float argument from i64 with padding.
487  // 63 31 0
488  // +------+------+
489  // | float| 0 |
490  // +------+------+
491  assert(VA.getLocVT() == MVT::i64);
492  assert(VA.getValVT() == MVT::f32);
493  SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32);
494  Arg = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
495  MVT::f32, Arg, Sub_f32),
496  0);
497  break;
498  }
499  default:
500  break;
501  }
502 
503  // Truncate the register down to the argument type.
504  if (VA.isExtInLoc())
505  Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
506 
507  InVals.push_back(Arg);
508  continue;
509  }
510 
511  // The registers are exhausted. This argument was passed on the stack.
512  assert(VA.isMemLoc());
513  // The CC_VE_Full/Half functions compute stack offsets relative to the
514  // beginning of the arguments area at %fp + the size of reserved area.
515  unsigned Offset = VA.getLocMemOffset() + ArgsBaseOffset;
516  unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
517 
518  // Adjust offset for a float argument by adding 4 since the argument is
519  // stored in 8 bytes buffer with offset like below. LLVM generates
520  // 4 bytes load instruction, so need to adjust offset here. This
521  // adjustment is required in only LowerFormalArguments. In LowerCall,
522  // a float argument is converted to i64 first, and stored as 8 bytes
523  // data, which is required by ABI, so no need for adjustment.
524  // 0 4
525  // +------+------+
526  // | empty| float|
527  // +------+------+
528  if (VA.getValVT() == MVT::f32)
529  Offset += 4;
530 
531  int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true);
532  InVals.push_back(
533  DAG.getLoad(VA.getValVT(), DL, Chain,
536  }
537 
538  if (!IsVarArg)
539  return Chain;
540 
541  // This function takes variable arguments, some of which may have been passed
542  // in registers %s0-%s8.
543  //
544  // The va_start intrinsic needs to know the offset to the first variable
545  // argument.
546  // TODO: need to calculate offset correctly once we support f128.
547  unsigned ArgOffset = ArgLocs.size() * 8;
549  // Skip the reserved area at the top of stack.
550  FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgsBaseOffset);
551 
552  return Chain;
553 }
554 
555 // FIXME? Maybe this could be a TableGen attribute on some registers and
556 // this table could be generated automatically from RegInfo.
558  const MachineFunction &MF) const {
560  .Case("sp", VE::SX11) // Stack pointer
561  .Case("fp", VE::SX9) // Frame pointer
562  .Case("sl", VE::SX8) // Stack limit
563  .Case("lr", VE::SX10) // Link register
564  .Case("tp", VE::SX14) // Thread pointer
565  .Case("outer", VE::SX12) // Outer regiser
566  .Case("info", VE::SX17) // Info area register
567  .Case("got", VE::SX15) // Global offset table register
568  .Case("plt", VE::SX16) // Procedure linkage table register
569  .Default(0);
570 
571  if (Reg)
572  return Reg;
573 
574  report_fatal_error("Invalid register name global variable");
575 }
576 
577 //===----------------------------------------------------------------------===//
578 // TargetLowering Implementation
579 //===----------------------------------------------------------------------===//
580 
582  SmallVectorImpl<SDValue> &InVals) const {
583  SelectionDAG &DAG = CLI.DAG;
584  SDLoc DL = CLI.DL;
585  SDValue Chain = CLI.Chain;
586  auto PtrVT = getPointerTy(DAG.getDataLayout());
587 
588  // VE target does not yet support tail call optimization.
589  CLI.IsTailCall = false;
590 
591  // Get the base offset of the outgoing arguments stack space.
592  unsigned ArgsBaseOffset = Subtarget->getRsaSize();
593  // Get the size of the preserved arguments area
594  unsigned ArgsPreserved = 8 * 8u;
595 
596  // Analyze operands of the call, assigning locations to each operand.
598  CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
599  *DAG.getContext());
600  // Allocate the preserved area first.
601  CCInfo.AllocateStack(ArgsPreserved, Align(8));
602  // We already allocated the preserved area, so the stack offset computed
603  // by CC_VE would be correct now.
604  CCInfo.AnalyzeCallOperands(CLI.Outs, getParamCC(CLI.CallConv, false));
605 
606  // VE requires to use both register and stack for varargs or no-prototyped
607  // functions.
608  bool UseBoth = CLI.IsVarArg;
609 
610  // Analyze operands again if it is required to store BOTH.
612  CCState CCInfo2(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
613  ArgLocs2, *DAG.getContext());
614  if (UseBoth)
615  CCInfo2.AnalyzeCallOperands(CLI.Outs, getParamCC(CLI.CallConv, true));
616 
617  // Get the size of the outgoing arguments stack space requirement.
618  unsigned ArgsSize = CCInfo.getNextStackOffset();
619 
620  // Keep stack frames 16-byte aligned.
621  ArgsSize = alignTo(ArgsSize, 16);
622 
623  // Adjust the stack pointer to make room for the arguments.
624  // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
625  // with more than 6 arguments.
626  Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, DL);
627 
628  // Collect the set of registers to pass to the function and their values.
629  // This will be emitted as a sequence of CopyToReg nodes glued to the call
630  // instruction.
632 
633  // Collect chains from all the memory opeations that copy arguments to the
634  // stack. They must follow the stack pointer adjustment above and precede the
635  // call instruction itself.
636  SmallVector<SDValue, 8> MemOpChains;
637 
638  // VE needs to get address of callee function in a register
639  // So, prepare to copy it to SX12 here.
640 
641  // If the callee is a GlobalAddress node (quite common, every direct call is)
642  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
643  // Likewise ExternalSymbol -> TargetExternalSymbol.
644  SDValue Callee = CLI.Callee;
645 
646  bool IsPICCall = isPositionIndependent();
647 
648  // PC-relative references to external symbols should go through $stub.
649  // If so, we need to prepare GlobalBaseReg first.
650  const TargetMachine &TM = DAG.getTarget();
652  const GlobalValue *GV = nullptr;
653  auto *CalleeG = dyn_cast<GlobalAddressSDNode>(Callee);
654  if (CalleeG)
655  GV = CalleeG->getGlobal();
656  bool Local = TM.shouldAssumeDSOLocal(*Mod, GV);
657  bool UsePlt = !Local;
659 
660  // Turn GlobalAddress/ExternalSymbol node into a value node
661  // containing the address of them here.
662  if (CalleeG) {
663  if (IsPICCall) {
664  if (UsePlt)
665  Subtarget->getInstrInfo()->getGlobalBaseReg(&MF);
666  Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
667  Callee = DAG.getNode(VEISD::GETFUNPLT, DL, PtrVT, Callee);
668  } else {
669  Callee =
671  }
672  } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
673  if (IsPICCall) {
674  if (UsePlt)
675  Subtarget->getInstrInfo()->getGlobalBaseReg(&MF);
676  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0);
677  Callee = DAG.getNode(VEISD::GETFUNPLT, DL, PtrVT, Callee);
678  } else {
679  Callee =
681  }
682  }
683 
684  RegsToPass.push_back(std::make_pair(VE::SX12, Callee));
685 
686  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
687  CCValAssign &VA = ArgLocs[i];
688  SDValue Arg = CLI.OutVals[i];
689 
690  // Promote the value if needed.
691  switch (VA.getLocInfo()) {
692  default:
693  llvm_unreachable("Unknown location info!");
694  case CCValAssign::Full:
695  break;
696  case CCValAssign::SExt:
697  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
698  break;
699  case CCValAssign::ZExt:
700  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
701  break;
702  case CCValAssign::AExt:
703  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
704  break;
705  case CCValAssign::BCvt: {
706  // Convert a float argument to i64 with padding.
707  // 63 31 0
708  // +------+------+
709  // | float| 0 |
710  // +------+------+
711  assert(VA.getLocVT() == MVT::i64);
712  assert(VA.getValVT() == MVT::f32);
714  DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64), 0);
715  SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32);
716  Arg = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
717  MVT::i64, Undef, Arg, Sub_f32),
718  0);
719  break;
720  }
721  }
722 
723  if (VA.isRegLoc()) {
724  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
725  if (!UseBoth)
726  continue;
727  VA = ArgLocs2[i];
728  }
729 
730  assert(VA.isMemLoc());
731 
732  // Create a store off the stack pointer for this argument.
733  SDValue StackPtr = DAG.getRegister(VE::SX11, PtrVT);
734  // The argument area starts at %fp/%sp + the size of reserved area.
735  SDValue PtrOff =
736  DAG.getIntPtrConstant(VA.getLocMemOffset() + ArgsBaseOffset, DL);
737  PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
738  MemOpChains.push_back(
739  DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
740  }
741 
742  // Emit all stores, make sure they occur before the call.
743  if (!MemOpChains.empty())
744  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
745 
746  // Build a sequence of CopyToReg nodes glued together with token chain and
747  // glue operands which copy the outgoing args into registers. The InGlue is
748  // necessary since all emitted instructions must be stuck together in order
749  // to pass the live physical registers.
750  SDValue InGlue;
751  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
752  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
753  RegsToPass[i].second, InGlue);
754  InGlue = Chain.getValue(1);
755  }
756 
757  // Build the operands for the call instruction itself.
759  Ops.push_back(Chain);
760  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
761  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
762  RegsToPass[i].second.getValueType()));
763 
764  // Add a register mask operand representing the call-preserved registers.
765  const VERegisterInfo *TRI = Subtarget->getRegisterInfo();
766  const uint32_t *Mask =
768  assert(Mask && "Missing call preserved mask for calling convention");
769  Ops.push_back(DAG.getRegisterMask(Mask));
770 
771  // Make sure the CopyToReg nodes are glued to the call instruction which
772  // consumes the registers.
773  if (InGlue.getNode())
774  Ops.push_back(InGlue);
775 
776  // Now the call itself.
777  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
778  Chain = DAG.getNode(VEISD::CALL, DL, NodeTys, Ops);
779  InGlue = Chain.getValue(1);
780 
781  // Revert the stack pointer immediately after the call.
782  Chain = DAG.getCALLSEQ_END(Chain, ArgsSize, 0, InGlue, DL);
783  InGlue = Chain.getValue(1);
784 
785  // Now extract the return values. This is more or less the same as
786  // LowerFormalArguments.
787 
788  // Assign locations to each value returned by this call.
790  CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
791  *DAG.getContext());
792 
793  // Set inreg flag manually for codegen generated library calls that
794  // return float.
795  if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB)
796  CLI.Ins[0].Flags.setInReg();
797 
798  RVInfo.AnalyzeCallResult(CLI.Ins, getReturnCC(CLI.CallConv));
799 
800  // Copy all of the result registers out of their specified physreg.
801  for (unsigned i = 0; i != RVLocs.size(); ++i) {
802  CCValAssign &VA = RVLocs[i];
803  assert(!VA.needsCustom() && "Unexpected custom lowering");
804  Register Reg = VA.getLocReg();
805 
806  // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
807  // reside in the same register in the high and low bits. Reuse the
808  // CopyFromReg previous node to avoid duplicate copies.
809  SDValue RV;
810  if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
811  if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
812  RV = Chain.getValue(0);
813 
814  // But usually we'll create a new CopyFromReg for a different register.
815  if (!RV.getNode()) {
816  RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
817  Chain = RV.getValue(1);
818  InGlue = Chain.getValue(2);
819  }
820 
821  // The callee promoted the return value, so insert an Assert?ext SDNode so
822  // we won't promote the value again in this function.
823  switch (VA.getLocInfo()) {
824  case CCValAssign::SExt:
825  RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
826  DAG.getValueType(VA.getValVT()));
827  break;
828  case CCValAssign::ZExt:
829  RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
830  DAG.getValueType(VA.getValVT()));
831  break;
832  case CCValAssign::BCvt: {
833  // Extract a float return value from i64 with padding.
834  // 63 31 0
835  // +------+------+
836  // | float| 0 |
837  // +------+------+
838  assert(VA.getLocVT() == MVT::i64);
839  assert(VA.getValVT() == MVT::f32);
840  SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32);
841  RV = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
842  MVT::f32, RV, Sub_f32),
843  0);
844  break;
845  }
846  default:
847  break;
848  }
849 
850  // Truncate the register down to the return value type.
851  if (VA.isExtInLoc())
852  RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
853 
854  InVals.push_back(RV);
855  }
856 
857  return Chain;
858 }
859 
861  const GlobalAddressSDNode *GA) const {
862  // VE uses 64 bit addressing, so we need multiple instructions to generate
863  // an address. Folding address with offset increases the number of
864  // instructions, so that we disable it here. Offsets will be folded in
865  // the DAG combine later if it worth to do so.
866  return false;
867 }
868 
869 /// isFPImmLegal - Returns true if the target can instruction select the
870 /// specified FP immediate natively. If false, the legalizer will
871 /// materialize the FP immediate as a load from a constant pool.
873  bool ForCodeSize) const {
874  return VT == MVT::f32 || VT == MVT::f64;
875 }
876 
877 /// Determine if the target supports unaligned memory accesses.
878 ///
879 /// This function returns true if the target allows unaligned memory accesses
880 /// of the specified type in the given address space. If true, it also returns
881 /// whether the unaligned memory access is "fast" in the last argument by
882 /// reference. This is used, for example, in situations where an array
883 /// copy/move/set is converted to a sequence of store operations. Its use
884 /// helps to ensure that such replacements don't generate code that causes an
885 /// alignment error (trap) on the target machine.
887  unsigned AddrSpace,
888  Align A,
890  unsigned *Fast) const {
891  if (Fast) {
892  // It's fast anytime on VE
893  *Fast = 1;
894  }
895  return true;
896 }
897 
899  const VESubtarget &STI)
900  : TargetLowering(TM), Subtarget(&STI) {
901  // Instructions which use registers as conditionals examine all the
902  // bits (as does the pseudo SELECT_CC expansion). I don't think it
903  // matters much whether it's ZeroOrOneBooleanContent, or
904  // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
905  // former.
908 
909  initRegisterClasses();
910  initSPUActions();
911  initVPUActions();
912 
914 
915  // We have target-specific dag combine patterns for the following nodes:
919 
920  // Set function alignment to 16 bytes
922 
923  // VE stores all argument by 8 bytes alignment
925 
927 }
928 
929 const char *VETargetLowering::getTargetNodeName(unsigned Opcode) const {
930 #define TARGET_NODE_CASE(NAME) \
931  case VEISD::NAME: \
932  return "VEISD::" #NAME;
933  switch ((VEISD::NodeType)Opcode) {
934  case VEISD::FIRST_NUMBER:
935  break;
949  TARGET_NODE_CASE(Hi)
950  TARGET_NODE_CASE(Lo)
960 
962 
963  // Register the VVP_* SDNodes.
964 #define ADD_VVP_OP(VVP_NAME, ...) TARGET_NODE_CASE(VVP_NAME)
965 #include "VVPNodes.def"
966  }
967 #undef TARGET_NODE_CASE
968  return nullptr;
969 }
970 
972  EVT VT) const {
973  return MVT::i32;
974 }
975 
976 // Convert to a target node and set target flags.
978  SelectionDAG &DAG) const {
979  if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
980  return DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(GA),
981  GA->getValueType(0), GA->getOffset(), TF);
982 
983  if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
984  return DAG.getTargetBlockAddress(BA->getBlockAddress(), Op.getValueType(),
985  0, TF);
986 
987  if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
988  return DAG.getTargetConstantPool(CP->getConstVal(), CP->getValueType(0),
989  CP->getAlign(), CP->getOffset(), TF);
990 
991  if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
992  return DAG.getTargetExternalSymbol(ES->getSymbol(), ES->getValueType(0),
993  TF);
994 
995  if (const JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op))
996  return DAG.getTargetJumpTable(JT->getIndex(), JT->getValueType(0), TF);
997 
998  llvm_unreachable("Unhandled address SDNode");
999 }
1000 
1001 // Split Op into high and low parts according to HiTF and LoTF.
1002 // Return an ADD node combining the parts.
1003 SDValue VETargetLowering::makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
1004  SelectionDAG &DAG) const {
1005  SDLoc DL(Op);
1006  EVT VT = Op.getValueType();
1007  SDValue Hi = DAG.getNode(VEISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1008  SDValue Lo = DAG.getNode(VEISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1009  return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1010 }
1011 
1012 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1013 // or ExternalSymbol SDNode.
1015  SDLoc DL(Op);
1016  EVT PtrVT = Op.getValueType();
1017 
1018  // Handle PIC mode first. VE needs a got load for every variable!
1019  if (isPositionIndependent()) {
1020  auto GlobalN = dyn_cast<GlobalAddressSDNode>(Op);
1021 
1022  if (isa<ConstantPoolSDNode>(Op) || isa<JumpTableSDNode>(Op) ||
1023  (GlobalN && GlobalN->getGlobal()->hasLocalLinkage())) {
1024  // Create following instructions for local linkage PIC code.
1025  // lea %reg, label@gotoff_lo
1026  // and %reg, %reg, (32)0
1027  // lea.sl %reg, label@gotoff_hi(%reg, %got)
1030  SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, PtrVT);
1031  return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalBase, HiLo);
1032  }
1033  // Create following instructions for not local linkage PIC code.
1034  // lea %reg, label@got_lo
1035  // and %reg, %reg, (32)0
1036  // lea.sl %reg, label@got_hi(%reg)
1037  // ld %reg, (%reg, %got)
1040  SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, PtrVT);
1041  SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, PtrVT, GlobalBase, HiLo);
1042  return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), AbsAddr,
1044  }
1045 
1046  // This is one of the absolute code models.
1047  switch (getTargetMachine().getCodeModel()) {
1048  default:
1049  llvm_unreachable("Unsupported absolute code model");
1050  case CodeModel::Small:
1051  case CodeModel::Medium:
1052  case CodeModel::Large:
1053  // abs64.
1055  }
1056 }
1057 
1058 /// Custom Lower {
1059 
1060 // The mappings for emitLeading/TrailingFence for VE is designed by following
1061 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
1063  Instruction *Inst,
1064  AtomicOrdering Ord) const {
1065  switch (Ord) {
1068  llvm_unreachable("Invalid fence: unordered/non-atomic");
1071  return nullptr; // Nothing to do
1074  return Builder.CreateFence(AtomicOrdering::Release);
1076  if (!Inst->hasAtomicStore())
1077  return nullptr; // Nothing to do
1078  return Builder.CreateFence(AtomicOrdering::SequentiallyConsistent);
1079  }
1080  llvm_unreachable("Unknown fence ordering in emitLeadingFence");
1081 }
1082 
1084  Instruction *Inst,
1085  AtomicOrdering Ord) const {
1086  switch (Ord) {
1089  llvm_unreachable("Invalid fence: unordered/not-atomic");
1092  return nullptr; // Nothing to do
1095  return Builder.CreateFence(AtomicOrdering::Acquire);
1097  return Builder.CreateFence(AtomicOrdering::SequentiallyConsistent);
1098  }
1099  llvm_unreachable("Unknown fence ordering in emitTrailingFence");
1100 }
1101 
1103  SelectionDAG &DAG) const {
1104  SDLoc DL(Op);
1105  AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
1106  cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
1107  SyncScope::ID FenceSSID = static_cast<SyncScope::ID>(
1108  cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
1109 
1110  // VE uses Release consistency, so need a fence instruction if it is a
1111  // cross-thread fence.
1112  if (FenceSSID == SyncScope::System) {
1113  switch (FenceOrdering) {
1117  // No need to generate fencem instruction here.
1118  break;
1120  // Generate "fencem 2" as acquire fence.
1121  return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other,
1122  DAG.getTargetConstant(2, DL, MVT::i32),
1123  Op.getOperand(0)),
1124  0);
1126  // Generate "fencem 1" as release fence.
1127  return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other,
1128  DAG.getTargetConstant(1, DL, MVT::i32),
1129  Op.getOperand(0)),
1130  0);
1133  // Generate "fencem 3" as acq_rel and seq_cst fence.
1134  // FIXME: "fencem 3" doesn't wait for for PCIe deveices accesses,
1135  // so seq_cst may require more instruction for them.
1136  return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other,
1137  DAG.getTargetConstant(3, DL, MVT::i32),
1138  Op.getOperand(0)),
1139  0);
1140  }
1141  }
1142 
1143  // MEMBARRIER is a compiler barrier; it codegens to a no-op.
1144  return DAG.getNode(VEISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
1145 }
1146 
1149  // We have TS1AM implementation for i8/i16/i32/i64, so use it.
1150  if (AI->getOperation() == AtomicRMWInst::Xchg) {
1152  }
1153  // FIXME: Support "ATMAM" instruction for LOAD_ADD/SUB/AND/OR.
1154 
1155  // Otherwise, expand it using compare and exchange instruction to not call
1156  // __sync_fetch_and_* functions.
1158 }
1159 
1161  SDValue &Bits) {
1162  SDLoc DL(Op);
1163  AtomicSDNode *N = cast<AtomicSDNode>(Op);
1164  SDValue Ptr = N->getOperand(1);
1165  SDValue Val = N->getOperand(2);
1166  EVT PtrVT = Ptr.getValueType();
1167  bool Byte = N->getMemoryVT() == MVT::i8;
1168  // Remainder = AND Ptr, 3
1169  // Flag = 1 << Remainder ; If Byte is true (1 byte swap flag)
1170  // Flag = 3 << Remainder ; If Byte is false (2 bytes swap flag)
1171  // Bits = Remainder << 3
1172  // NewVal = Val << Bits
1173  SDValue Const3 = DAG.getConstant(3, DL, PtrVT);
1174  SDValue Remainder = DAG.getNode(ISD::AND, DL, PtrVT, {Ptr, Const3});
1175  SDValue Mask = Byte ? DAG.getConstant(1, DL, MVT::i32)
1176  : DAG.getConstant(3, DL, MVT::i32);
1177  Flag = DAG.getNode(ISD::SHL, DL, MVT::i32, {Mask, Remainder});
1178  Bits = DAG.getNode(ISD::SHL, DL, PtrVT, {Remainder, Const3});
1179  return DAG.getNode(ISD::SHL, DL, Val.getValueType(), {Val, Bits});
1180 }
1181 
1183  SDValue Bits) {
1184  SDLoc DL(Op);
1185  EVT VT = Data.getValueType();
1186  bool Byte = cast<AtomicSDNode>(Op)->getMemoryVT() == MVT::i8;
1187  // NewData = Data >> Bits
1188  // Result = NewData & 0xff ; If Byte is true (1 byte)
1189  // Result = NewData & 0xffff ; If Byte is false (2 bytes)
1190 
1191  SDValue NewData = DAG.getNode(ISD::SRL, DL, VT, Data, Bits);
1192  return DAG.getNode(ISD::AND, DL, VT,
1193  {NewData, DAG.getConstant(Byte ? 0xff : 0xffff, DL, VT)});
1194 }
1195 
1197  SelectionDAG &DAG) const {
1198  SDLoc DL(Op);
1199  AtomicSDNode *N = cast<AtomicSDNode>(Op);
1200 
1201  if (N->getMemoryVT() == MVT::i8) {
1202  // For i8, use "ts1am"
1203  // Input:
1204  // ATOMIC_SWAP Ptr, Val, Order
1205  //
1206  // Output:
1207  // Remainder = AND Ptr, 3
1208  // Flag = 1 << Remainder ; 1 byte swap flag for TS1AM inst.
1209  // Bits = Remainder << 3
1210  // NewVal = Val << Bits
1211  //
1212  // Aligned = AND Ptr, -4
1213  // Data = TS1AM Aligned, Flag, NewVal
1214  //
1215  // NewData = Data >> Bits
1216  // Result = NewData & 0xff ; 1 byte result
1217  SDValue Flag;
1218  SDValue Bits;
1219  SDValue NewVal = prepareTS1AM(Op, DAG, Flag, Bits);
1220 
1221  SDValue Ptr = N->getOperand(1);
1222  SDValue Aligned = DAG.getNode(ISD::AND, DL, Ptr.getValueType(),
1223  {Ptr, DAG.getConstant(-4, DL, MVT::i64)});
1224  SDValue TS1AM = DAG.getAtomic(VEISD::TS1AM, DL, N->getMemoryVT(),
1225  DAG.getVTList(Op.getNode()->getValueType(0),
1226  Op.getNode()->getValueType(1)),
1227  {N->getChain(), Aligned, Flag, NewVal},
1228  N->getMemOperand());
1229 
1230  SDValue Result = finalizeTS1AM(Op, DAG, TS1AM, Bits);
1231  SDValue Chain = TS1AM.getValue(1);
1232  return DAG.getMergeValues({Result, Chain}, DL);
1233  }
1234  if (N->getMemoryVT() == MVT::i16) {
1235  // For i16, use "ts1am"
1236  SDValue Flag;
1237  SDValue Bits;
1238  SDValue NewVal = prepareTS1AM(Op, DAG, Flag, Bits);
1239 
1240  SDValue Ptr = N->getOperand(1);
1241  SDValue Aligned = DAG.getNode(ISD::AND, DL, Ptr.getValueType(),
1242  {Ptr, DAG.getConstant(-4, DL, MVT::i64)});
1243  SDValue TS1AM = DAG.getAtomic(VEISD::TS1AM, DL, N->getMemoryVT(),
1244  DAG.getVTList(Op.getNode()->getValueType(0),
1245  Op.getNode()->getValueType(1)),
1246  {N->getChain(), Aligned, Flag, NewVal},
1247  N->getMemOperand());
1248 
1249  SDValue Result = finalizeTS1AM(Op, DAG, TS1AM, Bits);
1250  SDValue Chain = TS1AM.getValue(1);
1251  return DAG.getMergeValues({Result, Chain}, DL);
1252  }
1253  // Otherwise, let llvm legalize it.
1254  return Op;
1255 }
1256 
1258  SelectionDAG &DAG) const {
1259  return makeAddress(Op, DAG);
1260 }
1261 
1263  SelectionDAG &DAG) const {
1264  return makeAddress(Op, DAG);
1265 }
1266 
1268  SelectionDAG &DAG) const {
1269  return makeAddress(Op, DAG);
1270 }
1271 
1272 SDValue
1274  SelectionDAG &DAG) const {
1275  SDLoc DL(Op);
1276 
1277  // Generate the following code:
1278  // t1: ch,glue = callseq_start t0, 0, 0
1279  // t2: i64,ch,glue = VEISD::GETTLSADDR t1, label, t1:1
1280  // t3: ch,glue = callseq_end t2, 0, 0, t2:2
1281  // t4: i64,ch,glue = CopyFromReg t3, Register:i64 $sx0, t3:1
1282  SDValue Label = withTargetFlags(Op, 0, DAG);
1283  EVT PtrVT = Op.getValueType();
1284 
1285  // Lowering the machine isd will make sure everything is in the right
1286  // location.
1287  SDValue Chain = DAG.getEntryNode();
1288  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1289  const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
1291  Chain = DAG.getCALLSEQ_START(Chain, 64, 0, DL);
1292  SDValue Args[] = {Chain, Label, DAG.getRegisterMask(Mask), Chain.getValue(1)};
1293  Chain = DAG.getNode(VEISD::GETTLSADDR, DL, NodeTys, Args);
1294  Chain = DAG.getCALLSEQ_END(Chain, 64, 0, Chain.getValue(1), DL);
1295  Chain = DAG.getCopyFromReg(Chain, DL, VE::SX0, PtrVT, Chain.getValue(1));
1296 
1297  // GETTLSADDR will be codegen'ed as call. Inform MFI that function has calls.
1299  MFI.setHasCalls(true);
1300 
1301  // Also generate code to prepare a GOT register if it is PIC.
1302  if (isPositionIndependent()) {
1303  MachineFunction &MF = DAG.getMachineFunction();
1304  Subtarget->getInstrInfo()->getGlobalBaseReg(&MF);
1305  }
1306 
1307  return Chain;
1308 }
1309 
1311  SelectionDAG &DAG) const {
1312  // The current implementation of nld (2.26) doesn't allow local exec model
1313  // code described in VE-tls_v1.1.pdf (*1) as its input. Instead, we always
1314  // generate the general dynamic model code sequence.
1315  //
1316  // *1: https://www.nec.com/en/global/prod/hpc/aurora/document/VE-tls_v1.1.pdf
1317  return lowerToTLSGeneralDynamicModel(Op, DAG);
1318 }
1319 
1321  return makeAddress(Op, DAG);
1322 }
1323 
1324 // Lower a f128 load into two f64 loads.
1326  SDLoc DL(Op);
1327  LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
1328  assert(LdNode && LdNode->getOffset().isUndef() && "Unexpected node type");
1329  unsigned Alignment = LdNode->getAlign().value();
1330  if (Alignment > 8)
1331  Alignment = 8;
1332 
1333  SDValue Lo64 =
1334  DAG.getLoad(MVT::f64, DL, LdNode->getChain(), LdNode->getBasePtr(),
1335  LdNode->getPointerInfo(), Alignment,
1338  EVT AddrVT = LdNode->getBasePtr().getValueType();
1339  SDValue HiPtr = DAG.getNode(ISD::ADD, DL, AddrVT, LdNode->getBasePtr(),
1340  DAG.getConstant(8, DL, AddrVT));
1341  SDValue Hi64 =
1342  DAG.getLoad(MVT::f64, DL, LdNode->getChain(), HiPtr,
1343  LdNode->getPointerInfo(), Alignment,
1346 
1347  SDValue SubRegEven = DAG.getTargetConstant(VE::sub_even, DL, MVT::i32);
1348  SDValue SubRegOdd = DAG.getTargetConstant(VE::sub_odd, DL, MVT::i32);
1349 
1350  // VE stores Hi64 to 8(addr) and Lo64 to 0(addr)
1351  SDNode *InFP128 =
1352  DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f128);
1353  InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f128,
1354  SDValue(InFP128, 0), Hi64, SubRegEven);
1355  InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f128,
1356  SDValue(InFP128, 0), Lo64, SubRegOdd);
1357  SDValue OutChains[2] = {SDValue(Lo64.getNode(), 1),
1358  SDValue(Hi64.getNode(), 1)};
1359  SDValue OutChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
1360  SDValue Ops[2] = {SDValue(InFP128, 0), OutChain};
1361  return DAG.getMergeValues(Ops, DL);
1362 }
1363 
1364 // Lower a vXi1 load into following instructions
1365 // LDrii %1, (,%addr)
1366 // LVMxir %vm, 0, %1
1367 // LDrii %2, 8(,%addr)
1368 // LVMxir %vm, 0, %2
1369 // ...
1371  SDLoc DL(Op);
1372  LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
1373  assert(LdNode && LdNode->getOffset().isUndef() && "Unexpected node type");
1374 
1375  SDValue BasePtr = LdNode->getBasePtr();
1376  unsigned Alignment = LdNode->getAlign().value();
1377  if (Alignment > 8)
1378  Alignment = 8;
1379 
1380  EVT AddrVT = BasePtr.getValueType();
1381  EVT MemVT = LdNode->getMemoryVT();
1382  if (MemVT == MVT::v256i1 || MemVT == MVT::v4i64) {
1383  SDValue OutChains[4];
1384  SDNode *VM = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MemVT);
1385  for (int i = 0; i < 4; ++i) {
1386  // Generate load dag and prepare chains.
1387  SDValue Addr = DAG.getNode(ISD::ADD, DL, AddrVT, BasePtr,
1388  DAG.getConstant(8 * i, DL, AddrVT));
1389  SDValue Val =
1390  DAG.getLoad(MVT::i64, DL, LdNode->getChain(), Addr,
1391  LdNode->getPointerInfo(), Alignment,
1394  OutChains[i] = SDValue(Val.getNode(), 1);
1395 
1396  VM = DAG.getMachineNode(VE::LVMir_m, DL, MVT::i64,
1397  DAG.getTargetConstant(i, DL, MVT::i64), Val,
1398  SDValue(VM, 0));
1399  }
1400  SDValue OutChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
1401  SDValue Ops[2] = {SDValue(VM, 0), OutChain};
1402  return DAG.getMergeValues(Ops, DL);
1403  } else if (MemVT == MVT::v512i1 || MemVT == MVT::v8i64) {
1404  SDValue OutChains[8];
1405  SDNode *VM = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MemVT);
1406  for (int i = 0; i < 8; ++i) {
1407  // Generate load dag and prepare chains.
1408  SDValue Addr = DAG.getNode(ISD::ADD, DL, AddrVT, BasePtr,
1409  DAG.getConstant(8 * i, DL, AddrVT));
1410  SDValue Val =
1411  DAG.getLoad(MVT::i64, DL, LdNode->getChain(), Addr,
1412  LdNode->getPointerInfo(), Alignment,
1415  OutChains[i] = SDValue(Val.getNode(), 1);
1416 
1417  VM = DAG.getMachineNode(VE::LVMyir_y, DL, MVT::i64,
1418  DAG.getTargetConstant(i, DL, MVT::i64), Val,
1419  SDValue(VM, 0));
1420  }
1421  SDValue OutChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
1422  SDValue Ops[2] = {SDValue(VM, 0), OutChain};
1423  return DAG.getMergeValues(Ops, DL);
1424  } else {
1425  // Otherwise, ask llvm to expand it.
1426  return SDValue();
1427  }
1428 }
1429 
1431  LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
1432 
1433  EVT MemVT = LdNode->getMemoryVT();
1434 
1435  // Dispatch to vector isel.
1436  if (MemVT.isVector() && !isMaskType(MemVT))
1437  return lowerToVVP(Op, DAG);
1438 
1439  SDValue BasePtr = LdNode->getBasePtr();
1440  if (isa<FrameIndexSDNode>(BasePtr.getNode())) {
1441  // Do not expand store instruction with frame index here because of
1442  // dependency problems. We expand it later in eliminateFrameIndex().
1443  return Op;
1444  }
1445 
1446  if (MemVT == MVT::f128)
1447  return lowerLoadF128(Op, DAG);
1448  if (isMaskType(MemVT))
1449  return lowerLoadI1(Op, DAG);
1450 
1451  return Op;
1452 }
1453 
1454 // Lower a f128 store into two f64 stores.
1456  SDLoc DL(Op);
1457  StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
1458  assert(StNode && StNode->getOffset().isUndef() && "Unexpected node type");
1459 
1460  SDValue SubRegEven = DAG.getTargetConstant(VE::sub_even, DL, MVT::i32);
1461  SDValue SubRegOdd = DAG.getTargetConstant(VE::sub_odd, DL, MVT::i32);
1462 
1463  SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::i64,
1464  StNode->getValue(), SubRegEven);
1465  SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::i64,
1466  StNode->getValue(), SubRegOdd);
1467 
1468  unsigned Alignment = StNode->getAlign().value();
1469  if (Alignment > 8)
1470  Alignment = 8;
1471 
1472  // VE stores Hi64 to 8(addr) and Lo64 to 0(addr)
1473  SDValue OutChains[2];
1474  OutChains[0] =
1475  DAG.getStore(StNode->getChain(), DL, SDValue(Lo64, 0),
1476  StNode->getBasePtr(), MachinePointerInfo(), Alignment,
1479  EVT AddrVT = StNode->getBasePtr().getValueType();
1480  SDValue HiPtr = DAG.getNode(ISD::ADD, DL, AddrVT, StNode->getBasePtr(),
1481  DAG.getConstant(8, DL, AddrVT));
1482  OutChains[1] =
1483  DAG.getStore(StNode->getChain(), DL, SDValue(Hi64, 0), HiPtr,
1484  MachinePointerInfo(), Alignment,
1487  return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
1488 }
1489 
1490 // Lower a vXi1 store into following instructions
1491 // SVMi %1, %vm, 0
1492 // STrii %1, (,%addr)
1493 // SVMi %2, %vm, 1
1494 // STrii %2, 8(,%addr)
1495 // ...
1497  SDLoc DL(Op);
1498  StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
1499  assert(StNode && StNode->getOffset().isUndef() && "Unexpected node type");
1500 
1501  SDValue BasePtr = StNode->getBasePtr();
1502  unsigned Alignment = StNode->getAlign().value();
1503  if (Alignment > 8)
1504  Alignment = 8;
1505  EVT AddrVT = BasePtr.getValueType();
1506  EVT MemVT = StNode->getMemoryVT();
1507  if (MemVT == MVT::v256i1 || MemVT == MVT::v4i64) {
1508  SDValue OutChains[4];
1509  for (int i = 0; i < 4; ++i) {
1510  SDNode *V =
1511  DAG.getMachineNode(VE::SVMmi, DL, MVT::i64, StNode->getValue(),
1512  DAG.getTargetConstant(i, DL, MVT::i64));
1513  SDValue Addr = DAG.getNode(ISD::ADD, DL, AddrVT, BasePtr,
1514  DAG.getConstant(8 * i, DL, AddrVT));
1515  OutChains[i] =
1516  DAG.getStore(StNode->getChain(), DL, SDValue(V, 0), Addr,
1517  MachinePointerInfo(), Alignment,
1520  }
1521  return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
1522  } else if (MemVT == MVT::v512i1 || MemVT == MVT::v8i64) {
1523  SDValue OutChains[8];
1524  for (int i = 0; i < 8; ++i) {
1525  SDNode *V =
1526  DAG.getMachineNode(VE::SVMyi, DL, MVT::i64, StNode->getValue(),
1527  DAG.getTargetConstant(i, DL, MVT::i64));
1528  SDValue Addr = DAG.getNode(ISD::ADD, DL, AddrVT, BasePtr,
1529  DAG.getConstant(8 * i, DL, AddrVT));
1530  OutChains[i] =
1531  DAG.getStore(StNode->getChain(), DL, SDValue(V, 0), Addr,
1532  MachinePointerInfo(), Alignment,
1535  }
1536  return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
1537  } else {
1538  // Otherwise, ask llvm to expand it.
1539  return SDValue();
1540  }
1541 }
1542 
1544  StoreSDNode *StNode = cast<StoreSDNode>(Op.getNode());
1545  assert(StNode && StNode->getOffset().isUndef() && "Unexpected node type");
1546 
1547  // always expand non-mask vector loads to VVP
1548  EVT MemVT = StNode->getMemoryVT();
1549  if (MemVT.isVector() && !isMaskType(MemVT))
1550  return lowerToVVP(Op, DAG);
1551 
1552  SDValue BasePtr = StNode->getBasePtr();
1553  if (isa<FrameIndexSDNode>(BasePtr.getNode())) {
1554  // Do not expand store instruction with frame index here because of
1555  // dependency problems. We expand it later in eliminateFrameIndex().
1556  return Op;
1557  }
1558 
1559  if (MemVT == MVT::f128)
1560  return lowerStoreF128(Op, DAG);
1561  if (isMaskType(MemVT))
1562  return lowerStoreI1(Op, DAG);
1563 
1564  // Otherwise, ask llvm to expand it.
1565  return SDValue();
1566 }
1567 
1569  MachineFunction &MF = DAG.getMachineFunction();
1571  auto PtrVT = getPointerTy(DAG.getDataLayout());
1572 
1573  // Need frame address to find the address of VarArgsFrameIndex.
1575 
1576  // vastart just stores the address of the VarArgsFrameIndex slot into the
1577  // memory location argument.
1578  SDLoc DL(Op);
1579  SDValue Offset =
1580  DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(VE::SX9, PtrVT),
1581  DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL));
1582  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1583  return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
1584  MachinePointerInfo(SV));
1585 }
1586 
1588  SDNode *Node = Op.getNode();
1589  EVT VT = Node->getValueType(0);
1590  SDValue InChain = Node->getOperand(0);
1591  SDValue VAListPtr = Node->getOperand(1);
1592  EVT PtrVT = VAListPtr.getValueType();
1593  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1594  SDLoc DL(Node);
1595  SDValue VAList =
1596  DAG.getLoad(PtrVT, DL, InChain, VAListPtr, MachinePointerInfo(SV));
1597  SDValue Chain = VAList.getValue(1);
1598  SDValue NextPtr;
1599 
1600  if (VT == MVT::f128) {
1601  // VE f128 values must be stored with 16 bytes alignment. We don't
1602  // know the actual alignment of VAList, so we take alignment of it
1603  // dynamically.
1604  int Align = 16;
1605  VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
1606  DAG.getConstant(Align - 1, DL, PtrVT));
1607  VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
1608  DAG.getConstant(-Align, DL, PtrVT));
1609  // Increment the pointer, VAList, by 16 to the next vaarg.
1610  NextPtr =
1611  DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getIntPtrConstant(16, DL));
1612  } else if (VT == MVT::f32) {
1613  // float --> need special handling like below.
1614  // 0 4
1615  // +------+------+
1616  // | empty| float|
1617  // +------+------+
1618  // Increment the pointer, VAList, by 8 to the next vaarg.
1619  NextPtr =
1620  DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getIntPtrConstant(8, DL));
1621  // Then, adjust VAList.
1622  unsigned InternalOffset = 4;
1623  VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
1624  DAG.getConstant(InternalOffset, DL, PtrVT));
1625  } else {
1626  // Increment the pointer, VAList, by 8 to the next vaarg.
1627  NextPtr =
1628  DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getIntPtrConstant(8, DL));
1629  }
1630 
1631  // Store the incremented VAList to the legalized pointer.
1632  InChain = DAG.getStore(Chain, DL, NextPtr, VAListPtr, MachinePointerInfo(SV));
1633 
1634  // Load the actual argument out of the pointer VAList.
1635  // We can't count on greater alignment than the word size.
1636  return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
1637  std::min(PtrVT.getSizeInBits(), VT.getSizeInBits()) / 8);
1638 }
1639 
1641  SelectionDAG &DAG) const {
1642  // Generate following code.
1643  // (void)__llvm_grow_stack(size);
1644  // ret = GETSTACKTOP; // pseudo instruction
1645  SDLoc DL(Op);
1646 
1647  // Get the inputs.
1648  SDNode *Node = Op.getNode();
1649  SDValue Chain = Op.getOperand(0);
1650  SDValue Size = Op.getOperand(1);
1651  MaybeAlign Alignment(Op.getConstantOperandVal(2));
1652  EVT VT = Node->getValueType(0);
1653 
1654  // Chain the dynamic stack allocation so that it doesn't modify the stack
1655  // pointer when other instructions are using the stack.
1656  Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
1657 
1658  const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
1659  Align StackAlign = TFI.getStackAlign();
1660  bool NeedsAlign = Alignment.valueOrOne() > StackAlign;
1661 
1662  // Prepare arguments
1665  Entry.Node = Size;
1666  Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1667  Args.push_back(Entry);
1668  if (NeedsAlign) {
1669  Entry.Node = DAG.getConstant(~(Alignment->value() - 1ULL), DL, VT);
1670  Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1671  Args.push_back(Entry);
1672  }
1673  Type *RetTy = Type::getVoidTy(*DAG.getContext());
1674 
1675  EVT PtrVT = Op.getValueType();
1676  SDValue Callee;
1677  if (NeedsAlign) {
1678  Callee = DAG.getTargetExternalSymbol("__ve_grow_stack_align", PtrVT, 0);
1679  } else {
1680  Callee = DAG.getTargetExternalSymbol("__ve_grow_stack", PtrVT, 0);
1681  }
1682 
1684  CLI.setDebugLoc(DL)
1685  .setChain(Chain)
1687  .setDiscardResult(true);
1688  std::pair<SDValue, SDValue> pair = LowerCallTo(CLI);
1689  Chain = pair.second;
1690  SDValue Result = DAG.getNode(VEISD::GETSTACKTOP, DL, VT, Chain);
1691  if (NeedsAlign) {
1692  Result = DAG.getNode(ISD::ADD, DL, VT, Result,
1693  DAG.getConstant((Alignment->value() - 1ULL), DL, VT));
1694  Result = DAG.getNode(ISD::AND, DL, VT, Result,
1695  DAG.getConstant(~(Alignment->value() - 1ULL), DL, VT));
1696  }
1697  // Chain = Result.getValue(1);
1698  Chain = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), DL);
1699 
1700  SDValue Ops[2] = {Result, Chain};
1701  return DAG.getMergeValues(Ops, DL);
1702 }
1703 
1705  SelectionDAG &DAG) const {
1706  SDLoc DL(Op);
1707  return DAG.getNode(VEISD::EH_SJLJ_LONGJMP, DL, MVT::Other, Op.getOperand(0),
1708  Op.getOperand(1));
1709 }
1710 
1712  SelectionDAG &DAG) const {
1713  SDLoc DL(Op);
1714  return DAG.getNode(VEISD::EH_SJLJ_SETJMP, DL,
1715  DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
1716  Op.getOperand(1));
1717 }
1718 
1720  SelectionDAG &DAG) const {
1721  SDLoc DL(Op);
1723  Op.getOperand(0));
1724 }
1725 
1727  const VETargetLowering &TLI,
1728  const VESubtarget *Subtarget) {
1729  SDLoc DL(Op);
1730  MachineFunction &MF = DAG.getMachineFunction();
1731  EVT PtrVT = TLI.getPointerTy(MF.getDataLayout());
1732 
1733  MachineFrameInfo &MFI = MF.getFrameInfo();
1734  MFI.setFrameAddressIsTaken(true);
1735 
1736  unsigned Depth = Op.getConstantOperandVal(0);
1737  const VERegisterInfo *RegInfo = Subtarget->getRegisterInfo();
1738  Register FrameReg = RegInfo->getFrameRegister(MF);
1739  SDValue FrameAddr =
1740  DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, PtrVT);
1741  while (Depth--)
1742  FrameAddr = DAG.getLoad(Op.getValueType(), DL, DAG.getEntryNode(),
1743  FrameAddr, MachinePointerInfo());
1744  return FrameAddr;
1745 }
1746 
1748  const VETargetLowering &TLI,
1749  const VESubtarget *Subtarget) {
1750  MachineFunction &MF = DAG.getMachineFunction();
1751  MachineFrameInfo &MFI = MF.getFrameInfo();
1752  MFI.setReturnAddressIsTaken(true);
1753 
1755  return SDValue();
1756 
1757  SDValue FrameAddr = lowerFRAMEADDR(Op, DAG, TLI, Subtarget);
1758 
1759  SDLoc DL(Op);
1760  EVT VT = Op.getValueType();
1761  SDValue Offset = DAG.getConstant(8, DL, VT);
1762  return DAG.getLoad(VT, DL, DAG.getEntryNode(),
1763  DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
1764  MachinePointerInfo());
1765 }
1766 
1768  SelectionDAG &DAG) const {
1769  SDLoc DL(Op);
1770  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1771  switch (IntNo) {
1772  default: // Don't custom lower most intrinsics.
1773  return SDValue();
1774  case Intrinsic::eh_sjlj_lsda: {
1775  MachineFunction &MF = DAG.getMachineFunction();
1776  MVT VT = Op.getSimpleValueType();
1777  const VETargetMachine *TM =
1778  static_cast<const VETargetMachine *>(&DAG.getTarget());
1779 
1780  // Create GCC_except_tableXX string. The real symbol for that will be
1781  // generated in EHStreamer::emitExceptionTable() later. So, we just
1782  // borrow it's name here.
1783  TM->getStrList()->push_back(std::string(
1784  (Twine("GCC_except_table") + Twine(MF.getFunctionNumber())).str()));
1785  SDValue Addr =
1786  DAG.getTargetExternalSymbol(TM->getStrList()->back().c_str(), VT, 0);
1787  if (isPositionIndependent()) {
1790  SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, VT);
1791  return DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Addr);
1792  }
1794  }
1795  }
1796 }
1797 
1798 static bool getUniqueInsertion(SDNode *N, unsigned &UniqueIdx) {
1799  if (!isa<BuildVectorSDNode>(N))
1800  return false;
1801  const auto *BVN = cast<BuildVectorSDNode>(N);
1802 
1803  // Find first non-undef insertion.
1804  unsigned Idx;
1805  for (Idx = 0; Idx < BVN->getNumOperands(); ++Idx) {
1806  auto ElemV = BVN->getOperand(Idx);
1807  if (!ElemV->isUndef())
1808  break;
1809  }
1810  // Catch the (hypothetical) all-undef case.
1811  if (Idx == BVN->getNumOperands())
1812  return false;
1813  // Remember insertion.
1814  UniqueIdx = Idx++;
1815  // Verify that all other insertions are undef.
1816  for (; Idx < BVN->getNumOperands(); ++Idx) {
1817  auto ElemV = BVN->getOperand(Idx);
1818  if (!ElemV->isUndef())
1819  return false;
1820  }
1821  return true;
1822 }
1823 
1825  if (auto *BuildVec = dyn_cast<BuildVectorSDNode>(N)) {
1826  return BuildVec->getSplatValue();
1827  }
1828  return SDValue();
1829 }
1830 
1832  SelectionDAG &DAG) const {
1833  VECustomDAG CDAG(DAG, Op);
1834  MVT ResultVT = Op.getSimpleValueType();
1835 
1836  // If there is just one element, expand to INSERT_VECTOR_ELT.
1837  unsigned UniqueIdx;
1838  if (getUniqueInsertion(Op.getNode(), UniqueIdx)) {
1839  SDValue AccuV = CDAG.getUNDEF(Op.getValueType());
1840  auto ElemV = Op->getOperand(UniqueIdx);
1841  SDValue IdxV = CDAG.getConstant(UniqueIdx, MVT::i64);
1842  return CDAG.getNode(ISD::INSERT_VECTOR_ELT, ResultVT, {AccuV, ElemV, IdxV});
1843  }
1844 
1845  // Else emit a broadcast.
1846  if (SDValue ScalarV = getSplatValue(Op.getNode())) {
1847  unsigned NumEls = ResultVT.getVectorNumElements();
1848  auto AVL = CDAG.getConstant(NumEls, MVT::i32);
1849  return CDAG.getBroadcast(ResultVT, ScalarV, AVL);
1850  }
1851 
1852  // Expand
1853  return SDValue();
1854 }
1855 
1858  // Custom legalization on VVP_* and VEC_* opcodes is required to pack-legalize
1859  // these operations (transform nodes such that their AVL parameter refers to
1860  // packs of 64bit, instead of number of elements.
1861 
1862  // Packing opcodes are created with a pack-legal AVL (LEGALAVL). No need to
1863  // re-visit them.
1864  if (isPackingSupportOpcode(Op.getOpcode()))
1865  return Legal;
1866 
1867  // Custom lower to legalize AVL for packed mode.
1868  if (isVVPOrVEC(Op.getOpcode()))
1869  return Custom;
1870  return Legal;
1871 }
1872 
1874  LLVM_DEBUG(dbgs() << "::LowerOperation"; Op->print(dbgs()););
1875  unsigned Opcode = Op.getOpcode();
1876 
1877  /// Scalar isel.
1878  switch (Opcode) {
1879  case ISD::ATOMIC_FENCE:
1880  return lowerATOMIC_FENCE(Op, DAG);
1881  case ISD::ATOMIC_SWAP:
1882  return lowerATOMIC_SWAP(Op, DAG);
1883  case ISD::BlockAddress:
1884  return lowerBlockAddress(Op, DAG);
1885  case ISD::ConstantPool:
1886  return lowerConstantPool(Op, DAG);
1888  return lowerDYNAMIC_STACKALLOC(Op, DAG);
1889  case ISD::EH_SJLJ_LONGJMP:
1890  return lowerEH_SJLJ_LONGJMP(Op, DAG);
1891  case ISD::EH_SJLJ_SETJMP:
1892  return lowerEH_SJLJ_SETJMP(Op, DAG);
1894  return lowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
1895  case ISD::FRAMEADDR:
1896  return lowerFRAMEADDR(Op, DAG, *this, Subtarget);
1897  case ISD::GlobalAddress:
1898  return lowerGlobalAddress(Op, DAG);
1899  case ISD::GlobalTLSAddress:
1900  return lowerGlobalTLSAddress(Op, DAG);
1902  return lowerINTRINSIC_WO_CHAIN(Op, DAG);
1903  case ISD::JumpTable:
1904  return lowerJumpTable(Op, DAG);
1905  case ISD::LOAD:
1906  return lowerLOAD(Op, DAG);
1907  case ISD::RETURNADDR:
1908  return lowerRETURNADDR(Op, DAG, *this, Subtarget);
1909  case ISD::BUILD_VECTOR:
1910  return lowerBUILD_VECTOR(Op, DAG);
1911  case ISD::STORE:
1912  return lowerSTORE(Op, DAG);
1913  case ISD::VASTART:
1914  return lowerVASTART(Op, DAG);
1915  case ISD::VAARG:
1916  return lowerVAARG(Op, DAG);
1917 
1919  return lowerINSERT_VECTOR_ELT(Op, DAG);
1921  return lowerEXTRACT_VECTOR_ELT(Op, DAG);
1922  }
1923 
1924  /// Vector isel.
1925  LLVM_DEBUG(dbgs() << "::LowerOperation_VVP"; Op->print(dbgs()););
1926  if (ISD::isVPOpcode(Opcode))
1927  return lowerToVVP(Op, DAG);
1928 
1929  switch (Opcode) {
1930  default:
1931  llvm_unreachable("Should not custom lower this!");
1932 
1933  // Legalize the AVL of this internal node.
1934  case VEISD::VEC_BROADCAST:
1935 #define ADD_VVP_OP(VVP_NAME, ...) case VEISD::VVP_NAME:
1936 #include "VVPNodes.def"
1937  // AVL already legalized.
1938  if (getAnnotatedNodeAVL(Op).second)
1939  return Op;
1940  return legalizeInternalVectorOp(Op, DAG);
1941 
1942  // Translate into a VEC_*/VVP_* layer operation.
1943  case ISD::MLOAD:
1944  case ISD::MSTORE:
1945 #define ADD_VVP_OP(VVP_NAME, ISD_NAME) case ISD::ISD_NAME:
1946 #include "VVPNodes.def"
1947  if (isMaskArithmetic(Op) && isPackedVectorType(Op.getValueType()))
1948  return splitMaskArithmetic(Op, DAG);
1949  return lowerToVVP(Op, DAG);
1950  }
1951 }
1952 /// } Custom Lower
1953 
1956  SelectionDAG &DAG) const {
1957  switch (N->getOpcode()) {
1958  case ISD::ATOMIC_SWAP:
1959  // Let LLVM expand atomic swap instruction through LowerOperation.
1960  return;
1961  default:
1962  LLVM_DEBUG(N->dumpr(&DAG));
1963  llvm_unreachable("Do not know how to custom type legalize this operation!");
1964  }
1965 }
1966 
1967 /// JumpTable for VE.
1968 ///
1969 /// VE cannot generate relocatable symbol in jump table. VE cannot
1970 /// generate expressions using symbols in both text segment and data
1971 /// segment like below.
1972 /// .4byte .LBB0_2-.LJTI0_0
1973 /// So, we generate offset from the top of function like below as
1974 /// a custom label.
1975 /// .4byte .LBB0_2-<function name>
1976 
1978  // Use custom label for PIC.
1979  if (isPositionIndependent())
1981 
1982  // Otherwise, use the normal jump table encoding heuristics.
1984 }
1985 
1987  const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB,
1988  unsigned Uid, MCContext &Ctx) const {
1990 
1991  // Generate custom label for PIC like below.
1992  // .4bytes .LBB0_2-<function name>
1993  const auto *Value = MCSymbolRefExpr::create(MBB->getSymbol(), Ctx);
1994  MCSymbol *Sym = Ctx.getOrCreateSymbol(MBB->getParent()->getName().data());
1995  const auto *Base = MCSymbolRefExpr::create(Sym, Ctx);
1996  return MCBinaryExpr::createSub(Value, Base, Ctx);
1997 }
1998 
2000  SelectionDAG &DAG) const {
2002  SDLoc DL(Table);
2004  assert(Function != nullptr);
2005  auto PtrTy = getPointerTy(DAG.getDataLayout(), Function->getAddressSpace());
2006 
2007  // In the jump table, we have following values in PIC mode.
2008  // .4bytes .LBB0_2-<function name>
2009  // We need to add this value and the address of this function to generate
2010  // .LBB0_2 label correctly under PIC mode. So, we want to generate following
2011  // instructions:
2012  // lea %reg, fun@gotoff_lo
2013  // and %reg, %reg, (32)0
2014  // lea.sl %reg, fun@gotoff_hi(%reg, %got)
2015  // In order to do so, we need to genarate correctly marked DAG node using
2016  // makeHiLoPair.
2017  SDValue Op = DAG.getGlobalAddress(Function, DL, PtrTy);
2020  SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, PtrTy);
2021  return DAG.getNode(ISD::ADD, DL, PtrTy, GlobalBase, HiLo);
2022 }
2023 
2026  MachineBasicBlock *TargetBB,
2027  const DebugLoc &DL) const {
2028  MachineFunction *MF = MBB.getParent();
2030  const VEInstrInfo *TII = Subtarget->getInstrInfo();
2031 
2032  const TargetRegisterClass *RC = &VE::I64RegClass;
2033  Register Tmp1 = MRI.createVirtualRegister(RC);
2034  Register Tmp2 = MRI.createVirtualRegister(RC);
2035  Register Result = MRI.createVirtualRegister(RC);
2036 
2037  if (isPositionIndependent()) {
2038  // Create following instructions for local linkage PIC code.
2039  // lea %Tmp1, TargetBB@gotoff_lo
2040  // and %Tmp2, %Tmp1, (32)0
2041  // lea.sl %Result, TargetBB@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
2042  BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1)
2043  .addImm(0)
2044  .addImm(0)
2045  .addMBB(TargetBB, VEMCExpr::VK_VE_GOTOFF_LO32);
2046  BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2)
2047  .addReg(Tmp1, getKillRegState(true))
2048  .addImm(M0(32));
2049  BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Result)
2050  .addReg(VE::SX15)
2051  .addReg(Tmp2, getKillRegState(true))
2052  .addMBB(TargetBB, VEMCExpr::VK_VE_GOTOFF_HI32);
2053  } else {
2054  // Create following instructions for non-PIC code.
2055  // lea %Tmp1, TargetBB@lo
2056  // and %Tmp2, %Tmp1, (32)0
2057  // lea.sl %Result, TargetBB@hi(%Tmp2)
2058  BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1)
2059  .addImm(0)
2060  .addImm(0)
2061  .addMBB(TargetBB, VEMCExpr::VK_VE_LO32);
2062  BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2)
2063  .addReg(Tmp1, getKillRegState(true))
2064  .addImm(M0(32));
2065  BuildMI(MBB, I, DL, TII->get(VE::LEASLrii), Result)
2066  .addReg(Tmp2, getKillRegState(true))
2067  .addImm(0)
2068  .addMBB(TargetBB, VEMCExpr::VK_VE_HI32);
2069  }
2070  return Result;
2071 }
2072 
2075  StringRef Symbol, const DebugLoc &DL,
2076  bool IsLocal = false,
2077  bool IsCall = false) const {
2078  MachineFunction *MF = MBB.getParent();
2080  const VEInstrInfo *TII = Subtarget->getInstrInfo();
2081 
2082  const TargetRegisterClass *RC = &VE::I64RegClass;
2083  Register Result = MRI.createVirtualRegister(RC);
2084 
2085  if (isPositionIndependent()) {
2086  if (IsCall && !IsLocal) {
2087  // Create following instructions for non-local linkage PIC code function
2088  // calls. These instructions uses IC and magic number -24, so we expand
2089  // them in VEAsmPrinter.cpp from GETFUNPLT pseudo instruction.
2090  // lea %Reg, Symbol@plt_lo(-24)
2091  // and %Reg, %Reg, (32)0
2092  // sic %s16
2093  // lea.sl %Result, Symbol@plt_hi(%Reg, %s16) ; %s16 is PLT
2094  BuildMI(MBB, I, DL, TII->get(VE::GETFUNPLT), Result)
2095  .addExternalSymbol("abort");
2096  } else if (IsLocal) {
2097  Register Tmp1 = MRI.createVirtualRegister(RC);
2098  Register Tmp2 = MRI.createVirtualRegister(RC);
2099  // Create following instructions for local linkage PIC code.
2100  // lea %Tmp1, Symbol@gotoff_lo
2101  // and %Tmp2, %Tmp1, (32)0
2102  // lea.sl %Result, Symbol@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
2103  BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1)
2104  .addImm(0)
2105  .addImm(0)
2107  BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2)
2108  .addReg(Tmp1, getKillRegState(true))
2109  .addImm(M0(32));
2110  BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Result)
2111  .addReg(VE::SX15)
2112  .addReg(Tmp2, getKillRegState(true))
2114  } else {
2115  Register Tmp1 = MRI.createVirtualRegister(RC);
2116  Register Tmp2 = MRI.createVirtualRegister(RC);
2117  // Create following instructions for not local linkage PIC code.
2118  // lea %Tmp1, Symbol@got_lo
2119  // and %Tmp2, %Tmp1, (32)0
2120  // lea.sl %Tmp3, Symbol@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
2121  // ld %Result, 0(%Tmp3)
2122  Register Tmp3 = MRI.createVirtualRegister(RC);
2123  BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1)
2124  .addImm(0)
2125  .addImm(0)
2127  BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2)
2128  .addReg(Tmp1, getKillRegState(true))
2129  .addImm(M0(32));
2130  BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Tmp3)
2131  .addReg(VE::SX15)
2132  .addReg(Tmp2, getKillRegState(true))
2134  BuildMI(MBB, I, DL, TII->get(VE::LDrii), Result)
2135  .addReg(Tmp3, getKillRegState(true))
2136  .addImm(0)
2137  .addImm(0);
2138  }
2139  } else {
2140  Register Tmp1 = MRI.createVirtualRegister(RC);
2141  Register Tmp2 = MRI.createVirtualRegister(RC);
2142  // Create following instructions for non-PIC code.
2143  // lea %Tmp1, Symbol@lo
2144  // and %Tmp2, %Tmp1, (32)0
2145  // lea.sl %Result, Symbol@hi(%Tmp2)
2146  BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1)
2147  .addImm(0)
2148  .addImm(0)
2149  .addExternalSymbol(Symbol.data(), VEMCExpr::VK_VE_LO32);
2150  BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2)
2151  .addReg(Tmp1, getKillRegState(true))
2152  .addImm(M0(32));
2153  BuildMI(MBB, I, DL, TII->get(VE::LEASLrii), Result)
2154  .addReg(Tmp2, getKillRegState(true))
2155  .addImm(0)
2156  .addExternalSymbol(Symbol.data(), VEMCExpr::VK_VE_HI32);
2157  }
2158  return Result;
2159 }
2160 
2163  MachineBasicBlock *DispatchBB,
2164  int FI, int Offset) const {
2165  DebugLoc DL = MI.getDebugLoc();
2166  const VEInstrInfo *TII = Subtarget->getInstrInfo();
2167 
2168  Register LabelReg =
2169  prepareMBB(*MBB, MachineBasicBlock::iterator(MI), DispatchBB, DL);
2170 
2171  // Store an address of DispatchBB to a given jmpbuf[1] where has next IC
2172  // referenced by longjmp (throw) later.
2173  MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii));
2174  addFrameReference(MIB, FI, Offset); // jmpbuf[1]
2175  MIB.addReg(LabelReg, getKillRegState(true));
2176 }
2177 
2180  MachineBasicBlock *MBB) const {
2181  DebugLoc DL = MI.getDebugLoc();
2182  MachineFunction *MF = MBB->getParent();
2183  const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2184  const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
2186 
2187  const BasicBlock *BB = MBB->getBasicBlock();
2189 
2190  // Memory Reference.
2191  SmallVector<MachineMemOperand *, 2> MMOs(MI.memoperands_begin(),
2192  MI.memoperands_end());
2193  Register BufReg = MI.getOperand(1).getReg();
2194 
2195  Register DstReg;
2196 
2197  DstReg = MI.getOperand(0).getReg();
2198  const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
2199  assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!");
2200  (void)TRI;
2201  Register MainDestReg = MRI.createVirtualRegister(RC);
2202  Register RestoreDestReg = MRI.createVirtualRegister(RC);
2203 
2204  // For `v = call @llvm.eh.sjlj.setjmp(buf)`, we generate following
2205  // instructions. SP/FP must be saved in jmpbuf before `llvm.eh.sjlj.setjmp`.
2206  //
2207  // ThisMBB:
2208  // buf[3] = %s17 iff %s17 is used as BP
2209  // buf[1] = RestoreMBB as IC after longjmp
2210  // # SjLjSetup RestoreMBB
2211  //
2212  // MainMBB:
2213  // v_main = 0
2214  //
2215  // SinkMBB:
2216  // v = phi(v_main, MainMBB, v_restore, RestoreMBB)
2217  // ...
2218  //
2219  // RestoreMBB:
2220  // %s17 = buf[3] = iff %s17 is used as BP
2221  // v_restore = 1
2222  // goto SinkMBB
2223 
2224  MachineBasicBlock *ThisMBB = MBB;
2227  MachineBasicBlock *RestoreMBB = MF->CreateMachineBasicBlock(BB);
2228  MF->insert(I, MainMBB);
2229  MF->insert(I, SinkMBB);
2230  MF->push_back(RestoreMBB);
2231  RestoreMBB->setMachineBlockAddressTaken();
2232 
2233  // Transfer the remainder of BB and its successor edges to SinkMBB.
2234  SinkMBB->splice(SinkMBB->begin(), MBB,
2235  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
2237 
2238  // ThisMBB:
2239  Register LabelReg =
2240  prepareMBB(*MBB, MachineBasicBlock::iterator(MI), RestoreMBB, DL);
2241 
2242  // Store BP in buf[3] iff this function is using BP.
2243  const VEFrameLowering *TFI = Subtarget->getFrameLowering();
2244  if (TFI->hasBP(*MF)) {
2245  MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii));
2246  MIB.addReg(BufReg);
2247  MIB.addImm(0);
2248  MIB.addImm(24);
2249  MIB.addReg(VE::SX17);
2250  MIB.setMemRefs(MMOs);
2251  }
2252 
2253  // Store IP in buf[1].
2254  MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii));
2255  MIB.add(MI.getOperand(1)); // we can preserve the kill flags here.
2256  MIB.addImm(0);
2257  MIB.addImm(8);
2258  MIB.addReg(LabelReg, getKillRegState(true));
2259  MIB.setMemRefs(MMOs);
2260 
2261  // SP/FP are already stored in jmpbuf before `llvm.eh.sjlj.setjmp`.
2262 
2263  // Insert setup.
2264  MIB =
2265  BuildMI(*ThisMBB, MI, DL, TII->get(VE::EH_SjLj_Setup)).addMBB(RestoreMBB);
2266 
2267  const VERegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2268  MIB.addRegMask(RegInfo->getNoPreservedMask());
2269  ThisMBB->addSuccessor(MainMBB);
2270  ThisMBB->addSuccessor(RestoreMBB);
2271 
2272  // MainMBB:
2273  BuildMI(MainMBB, DL, TII->get(VE::LEAzii), MainDestReg)
2274  .addImm(0)
2275  .addImm(0)
2276  .addImm(0);
2277  MainMBB->addSuccessor(SinkMBB);
2278 
2279  // SinkMBB:
2280  BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII->get(VE::PHI), DstReg)
2281  .addReg(MainDestReg)
2282  .addMBB(MainMBB)
2283  .addReg(RestoreDestReg)
2284  .addMBB(RestoreMBB);
2285 
2286  // RestoreMBB:
2287  // Restore BP from buf[3] iff this function is using BP. The address of
2288  // buf is in SX10.
2289  // FIXME: Better to not use SX10 here
2290  if (TFI->hasBP(*MF)) {
2291  MachineInstrBuilder MIB =
2292  BuildMI(RestoreMBB, DL, TII->get(VE::LDrii), VE::SX17);
2293  MIB.addReg(VE::SX10);
2294  MIB.addImm(0);
2295  MIB.addImm(24);
2296  MIB.setMemRefs(MMOs);
2297  }
2298  BuildMI(RestoreMBB, DL, TII->get(VE::LEAzii), RestoreDestReg)
2299  .addImm(0)
2300  .addImm(0)
2301  .addImm(1);
2302  BuildMI(RestoreMBB, DL, TII->get(VE::BRCFLa_t)).addMBB(SinkMBB);
2303  RestoreMBB->addSuccessor(SinkMBB);
2304 
2305  MI.eraseFromParent();
2306  return SinkMBB;
2307 }
2308 
2311  MachineBasicBlock *MBB) const {
2312  DebugLoc DL = MI.getDebugLoc();
2313  MachineFunction *MF = MBB->getParent();
2314  const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2316 
2317  // Memory Reference.
2318  SmallVector<MachineMemOperand *, 2> MMOs(MI.memoperands_begin(),
2319  MI.memoperands_end());
2320  Register BufReg = MI.getOperand(0).getReg();
2321 
2322  Register Tmp = MRI.createVirtualRegister(&VE::I64RegClass);
2323  // Since FP is only updated here but NOT referenced, it's treated as GPR.
2324  Register FP = VE::SX9;
2325  Register SP = VE::SX11;
2326 
2327  MachineInstrBuilder MIB;
2328 
2329  MachineBasicBlock *ThisMBB = MBB;
2330 
2331  // For `call @llvm.eh.sjlj.longjmp(buf)`, we generate following instructions.
2332  //
2333  // ThisMBB:
2334  // %fp = load buf[0]
2335  // %jmp = load buf[1]
2336  // %s10 = buf ; Store an address of buf to SX10 for RestoreMBB
2337  // %sp = load buf[2] ; generated by llvm.eh.sjlj.setjmp.
2338  // jmp %jmp
2339 
2340  // Reload FP.
2341  MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), FP);
2342  MIB.addReg(BufReg);
2343  MIB.addImm(0);
2344  MIB.addImm(0);
2345  MIB.setMemRefs(MMOs);
2346 
2347  // Reload IP.
2348  MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), Tmp);
2349  MIB.addReg(BufReg);
2350  MIB.addImm(0);
2351  MIB.addImm(8);
2352  MIB.setMemRefs(MMOs);
2353 
2354  // Copy BufReg to SX10 for later use in setjmp.
2355  // FIXME: Better to not use SX10 here
2356  BuildMI(*ThisMBB, MI, DL, TII->get(VE::ORri), VE::SX10)
2357  .addReg(BufReg)
2358  .addImm(0);
2359 
2360  // Reload SP.
2361  MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), SP);
2362  MIB.add(MI.getOperand(0)); // we can preserve the kill flags here.
2363  MIB.addImm(0);
2364  MIB.addImm(16);
2365  MIB.setMemRefs(MMOs);
2366 
2367  // Jump.
2368  BuildMI(*ThisMBB, MI, DL, TII->get(VE::BCFLari_t))
2369  .addReg(Tmp, getKillRegState(true))
2370  .addImm(0);
2371 
2372  MI.eraseFromParent();
2373  return ThisMBB;
2374 }
2375 
2378  MachineBasicBlock *BB) const {
2379  DebugLoc DL = MI.getDebugLoc();
2380  MachineFunction *MF = BB->getParent();
2381  MachineFrameInfo &MFI = MF->getFrameInfo();
2383  const VEInstrInfo *TII = Subtarget->getInstrInfo();
2384  int FI = MFI.getFunctionContextIndex();
2385 
2386  // Get a mapping of the call site numbers to all of the landing pads they're
2387  // associated with.
2389  unsigned MaxCSNum = 0;
2390  for (auto &MBB : *MF) {
2391  if (!MBB.isEHPad())
2392  continue;
2393 
2394  MCSymbol *Sym = nullptr;
2395  for (const auto &MI : MBB) {
2396  if (MI.isDebugInstr())
2397  continue;
2398 
2399  assert(MI.isEHLabel() && "expected EH_LABEL");
2400  Sym = MI.getOperand(0).getMCSymbol();
2401  break;
2402  }
2403 
2404  if (!MF->hasCallSiteLandingPad(Sym))
2405  continue;
2406 
2407  for (unsigned CSI : MF->getCallSiteLandingPad(Sym)) {
2408  CallSiteNumToLPad[CSI].push_back(&MBB);
2409  MaxCSNum = std::max(MaxCSNum, CSI);
2410  }
2411  }
2412 
2413  // Get an ordered list of the machine basic blocks for the jump table.
2414  std::vector<MachineBasicBlock *> LPadList;
2416  LPadList.reserve(CallSiteNumToLPad.size());
2417 
2418  for (unsigned CSI = 1; CSI <= MaxCSNum; ++CSI) {
2419  for (auto &LP : CallSiteNumToLPad[CSI]) {
2420  LPadList.push_back(LP);
2421  InvokeBBs.insert(LP->pred_begin(), LP->pred_end());
2422  }
2423  }
2424 
2425  assert(!LPadList.empty() &&
2426  "No landing pad destinations for the dispatch jump table!");
2427 
2428  // The %fn_context is allocated like below (from --print-after=sjljehprepare):
2429  // %fn_context = alloca { i8*, i64, [4 x i64], i8*, i8*, [5 x i8*] }
2430  //
2431  // This `[5 x i8*]` is jmpbuf, so jmpbuf[1] is FI+72.
2432  // First `i64` is callsite, so callsite is FI+8.
2433  static const int OffsetIC = 72;
2434  static const int OffsetCS = 8;
2435 
2436  // Create the MBBs for the dispatch code like following:
2437  //
2438  // ThisMBB:
2439  // Prepare DispatchBB address and store it to buf[1].
2440  // ...
2441  //
2442  // DispatchBB:
2443  // %s15 = GETGOT iff isPositionIndependent
2444  // %callsite = load callsite
2445  // brgt.l.t #size of callsites, %callsite, DispContBB
2446  //
2447  // TrapBB:
2448  // Call abort.
2449  //
2450  // DispContBB:
2451  // %breg = address of jump table
2452  // %pc = load and calculate next pc from %breg and %callsite
2453  // jmp %pc
2454 
2455  // Shove the dispatch's address into the return slot in the function context.
2456  MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
2457  DispatchBB->setIsEHPad(true);
2458 
2459  // Trap BB will causes trap like `assert(0)`.
2460  MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
2461  DispatchBB->addSuccessor(TrapBB);
2462 
2463  MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
2464  DispatchBB->addSuccessor(DispContBB);
2465 
2466  // Insert MBBs.
2467  MF->push_back(DispatchBB);
2468  MF->push_back(DispContBB);
2469  MF->push_back(TrapBB);
2470 
2471  // Insert code to call abort in the TrapBB.
2472  Register Abort = prepareSymbol(*TrapBB, TrapBB->end(), "abort", DL,
2473  /* Local */ false, /* Call */ true);
2474  BuildMI(TrapBB, DL, TII->get(VE::BSICrii), VE::SX10)
2475  .addReg(Abort, getKillRegState(true))
2476  .addImm(0)
2477  .addImm(0);
2478 
2479  // Insert code into the entry block that creates and registers the function
2480  // context.
2481  setupEntryBlockForSjLj(MI, BB, DispatchBB, FI, OffsetIC);
2482 
2483  // Create the jump table and associated information
2484  unsigned JTE = getJumpTableEncoding();
2485  MachineJumpTableInfo *JTI = MF->getOrCreateJumpTableInfo(JTE);
2486  unsigned MJTI = JTI->createJumpTableIndex(LPadList);
2487 
2488  const VERegisterInfo &RI = TII->getRegisterInfo();
2489  // Add a register mask with no preserved registers. This results in all
2490  // registers being marked as clobbered.
2491  BuildMI(DispatchBB, DL, TII->get(VE::NOP))
2493 
2494  if (isPositionIndependent()) {
2495  // Force to generate GETGOT, since current implementation doesn't store GOT
2496  // register.
2497  BuildMI(DispatchBB, DL, TII->get(VE::GETGOT), VE::SX15);
2498  }
2499 
2500  // IReg is used as an index in a memory operand and therefore can't be SP
2501  const TargetRegisterClass *RC = &VE::I64RegClass;
2502  Register IReg = MRI.createVirtualRegister(RC);
2503  addFrameReference(BuildMI(DispatchBB, DL, TII->get(VE::LDLZXrii), IReg), FI,
2504  OffsetCS);
2505  if (LPadList.size() < 64) {
2506  BuildMI(DispatchBB, DL, TII->get(VE::BRCFLir_t))
2508  .addImm(LPadList.size())
2509  .addReg(IReg)
2510  .addMBB(TrapBB);
2511  } else {
2512  assert(LPadList.size() <= 0x7FFFFFFF && "Too large Landing Pad!");
2513  Register TmpReg = MRI.createVirtualRegister(RC);
2514  BuildMI(DispatchBB, DL, TII->get(VE::LEAzii), TmpReg)
2515  .addImm(0)
2516  .addImm(0)
2517  .addImm(LPadList.size());
2518  BuildMI(DispatchBB, DL, TII->get(VE::BRCFLrr_t))
2520  .addReg(TmpReg, getKillRegState(true))
2521  .addReg(IReg)
2522  .addMBB(TrapBB);
2523  }
2524 
2525  Register BReg = MRI.createVirtualRegister(RC);
2526  Register Tmp1 = MRI.createVirtualRegister(RC);
2527  Register Tmp2 = MRI.createVirtualRegister(RC);
2528 
2529  if (isPositionIndependent()) {
2530  // Create following instructions for local linkage PIC code.
2531  // lea %Tmp1, .LJTI0_0@gotoff_lo
2532  // and %Tmp2, %Tmp1, (32)0
2533  // lea.sl %BReg, .LJTI0_0@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
2534  BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1)
2535  .addImm(0)
2536  .addImm(0)
2538  BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2)
2539  .addReg(Tmp1, getKillRegState(true))
2540  .addImm(M0(32));
2541  BuildMI(DispContBB, DL, TII->get(VE::LEASLrri), BReg)
2542  .addReg(VE::SX15)
2543  .addReg(Tmp2, getKillRegState(true))
2545  } else {
2546  // Create following instructions for non-PIC code.
2547  // lea %Tmp1, .LJTI0_0@lo
2548  // and %Tmp2, %Tmp1, (32)0
2549  // lea.sl %BReg, .LJTI0_0@hi(%Tmp2)
2550  BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1)
2551  .addImm(0)
2552  .addImm(0)
2554  BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2)
2555  .addReg(Tmp1, getKillRegState(true))
2556  .addImm(M0(32));
2557  BuildMI(DispContBB, DL, TII->get(VE::LEASLrii), BReg)
2558  .addReg(Tmp2, getKillRegState(true))
2559  .addImm(0)
2561  }
2562 
2563  switch (JTE) {
2565  // Generate simple block address code for no-PIC model.
2566  // sll %Tmp1, %IReg, 3
2567  // lds %TReg, 0(%Tmp1, %BReg)
2568  // bcfla %TReg
2569 
2570  Register TReg = MRI.createVirtualRegister(RC);
2571  Register Tmp1 = MRI.createVirtualRegister(RC);
2572 
2573  BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1)
2574  .addReg(IReg, getKillRegState(true))
2575  .addImm(3);
2576  BuildMI(DispContBB, DL, TII->get(VE::LDrri), TReg)
2577  .addReg(BReg, getKillRegState(true))
2578  .addReg(Tmp1, getKillRegState(true))
2579  .addImm(0);
2580  BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t))
2581  .addReg(TReg, getKillRegState(true))
2582  .addImm(0);
2583  break;
2584  }
2586  // Generate block address code using differences from the function pointer
2587  // for PIC model.
2588  // sll %Tmp1, %IReg, 2
2589  // ldl.zx %OReg, 0(%Tmp1, %BReg)
2590  // Prepare function address in BReg2.
2591  // adds.l %TReg, %BReg2, %OReg
2592  // bcfla %TReg
2593 
2595  Register OReg = MRI.createVirtualRegister(RC);
2596  Register TReg = MRI.createVirtualRegister(RC);
2597  Register Tmp1 = MRI.createVirtualRegister(RC);
2598 
2599  BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1)
2600  .addReg(IReg, getKillRegState(true))
2601  .addImm(2);
2602  BuildMI(DispContBB, DL, TII->get(VE::LDLZXrri), OReg)
2603  .addReg(BReg, getKillRegState(true))
2604  .addReg(Tmp1, getKillRegState(true))
2605  .addImm(0);
2606  Register BReg2 =
2607  prepareSymbol(*DispContBB, DispContBB->end(),
2608  DispContBB->getParent()->getName(), DL, /* Local */ true);
2609  BuildMI(DispContBB, DL, TII->get(VE::ADDSLrr), TReg)
2610  .addReg(OReg, getKillRegState(true))
2611  .addReg(BReg2, getKillRegState(true));
2612  BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t))
2613  .addReg(TReg, getKillRegState(true))
2614  .addImm(0);
2615  break;
2616  }
2617  default:
2618  llvm_unreachable("Unexpected jump table encoding");
2619  }
2620 
2621  // Add the jump table entries as successors to the MBB.
2623  for (auto &LP : LPadList)
2624  if (SeenMBBs.insert(LP).second)
2625  DispContBB->addSuccessor(LP);
2626 
2627  // N.B. the order the invoke BBs are processed in doesn't matter here.
2629  const MCPhysReg *SavedRegs = MF->getRegInfo().getCalleeSavedRegs();
2630  for (MachineBasicBlock *MBB : InvokeBBs) {
2631  // Remove the landing pad successor from the invoke block and replace it
2632  // with the new dispatch block.
2633  // Keep a copy of Successors since it's modified inside the loop.
2635  MBB->succ_rend());
2636  // FIXME: Avoid quadratic complexity.
2637  for (auto *MBBS : Successors) {
2638  if (MBBS->isEHPad()) {
2639  MBB->removeSuccessor(MBBS);
2640  MBBLPads.push_back(MBBS);
2641  }
2642  }
2643 
2644  MBB->addSuccessor(DispatchBB);
2645 
2646  // Find the invoke call and mark all of the callee-saved registers as
2647  // 'implicit defined' so that they're spilled. This prevents code from
2648  // moving instructions to before the EH block, where they will never be
2649  // executed.
2650  for (auto &II : reverse(*MBB)) {
2651  if (!II.isCall())
2652  continue;
2653 
2654  DenseMap<Register, bool> DefRegs;
2655  for (auto &MOp : II.operands())
2656  if (MOp.isReg())
2657  DefRegs[MOp.getReg()] = true;
2658 
2659  MachineInstrBuilder MIB(*MF, &II);
2660  for (unsigned RI = 0; SavedRegs[RI]; ++RI) {
2661  Register Reg = SavedRegs[RI];
2662  if (!DefRegs[Reg])
2664  }
2665 
2666  break;
2667  }
2668  }
2669 
2670  // Mark all former landing pads as non-landing pads. The dispatch is the only
2671  // landing pad now.
2672  for (auto &LP : MBBLPads)
2673  LP->setIsEHPad(false);
2674 
2675  // The instruction is gone now.
2676  MI.eraseFromParent();
2677  return BB;
2678 }
2679 
2682  MachineBasicBlock *BB) const {
2683  switch (MI.getOpcode()) {
2684  default:
2685  llvm_unreachable("Unknown Custom Instruction!");
2686  case VE::EH_SjLj_LongJmp:
2687  return emitEHSjLjLongJmp(MI, BB);
2688  case VE::EH_SjLj_SetJmp:
2689  return emitEHSjLjSetJmp(MI, BB);
2690  case VE::EH_SjLj_Setup_Dispatch:
2691  return emitSjLjDispatchBlock(MI, BB);
2692  }
2693 }
2694 
2695 static bool isSimm7(SDValue V) {
2696  EVT VT = V.getValueType();
2697  if (VT.isVector())
2698  return false;
2699 
2700  if (VT.isInteger()) {
2701  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(V))
2702  return isInt<7>(C->getSExtValue());
2703  } else if (VT.isFloatingPoint()) {
2704  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(V)) {
2705  if (VT == MVT::f32 || VT == MVT::f64) {
2706  const APInt &Imm = C->getValueAPF().bitcastToAPInt();
2707  uint64_t Val = Imm.getSExtValue();
2708  if (Imm.getBitWidth() == 32)
2709  Val <<= 32; // Immediate value of float place at higher bits on VE.
2710  return isInt<7>(Val);
2711  }
2712  }
2713  }
2714  return false;
2715 }
2716 
2717 static bool isMImm(SDValue V) {
2718  EVT VT = V.getValueType();
2719  if (VT.isVector())
2720  return false;
2721 
2722  if (VT.isInteger()) {
2723  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(V))
2724  return isMImmVal(getImmVal(C));
2725  } else if (VT.isFloatingPoint()) {
2726  if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(V)) {
2727  if (VT == MVT::f32) {
2728  // Float value places at higher bits, so ignore lower 32 bits.
2729  return isMImm32Val(getFpImmVal(C) >> 32);
2730  } else if (VT == MVT::f64) {
2731  return isMImmVal(getFpImmVal(C));
2732  }
2733  }
2734  }
2735  return false;
2736 }
2737 
2738 static unsigned decideComp(EVT SrcVT, ISD::CondCode CC) {
2739  if (SrcVT.isFloatingPoint()) {
2740  if (SrcVT == MVT::f128)
2741  return VEISD::CMPQ;
2742  return VEISD::CMPF;
2743  }
2745 }
2746 
2747 static EVT decideCompType(EVT SrcVT) {
2748  if (SrcVT == MVT::f128)
2749  return MVT::f64;
2750  return SrcVT;
2751 }
2752 
2754  bool WithCMov) {
2755  if (SrcVT.isFloatingPoint()) {
2756  // For the case of floating point setcc, only unordered comparison
2757  // or general comparison with -enable-no-nans-fp-math option reach
2758  // here, so it is safe even if values are NaN. Only f128 doesn't
2759  // safe since VE uses f64 result of f128 comparison.
2760  return SrcVT != MVT::f128;
2761  }
2762  if (isIntEqualitySetCC(CC)) {
2763  // For the case of equal or not equal, it is safe without comparison with 0.
2764  return true;
2765  }
2766  if (WithCMov) {
2767  // For the case of integer setcc with cmov, all signed comparison with 0
2768  // are safe.
2769  return isSignedIntSetCC(CC);
2770  }
2771  // For the case of integer setcc, only signed 64 bits comparison is safe.
2772  // For unsigned, "CMPU 0x80000000, 0" has to be greater than 0, but it becomes
2773  // less than 0 witout CMPU. For 32 bits, other half of 32 bits are
2774  // uncoditional, so it is not safe too without CMPI..
2775  return isSignedIntSetCC(CC) && SrcVT == MVT::i64;
2776 }
2777 
2779  ISD::CondCode CC, bool WithCMov,
2780  const SDLoc &DL, SelectionDAG &DAG) {
2781  // Compare values. If RHS is 0 and it is safe to calculate without
2782  // comparison, we don't generate an instruction for comparison.
2783  EVT CompVT = decideCompType(VT);
2784  if (CompVT == VT && safeWithoutCompWithNull(VT, CC, WithCMov) &&
2786  return LHS;
2787  }
2788  return DAG.getNode(decideComp(VT, CC), DL, CompVT, LHS, RHS);
2789 }
2790 
2792  DAGCombinerInfo &DCI) const {
2793  assert(N->getOpcode() == ISD::SELECT &&
2794  "Should be called with a SELECT node");
2796  SDValue Cond = N->getOperand(0);
2797  SDValue True = N->getOperand(1);
2798  SDValue False = N->getOperand(2);
2799 
2800  // We handle only scalar SELECT.
2801  EVT VT = N->getValueType(0);
2802  if (VT.isVector())
2803  return SDValue();
2804 
2805  // Peform combineSelect after leagalize DAG.
2806  if (!DCI.isAfterLegalizeDAG())
2807  return SDValue();
2808 
2809  EVT VT0 = Cond.getValueType();
2810  if (isMImm(True)) {
2811  // VE's condition move can handle MImm in True clause, so nothing to do.
2812  } else if (isMImm(False)) {
2813  // VE's condition move can handle MImm in True clause, so swap True and
2814  // False clauses if False has MImm value. And, update condition code.
2815  std::swap(True, False);
2816  CC = getSetCCInverse(CC, VT0);
2817  }
2818 
2819  SDLoc DL(N);
2820  SelectionDAG &DAG = DCI.DAG;
2821  VECC::CondCode VECCVal;
2822  if (VT0.isFloatingPoint()) {
2823  VECCVal = fpCondCode2Fcc(CC);
2824  } else {
2825  VECCVal = intCondCode2Icc(CC);
2826  }
2827  SDValue Ops[] = {Cond, True, False,
2828  DAG.getConstant(VECCVal, DL, MVT::i32)};
2829  return DAG.getNode(VEISD::CMOV, DL, VT, Ops);
2830 }
2831 
2833  DAGCombinerInfo &DCI) const {
2834  assert(N->getOpcode() == ISD::SELECT_CC &&
2835  "Should be called with a SELECT_CC node");
2836  ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
2837  SDValue LHS = N->getOperand(0);
2838  SDValue RHS = N->getOperand(1);
2839  SDValue True = N->getOperand(2);
2840  SDValue False = N->getOperand(3);
2841 
2842  // We handle only scalar SELECT_CC.
2843  EVT VT = N->getValueType(0);
2844  if (VT.isVector())
2845  return SDValue();
2846 
2847  // Peform combineSelectCC after leagalize DAG.
2848  if (!DCI.isAfterLegalizeDAG())
2849  return SDValue();
2850 
2851  // We handle only i32/i64/f32/f64/f128 comparisons.
2852  EVT LHSVT = LHS.getValueType();
2853  assert(LHSVT == RHS.getValueType());
2854  switch (LHSVT.getSimpleVT().SimpleTy) {
2855  case MVT::i32:
2856  case MVT::i64:
2857  case MVT::f32:
2858  case MVT::f64:
2859  case MVT::f128:
2860  break;
2861  default:
2862  // Return SDValue to let llvm handle other types.
2863  return SDValue();
2864  }
2865 
2866  if (isMImm(RHS)) {
2867  // VE's comparison can handle MImm in RHS, so nothing to do.
2868  } else if (isSimm7(RHS)) {
2869  // VE's comparison can handle Simm7 in LHS, so swap LHS and RHS, and
2870  // update condition code.
2871  std::swap(LHS, RHS);
2873  }
2874  if (isMImm(True)) {
2875  // VE's condition move can handle MImm in True clause, so nothing to do.
2876  } else if (isMImm(False)) {
2877  // VE's condition move can handle MImm in True clause, so swap True and
2878  // False clauses if False has MImm value. And, update condition code.
2879  std::swap(True, False);
2880  CC = getSetCCInverse(CC, LHSVT);
2881  }
2882 
2883  SDLoc DL(N);
2884  SelectionDAG &DAG = DCI.DAG;
2885 
2886  bool WithCMov = true;
2887  SDValue CompNode = generateComparison(LHSVT, LHS, RHS, CC, WithCMov, DL, DAG);
2888 
2889  VECC::CondCode VECCVal;
2890  if (LHSVT.isFloatingPoint()) {
2891  VECCVal = fpCondCode2Fcc(CC);
2892  } else {
2893  VECCVal = intCondCode2Icc(CC);
2894  }
2895  SDValue Ops[] = {CompNode, True, False,
2896  DAG.getConstant(VECCVal, DL, MVT::i32)};
2897  return DAG.getNode(VEISD::CMOV, DL, VT, Ops);
2898 }
2899 
2900 static bool isI32InsnAllUses(const SDNode *User, const SDNode *N);
2901 static bool isI32Insn(const SDNode *User, const SDNode *N) {
2902  switch (User->getOpcode()) {
2903  default:
2904  return false;
2905  case ISD::ADD:
2906  case ISD::SUB:
2907  case ISD::MUL:
2908  case ISD::SDIV:
2909  case ISD::UDIV:
2910  case ISD::SETCC:
2911  case ISD::SMIN:
2912  case ISD::SMAX:
2913  case ISD::SHL:
2914  case ISD::SRA:
2915  case ISD::BSWAP:
2916  case ISD::SINT_TO_FP:
2917  case ISD::UINT_TO_FP:
2918  case ISD::BR_CC:
2919  case ISD::BITCAST:
2920  case ISD::ATOMIC_CMP_SWAP:
2921  case ISD::ATOMIC_SWAP:
2922  case VEISD::CMPU:
2923  case VEISD::CMPI:
2924  return true;
2925  case ISD::SRL:
2926  if (N->getOperand(0).getOpcode() != ISD::SRL)
2927  return true;
2928  // (srl (trunc (srl ...))) may be optimized by combining srl, so
2929  // doesn't optimize trunc now.
2930  return false;
2931  case ISD::SELECT_CC:
2932  if (User->getOperand(2).getNode() != N &&
2933  User->getOperand(3).getNode() != N)
2934  return true;
2935  return isI32InsnAllUses(User, N);
2936  case VEISD::CMOV:
2937  // CMOV in (cmov (trunc ...), true, false, int-comparison) is safe.
2938  // However, trunc in true or false clauses is not safe.
2939  if (User->getOperand(1).getNode() != N &&
2940  User->getOperand(2).getNode() != N &&
2941  isa<ConstantSDNode>(User->getOperand(3))) {
2942  VECC::CondCode VECCVal = static_cast<VECC::CondCode>(
2943  cast<ConstantSDNode>(User->getOperand(3))->getZExtValue());
2944  return isIntVECondCode(VECCVal);
2945  }
2946  [[fallthrough]];
2947  case ISD::AND:
2948  case ISD::OR:
2949  case ISD::XOR:
2950  case ISD::SELECT:
2951  case ISD::CopyToReg:
2952  // Check all use of selections, bit operations, and copies. If all of them
2953  // are safe, optimize truncate to extract_subreg.
2954  return isI32InsnAllUses(User, N);
2955  }
2956 }
2957 
2958 static bool isI32InsnAllUses(const SDNode *User, const SDNode *N) {
2959  // Check all use of User node. If all of them are safe, optimize
2960  // truncate to extract_subreg.
2961  for (const SDNode *U : User->uses()) {
2962  switch (U->getOpcode()) {
2963  default:
2964  // If the use is an instruction which treats the source operand as i32,
2965  // it is safe to avoid truncate here.
2966  if (isI32Insn(U, N))
2967  continue;
2968  break;
2969  case ISD::ANY_EXTEND:
2970  case ISD::SIGN_EXTEND:
2971  case ISD::ZERO_EXTEND: {
2972  // Special optimizations to the combination of ext and trunc.
2973  // (ext ... (select ... (trunc ...))) is safe to avoid truncate here
2974  // since this truncate instruction clears higher 32 bits which is filled
2975  // by one of ext instructions later.
2976  assert(N->getValueType(0) == MVT::i32 &&
2977  "find truncate to not i32 integer");
2978  if (User->getOpcode() == ISD::SELECT_CC ||
2979  User->getOpcode() == ISD::SELECT || User->getOpcode() == VEISD::CMOV)
2980  continue;
2981  break;
2982  }
2983  }
2984  return false;
2985  }
2986  return true;
2987 }
2988 
2989 // Optimize TRUNCATE in DAG combining. Optimizing it in CUSTOM lower is
2990 // sometime too early. Optimizing it in DAG pattern matching in VEInstrInfo.td
2991 // is sometime too late. So, doing it at here.
2993  DAGCombinerInfo &DCI) const {
2994  assert(N->getOpcode() == ISD::TRUNCATE &&
2995  "Should be called with a TRUNCATE node");
2996 
2997  SelectionDAG &DAG = DCI.DAG;
2998  SDLoc DL(N);
2999  EVT VT = N->getValueType(0);
3000 
3001  // We prefer to do this when all types are legal.
3002  if (!DCI.isAfterLegalizeDAG())
3003  return SDValue();
3004 
3005  // Skip combine TRUNCATE atm if the operand of TRUNCATE might be a constant.
3006  if (N->getOperand(0)->getOpcode() == ISD::SELECT_CC &&
3007  isa<ConstantSDNode>(N->getOperand(0)->getOperand(0)) &&
3008  isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
3009  return SDValue();
3010 
3011  // Check all use of this TRUNCATE.
3012  for (const SDNode *User : N->uses()) {
3013  // Make sure that we're not going to replace TRUNCATE for non i32
3014  // instructions.
3015  //
3016  // FIXME: Although we could sometimes handle this, and it does occur in
3017  // practice that one of the condition inputs to the select is also one of
3018  // the outputs, we currently can't deal with this.
3019  if (isI32Insn(User, N))
3020  continue;
3021 
3022  return SDValue();
3023  }
3024 
3025  SDValue SubI32 = DAG.getTargetConstant(VE::sub_i32, DL, MVT::i32);
3026  return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, VT,
3027  N->getOperand(0), SubI32),
3028  0);
3029 }
3030 
3032  DAGCombinerInfo &DCI) const {
3033  switch (N->getOpcode()) {
3034  default:
3035  break;
3036  case ISD::SELECT:
3037  return combineSelect(N, DCI);
3038  case ISD::SELECT_CC:
3039  return combineSelectCC(N, DCI);
3040  case ISD::TRUNCATE:
3041  return combineTRUNCATE(N, DCI);
3042  }
3043 
3044  return SDValue();
3045 }
3046 
3047 //===----------------------------------------------------------------------===//
3048 // VE Inline Assembly Support
3049 //===----------------------------------------------------------------------===//
3050 
3053  if (Constraint.size() == 1) {
3054  switch (Constraint[0]) {
3055  default:
3056  break;
3057  case 'v': // vector registers
3058  return C_RegisterClass;
3059  }
3060  }
3061  return TargetLowering::getConstraintType(Constraint);
3062 }
3063 
3064 std::pair<unsigned, const TargetRegisterClass *>
3066  StringRef Constraint,
3067  MVT VT) const {
3068  const TargetRegisterClass *RC = nullptr;
3069  if (Constraint.size() == 1) {
3070  switch (Constraint[0]) {
3071  default:
3072  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3073  case 'r':
3074  RC = &VE::I64RegClass;
3075  break;
3076  case 'v':
3077  RC = &VE::V64RegClass;
3078  break;
3079  }
3080  return std::make_pair(0U, RC);
3081  }
3082 
3083  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3084 }
3085 
3086 //===----------------------------------------------------------------------===//
3087 // VE Target Optimization Support
3088 //===----------------------------------------------------------------------===//
3089 
3091  // Specify 8 for PIC model to relieve the impact of PIC load instructions.
3092  if (isJumpTableRelative())
3093  return 8;
3094 
3096 }
3097 
3099  EVT VT = Y.getValueType();
3100 
3101  // VE doesn't have vector and not instruction.
3102  if (VT.isVector())
3103  return false;
3104 
3105  // VE allows different immediate values for X and Y where ~X & Y.
3106  // Only simm7 works for X, and only mimm works for Y on VE. However, this
3107  // function is used to check whether an immediate value is OK for and-not
3108  // instruction as both X and Y. Generating additional instruction to
3109  // retrieve an immediate value is no good since the purpose of this
3110  // function is to convert a series of 3 instructions to another series of
3111  // 3 instructions with better parallelism. Therefore, we return false
3112  // for all immediate values now.
3113  // FIXME: Change hasAndNot function to have two operands to make it work
3114  // correctly with Aurora VE.
3115  if (isa<ConstantSDNode>(Y))
3116  return false;
3117 
3118  // It's ok for generic registers.
3119  return true;
3120 }
3121 
3123  SelectionDAG &DAG) const {
3124  assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
3125  MVT VT = Op.getOperand(0).getSimpleValueType();
3126 
3127  // Special treatment for packed V64 types.
3128  assert(VT == MVT::v512i32 || VT == MVT::v512f32);
3129  (void)VT;
3130  // Example of codes:
3131  // %packed_v = extractelt %vr, %idx / 2
3132  // %v = %packed_v >> (%idx % 2 * 32)
3133  // %res = %v & 0xffffffff
3134 
3135  SDValue Vec = Op.getOperand(0);
3136  SDValue Idx = Op.getOperand(1);
3137  SDLoc DL(Op);
3138  SDValue Result = Op;
3139  if (false /* Idx->isConstant() */) {
3140  // TODO: optimized implementation using constant values
3141  } else {
3142  SDValue Const1 = DAG.getConstant(1, DL, MVT::i64);
3143  SDValue HalfIdx = DAG.getNode(ISD::SRL, DL, MVT::i64, {Idx, Const1});
3144  SDValue PackedElt =
3145  SDValue(DAG.getMachineNode(VE::LVSvr, DL, MVT::i64, {Vec, HalfIdx}), 0);
3146  SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1});
3147  SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1});
3148  SDValue Const5 = DAG.getConstant(5, DL, MVT::i64);
3149  Shift = DAG.getNode(ISD::SHL, DL, MVT::i64, {Shift, Const5});
3150  PackedElt = DAG.getNode(ISD::SRL, DL, MVT::i64, {PackedElt, Shift});
3151  SDValue Mask = DAG.getConstant(0xFFFFFFFFL, DL, MVT::i64);
3152  PackedElt = DAG.getNode(ISD::AND, DL, MVT::i64, {PackedElt, Mask});
3153  SDValue SubI32 = DAG.getTargetConstant(VE::sub_i32, DL, MVT::i32);
3154  Result = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
3155  MVT::i32, PackedElt, SubI32),
3156  0);
3157 
3158  if (Op.getSimpleValueType() == MVT::f32) {
3159  Result = DAG.getBitcast(MVT::f32, Result);
3160  } else {
3161  assert(Op.getSimpleValueType() == MVT::i32);
3162  }
3163  }
3164  return Result;
3165 }
3166 
3168  SelectionDAG &DAG) const {
3169  assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
3170  MVT VT = Op.getOperand(0).getSimpleValueType();
3171 
3172  // Special treatment for packed V64 types.
3173  assert(VT == MVT::v512i32 || VT == MVT::v512f32);
3174  (void)VT;
3175  // The v512i32 and v512f32 starts from upper bits (0..31). This "upper
3176  // bits" required `val << 32` from C implementation's point of view.
3177  //
3178  // Example of codes:
3179  // %packed_elt = extractelt %vr, (%idx >> 1)
3180  // %shift = ((%idx & 1) ^ 1) << 5
3181  // %packed_elt &= 0xffffffff00000000 >> shift
3182  // %packed_elt |= (zext %val) << shift
3183  // %vr = insertelt %vr, %packed_elt, (%idx >> 1)
3184 
3185  SDLoc DL(Op);
3186  SDValue Vec = Op.getOperand(0);
3187  SDValue Val = Op.getOperand(1);
3188  SDValue Idx = Op.getOperand(2);
3189  if (Idx.getSimpleValueType() == MVT::i32)
3190  Idx = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Idx);
3191  if (Val.getSimpleValueType() == MVT::f32)
3192  Val = DAG.getBitcast(MVT::i32, Val);
3194  Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
3195 
3196  SDValue Result = Op;
3197  if (false /* Idx->isConstant()*/) {
3198  // TODO: optimized implementation using constant values
3199  } else {
3200  SDValue Const1 = DAG.getConstant(1, DL, MVT::i64);
3201  SDValue HalfIdx = DAG.getNode(ISD::SRL, DL, MVT::i64, {Idx, Const1});
3202  SDValue PackedElt =
3203  SDValue(DAG.getMachineNode(VE::LVSvr, DL, MVT::i64, {Vec, HalfIdx}), 0);
3204  SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1});
3205  SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1});
3206  SDValue Const5 = DAG.getConstant(5, DL, MVT::i64);
3207  Shift = DAG.getNode(ISD::SHL, DL, MVT::i64, {Shift, Const5});
3208  SDValue Mask = DAG.getConstant(0xFFFFFFFF00000000L, DL, MVT::i64);
3209  Mask = DAG.getNode(ISD::SRL, DL, MVT::i64, {Mask, Shift});
3210  PackedElt = DAG.getNode(ISD::AND, DL, MVT::i64, {PackedElt, Mask});
3211  Val = DAG.getNode(ISD::SHL, DL, MVT::i64, {Val, Shift});
3212  PackedElt = DAG.getNode(ISD::OR, DL, MVT::i64, {PackedElt, Val});
3213  Result =
3214  SDValue(DAG.getMachineNode(VE::LSVrr_v, DL, Vec.getSimpleValueType(),
3215  {HalfIdx, PackedElt, Vec}),
3216  0);
3217  }
3218  return Result;
3219 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
lowerLoadF128
static SDValue lowerLoadF128(SDValue Op, SelectionDAG &DAG)
Definition: VEISelLowering.cpp:1325
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:70
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
i
i
Definition: README.txt:29
llvm::VETargetLowering::legalizeInternalVectorOp
SDValue legalizeInternalVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: VVPISelLowering.cpp:323
VECustomDAG.h
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:156
llvm::LoadSDNode::getOffset
const SDValue & getOffset() const
Definition: SelectionDAGNodes.h:2364
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:36
CmpMode::FP
@ FP
llvm::VETargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: VEISelLowering.cpp:3065
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1582
llvm::RegisterSDNode
Definition: SelectionDAGNodes.h:2161
llvm::StoreSDNode::getBasePtr
const SDValue & getBasePtr() const
Definition: SelectionDAGNodes.h:2394
llvm::AtomicOrdering::AcquireRelease
@ AcquireRelease
llvm::RISCVAttrs::StackAlign
StackAlign
Definition: RISCVAttributes.h:37
llvm::VETargetLowering::makeHiLoPair
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1003
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:533
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:988
llvm::ISD::isSignedIntSetCC
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
Definition: ISDOpcodes.h:1457
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::VETargetLowering::prepareSymbol
Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, StringRef Symbol, const DebugLoc &DL, bool IsLocal, bool IsCall) const
Definition: VEISelLowering.cpp:2073
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:81
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::VETargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: VEISelLowering.cpp:367
llvm::VEISD::REPL_F32
@ REPL_F32
Definition: VEISelLowering.h:56
llvm::VERegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: VERegisterInfo.cpp:62
llvm::VETargetLowering::lowerBUILD_VECTOR
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1831
llvm::VEISD::REPL_I32
@ REPL_I32
Definition: VEISelLowering.h:55
llvm::VETargetLowering::emitEHSjLjSetJmp
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: VEISelLowering.cpp:2179
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::MachineJumpTableInfo::createJumpTableIndex
unsigned createJumpTableIndex(const std::vector< MachineBasicBlock * > &DestBBs)
createJumpTableIndex - Create a new jump table.
Definition: MachineFunction.cpp:1310
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:196
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:209
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1449
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MachineFrameInfo::setReturnAddressIsTaken
void setReturnAddressIsTaken(bool s)
Definition: MachineFrameInfo.h:378
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4550
llvm::VEISD::NodeType
NodeType
Definition: VEISelLowering.h:24
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:991
PHI
Rewrite undef for PHI
Definition: AMDGPURewriteUndefForPHI.cpp:101
llvm::TargetLowering::CallLoweringInfo::setChain
CallLoweringInfo & setChain(SDValue InChain)
Definition: TargetLowering.h:4179
llvm::VEISD::CMPU
@ CMPU
Definition: VEISelLowering.h:28
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:943
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:767
llvm::ExceptionHandling::SjLj
@ SjLj
setjmp/longjmp based exceptions
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::ISD::ATOMIC_LOAD_UMAX
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1195
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:159
llvm::VESubtarget::getRsaSize
unsigned getRsaSize() const
Get the size of RSA, return address, and frame pointer as described in VEFrameLowering....
Definition: VESubtarget.h:79
llvm::VECC::CondCode
CondCode
Definition: VE.h:42
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::Function
Definition: Function.h:60
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
llvm::getImmVal
static uint64_t getImmVal(const ConstantSDNode *N)
getImmVal - get immediate representation of integer value
Definition: VE.h:404
llvm::VERegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: VERegisterInfo.cpp:506
llvm::VEISD::CALL
@ CALL
Definition: VEISelLowering.h:33
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:700
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:976
llvm::ISD::ATOMIC_LOAD_CLR
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1188
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1858
llvm::isPackedVectorType
bool isPackedVectorType(EVT SomeVT)
Definition: VECustomDAG.cpp:22
llvm::ISD::MLOAD
@ MLOAD
Definition: ISDOpcodes.h:1207
llvm::CodeModel::Medium
@ Medium
Definition: CodeGen.h:28
llvm::AtomicRMWInst::getOperation
BinOp getOperation() const
Definition: Instructions.h:801
llvm::TargetLoweringBase::setMinCmpXchgSizeInBits
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Definition: TargetLowering.h:2540
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1739
llvm::VESubtarget::enableVPU
bool enableVPU() const
Definition: VESubtarget.h:65
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::VETargetLowering::lowerATOMIC_SWAP
SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1196
llvm::VEISD::Hi
@ Hi
Definition: VEISelLowering.h:42
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1057
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:9353
llvm::intCondCode2Icc
static VECC::CondCode intCondCode2Icc(ISD::CondCode CC)
Convert a DAG integer condition code to a VE ICC condition.
Definition: VE.h:206
llvm::VETargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: VEISelLowering.cpp:1999
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:371
ErrorHandling.h
llvm::isMaskArithmetic
bool isMaskArithmetic(SDValue Op)
Definition: VECustomDAG.cpp:50
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::isIntVECondCode
static bool isIntVECondCode(VECC::CondCode CC)
Definition: VE.h:150
llvm::MemSDNode::getMemoryVT
EVT getMemoryVT() const
Return the type of the in-memory value.
Definition: SelectionDAGNodes.h:1355
llvm::MachineFunction::getFunctionNumber
unsigned getFunctionNumber() const
getFunctionNumber - Return a unique ID for the current function.
Definition: MachineFunction.h:632
llvm::MemSDNode::getChain
const SDValue & getChain() const
Definition: SelectionDAGNodes.h:1378
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::MVT::v512i32
@ v512i32
Definition: MachineValueType.h:122
llvm::AtomicOrdering::SequentiallyConsistent
@ SequentiallyConsistent
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::ISD::FMA
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:482
llvm::TargetLowering::DAGCombinerInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:3909
llvm::VEMachineFunctionInfo::getVarArgsFrameOffset
int getVarArgsFrameOffset() const
Definition: VEMachineFunctionInfo.h:44
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2344
llvm::TargetLowering::CallLoweringInfo::setCallee
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
Definition: TargetLowering.h:4198
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:273
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::TargetLowering::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetLowering.cpp:46
llvm::VETargetLowering::combineSelectCC
SDValue combineSelectCC(SDNode *N, DAGCombinerInfo &DCI) const
Definition: VEISelLowering.cpp:2832
llvm::VETargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: VEISelLowering.cpp:1083
llvm::VESubtarget::getRegisterInfo
const VERegisterInfo * getRegisterInfo() const override
Definition: VESubtarget.h:55
Shift
bool Shift
Definition: README.txt:468
MachineJumpTableInfo.h
llvm::CCState::AnalyzeFormalArguments
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Definition: CallingConvLower.cpp:82
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::VETargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Inline Assembly {.
Definition: VEISelLowering.cpp:3052
Module.h
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::MaybeAlign::valueOrOne
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
Definition: Alignment.h:142
llvm::TargetLoweringBase::setSupportsUnalignedAtomics
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
Definition: TargetLowering.h:2545
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:8013
decideCompType
static EVT decideCompType(EVT SrcVT)
Definition: VEISelLowering.cpp:2747
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:873
llvm::VETargetLowering::lowerToTLSGeneralDynamicModel
SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1273
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:736
llvm::AArch64ISD::CALL
@ CALL
Definition: AArch64ISelLowering.h:53
llvm::MachineJumpTableInfo::EK_BlockAddress
@ EK_BlockAddress
EK_BlockAddress - Each entry is a plain address of block, e.g.
Definition: MachineJumpTableInfo.h:49
llvm::isMImmVal
static bool isMImmVal(uint64_t Val)
Definition: VE.h:421
llvm::TargetLowering::CallLoweringInfo::CB
const CallBase * CB
Definition: TargetLowering.h:4161
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:44
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2502
llvm::TargetLowering::LowerCallTo
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
Definition: SelectionDAGBuilder.cpp:9808
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::VETargetLowering::shouldExpandAtomicRMWInIR
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: VEISelLowering.cpp:1148
llvm::TargetLoweringBase::isJumpTableRelative
virtual bool isJumpTableRelative() const
Definition: TargetLoweringBase.cpp:2014
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:772
llvm::VETargetLowering::lowerATOMIC_FENCE
SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1102
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
AllPackedVTs
static const MVT AllPackedVTs[]
Definition: VEISelLowering.cpp:81
AllVectorVTs
static const MVT AllVectorVTs[]
Definition: VEISelLowering.cpp:76
llvm::VEISD::GETFUNPLT
@ GETFUNPLT
Definition: VEISelLowering.h:37
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1086
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1404
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::MVT::v256i32
@ v256i32
Definition: MachineValueType.h:121
llvm::VEISD::GETSTACKTOP
@ GETSTACKTOP
Definition: VEISelLowering.h:39
llvm::TargetLoweringBase::LegalizeAction
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
Definition: TargetLowering.h:195
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2195
VEISelLowering.h
SelectionDAG.h
llvm::MachineJumpTableInfo::EK_Custom32
@ EK_Custom32
EK_Custom32 - Each entry is a 32-bit value that is custom lowered by the TargetLowering::LowerCustomJ...
Definition: MachineJumpTableInfo.h:76
llvm::VETargetLowering::withTargetFlags
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
} Custom DAGCombine
Definition: VEISelLowering.cpp:977
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::VEISD::LEGALAVL
@ LEGALAVL
Definition: VEISelLowering.h:61
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::CCState::AnalyzeCallOperands
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
Definition: CallingConvLower.cpp:123
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:661
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:479
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::ISD::ATOMIC_LOAD_OR
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1189
llvm::ISD::FABS
@ FABS
Definition: ISDOpcodes.h:912
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:1001
llvm::ISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
Definition: ISDOpcodes.h:141
MachineRegisterInfo.h
llvm::MachineBasicBlock::succ_rbegin
succ_reverse_iterator succ_rbegin()
Definition: MachineBasicBlock.h:373
KnownBits.h
llvm::AtomicOrdering::Monotonic
@ Monotonic
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:2121
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::VEISD::VEC_UNPACK_LO
@ VEC_UNPACK_LO
Definition: VEISelLowering.h:47
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:694
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::VEInstrInfo::getGlobalBaseReg
Register getGlobalBaseReg(MachineFunction *MF) const
} Optimization
Definition: VEInstrInfo.cpp:754
llvm::TargetLoweringBase::setTargetDAGCombine
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
Definition: TargetLowering.h:2494
llvm::ISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
Definition: ISDOpcodes.h:147
llvm::ISD::VECREDUCE_UMAX
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1287
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::MVT::integer_valuetypes
static auto integer_valuetypes()
Definition: MachineValueType.h:1478
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:762
llvm::VETargetLowering::prepareMBB
Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TargetBB, const DebugLoc &DL) const
Definition: VEISelLowering.cpp:2024
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::CallingConv::PreserveAll
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
Definition: CallingConv.h:66
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:58
llvm::VETargetLowering::VETargetLowering
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI)
Definition: VEISelLowering.cpp:898
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1008
llvm::VETargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: VEISelLowering.cpp:581
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7963
llvm::MVT::v256f32
@ v256f32
Definition: MachineValueType.h:175
llvm::VEMCExpr::VK_VE_GOT_LO32
@ VK_VE_GOT_LO32
Definition: VEMCExpr.h:33
llvm::VETargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: VEISelLowering.cpp:929
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::SDNode::getOpcode
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
Definition: SelectionDAGNodes.h:644
llvm::TargetLowering::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: TargetLowering.h:4139
llvm::ISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
Definition: ISDOpcodes.h:151
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:37
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:201
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2237
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::CCValAssign::isExtInLoc
bool isExtInLoc() const
Definition: CallingConvLower.h:154
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1141
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::VEISD::GLOBAL_BASE_REG
@ GLOBAL_BASE_REG
Definition: VEISelLowering.h:41
llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:3122
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:702
llvm::VETargetLowering::lowerGlobalAddress
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1257
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::getFpImmVal
static uint64_t getFpImmVal(const ConstantFPSDNode *N)
getFpImmVal - get immediate representation of floating point value
Definition: VE.h:409
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::SelectionDAG::getTargetBlockAddress
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:762
llvm::AArch64ISD::RET_FLAG
@ RET_FLAG
Definition: AArch64ISelLowering.h:80
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:148
llvm::VETargetLowering::lowerEH_SJLJ_SETJMP
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1711
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::User
Definition: User.h:44
llvm::ISD::CopyToReg
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Definition: ISDOpcodes.h:203
llvm::VEISD::VEC_BROADCAST
@ VEC_BROADCAST
Definition: VEISelLowering.h:53
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::VETargetLowering::splitMaskArithmetic
SDValue splitMaskArithmetic(SDValue Op, SelectionDAG &DAG) const
Definition: VVPISelLowering.cpp:21
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::VETargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: VEISelLowering.cpp:886
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:58
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1514
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1862
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3486
llvm::VETargetLowering::lowerVAARG
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1587
llvm::MVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: MachineValueType.h:1105
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::VETargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
Definition: VEISelLowering.cpp:872
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::VETargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: VEISelLowering.cpp:441
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3903
llvm::CCState::AnalyzeReturn
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
Definition: CallingConvLower.cpp:110
llvm::isMImm32Val
static bool isMImm32Val(uint32_t Val)
Definition: VE.h:434
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:332
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
llvm::Value::uses
iterator_range< use_iterator > uses()
Definition: Value.h:376
llvm::VETargetLowering::hasAndNot
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition: VEISelLowering.cpp:3098
llvm::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
Definition: PPCInstrBuilder.h:32
llvm::VEISD::VEC_UNPACK_HI
@ VEC_UNPACK_HI
Definition: VEISelLowering.h:48
llvm::TargetLowering::CallLoweringInfo::setDebugLoc
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
Definition: TargetLowering.h:4174
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1028
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2339
llvm::MVT::v256f64
@ v256f64
Definition: MachineValueType.h:189
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::VECustomDAG::getBroadcast
SDValue getBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const
Definition: VECustomDAG.cpp:451
llvm::ISD::ATOMIC_LOAD_AND
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1187
llvm::CallingConv::C
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::StoreSDNode::getOffset
const SDValue & getOffset() const
Definition: SelectionDAGNodes.h:2395
llvm::M0
unsigned M0(unsigned Val)
Definition: VE.h:465
llvm::EVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:144
llvm::Instruction
Definition: Instruction.h:42
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::VEFrameLowering::hasBP
bool hasBP(const MachineFunction &MF) const
Definition: VEFrameLowering.cpp:430
llvm::ISD::ATOMIC_LOAD_UMIN
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1194
llvm::AtomicOrdering::Acquire
@ Acquire
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:773
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::ISD::FP16_TO_FP
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
Definition: ISDOpcodes.h:896
llvm::StringRef::data
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:131
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::VEMCExpr::VK_VE_LO32
@ VK_VE_LO32
Definition: VEMCExpr.h:29
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:153
llvm::VETargetLowering::emitSjLjDispatchBlock
MachineBasicBlock * emitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: VEISelLowering.cpp:2377
llvm::VETargetLowering::lowerEH_SJLJ_SETUP_DISPATCH
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1719
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:149
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::TargetLoweringBase::setBooleanVectorContents
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Definition: TargetLowering.h:2287
llvm::AtomicRMWInst::Xchg
@ Xchg
*p = v
Definition: Instructions.h:729
llvm::ISD::CopyFromReg
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:208
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::VEInstrInfo
Definition: VEInstrInfo.h:51
llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1640
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:143
llvm::MemSDNode::isVolatile
bool isVolatile() const
Definition: SelectionDAGNodes.h:1314
isI32Insn
static bool isI32Insn(const SDNode *User, const SDNode *N)
Definition: VEISelLowering.cpp:2901
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::VETargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned Uid, MCContext &Ctx) const override
Definition: VEISelLowering.cpp:1986
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:715
decideComp
static unsigned decideComp(EVT SrcVT, ISD::CondCode CC)
Definition: VEISelLowering.cpp:2738
llvm::getAnnotatedNodeAVL
std::pair< SDValue, bool > getAnnotatedNodeAVL(SDValue Op)
Definition: VECustomDAG.cpp:395
llvm::VETargetLowering::lowerBlockAddress
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1262
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:647
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::VEISD::EH_SJLJ_SETJMP
@ EH_SJLJ_SETJMP
Definition: VEISelLowering.h:35
llvm::ISD::FPOW
@ FPOW
Definition: ISDOpcodes.h:918
llvm::isPackingSupportOpcode
bool isPackingSupportOpcode(unsigned Opc)
Definition: VECustomDAG.cpp:116
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::VEMCExpr::VK_VE_GOT_HI32
@ VK_VE_GOT_HI32
Definition: VEMCExpr.h:32
llvm::TargetLowering::CallLoweringInfo::Outs
SmallVector< ISD::OutputArg, 32 > Outs
Definition: TargetLowering.h:4162
llvm::MVT::v4i64
@ v4i64
Definition: MachineValueType.h:129
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2356
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::ISD::SMIN
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:660
llvm::APFloat
Definition: APFloat.h:716
llvm::TargetLoweringBase::getMinimumJumpTableEntries
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
Definition: TargetLoweringBase.cpp:1994
llvm::MachineFunction::push_back
void push_back(MachineBasicBlock *MBB)
Definition: MachineFunction.h:871
llvm::ISD::isVPOpcode
bool isVPOpcode(unsigned Opcode)
Whether this is a vector-predicated Opcode.
Definition: SelectionDAG.cpp:460
llvm::isNullFPConstant
bool isNullFPConstant(SDValue V)
Returns true if V is an FP constant with a value of positive zero.
Definition: SelectionDAG.cpp:10767
getParamCC
CCAssignFn * getParamCC(CallingConv::ID CallConv, bool IsVarArg)
Definition: VEISelLowering.cpp:56
llvm::VETargetLowering::lowerSTORE
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1543
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:35
llvm::VETargetLowering::getMinimumJumpTableEntries
unsigned getMinimumJumpTableEntries() const override
} Inline Assembly
Definition: VEISelLowering.cpp:3090
llvm::SyncScope::System
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:57
llvm::VEISD::CMPF
@ CMPF
Definition: VEISelLowering.h:29
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::ISD::ATOMIC_FENCE
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:1155
llvm::VEMCExpr::VK_VE_GOTOFF_LO32
@ VK_VE_GOTOFF_LO32
Definition: VEMCExpr.h:35
uint64_t
llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1176
llvm::ISD::ATOMIC_LOAD_MIN
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1192
llvm::ISD::FP_TO_UINT
@ FP_TO_UINT
Definition: ISDOpcodes.h:820
llvm::ConstantFPSDNode
Definition: SelectionDAGNodes.h:1631
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:650
llvm::TargetLowering::verifyReturnAddressArgumentIsConstant
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
Definition: TargetLowering.cpp:6653
llvm::ISD::VECREDUCE_ADD
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1280
llvm::ISD::LOAD
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:966
llvm::ISD::VECREDUCE_SMAX
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1285
llvm::VEISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: VEISelLowering.h:25
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
lowerStoreF128
static SDValue lowerStoreF128(SDValue Op, SelectionDAG &DAG)
Definition: VEISelLowering.cpp:1455
llvm::TargetLowering::CallLoweringInfo::Chain
SDValue Chain
Definition: TargetLowering.h:4135
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1634
llvm::MachineBasicBlock::setIsEHPad
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
Definition: MachineBasicBlock.h:580
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:197
llvm::TargetLowering::getJumpTableEncoding
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
Definition: TargetLowering.cpp:441
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
VEInstrBuilder.h
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::DenseMap
Definition: DenseMap.h:714
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:793
llvm::SyncScope::ID
uint8_t ID
Definition: LLVMContext.h:46
llvm::TargetLowering::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: TargetLowering.h:4156
llvm::ISD::EXTRACT_VECTOR_ELT
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:534
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2305
llvm::ISD::CTLZ_ZERO_UNDEF
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:709
llvm::ISD::ATOMIC_LOAD_NAND
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1191
llvm::AtomicOrdering::Unordered
@ Unordered
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:9047
llvm::ISD::FP_TO_FP16
@ FP_TO_FP16
Definition: ISDOpcodes.h:897
llvm::ISD::ATOMIC_CMP_SWAP
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1170
llvm::ISD::ATOMIC_LOAD_ADD
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1185
llvm::TargetLowering::CallLoweringInfo::DL
SDLoc DL
Definition: TargetLowering.h:4160
llvm::ISD::FCOPYSIGN
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:492
VERegisterInfo.h
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:439
llvm::VETargetLowering::lowerJumpTable
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1320
llvm::VEISD::CMPQ
@ CMPQ
Definition: VEISelLowering.h:30
llvm::VECustomDAG::getUNDEF
SDValue getUNDEF(EVT VT) const
Definition: VECustomDAG.h:180
llvm::VEMachineFunctionInfo::setVarArgsFrameOffset
void setVarArgsFrameOffset(int Offset)
Definition: VEMachineFunctionInfo.h:45
llvm::VETargetLowering::lowerConstantPool
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1267
llvm::VEISD::MEMBARRIER
@ MEMBARRIER
Definition: VEISelLowering.h:44
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:880
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:567
llvm::ISD::MSTORE
@ MSTORE
Definition: ISDOpcodes.h:1208
llvm::AllocFnKind::Aligned
@ Aligned
llvm::StoreSDNode
This class is used to represent ISD::STORE nodes.
Definition: SelectionDAGNodes.h:2372
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1404
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:179
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:4134
IRBuilder.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
llvm::SelectionDAG::getAtomic
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Definition: SelectionDAG.cpp:7686
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:638
llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1767
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::VETargetLowering::lowerGlobalTLSAddress
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1310
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MachineBasicBlock::succ_rend
succ_reverse_iterator succ_rend()
Definition: MachineBasicBlock.h:377
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:894
llvm::TargetLoweringBase::ArgListEntry
Definition: TargetLowering.h:284
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::VEFrameLowering
Definition: VEFrameLowering.h:23
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::VETargetLowering::lowerLOAD
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1430
llvm::Instruction::hasAtomicStore
bool hasAtomicStore() const LLVM_READONLY
Return true if this atomic instruction stores to memory.
Definition: Instruction.cpp:673
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:610
isSimm7
static bool isSimm7(SDValue V)
Definition: VEISelLowering.cpp:2695
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
llvm::SelectionDAG::getMachineNode
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
Definition: SelectionDAG.cpp:9791
MachineModuleInfo.h
llvm::ISD::VECREDUCE_AND
@ VECREDUCE_AND
Definition: ISDOpcodes.h:1282
llvm::SelectionDAG::getBitcast
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
Definition: SelectionDAG.cpp:2224
llvm::ISD::RETURNADDR
@ RETURNADDR
Definition: ISDOpcodes.h:95
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::ARCISD::CMOV
@ CMOV
Definition: ARCISelLowering.h:43
lowerFRAMEADDR
static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)
Definition: VEISelLowering.cpp:1726
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::VETargetLowering::makeAddress
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1014
llvm::MVT::v256i1
@ v256i1
Definition: MachineValueType.h:74
llvm::StoreSDNode::getValue
const SDValue & getValue() const
Definition: SelectionDAGNodes.h:2393
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:750
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1087
llvm::VESubtarget::getFrameLowering
const VEFrameLowering * getFrameLowering() const override
Definition: VESubtarget.h:52
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::SelectionDAG::getGlobalAddress
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1706
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
Definition: SelectionDAG.h:1000
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:679
llvm::VETargetLowering::lowerVASTART
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1568
llvm::fpCondCode2Fcc
static VECC::CondCode fpCondCode2Fcc(ISD::CondCode CC)
Convert a DAG floating point condition code to a VE FCC condition.
Definition: VE.h:234
llvm::TargetLowering::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 32 > Ins
Definition: TargetLowering.h:4164
llvm::ISD::ConstantPool
@ ConstantPool
Definition: ISDOpcodes.h:82
llvm::ISD::GlobalTLSAddress
@ GlobalTLSAddress
Definition: ISDOpcodes.h:79
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::TargetLowering::CallLoweringInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:4159
llvm::VETargetLowering::getCustomOperationAction
TargetLoweringBase::LegalizeAction getCustomOperationAction(SDNode &) const override
Custom Lower {.
Definition: VEISelLowering.cpp:1857
llvm::SelectionDAG::getTargetConstantPool
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:731
llvm::VETargetLowering::combineSelect
SDValue combineSelect(SDNode *N, DAGCombinerInfo &DCI) const
Definition: VEISelLowering.cpp:2791
llvm::MachineBasicBlock::setMachineBlockAddressTaken
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
Definition: MachineBasicBlock.h:247
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1883
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::MachineFrameInfo::setHasCalls
void setHasCalls(bool V)
Definition: MachineFrameInfo.h:614
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:138
llvm::MachineBasicBlock::isEHPad
bool isEHPad() const
Returns true if the block is a landing pad.
Definition: MachineBasicBlock.h:576
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:1009
lowerRETURNADDR
static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)
Definition: VEISelLowering.cpp:1747
llvm::VEISD::GETTLSADDR
@ GETTLSADDR
Definition: VEISelLowering.h:38
llvm::MachineInstrBuilder::addJumpTableIndex
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:171
llvm::VETargetLowering::emitEHSjLjLongJmp
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Definition: VEISelLowering.cpp:2310
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG
bool isAfterLegalizeDAG() const
Definition: TargetLowering.h:3916
llvm::VECustomDAG
Definition: VECustomDAG.h:142
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
llvm::ISD::ATOMIC_LOAD_SUB
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1186
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition: TargetRegisterInfo.h:297
llvm::VETargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
Definition: VEISelLowering.cpp:971
uint32_t
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:1149
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:93
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::VEMachineFunctionInfo
Definition: VEMachineFunctionInfo.h:19
llvm::isVVPOrVEC
bool isVVPOrVEC(unsigned Opcode)
Definition: VECustomDAG.cpp:126
llvm::VETargetLowering::lowerEH_SJLJ_LONGJMP
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
Definition: VEISelLowering.cpp:1704
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
getReturnCC
CCAssignFn * getReturnCC(CallingConv::ID CallConv)
Definition: VEISelLowering.cpp:47
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:5254
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2395
llvm::ISD::getSetCCInverse
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
Definition: SelectionDAG.cpp:557
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:190
llvm::CCState::CheckReturn
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
Definition: CallingConvLower.cpp:96
llvm::TargetLoweringBase::setMinStackArgumentAlignment
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
Definition: TargetLowering.h:2521
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:79
llvm::ISD::VECREDUCE_XOR
@ VECREDUCE_XOR
Definition: ISDOpcodes.h:1284
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:138
llvm::ISD::ATOMIC_SWAP
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1184
llvm::MVT::v512i1
@ v512i1
Definition: MachineValueType.h:75
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1404
llvm::M68kISD::GLOBAL_BASE_REG
@ GLOBAL_BASE_REG
Definition: M68kISelLowering.h:83
llvm::MVT::v8i64
@ v8i64
Definition: MachineValueType.h:130
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:715
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetLowering::C_RegisterClass
@ C_RegisterClass
Definition: TargetLowering.h:4552
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::INTRINSIC_WO_CHAIN
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:184
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::VETargetMachine
Definition: VETargetMachine.h:22
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:314
llvm::LoadSDNode::getBasePtr
const SDValue & getBasePtr() const
Definition: SelectionDAGNodes.h:2363
llvm::SelectionDAG::getTargetJumpTable
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:725
llvm::VEISD::EH_SJLJ_LONGJMP
@ EH_SJLJ_LONGJMP
Definition: VEISelLowering.h:34
llvm::ISD::FRAMEADDR
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:94
llvm::MVT::v256i64
@ v256i64
Definition: MachineValueType.h:135
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
llvm::AtomicOrdering::Release
@ Release
llvm::AtomicSDNode
This is an SDNode representing atomic operations.
Definition: SelectionDAGNodes.h:1442
llvm::ISD::isIntEqualitySetCC
bool isIntEqualitySetCC(CondCode Code)
Return true if this is a setcc instruction that performs an equality comparison when used with intege...
Definition: ISDOpcodes.h:1469
llvm::ISD::FSQRT
@ FSQRT
Definition: ISDOpcodes.h:913
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:349
llvm::TargetLowering::CallLoweringInfo::IsTailCall
bool IsTailCall
Definition: TargetLowering.h:4150
llvm::VEISD::CMOV
@ CMOV
Definition: VEISelLowering.h:31
llvm::CCState::AnalyzeCallResult
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
Definition: CallingConvLower.cpp:159
llvm::VEISD::VEC_PACK
@ VEC_PACK
Definition: VEISelLowering.h:50
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:144
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
VEMCExpr.h
llvm::ISD::FMAXNUM
@ FMAXNUM
Definition: ISDOpcodes.h:944
llvm::VESubtarget::getInstrInfo
const VEInstrInfo * getInstrInfo() const override
Definition: VESubtarget.h:51
llvm::VETargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: VEISelLowering.cpp:860
llvm::VEISD::RET_FLAG
@ RET_FLAG
Definition: VEISelLowering.h:45
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2373
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1759
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::SystemZISD::MEMBARRIER
@ MEMBARRIER
Definition: SystemZISelLowering.h:149
VEMachineFunctionInfo.h
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
llvm::VETargetLowering::setupEntryBlockForSjLj
void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI, int Offset) const
Definition: VEISelLowering.cpp:2161
uint16_t
CallingConvLower.h
llvm::MachineBasicBlock::removeSuccessor
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:800
llvm::isNullConstant
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
Definition: SelectionDAG.cpp:10762
llvm::VEISD::EH_SJLJ_SETUP_DISPATCH
@ EH_SJLJ_SETUP_DISPATCH
Definition: VEISelLowering.h:36
llvm::ISD::VECREDUCE_MUL
@ VECREDUCE_MUL
Definition: ISDOpcodes.h:1281
AllMaskVTs
static const MVT AllMaskVTs[]
Definition: VEISelLowering.cpp:79
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::VETargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Custom Lower {.
Definition: VEISelLowering.cpp:1062
llvm::ISD::FCOS
@ FCOS
Definition: ISDOpcodes.h:916
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:548
llvm::ISD::getSetCCSwappedOperands
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
Definition: SelectionDAG.cpp:534
llvm::TargetLowering::CallLoweringInfo::setDiscardResult
CallLoweringInfo & setDiscardResult(bool Value=true)
Definition: TargetLowering.h:4254
llvm::ISD::FSIN
@ FSIN
Definition: ISDOpcodes.h:915
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:469
llvm::VECustomDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool IsTarget=false, bool IsOpaque=false) const
Definition: VECustomDAG.cpp:404
llvm::ISD::BUILD_VECTOR
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
Definition: ISDOpcodes.h:514
llvm::VERegisterInfo
Definition: VERegisterInfo.h:22
Function.h
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Definition: CallingConvLower.h:423
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:200
llvm::VEISD::TS1AM
@ TS1AM
Definition: VEISelLowering.h:46
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::size
unsigned size() const
Definition: DenseMap.h:99
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1889
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:262
llvm::ISD::VECREDUCE_OR
@ VECREDUCE_OR
Definition: ISDOpcodes.h:1283
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242