39#define DEBUG_TYPE "ve-lower"
45#include "VEGenCallingConv.inc"
83void VETargetLowering::initRegisterClasses() {
99void VETargetLowering::initSPUActions() {
309void VETargetLowering::initVPUActions() {
325#define HANDLE_VP_TO_VVP(VP_OPC, VVP_NAME) \
326 setOperationAction(ISD::VP_OPC, LegalVecVT, Custom);
327#define ADD_VVP_OP(VVP_NAME, ISD_NAME) \
328 setOperationAction(ISD::ISD_NAME, LegalVecVT, Custom);
331#include "VVPNodes.def"
343 if (ElemBits != 32 && ElemBits != 64)
354 for (
unsigned IntRedOpc : IntReductionOCs)
386 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
448 unsigned ArgsBaseOffset = Subtarget->
getRsaSize();
450 unsigned ArgsPreserved = 64;
462 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
547 unsigned ArgOffset = ArgLocs.
size() * 8;
560 .
Case(
"sp", VE::SX11)
563 .
Case(
"lr", VE::SX10)
564 .
Case(
"tp", VE::SX14)
565 .
Case(
"outer", VE::SX12)
566 .
Case(
"info", VE::SX17)
567 .
Case(
"got", VE::SX15)
568 .
Case(
"plt", VE::SX16)
592 unsigned ArgsBaseOffset = Subtarget->
getRsaSize();
594 unsigned ArgsPreserved = 8 * 8u;
621 ArgsSize =
alignTo(ArgsSize, 16);
653 auto *CalleeG = dyn_cast<GlobalAddressSDNode>(
Callee);
655 GV = CalleeG->getGlobal();
656 bool Local =
TM.shouldAssumeDSOLocal(*
Mod, GV);
657 bool UsePlt = !Local;
686 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
743 if (!MemOpChains.
empty())
751 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i) {
753 RegsToPass[i].second, InGlue);
760 for (
unsigned i = 0, e = RegsToPass.
size(); i != e; ++i)
762 RegsToPass[i].second.getValueType()));
768 assert(Mask &&
"Missing call preserved mask for calling convention");
796 CLI.
Ins[0].Flags.setInReg();
801 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
873 bool ForCodeSize)
const {
890 unsigned *
Fast)
const {
909 initRegisterClasses();
930#define TARGET_NODE_CASE(NAME) \
932 return "VEISD::" #NAME;
963#define ADD_VVP_OP(VVP_NAME, ...) TARGET_NODE_CASE(VVP_NAME)
964#include "VVPNodes.def"
966#undef TARGET_NODE_CASE
980 GA->getValueType(0), GA->getOffset(), TF);
988 CP->getAlign(), CP->getOffset(), TF);
1005 EVT VT = Op.getValueType();
1015 EVT PtrVT = Op.getValueType();
1019 auto GlobalN = dyn_cast<GlobalAddressSDNode>(Op);
1021 if (isa<ConstantPoolSDNode>(Op) || isa<JumpTableSDNode>(Op) ||
1022 (GlobalN && GlobalN->getGlobal()->hasLocalLinkage())) {
1105 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
1107 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
1112 switch (FenceOrdering) {
1165 EVT PtrVT =
Ptr.getValueType();
1166 bool Byte =
N->getMemoryVT() ==
MVT::i8;
1185 bool Byte = cast<AtomicSDNode>(Op)->getMemoryVT() ==
MVT::i8;
1222 {Ptr, DAG.getConstant(-4, DL, MVT::i64)});
1224 DAG.
getVTList(Op.getNode()->getValueType(0),
1225 Op.getNode()->getValueType(1)),
1226 {N->getChain(), Aligned, Flag, NewVal},
1227 N->getMemOperand());
1230 SDValue Chain = TS1AM.getValue(1);
1241 {Ptr, DAG.getConstant(-4, DL, MVT::i64)});
1243 DAG.
getVTList(Op.getNode()->getValueType(0),
1244 Op.getNode()->getValueType(1)),
1245 {N->getChain(), Aligned, Flag, NewVal},
1246 N->getMemOperand());
1249 SDValue Chain = TS1AM.getValue(1);
1282 EVT PtrVT = Op.getValueType();
1326 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
1330 Alignment =
Align(8);
1353 SDValue(InFP128, 0), Hi64, SubRegEven);
1355 SDValue(InFP128, 0), Lo64, SubRegOdd);
1371 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
1377 Alignment =
Align(8);
1379 EVT AddrVT = BasePtr.getValueType();
1384 for (
int i = 0; i < 4; ++i) {
1405 for (
int i = 0; i < 8; ++i) {
1430 LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
1439 if (isa<FrameIndexSDNode>(BasePtr.getNode())) {
1456 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
1469 Alignment =
Align(8);
1497 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
1503 Alignment =
Align(8);
1504 EVT AddrVT = BasePtr.getValueType();
1508 for (
int i = 0; i < 4; ++i) {
1523 for (
int i = 0; i < 8; ++i) {
1543 StoreSDNode *StNode = cast<StoreSDNode>(Op.getNode());
1552 if (isa<FrameIndexSDNode>(BasePtr.getNode())) {
1581 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1587 SDNode *Node = Op.getNode();
1588 EVT VT = Node->getValueType(0);
1589 SDValue InChain = Node->getOperand(0);
1590 SDValue VAListPtr = Node->getOperand(1);
1592 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1621 unsigned InternalOffset = 4;
1648 SDNode *Node = Op.getNode();
1649 SDValue Chain = Op.getOperand(0);
1651 MaybeAlign Alignment(Op.getConstantOperandVal(2));
1652 EVT VT = Node->getValueType(0);
1660 bool NeedsAlign = Alignment.
valueOrOne() > StackAlign;
1666 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.
getContext());
1667 Args.push_back(Entry);
1669 Entry.Node = DAG.
getConstant(~(Alignment->value() - 1ULL),
DL, VT);
1670 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.
getContext());
1671 Args.push_back(Entry);
1675 EVT PtrVT = Op.getValueType();
1688 std::pair<SDValue, SDValue> pair =
LowerCallTo(CLI);
1689 Chain = pair.second;
1700 SDValue Ops[2] = {Result, Chain};
1736 unsigned Depth = Op.getConstantOperandVal(0);
1760 EVT VT = Op.getValueType();
1770 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1774 case Intrinsic::eh_sjlj_lsda: {
1776 MVT VT = Op.getSimpleValueType();
1783 TM->getStrList()->push_back(std::string(
1799 if (!isa<BuildVectorSDNode>(
N))
1801 const auto *BVN = cast<BuildVectorSDNode>(
N);
1805 for (
Idx = 0;
Idx < BVN->getNumOperands(); ++
Idx) {
1806 auto ElemV = BVN->getOperand(
Idx);
1807 if (!ElemV->isUndef())
1811 if (
Idx == BVN->getNumOperands())
1816 for (;
Idx < BVN->getNumOperands(); ++
Idx) {
1817 auto ElemV = BVN->getOperand(
Idx);
1818 if (!ElemV->isUndef())
1825 if (
auto *BuildVec = dyn_cast<BuildVectorSDNode>(
N)) {
1826 return BuildVec->getSplatValue();
1834 MVT ResultVT = Op.getSimpleValueType();
1840 auto ElemV = Op->getOperand(UniqueIdx);
1875 unsigned Opcode = Op.getOpcode();
1935#define ADD_VVP_OP(VVP_NAME, ...) case VEISD::VVP_NAME:
1936#include "VVPNodes.def"
1945#define ADD_VVP_OP(VVP_NAME, ISD_NAME) case ISD::ISD_NAME:
1946#include "VVPNodes.def"
1957 switch (
N->getOpcode()) {
1963 llvm_unreachable(
"Do not know how to custom type legalize this operation!");
2076 bool IsLocal =
false,
2077 bool IsCall =
false)
const {
2086 if (IsCall && !IsLocal) {
2096 }
else if (IsLocal) {
2164 int FI,
int Offset)
const {
2192 MI.memoperands_end());
2197 DstReg =
MI.getOperand(0).getReg();
2201 Register MainDestReg =
MRI.createVirtualRegister(RC);
2202 Register RestoreDestReg =
MRI.createVirtualRegister(RC);
2244 if (TFI->
hasBP(*MF)) {
2255 MIB.
add(
MI.getOperand(1));
2273 BuildMI(MainMBB,
DL,
TII->get(VE::LEAzii), MainDestReg)
2290 if (TFI->
hasBP(*MF)) {
2292 BuildMI(RestoreMBB,
DL,
TII->get(VE::LDrii), VE::SX17);
2298 BuildMI(RestoreMBB,
DL,
TII->get(VE::LEAzii), RestoreDestReg)
2305 MI.eraseFromParent();
2319 MI.memoperands_end());
2322 Register Tmp =
MRI.createVirtualRegister(&VE::I64RegClass);
2362 MIB.
add(
MI.getOperand(0));
2372 MI.eraseFromParent();
2389 unsigned MaxCSNum = 0;
2390 for (
auto &
MBB : *MF) {
2395 for (
const auto &
MI :
MBB) {
2396 if (
MI.isDebugInstr())
2399 assert(
MI.isEHLabel() &&
"expected EH_LABEL");
2400 Sym =
MI.getOperand(0).getMCSymbol();
2408 CallSiteNumToLPad[CSI].push_back(&
MBB);
2409 MaxCSNum = std::max(MaxCSNum, CSI);
2414 std::vector<MachineBasicBlock *> LPadList;
2416 LPadList.reserve(CallSiteNumToLPad.
size());
2418 for (
unsigned CSI = 1; CSI <= MaxCSNum; ++CSI) {
2419 for (
auto &LP : CallSiteNumToLPad[CSI]) {
2420 LPadList.push_back(LP);
2421 InvokeBBs.
insert(LP->pred_begin(), LP->pred_end());
2425 assert(!LPadList.empty() &&
2426 "No landing pad destinations for the dispatch jump table!");
2433 static const int OffsetIC = 72;
2434 static const int OffsetCS = 8;
2497 BuildMI(DispatchBB,
DL,
TII->get(VE::GETGOT), VE::SX15);
2505 if (LPadList.size() < 64) {
2512 assert(LPadList.size() <= 0x7FFFFFFF &&
"Too large Landing Pad!");
2517 .
addImm(LPadList.size());
2623 for (
auto &LP : LPadList)
2624 if (SeenMBBs.
insert(LP).second)
2637 for (
auto *MBBS : Successors) {
2638 if (MBBS->isEHPad()) {
2655 for (
auto &MOp : II.operands())
2657 DefRegs[MOp.getReg()] =
true;
2660 for (
unsigned RI = 0; SavedRegs[RI]; ++RI) {
2672 for (
auto &LP : MBBLPads)
2673 LP->setIsEHPad(
false);
2676 MI.eraseFromParent();
2683 switch (
MI.getOpcode()) {
2686 case VE::EH_SjLj_LongJmp:
2688 case VE::EH_SjLj_SetJmp:
2690 case VE::EH_SjLj_Setup_Dispatch:
2696 EVT VT = V.getValueType();
2702 return isInt<7>(
C->getSExtValue());
2706 const APInt &Imm =
C->getValueAPF().bitcastToAPInt();
2708 if (Imm.getBitWidth() == 32)
2710 return isInt<7>(Val);
2718 EVT VT = V.getValueType();
2762 if (isIntEqualitySetCC(
CC)) {
2769 return isSignedIntSetCC(
CC);
2775 return isSignedIntSetCC(
CC) && SrcVT ==
MVT::i64;
2794 "Should be called with a SELECT node");
2801 EVT VT =
N->getValueType(0);
2809 EVT VT0 =
Cond.getValueType();
2812 }
else if (
isMImm(False)) {
2816 CC = getSetCCInverse(
CC, VT0);
2835 "Should be called with a SELECT_CC node");
2843 EVT VT =
N->getValueType(0);
2852 EVT LHSVT =
LHS.getValueType();
2872 CC = getSetCCSwappedOperands(
CC);
2876 }
else if (
isMImm(False)) {
2880 CC = getSetCCInverse(
CC, LHSVT);
2886 bool WithCMov =
true;
2895 SDValue Ops[] = {CompNode, True, False,
2902 switch (
User->getOpcode()) {
2926 if (
N->getOperand(0).getOpcode() !=
ISD::SRL)
2962 switch (U->getOpcode()) {
2977 "find truncate to not i32 integer");
2995 "Should be called with a TRUNCATE node");
2999 EVT VT =
N->getValueType(0);
3007 isa<ConstantSDNode>(
N->getOperand(0)->getOperand(0)) &&
3008 isa<ConstantSDNode>(
N->getOperand(0)->getOperand(1)))
3027 N->getOperand(0), SubI32),
3033 switch (
N->getOpcode()) {
3053 if (Constraint.
size() == 1) {
3054 switch (Constraint[0]) {
3064std::pair<unsigned, const TargetRegisterClass *>
3069 if (Constraint.
size() == 1) {
3070 switch (Constraint[0]) {
3074 RC = &VE::I64RegClass;
3077 RC = &VE::V64RegClass;
3080 return std::make_pair(0U, RC);
3099 EVT VT =
Y.getValueType();
3115 if (isa<ConstantSDNode>(
Y))
3125 MVT VT = Op.getOperand(0).getSimpleValueType();
3135 SDValue Vec = Op.getOperand(0);
3158 if (Op.getSimpleValueType() ==
MVT::f32) {
3170 MVT VT = Op.getOperand(0).getSimpleValueType();
3186 SDValue Vec = Op.getOperand(0);
3187 SDValue Val = Op.getOperand(1);
3215 {HalfIdx, PackedElt, Vec}),
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Callee
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Function Alias Analysis Results
SmallVector< MachineOperand, 4 > Cond
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
typename CallsiteContextGraph< DerivedCCG, FuncTy, CallTy >::FuncInfo FuncInfo
Module.h This file contains the declarations for the Module class.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static unsigned decideComp(EVT SrcVT, ISD::CondCode CC)
static bool isSimm7(SDValue V)
CCAssignFn * getParamCC(CallingConv::ID CallConv, bool IsVarArg)
static SDValue lowerLoadF128(SDValue Op, SelectionDAG &DAG)
static bool isMImm(SDValue V)
static SDValue prepareTS1AM(SDValue Op, SelectionDAG &DAG, SDValue &Flag, SDValue &Bits)
CCAssignFn * getReturnCC(CallingConv::ID CallConv)
static bool safeWithoutCompWithNull(EVT SrcVT, ISD::CondCode CC, bool WithCMov)
static bool isI32InsnAllUses(const SDNode *User, const SDNode *N)
static SDValue lowerLoadI1(SDValue Op, SelectionDAG &DAG)
static SDValue generateComparison(EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode CC, bool WithCMov, const SDLoc &DL, SelectionDAG &DAG)
static EVT decideCompType(EVT SrcVT)
static bool isI32Insn(const SDNode *User, const SDNode *N)
static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)
static const MVT AllMaskVTs[]
static bool getUniqueInsertion(SDNode *N, unsigned &UniqueIdx)
static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)
static const MVT AllVectorVTs[]
static const MVT AllPackedVTs[]
static SDValue finalizeTS1AM(SDValue Op, SelectionDAG &DAG, SDValue Data, SDValue Bits)
static SDValue lowerStoreF128(SDValue Op, SelectionDAG &DAG)
static SDValue lowerStoreI1(SDValue Op, SelectionDAG &DAG)
#define TARGET_NODE_CASE(NAME)
Class for arbitrary precision integers.
an instruction that atomically reads a memory location, combines it with another value,...
BinOp getOperation() const
This is an SDNode representing atomic operations.
LLVM Basic Block Representation.
CCState - This class holds information needed while lowering arguments and return values.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
CCValAssign - Represent assignment of one arg/retval to a location.
unsigned getLocMemOffset() const
Register getLocReg() const
LocInfo getLocInfo() const
A parsed version of the target data layout string in and methods for querying it.
unsigned getAddressSpace() const
Module * getParent()
Get the module that this global value is contained inside of...
Common base class shared among various IRBuilders.
bool hasAtomicStore() const LLVM_READONLY
Return true if this atomic instruction stores to memory.
This is an important class for using LLVM in a threaded context.
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Context object for machine code objects.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Base class for the full range of assembler expressions which are needed for parsing.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
uint64_t getScalarSizeInBits() const
unsigned getVectorNumElements() const
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static auto vector_valuetypes()
MVT getVectorElementType() const
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
bool isEHPad() const
Returns true if the block is a landing pad.
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
succ_reverse_iterator succ_rbegin()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
succ_reverse_iterator succ_rend()
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setFrameAddressIsTaken(bool T)
void setReturnAddressIsTaken(bool s)
int getFunctionContextIndex() const
Return the index for the function context object.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
unsigned getFunctionNumber() const
getFunctionNumber - Return a unique ID for the current function.
MachineJumpTableInfo * getOrCreateJumpTableInfo(unsigned JTEntryKind)
getOrCreateJumpTableInfo - Get the JumpTableInfo for this function, if it does already exist,...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void push_back(MachineBasicBlock *MBB)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool hasCallSiteLandingPad(MCSymbol *Sym)
Return true if the landing pad Eh symbol has an associated call site.
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void insert(iterator MBBI, MachineBasicBlock *MBB)
SmallVectorImpl< unsigned > & getCallSiteLandingPad(MCSymbol *Sym)
Get the call site indexes for a landing pad EH symbol.
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
unsigned createJumpTableIndex(const std::vector< MachineBasicBlock * > &DestBBs)
createJumpTableIndex - Create a new jump table.
@ EK_Custom32
EK_Custom32 - Each entry is a 32-bit value that is custom lowered by the TargetLowering::LowerCustomJ...
@ EK_BlockAddress
EK_BlockAddress - Each entry is a plain address of block, e.g.: .word LBB123.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
A Module instance is used to store all the information related to an LLVM module.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
const TargetMachine & getTarget() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getRegisterMask(const uint32_t *RegMask)
LLVMContext * getContext() const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
const SDValue & getValue() const
StringRef - Represent a constant reference to a string, i.e.
constexpr size_t size() const
size - Get the string size.
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Information about stack frame layout on the target.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
const TargetMachine & getTargetMachine() const
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
virtual bool isJumpTableRelative() const
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
std::vector< ArgListEntry > ArgListTy
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
static Type * getVoidTy(LLVMContext &C)
Value * getOperand(unsigned i) const
SDValue getBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const
SDValue getNode(unsigned OC, SDVTList VTL, ArrayRef< SDValue > OpV, std::optional< SDNodeFlags > Flags=std::nullopt) const
getNode {
SDValue getUNDEF(EVT VT) const
SDValue getConstant(uint64_t Val, EVT VT, bool IsTarget=false, bool IsOpaque=false) const
bool hasBP(const MachineFunction &MF) const
Register getGlobalBaseReg(MachineFunction *MF) const
} Optimization
void setVarArgsFrameOffset(int Offset)
unsigned getRsaSize() const
Get the size of RSA, return address, and frame pointer as described in VEFrameLowering....
const VEInstrInfo * getInstrInfo() const override
const VEFrameLowering * getFrameLowering() const override
const VERegisterInfo * getRegisterInfo() const override
SDValue splitMaskArithmetic(SDValue Op, SelectionDAG &DAG) const
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const
} Custom Inserter
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const
SDValue combineSelect(SDNode *N, DAGCombinerInfo &DCI) const
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI)
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Custom Lower {.
SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
} VVPLowering
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
SDValue combineSelectCC(SDNode *N, DAGCombinerInfo &DCI) const
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const
unsigned getMinimumJumpTableEntries() const override
} Inline Assembly
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
MachineBasicBlock * emitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TargetBB, const DebugLoc &DL) const
void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI, int Offset) const
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
Custom Inserter {.
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
TargetLoweringBase::LegalizeAction getCustomOperationAction(SDNode &) const override
Custom Lower {.
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue legalizeInternalVectorOp(SDValue Op, SelectionDAG &DAG) const
Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, StringRef Symbol, const DebugLoc &DL, bool IsLocal, bool IsCall) const
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
} Custom Lower
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
} Custom DAGCombine
SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned Uid, MCContext &Ctx) const override
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const
unsigned getJumpTableEncoding() const override
JumpTable for VE.
SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
ConstraintType getConstraintType(StringRef Constraint) const override
Inline Assembly {.
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const
LLVM Value Representation.
iterator_range< use_iterator > uses()
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ MEMBARRIER
MEMBARRIER - Compiler barrier only; generate a no-op.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ SIGN_EXTEND
Conversion operators.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ BR_JT
BR_JT - Jumptable branch.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...