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39 #define DEBUG_TYPE "ve-lower"
45 #include "VEGenCallingConv.inc"
83 void VETargetLowering::initRegisterClasses() {
99 void VETargetLowering::initSPUActions() {
298 void VETargetLowering::initVPUActions() {
314 #define HANDLE_VP_TO_VVP(VP_OPC, VVP_NAME) \
315 setOperationAction(ISD::VP_OPC, LegalVecVT, Custom);
316 #define ADD_VVP_OP(VVP_NAME, ISD_NAME) \
317 setOperationAction(ISD::ISD_NAME, LegalVecVT, Custom);
320 #include "VVPNodes.def"
332 if (ElemBits != 32 && ElemBits != 64)
343 for (
unsigned IntRedOpc : IntReductionOCs)
368 for (
unsigned i = 0;
i != RVLocs.size(); ++
i) {
418 RetOps.push_back(
Flag);
430 unsigned ArgsBaseOffset = Subtarget->
getRsaSize();
432 unsigned ArgsPreserved = 64;
444 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
489 InVals.push_back(
Arg);
529 unsigned ArgOffset = ArgLocs.size() * 8;
542 .
Case(
"sp", VE::SX11)
545 .
Case(
"lr", VE::SX10)
546 .
Case(
"tp", VE::SX14)
547 .
Case(
"outer", VE::SX12)
548 .
Case(
"info", VE::SX17)
549 .
Case(
"got", VE::SX15)
550 .
Case(
"plt", VE::SX16)
574 unsigned ArgsBaseOffset = Subtarget->
getRsaSize();
576 unsigned ArgsPreserved = 8 * 8u;
603 ArgsSize =
alignTo(ArgsSize, 16);
635 auto *CalleeG = dyn_cast<GlobalAddressSDNode>(
Callee);
637 GV = CalleeG->getGlobal();
638 bool Local =
TM.shouldAssumeDSOLocal(*
Mod, GV);
639 bool UsePlt = !Local;
666 RegsToPass.push_back(std::make_pair(VE::SX12,
Callee));
668 for (
unsigned i = 0,
e = ArgLocs.size();
i !=
e; ++
i) {
706 RegsToPass.push_back(std::make_pair(VA.
getLocReg(),
Arg));
720 MemOpChains.push_back(
725 if (!MemOpChains.empty())
733 for (
unsigned i = 0,
e = RegsToPass.size();
i !=
e; ++
i) {
735 RegsToPass[
i].second, InGlue);
741 Ops.push_back(Chain);
742 for (
unsigned i = 0,
e = RegsToPass.size();
i !=
e; ++
i)
744 RegsToPass[
i].second.getValueType()));
750 assert(
Mask &&
"Missing call preserved mask for calling convention");
756 Ops.push_back(InGlue);
779 CLI.
Ins[0].Flags.setInReg();
784 for (
unsigned i = 0;
i != RVLocs.size(); ++
i) {
837 InVals.push_back(RV);
856 bool ForCodeSize)
const {
892 initRegisterClasses();
911 #define TARGET_NODE_CASE(NAME) \
913 return "VEISD::" #NAME;
940 #define ADD_VVP_OP(VVP_NAME, ...) TARGET_NODE_CASE(VVP_NAME)
941 #include "VVPNodes.def"
943 #undef TARGET_NODE_CASE
957 GA->getValueType(0), GA->getOffset(), TF);
965 CP->getAlign(),
CP->getOffset(), TF);
982 EVT VT =
Op.getValueType();
992 EVT PtrVT =
Op.getValueType();
996 auto GlobalN = dyn_cast<GlobalAddressSDNode>(
Op);
998 if (isa<ConstantPoolSDNode>(
Op) || isa<JumpTableSDNode>(
Op) ||
999 (GlobalN && GlobalN->getGlobal()->hasLocalLinkage())) {
1082 cast<ConstantSDNode>(
Op.getOperand(1))->getZExtValue());
1084 cast<ConstantSDNode>(
Op.getOperand(2))->getZExtValue());
1089 switch (FenceOrdering) {
1143 bool Byte =
N->getMemoryVT() ==
MVT::i8;
1162 bool Byte = cast<AtomicSDNode>(
Op)->getMemoryVT() ==
MVT::i8;
1199 {Ptr, DAG.getConstant(-4, DL, MVT::i64)});
1202 Op.getNode()->getValueType(1)),
1203 {N->getChain(), Aligned, Flag, NewVal},
1204 N->getMemOperand());
1218 {Ptr, DAG.getConstant(-4, DL, MVT::i64)});
1221 Op.getNode()->getValueType(1)),
1222 {N->getChain(), Aligned, Flag, NewVal},
1223 N->getMemOperand());
1259 EVT PtrVT =
Op.getValueType();
1305 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(
Op.getNode());
1332 SDValue(InFP128, 0), Hi64, SubRegEven);
1334 SDValue(InFP128, 0), Lo64, SubRegOdd);
1352 if (isa<FrameIndexSDNode>(BasePtr.getNode())) {
1410 if (isa<FrameIndexSDNode>(BasePtr.getNode())) {
1437 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
1438 return DAG.
getStore(
Op.getOperand(0),
DL, Offset,
Op.getOperand(1),
1444 EVT VT = Node->getValueType(0);
1445 SDValue InChain = Node->getOperand(0);
1446 SDValue VAListPtr = Node->getOperand(1);
1448 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1477 unsigned InternalOffset = 4;
1507 EVT VT = Node->getValueType(0);
1515 bool NeedsAlign = Alignment.valueOrOne() >
StackAlign;
1521 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.
getContext());
1522 Args.push_back(Entry);
1524 Entry.Node = DAG.
getConstant(~(Alignment->value() - 1ULL),
DL, VT);
1525 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.
getContext());
1526 Args.push_back(Entry);
1530 EVT PtrVT =
Op.getValueType();
1543 std::pair<SDValue, SDValue> pair =
LowerCallTo(CLI);
1544 Chain = pair.second;
1556 SDValue Ops[2] = {Result, Chain};
1592 unsigned Depth =
Op.getConstantOperandVal(0);
1616 EVT VT =
Op.getValueType();
1626 unsigned IntNo = cast<ConstantSDNode>(
Op.getOperand(0))->getZExtValue();
1630 case Intrinsic::eh_sjlj_lsda: {
1632 MVT VT =
Op.getSimpleValueType();
1639 TM->getStrList()->push_back(std::string(
1655 if (!isa<BuildVectorSDNode>(
N))
1657 const auto *BVN = cast<BuildVectorSDNode>(
N);
1661 for (Idx = 0; Idx < BVN->getNumOperands(); ++Idx) {
1662 auto ElemV = BVN->getOperand(Idx);
1663 if (!ElemV->isUndef())
1667 if (Idx == BVN->getNumOperands())
1672 for (; Idx < BVN->getNumOperands(); ++Idx) {
1673 auto ElemV = BVN->getOperand(Idx);
1674 if (!ElemV->isUndef())
1681 if (
auto *BuildVec = dyn_cast<BuildVectorSDNode>(
N)) {
1682 return BuildVec->getSplatValue();
1690 MVT ResultVT =
Op.getSimpleValueType();
1696 auto ElemV =
Op->getOperand(UniqueIdx);
1731 unsigned Opcode =
Op.getOpcode();
1791 #define ADD_VVP_OP(VVP_NAME, ...) case VEISD::VVP_NAME:
1792 #include "VVPNodes.def"
1801 #define ADD_VVP_OP(VVP_NAME, ISD_NAME) case ISD::ISD_NAME:
1802 #include "VVPNodes.def"
1813 switch (
N->getOpcode()) {
1819 llvm_unreachable(
"Do not know how to custom type legalize this operation!");
1932 bool IsLocal =
false,
1933 bool IsCall =
false)
const {
1942 if (IsCall && !IsLocal) {
1952 }
else if (IsLocal) {
2020 int FI,
int Offset)
const {
2048 MI.memoperands_end());
2053 DstReg =
MI.getOperand(0).getReg();
2100 if (TFI->
hasBP(*MF)) {
2111 MIB.
add(
MI.getOperand(1));
2129 BuildMI(MainMBB,
DL,
TII->get(VE::LEAzii), MainDestReg)
2146 if (TFI->
hasBP(*MF)) {
2148 BuildMI(RestoreMBB,
DL,
TII->get(VE::LDrii), VE::SX17);
2154 BuildMI(RestoreMBB,
DL,
TII->get(VE::LEAzii), RestoreDestReg)
2161 MI.eraseFromParent();
2175 MI.memoperands_end());
2218 MIB.
add(
MI.getOperand(0));
2228 MI.eraseFromParent();
2245 unsigned MaxCSNum = 0;
2246 for (
auto &
MBB : *MF) {
2251 for (
const auto &
MI :
MBB) {
2252 if (
MI.isDebugInstr())
2255 assert(
MI.isEHLabel() &&
"expected EH_LABEL");
2256 Sym =
MI.getOperand(0).getMCSymbol();
2260 if (!MF->hasCallSiteLandingPad(Sym))
2263 for (
unsigned CSI : MF->getCallSiteLandingPad(Sym)) {
2264 CallSiteNumToLPad[CSI].push_back(&
MBB);
2265 MaxCSNum =
std::max(MaxCSNum, CSI);
2270 std::vector<MachineBasicBlock *> LPadList;
2272 LPadList.reserve(CallSiteNumToLPad.
size());
2274 for (
unsigned CSI = 1; CSI <= MaxCSNum; ++CSI) {
2275 for (
auto &LP : CallSiteNumToLPad[CSI]) {
2276 LPadList.push_back(LP);
2277 InvokeBBs.
insert(LP->pred_begin(), LP->pred_end());
2281 assert(!LPadList.empty() &&
2282 "No landing pad destinations for the dispatch jump table!");
2289 static const int OffsetIC = 72;
2290 static const int OffsetCS = 8;
2323 MF->push_back(DispatchBB);
2324 MF->push_back(DispContBB);
2325 MF->push_back(TrapBB);
2353 BuildMI(DispatchBB,
DL,
TII->get(VE::GETGOT), VE::SX15);
2361 if (LPadList.size() < 64) {
2368 assert(LPadList.size() <= 0x7FFFFFFF &&
"Too large Landing Pad!");
2373 .
addImm(LPadList.size());
2479 for (
auto &LP : LPadList)
2480 if (SeenMBBs.
insert(LP).second)
2485 const MCPhysReg *SavedRegs = MF->getRegInfo().getCalleeSavedRegs();
2493 for (
auto MBBS : Successors) {
2494 if (MBBS->isEHPad()) {
2496 MBBLPads.push_back(MBBS);
2511 for (
auto &MOp : II.operands())
2513 DefRegs[MOp.getReg()] =
true;
2516 for (
unsigned RI = 0; SavedRegs[RI]; ++RI) {
2528 for (
auto &LP : MBBLPads)
2529 LP->setIsEHPad(
false);
2532 MI.eraseFromParent();
2539 switch (
MI.getOpcode()) {
2542 case VE::EH_SjLj_LongJmp:
2544 case VE::EH_SjLj_SetJmp:
2546 case VE::EH_SjLj_Setup_Dispatch:
2552 switch (
User->getOpcode()) {
2574 if (
N->getOperand(0).getOpcode() !=
ISD::SRL)
2592 switch (U->getOpcode()) {
2607 "find truncate to not i32 integer");
2626 "Should be called with a TRUNCATE node");
2630 EVT VT =
N->getValueType(0);
2638 isa<ConstantSDNode>(
N->getOperand(0)->getOperand(0)) &&
2639 isa<ConstantSDNode>(
N->getOperand(0)->getOperand(1)))
2658 N->getOperand(0), SubI32),
2664 switch (
N->getOpcode()) {
2680 if (Constraint.
size() == 1) {
2681 switch (Constraint[0]) {
2691 std::pair<unsigned, const TargetRegisterClass *>
2696 if (Constraint.
size() == 1) {
2697 switch (Constraint[0]) {
2701 RC = &VE::I64RegClass;
2704 RC = &VE::V64RegClass;
2707 return std::make_pair(0U, RC);
2726 EVT VT =
Y.getValueType();
2742 if (isa<ConstantSDNode>(
Y))
2752 MVT VT =
Op.getOperand(0).getSimpleValueType();
2797 MVT VT =
Op.getOperand(0).getSimpleValueType();
2842 {HalfIdx, PackedElt, Vec}),
static SDValue lowerLoadF128(SDValue Op, SelectionDAG &DAG)
StringSwitch & Case(StringLiteral S, T Value)
SDValue legalizeInternalVectorOp(SDValue Op, SelectionDAG &DAG) const
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
const SDValue & getOffset() const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
const SDValue & getBasePtr() const
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
MVT getVectorElementType() const
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
Register prepareSymbol(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, StringRef Symbol, const DebugLoc &DL, bool IsLocal, bool IsCall) const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
const uint32_t * getNoPreservedMask() const override
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
unsigned createJumpTableIndex(const std::vector< MachineBasicBlock * > &DestBBs)
createJumpTableIndex - Create a new jump table.
A parsed version of the target data layout string in and methods for querying it.
Information about stack frame layout on the target.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void setReturnAddressIsTaken(bool s)
@ BR_JT
BR_JT - Jumptable branch.
CallLoweringInfo & setChain(SDValue InChain)
CCState - This class holds information needed while lowering arguments and return values.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
@ SjLj
setjmp/longjmp based exceptions
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getRsaSize() const
Get the size of RSA, return address, and frame pointer as described in VEFrameLowering....
const MachineInstrBuilder & add(const MachineOperand &MO) const
Context object for machine code objects.
Register getFrameRegister(const MachineFunction &MF) const override
@ BSWAP
Byte Swap and Counting operators.
LLVM_NODISCARD R Default(T Value)
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
SDValue getValueType(EVT)
bool isPackedVectorType(EVT SomeVT)
BinOp getOperation() const
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
bool isMaskArithmetic(SDValue Op)
Reg
All possible values of the reg field in the ModR/M byte.
EVT getMemoryVT() const
Return the type of the in-memory value.
unsigned getFunctionNumber() const
getFunctionNumber - Return a unique ID for the current function.
const SDValue & getChain() const
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Represents one node in the SelectionDAG.
int getVarArgsFrameOffset() const
This class is used to represent ISD::LOAD nodes.
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isPositionIndependent() const
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
const VERegisterInfo * getRegisterInfo() const override
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
The instances of the Type class are immutable: once they are created, they are never changed.
ConstraintType getConstraintType(StringRef Constraint) const override
Inline Assembly {.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
void setSupportsUnalignedAtomics(bool UnalignedSupported)
Sets whether unaligned atomic operations are supported.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue lowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ EK_BlockAddress
EK_BlockAddress - Each entry is a plain address of block, e.g.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
virtual bool isJumpTableRelative() const
Function Alias Analysis Results
SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
static const MVT AllPackedVTs[]
static const MVT AllVectorVTs[]
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
@ EK_Custom32
EK_Custom32 - Each entry is a 32-bit value that is custom lowered by the TargetLowering::LowerCustomJ...
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
} Custom DAGCombine
unsigned const TargetRegisterInfo * TRI
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
LLVMContext * getContext() const
@ BRCOND
BRCOND - Conditional branch.
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
succ_reverse_iterator succ_rbegin()
SDValue getRegister(unsigned Reg, EVT VT)
LLVM Basic Block Representation.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Register getGlobalBaseReg(MachineFunction *MF) const
} Optimization
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static auto integer_valuetypes()
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Register prepareMBB(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *TargetBB, const DebugLoc &DL) const
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
VETargetLowering(const TargetMachine &TM, const VESubtarget &STI)
@ BR_CC
BR_CC - Conditional branch.
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
TargetInstrInfo - Interface to description of machine instruction set.
EVT getValueType() const
Return the ValueType of the referenced return value.
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Register getLocReg() const
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
SDValue splitMaskArithmetic(SDValue Op, SelectionDAG &DAG) const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const
uint64_t getScalarSizeInBits() const
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
iterator_range< use_iterator > uses()
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
const HexagonInstrInfo * TII
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
SDValue getBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const
const SDValue & getOffset() const
unsigned M0(unsigned Val)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
bool hasBP(const MachineFunction &MF) const
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ System
Synchronized with respect to all concurrently executing threads.
LocInfo getLocInfo() const
MachineBasicBlock * emitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *BB) const
SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const
unsigned getLocMemOffset() const
This struct is a compact representation of a valid (non-zero power of two) alignment.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
static bool isI32Insn(const SDNode *User, const SDNode *N)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned Uid, MCContext &Ctx) const override
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
std::pair< SDValue, bool > getAnnotatedNodeAVL(SDValue Op)
SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
bool isPackingSupportOpcode(unsigned Opc)
SmallVector< ISD::OutputArg, 32 > Outs
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
void push_back(MachineBasicBlock *MBB)
bool isVPOpcode(unsigned Opcode)
Whether this is a vector-predicated Opcode.
CCAssignFn * getParamCC(CallingConv::ID CallConv, bool IsVarArg)
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
unsigned getMinimumJumpTableEntries() const override
} Inline Assembly
Representation of each machine instruction.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Module * getParent()
Get the module that this global value is contained inside of...
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
static SDValue lowerStoreF128(SDValue Op, SelectionDAG &DAG)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
This class contains a discriminated union of information about pointers in memory operands,...
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
This is an important class for using LLVM in a threaded context.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
bool hasAtomicStore() const
Return true if this atomic instruction stores to memory.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue getUNDEF(EVT VT) const
void setVarArgsFrameOffset(int Offset)
SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Flags
Flags values. These may be or'd together.
unsigned getVectorNumElements() const
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
This class is used to represent ISD::STORE nodes.
SDValue getValue(unsigned R) const
This structure contains all information that is necessary for lowering calls.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
succ_reverse_iterator succ_rend()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
void setHasAddressTaken()
Set this block to reflect that it potentially is the target of an indirect branch.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)
A Module instance is used to store all the information related to an LLVM module.
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
const SDValue & getValue() const
const VEFrameLowering * getFrameLowering() const override
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
@ C
C - The default llvm calling convention, compatible with C.
SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const
SmallVector< ISD::InputArg, 32 > Ins
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
TargetLoweringBase::LegalizeAction getCustomOperationAction(SDNode &) const override
Custom Lower {.
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
bool isVector() const
Return true if this is a vector value type.
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
bool isEHPad() const
Returns true if the block is a landing pad.
StringRef - Represent a constant reference to a string, i.e.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isAfterLegalizeDAG() const
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
const SDValue & getOperand(unsigned i) const
Common base class shared among various IRBuilders.
self_iterator getIterator()
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
bool isVVPOrVEC(unsigned Opcode)
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
CCAssignFn * getReturnCC(CallingConv::ID CallConv)
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
@ MOVolatile
The memory access is volatile.
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
an instruction that atomically reads a memory location, combines it with another value,...
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
std::vector< ArgListEntry > ArgListTy
const SDValue & getBasePtr() const
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
amdgpu Simplify well known AMD library false FunctionCallee Callee
This is an SDNode representing atomic operations.
const TargetMachine & getTargetMachine() const
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
const VEInstrInfo * getInstrInfo() const override
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Function & getFunction()
Return the LLVM function that this machine code represents.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, MachineBasicBlock *DispatchBB, int FI, int Offset) const
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
static const MVT AllMaskVTs[]
Iterator for intrusive lists based on ilist_node.
uint64_t value() const
This is a hole in the type system and should not be abused.
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Custom Lower {.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
CallLoweringInfo & setDiscardResult(bool Value=true)
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, EVT VT, bool IsTarget=false, bool IsOpaque=false) const
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
unsigned AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align A, MachineMemOperand::Flags Flags, bool *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
@ ZeroOrOneBooleanContent
unsigned getJumpTableEncoding() const override
JumpTable for VE.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ ADD
Simple integer binary arithmetic operators.
unsigned getAddressSpace() const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
static Type * getVoidTy(LLVMContext &C)
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
unsigned getKillRegState(bool B)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
static bool getUniqueInsertion(SDNode *N, unsigned &UniqueIdx)
SDValue getNode(unsigned OC, SDVTList VTL, ArrayRef< SDValue > OpV, Optional< SDNodeFlags > Flags=None) const
getNode {
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
} Custom Lower
@ SHL
Shift and rotation operations.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
static auto vector_valuetypes()
static SDValue finalizeTS1AM(SDValue Op, SelectionDAG &DAG, SDValue Data, SDValue Bits)
SDValue getRegisterMask(const uint32_t *RegMask)
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
const LLVM_NODISCARD char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
Custom Inserter {.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
SmallVector< SDValue, 32 > OutVals
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
A switch()-like statement whose cases are string literals.
const char LLVMTargetMachineRef TM
@ FNEG
Perform various unary floating-point operations inspired by libm.
MachineFunction & getMachineFunction() const
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
void setFrameAddressIsTaken(bool T)
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Value * getOperand(unsigned i) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
static auto fp_valuetypes()
@ SIGN_EXTEND
Conversion operators.
SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const
} Custom Inserter
static SDValue prepareTS1AM(SDValue Op, SelectionDAG &DAG, SDValue &Flag, SDValue &Bits)
bool isMaskType(EVT SomeVT)
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
CodeModel::Model getCodeModel()
LLVM Value Representation.
const TargetMachine & getTarget() const
Base class for the full range of assembler expressions which are needed for parsing.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
} VVPLowering
const MachinePointerInfo & getPointerInfo() const
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
int getFunctionContextIndex() const
Return the index for the function context object.
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
static MVT getIntegerVT(unsigned BitWidth)
#define TARGET_NODE_CASE(NAME)
@ Undef
Value of the register doesn't matter.