LLVM  14.0.0git
VEInstrInfo.h
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1 //===-- VEInstrInfo.h - VE Instruction Information --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the VE implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_VE_VEINSTRINFO_H
14 #define LLVM_LIB_TARGET_VE_VEINSTRINFO_H
15 
16 #include "VERegisterInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "VEGenInstrInfo.inc"
21 
22 namespace llvm {
23 
24 class VESubtarget;
25 
26 /// VEII - This namespace holds all of the Aurora VE target-specific
27 /// per-instruction flags. These must match the corresponding definitions in
28 /// VEInstrFormats.td.
29 namespace VEII {
30 enum {
31  // Aurora VE Instruction Flags. These flags describe the characteristics of
32  // the Aurora VE instructions for vector handling.
33 
34  /// VE_Vector - This instruction is Vector Instruction.
35  VE_Vector = 0x1,
36 
37  /// VE_VLInUse - This instruction has a vector register in its operands.
38  VE_VLInUse = 0x2,
39 
40  /// VE_VLMask/Shift - This is a bitmask that selects the index number where
41  /// an instruction holds vector length informatio (0 to 6, 7 means undef).n
43  VE_VLMask = 0x07 << VE_VLShift,
44 };
45 
46 #define HAS_VLINDEX(TSF) ((TSF)&VEII::VE_VLInUse)
47 #define GET_VLINDEX(TSF) \
48  (HAS_VLINDEX(TSF) ? (int)(((TSF)&VEII::VE_VLMask) >> VEII::VE_VLShift) : -1)
49 } // end namespace VEII
50 
51 class VEInstrInfo : public VEGenInstrInfo {
52  const VERegisterInfo RI;
53  virtual void anchor();
54 
55 public:
56  explicit VEInstrInfo(VESubtarget &ST);
57 
58  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
59  /// such, whenever a client has an instance of instruction info, it should
60  /// always be able to get register info as well (through this method).
61  ///
62  const VERegisterInfo &getRegisterInfo() const { return RI; }
63 
64  /// Branch Analysis & Modification {
66  MachineBasicBlock *&FBB,
68  bool AllowModify = false) const override;
69 
71  int *BytesRemoved = nullptr) const override;
72 
75  const DebugLoc &DL,
76  int *BytesAdded = nullptr) const override;
77 
78  bool
80  /// } Branch Analysis & Modification
81 
83  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
84  bool KillSrc) const override;
85 
86  /// Stack Spill & Reload {
87  unsigned isLoadFromStackSlot(const MachineInstr &MI,
88  int &FrameIndex) const override;
89  unsigned isStoreToStackSlot(const MachineInstr &MI,
90  int &FrameIndex) const override;
93  bool isKill, int FrameIndex,
94  const TargetRegisterClass *RC,
95  const TargetRegisterInfo *TRI) const override;
96 
99  int FrameIndex, const TargetRegisterClass *RC,
100  const TargetRegisterInfo *TRI) const override;
101  /// } Stack Spill & Reload
102 
103  /// Optimization {
104 
106  MachineRegisterInfo *MRI) const override;
107 
108  /// } Optimization
109 
111 
112  // Lower pseudo instructions after register allocation.
113  bool expandPostRAPseudo(MachineInstr &MI) const override;
114 
117 };
118 
119 } // namespace llvm
120 
121 #endif
llvm::VEInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: VEInstrInfo.cpp:843
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::VEInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: VEInstrInfo.cpp:291
llvm::VEInstrInfo::getRegisterInfo
const VERegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: VEInstrInfo.h:62
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::VEInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: VEInstrInfo.cpp:503
llvm::VEInstrInfo::VEInstrInfo
VEInstrInfo(VESubtarget &ST)
Definition: VEInstrInfo.cpp:38
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
TargetInstrInfo.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::VEInstrInfo::getGlobalBaseReg
Register getGlobalBaseReg(MachineFunction *MF) const
} Optimization
Definition: VEInstrInfo.cpp:724
llvm::VEInstrInfo::expandGetStackTopPseudo
bool expandGetStackTopPseudo(MachineInstr &MI) const
Definition: VEInstrInfo.cpp:1048
llvm::VEInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: VEInstrInfo.cpp:455
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::VEInstrInfo::FoldImmediate
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
} Stack Spill & Reload
Definition: VEInstrInfo.cpp:546
llvm::VEInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
} Branch Analysis & Modification
Definition: VEInstrInfo.cpp:359
llvm::VEII::VE_VLInUse
@ VE_VLInUse
VE_VLInUse - This instruction has a vector register in its operands.
Definition: VEInstrInfo.h:38
llvm::VEInstrInfo
Definition: VEInstrInfo.h:51
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::VEInstrInfo::expandExtendStackPseudo
bool expandExtendStackPseudo(MachineInstr &MI) const
Definition: VEInstrInfo.cpp:964
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
I
#define I(x, y, z)
Definition: MD5.cpp:59
VERegisterInfo.h
llvm::VEInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Branch Analysis & Modification {.
Definition: VEInstrInfo.cpp:145
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::VEInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: VEInstrInfo.cpp:226
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
VEGenInstrInfo
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::VEInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: VEInstrInfo.cpp:314
llvm::VEII::VE_Vector
@ VE_Vector
VE_Vector - This instruction is Vector Instruction.
Definition: VEInstrInfo.h:35
llvm::VERegisterInfo
Definition: VERegisterInfo.h:22
llvm::VEII::VE_VLMask
@ VE_VLMask
Definition: VEInstrInfo.h:43
llvm::VEII::VE_VLShift
@ VE_VLShift
VE_VLMask/Shift - This is a bitmask that selects the index number where an instruction holds vector l...
Definition: VEInstrInfo.h:42
llvm::VESubtarget
Definition: VESubtarget.h:31
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::VEInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Stack Spill & Reload {.
Definition: VEInstrInfo.cpp:416
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::VEInstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
Definition: VEInstrInfo.cpp:438
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24