LLVM  12.0.0git
VEInstrInfo.h
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1 //===-- VEInstrInfo.h - VE Instruction Information --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the VE implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_VE_VEINSTRINFO_H
14 #define LLVM_LIB_TARGET_VE_VEINSTRINFO_H
15 
16 #include "VERegisterInfo.h"
18 
19 #define GET_INSTRINFO_HEADER
20 #include "VEGenInstrInfo.inc"
21 
22 namespace llvm {
23 
24 class VESubtarget;
25 
26 class VEInstrInfo : public VEGenInstrInfo {
27  const VERegisterInfo RI;
28  virtual void anchor();
29 
30 public:
31  explicit VEInstrInfo(VESubtarget &ST);
32 
33  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
34  /// such, whenever a client has an instance of instruction info, it should
35  /// always be able to get register info as well (through this method).
36  ///
37  const VERegisterInfo &getRegisterInfo() const { return RI; }
38 
39  /// Branch Analysis & Modification {
41  MachineBasicBlock *&FBB,
43  bool AllowModify = false) const override;
44 
45  unsigned removeBranch(MachineBasicBlock &MBB,
46  int *BytesRemoved = nullptr) const override;
47 
50  const DebugLoc &DL,
51  int *BytesAdded = nullptr) const override;
52 
53  bool
55  /// } Branch Analysis & Modification
56 
58  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
59  bool KillSrc) const override;
60 
61  /// Stack Spill & Reload {
62  unsigned isLoadFromStackSlot(const MachineInstr &MI,
63  int &FrameIndex) const override;
64  unsigned isStoreToStackSlot(const MachineInstr &MI,
65  int &FrameIndex) const override;
68  bool isKill, int FrameIndex,
69  const TargetRegisterClass *RC,
70  const TargetRegisterInfo *TRI) const override;
71 
74  int FrameIndex, const TargetRegisterClass *RC,
75  const TargetRegisterInfo *TRI) const override;
76  /// } Stack Spill & Reload
77 
79 
80  // Lower pseudo instructions after register allocation.
81  bool expandPostRAPseudo(MachineInstr &MI) const override;
82 
83  bool expandExtendStackPseudo(MachineInstr &MI) const;
84  bool expandGetStackTopPseudo(MachineInstr &MI) const;
85 };
86 
87 } // namespace llvm
88 
89 #endif
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
MachineBasicBlock & MBB
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
Register getGlobalBaseReg(MachineFunction *MF) const
} Stack Spill & Reload
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Branch Analysis & Modification {.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
SmallVector< MachineOperand, 4 > Cond
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const VERegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: VEInstrInfo.h:37
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Stack Spill & Reload {.
bool expandExtendStackPseudo(MachineInstr &MI) const
Representation of each machine instruction.
Definition: MachineInstr.h:62
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
VEInstrInfo(VESubtarget &ST)
Definition: VEInstrInfo.cpp:38
#define I(x, y, z)
Definition: MD5.cpp:59
bool expandGetStackTopPseudo(MachineInstr &MI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
IRTranslator LLVM IR MI
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
} Branch Analysis & Modification
MachineBasicBlock MachineBasicBlock::iterator MBBI
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL