LLVM 17.0.0git
AArch64ExpandPseudoInsts.cpp
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1//===- AArch64ExpandPseudoInsts.cpp - Expand pseudo instructions ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions to allow proper scheduling and other late optimizations. This
11// pass should be run after register allocation but before the post-regalloc
12// scheduling pass.
13//
14//===----------------------------------------------------------------------===//
15
16#include "AArch64ExpandImm.h"
17#include "AArch64InstrInfo.h"
19#include "AArch64Subtarget.h"
22#include "llvm/ADT/DenseMap.h"
32#include "llvm/IR/DebugLoc.h"
33#include "llvm/MC/MCInstrDesc.h"
34#include "llvm/Pass.h"
39#include <cassert>
40#include <cstdint>
41#include <iterator>
42#include <limits>
43#include <utility>
44
45using namespace llvm;
46
47#define AARCH64_EXPAND_PSEUDO_NAME "AArch64 pseudo instruction expansion pass"
48
49namespace {
50
51class AArch64ExpandPseudo : public MachineFunctionPass {
52public:
53 const AArch64InstrInfo *TII;
54
55 static char ID;
56
57 AArch64ExpandPseudo() : MachineFunctionPass(ID) {
59 }
60
61 bool runOnMachineFunction(MachineFunction &Fn) override;
62
63 StringRef getPassName() const override { return AARCH64_EXPAND_PSEUDO_NAME; }
64
65private:
66 bool expandMBB(MachineBasicBlock &MBB);
70 unsigned BitSize);
71
72 bool expand_DestructiveOp(MachineInstr &MI, MachineBasicBlock &MBB,
75 unsigned LdarOp, unsigned StlrOp, unsigned CmpOp,
76 unsigned ExtendImm, unsigned ZeroReg,
78 bool expandCMP_SWAP_128(MachineBasicBlock &MBB,
81 bool expandSetTagLoop(MachineBasicBlock &MBB,
84 bool expandSVESpillFill(MachineBasicBlock &MBB,
86 unsigned N);
87 bool expandCALL_RVMARKER(MachineBasicBlock &MBB,
90 bool expandStoreSwiftAsyncContext(MachineBasicBlock &MBB,
92 MachineBasicBlock *expandRestoreZA(MachineBasicBlock &MBB,
94 MachineBasicBlock *expandCondSMToggle(MachineBasicBlock &MBB,
96};
97
98} // end anonymous namespace
99
100char AArch64ExpandPseudo::ID = 0;
101
102INITIALIZE_PASS(AArch64ExpandPseudo, "aarch64-expand-pseudo",
103 AARCH64_EXPAND_PSEUDO_NAME, false, false)
104
105/// Transfer implicit operands on the pseudo instruction to the
106/// instructions created from the expansion.
107static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI,
109 const MCInstrDesc &Desc = OldMI.getDesc();
110 for (const MachineOperand &MO :
111 llvm::drop_begin(OldMI.operands(), Desc.getNumOperands())) {
112 assert(MO.isReg() && MO.getReg());
113 if (MO.isUse())
114 UseMI.add(MO);
115 else
116 DefMI.add(MO);
117 }
118}
119
120/// Expand a MOVi32imm or MOVi64imm pseudo instruction to one or more
121/// real move-immediate instructions to synthesize the immediate.
122bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
124 unsigned BitSize) {
125 MachineInstr &MI = *MBBI;
126 Register DstReg = MI.getOperand(0).getReg();
127 uint64_t RenamableState =
128 MI.getOperand(0).isRenamable() ? RegState::Renamable : 0;
129 uint64_t Imm = MI.getOperand(1).getImm();
130
131 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) {
132 // Useless def, and we don't want to risk creating an invalid ORR (which
133 // would really write to sp).
134 MI.eraseFromParent();
135 return true;
136 }
137
139 AArch64_IMM::expandMOVImm(Imm, BitSize, Insn);
140 assert(Insn.size() != 0);
141
143 for (auto I = Insn.begin(), E = Insn.end(); I != E; ++I) {
144 bool LastItem = std::next(I) == E;
145 switch (I->Opcode)
146 {
147 default: llvm_unreachable("unhandled!"); break;
148
149 case AArch64::ORRWri:
150 case AArch64::ORRXri:
151 if (I->Op1 == 0) {
152 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
153 .add(MI.getOperand(0))
154 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
155 .addImm(I->Op2));
156 } else {
157 Register DstReg = MI.getOperand(0).getReg();
158 bool DstIsDead = MI.getOperand(0).isDead();
159 MIBS.push_back(
160 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
161 .addReg(DstReg, RegState::Define |
162 getDeadRegState(DstIsDead && LastItem) |
163 RenamableState)
164 .addReg(DstReg)
165 .addImm(I->Op2));
166 }
167 break;
168 case AArch64::ANDXri:
169 if (I->Op1 == 0) {
170 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
171 .add(MI.getOperand(0))
172 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
173 .addImm(I->Op2));
174 } else {
175 Register DstReg = MI.getOperand(0).getReg();
176 bool DstIsDead = MI.getOperand(0).isDead();
177 MIBS.push_back(
178 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
179 .addReg(DstReg, RegState::Define |
180 getDeadRegState(DstIsDead && LastItem) |
181 RenamableState)
182 .addReg(DstReg)
183 .addImm(I->Op2));
184 }
185 break;
186 case AArch64::MOVNWi:
187 case AArch64::MOVNXi:
188 case AArch64::MOVZWi:
189 case AArch64::MOVZXi: {
190 bool DstIsDead = MI.getOperand(0).isDead();
191 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
192 .addReg(DstReg, RegState::Define |
193 getDeadRegState(DstIsDead && LastItem) |
194 RenamableState)
195 .addImm(I->Op1)
196 .addImm(I->Op2));
197 } break;
198 case AArch64::MOVKWi:
199 case AArch64::MOVKXi: {
200 Register DstReg = MI.getOperand(0).getReg();
201 bool DstIsDead = MI.getOperand(0).isDead();
202 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
203 .addReg(DstReg,
205 getDeadRegState(DstIsDead && LastItem) |
206 RenamableState)
207 .addReg(DstReg)
208 .addImm(I->Op1)
209 .addImm(I->Op2));
210 } break;
211 }
212 }
213 transferImpOps(MI, MIBS.front(), MIBS.back());
214 MI.eraseFromParent();
215 return true;
216}
217
218bool AArch64ExpandPseudo::expandCMP_SWAP(
220 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg,
221 MachineBasicBlock::iterator &NextMBBI) {
222 MachineInstr &MI = *MBBI;
223 MIMetadata MIMD(MI);
224 const MachineOperand &Dest = MI.getOperand(0);
225 Register StatusReg = MI.getOperand(1).getReg();
226 bool StatusDead = MI.getOperand(1).isDead();
227 // Duplicating undef operands into 2 instructions does not guarantee the same
228 // value on both; However undef should be replaced by xzr anyway.
229 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
230 Register AddrReg = MI.getOperand(2).getReg();
231 Register DesiredReg = MI.getOperand(3).getReg();
232 Register NewReg = MI.getOperand(4).getReg();
233
235 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
236 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
237 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
238
239 MF->insert(++MBB.getIterator(), LoadCmpBB);
240 MF->insert(++LoadCmpBB->getIterator(), StoreBB);
241 MF->insert(++StoreBB->getIterator(), DoneBB);
242
243 // .Lloadcmp:
244 // mov wStatus, 0
245 // ldaxr xDest, [xAddr]
246 // cmp xDest, xDesired
247 // b.ne .Ldone
248 if (!StatusDead)
249 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::MOVZWi), StatusReg)
250 .addImm(0).addImm(0);
251 BuildMI(LoadCmpBB, MIMD, TII->get(LdarOp), Dest.getReg())
252 .addReg(AddrReg);
253 BuildMI(LoadCmpBB, MIMD, TII->get(CmpOp), ZeroReg)
254 .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
255 .addReg(DesiredReg)
256 .addImm(ExtendImm);
257 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::Bcc))
259 .addMBB(DoneBB)
260 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
261 LoadCmpBB->addSuccessor(DoneBB);
262 LoadCmpBB->addSuccessor(StoreBB);
263
264 // .Lstore:
265 // stlxr wStatus, xNew, [xAddr]
266 // cbnz wStatus, .Lloadcmp
267 BuildMI(StoreBB, MIMD, TII->get(StlrOp), StatusReg)
268 .addReg(NewReg)
269 .addReg(AddrReg);
270 BuildMI(StoreBB, MIMD, TII->get(AArch64::CBNZW))
271 .addReg(StatusReg, getKillRegState(StatusDead))
272 .addMBB(LoadCmpBB);
273 StoreBB->addSuccessor(LoadCmpBB);
274 StoreBB->addSuccessor(DoneBB);
275
276 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
277 DoneBB->transferSuccessors(&MBB);
278
279 MBB.addSuccessor(LoadCmpBB);
280
281 NextMBBI = MBB.end();
282 MI.eraseFromParent();
283
284 // Recompute livein lists.
285 LivePhysRegs LiveRegs;
286 computeAndAddLiveIns(LiveRegs, *DoneBB);
287 computeAndAddLiveIns(LiveRegs, *StoreBB);
288 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
289 // Do an extra pass around the loop to get loop carried registers right.
290 StoreBB->clearLiveIns();
291 computeAndAddLiveIns(LiveRegs, *StoreBB);
292 LoadCmpBB->clearLiveIns();
293 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
294
295 return true;
296}
297
298bool AArch64ExpandPseudo::expandCMP_SWAP_128(
300 MachineBasicBlock::iterator &NextMBBI) {
301 MachineInstr &MI = *MBBI;
302 MIMetadata MIMD(MI);
303 MachineOperand &DestLo = MI.getOperand(0);
304 MachineOperand &DestHi = MI.getOperand(1);
305 Register StatusReg = MI.getOperand(2).getReg();
306 bool StatusDead = MI.getOperand(2).isDead();
307 // Duplicating undef operands into 2 instructions does not guarantee the same
308 // value on both; However undef should be replaced by xzr anyway.
309 assert(!MI.getOperand(3).isUndef() && "cannot handle undef");
310 Register AddrReg = MI.getOperand(3).getReg();
311 Register DesiredLoReg = MI.getOperand(4).getReg();
312 Register DesiredHiReg = MI.getOperand(5).getReg();
313 Register NewLoReg = MI.getOperand(6).getReg();
314 Register NewHiReg = MI.getOperand(7).getReg();
315
316 unsigned LdxpOp, StxpOp;
317
318 switch (MI.getOpcode()) {
319 case AArch64::CMP_SWAP_128_MONOTONIC:
320 LdxpOp = AArch64::LDXPX;
321 StxpOp = AArch64::STXPX;
322 break;
323 case AArch64::CMP_SWAP_128_RELEASE:
324 LdxpOp = AArch64::LDXPX;
325 StxpOp = AArch64::STLXPX;
326 break;
327 case AArch64::CMP_SWAP_128_ACQUIRE:
328 LdxpOp = AArch64::LDAXPX;
329 StxpOp = AArch64::STXPX;
330 break;
331 case AArch64::CMP_SWAP_128:
332 LdxpOp = AArch64::LDAXPX;
333 StxpOp = AArch64::STLXPX;
334 break;
335 default:
336 llvm_unreachable("Unexpected opcode");
337 }
338
340 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
341 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
342 auto FailBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
343 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
344
345 MF->insert(++MBB.getIterator(), LoadCmpBB);
346 MF->insert(++LoadCmpBB->getIterator(), StoreBB);
347 MF->insert(++StoreBB->getIterator(), FailBB);
348 MF->insert(++FailBB->getIterator(), DoneBB);
349
350 // .Lloadcmp:
351 // ldaxp xDestLo, xDestHi, [xAddr]
352 // cmp xDestLo, xDesiredLo
353 // sbcs xDestHi, xDesiredHi
354 // b.ne .Ldone
355 BuildMI(LoadCmpBB, MIMD, TII->get(LdxpOp))
356 .addReg(DestLo.getReg(), RegState::Define)
357 .addReg(DestHi.getReg(), RegState::Define)
358 .addReg(AddrReg);
359 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::SUBSXrs), AArch64::XZR)
360 .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
361 .addReg(DesiredLoReg)
362 .addImm(0);
363 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::CSINCWr), StatusReg)
364 .addUse(AArch64::WZR)
365 .addUse(AArch64::WZR)
367 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::SUBSXrs), AArch64::XZR)
368 .addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
369 .addReg(DesiredHiReg)
370 .addImm(0);
371 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::CSINCWr), StatusReg)
372 .addUse(StatusReg, RegState::Kill)
373 .addUse(StatusReg, RegState::Kill)
375 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::CBNZW))
376 .addUse(StatusReg, getKillRegState(StatusDead))
377 .addMBB(FailBB);
378 LoadCmpBB->addSuccessor(FailBB);
379 LoadCmpBB->addSuccessor(StoreBB);
380
381 // .Lstore:
382 // stlxp wStatus, xNewLo, xNewHi, [xAddr]
383 // cbnz wStatus, .Lloadcmp
384 BuildMI(StoreBB, MIMD, TII->get(StxpOp), StatusReg)
385 .addReg(NewLoReg)
386 .addReg(NewHiReg)
387 .addReg(AddrReg);
388 BuildMI(StoreBB, MIMD, TII->get(AArch64::CBNZW))
389 .addReg(StatusReg, getKillRegState(StatusDead))
390 .addMBB(LoadCmpBB);
391 BuildMI(StoreBB, MIMD, TII->get(AArch64::B)).addMBB(DoneBB);
392 StoreBB->addSuccessor(LoadCmpBB);
393 StoreBB->addSuccessor(DoneBB);
394
395 // .Lfail:
396 // stlxp wStatus, xDestLo, xDestHi, [xAddr]
397 // cbnz wStatus, .Lloadcmp
398 BuildMI(FailBB, MIMD, TII->get(StxpOp), StatusReg)
399 .addReg(DestLo.getReg())
400 .addReg(DestHi.getReg())
401 .addReg(AddrReg);
402 BuildMI(FailBB, MIMD, TII->get(AArch64::CBNZW))
403 .addReg(StatusReg, getKillRegState(StatusDead))
404 .addMBB(LoadCmpBB);
405 FailBB->addSuccessor(LoadCmpBB);
406 FailBB->addSuccessor(DoneBB);
407
408 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
409 DoneBB->transferSuccessors(&MBB);
410
411 MBB.addSuccessor(LoadCmpBB);
412
413 NextMBBI = MBB.end();
414 MI.eraseFromParent();
415
416 // Recompute liveness bottom up.
417 LivePhysRegs LiveRegs;
418 computeAndAddLiveIns(LiveRegs, *DoneBB);
419 computeAndAddLiveIns(LiveRegs, *FailBB);
420 computeAndAddLiveIns(LiveRegs, *StoreBB);
421 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
422
423 // Do an extra pass in the loop to get the loop carried dependencies right.
424 FailBB->clearLiveIns();
425 computeAndAddLiveIns(LiveRegs, *FailBB);
426 StoreBB->clearLiveIns();
427 computeAndAddLiveIns(LiveRegs, *StoreBB);
428 LoadCmpBB->clearLiveIns();
429 computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
430
431 return true;
432}
433
434/// \brief Expand Pseudos to Instructions with destructive operands.
435///
436/// This mechanism uses MOVPRFX instructions for zeroing the false lanes
437/// or for fixing relaxed register allocation conditions to comply with
438/// the instructions register constraints. The latter case may be cheaper
439/// than setting the register constraints in the register allocator,
440/// since that will insert regular MOV instructions rather than MOVPRFX.
441///
442/// Example (after register allocation):
443///
444/// FSUB_ZPZZ_ZERO_B Z0, Pg, Z1, Z0
445///
446/// * The Pseudo FSUB_ZPZZ_ZERO_B maps to FSUB_ZPmZ_B.
447/// * We cannot map directly to FSUB_ZPmZ_B because the register
448/// constraints of the instruction are not met.
449/// * Also the _ZERO specifies the false lanes need to be zeroed.
450///
451/// We first try to see if the destructive operand == result operand,
452/// if not, we try to swap the operands, e.g.
453///
454/// FSUB_ZPmZ_B Z0, Pg/m, Z0, Z1
455///
456/// But because FSUB_ZPmZ is not commutative, this is semantically
457/// different, so we need a reverse instruction:
458///
459/// FSUBR_ZPmZ_B Z0, Pg/m, Z0, Z1
460///
461/// Then we implement the zeroing of the false lanes of Z0 by adding
462/// a zeroing MOVPRFX instruction:
463///
464/// MOVPRFX_ZPzZ_B Z0, Pg/z, Z0
465/// FSUBR_ZPmZ_B Z0, Pg/m, Z0, Z1
466///
467/// Note that this can only be done for _ZERO or _UNDEF variants where
468/// we can guarantee the false lanes to be zeroed (by implementing this)
469/// or that they are undef (don't care / not used), otherwise the
470/// swapping of operands is illegal because the operation is not
471/// (or cannot be emulated to be) fully commutative.
472bool AArch64ExpandPseudo::expand_DestructiveOp(
476 unsigned Opcode = AArch64::getSVEPseudoMap(MI.getOpcode());
477 uint64_t DType = TII->get(Opcode).TSFlags & AArch64::DestructiveInstTypeMask;
478 uint64_t FalseLanes = MI.getDesc().TSFlags & AArch64::FalseLanesMask;
479 bool FalseZero = FalseLanes == AArch64::FalseLanesZero;
480 Register DstReg = MI.getOperand(0).getReg();
481 bool DstIsDead = MI.getOperand(0).isDead();
482 bool UseRev = false;
483 unsigned PredIdx, DOPIdx, SrcIdx, Src2Idx;
484
485 switch (DType) {
488 if (DstReg == MI.getOperand(3).getReg()) {
489 // FSUB Zd, Pg, Zs1, Zd ==> FSUBR Zd, Pg/m, Zd, Zs1
490 std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(1, 3, 2);
491 UseRev = true;
492 break;
493 }
494 [[fallthrough]];
497 std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(1, 2, 3);
498 break;
500 std::tie(PredIdx, DOPIdx, SrcIdx) = std::make_tuple(2, 3, 3);
501 break;
503 std::tie(PredIdx, DOPIdx, SrcIdx, Src2Idx) = std::make_tuple(1, 2, 3, 4);
504 if (DstReg == MI.getOperand(3).getReg()) {
505 // FMLA Zd, Pg, Za, Zd, Zm ==> FMAD Zdn, Pg, Zm, Za
506 std::tie(PredIdx, DOPIdx, SrcIdx, Src2Idx) = std::make_tuple(1, 3, 4, 2);
507 UseRev = true;
508 } else if (DstReg == MI.getOperand(4).getReg()) {
509 // FMLA Zd, Pg, Za, Zm, Zd ==> FMAD Zdn, Pg, Zm, Za
510 std::tie(PredIdx, DOPIdx, SrcIdx, Src2Idx) = std::make_tuple(1, 4, 3, 2);
511 UseRev = true;
512 }
513 break;
514 default:
515 llvm_unreachable("Unsupported Destructive Operand type");
516 }
517
518 // MOVPRFX can only be used if the destination operand
519 // is the destructive operand, not as any other operand,
520 // so the Destructive Operand must be unique.
521 bool DOPRegIsUnique = false;
522 switch (DType) {
524 DOPRegIsUnique = DstReg != MI.getOperand(SrcIdx).getReg();
525 break;
528 DOPRegIsUnique =
529 DstReg != MI.getOperand(DOPIdx).getReg() ||
530 MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg();
531 break;
534 DOPRegIsUnique = true;
535 break;
537 DOPRegIsUnique =
538 DstReg != MI.getOperand(DOPIdx).getReg() ||
539 (MI.getOperand(DOPIdx).getReg() != MI.getOperand(SrcIdx).getReg() &&
540 MI.getOperand(DOPIdx).getReg() != MI.getOperand(Src2Idx).getReg());
541 break;
542 }
543
544 // Resolve the reverse opcode
545 if (UseRev) {
546 int NewOpcode;
547 // e.g. DIV -> DIVR
548 if ((NewOpcode = AArch64::getSVERevInstr(Opcode)) != -1)
549 Opcode = NewOpcode;
550 // e.g. DIVR -> DIV
551 else if ((NewOpcode = AArch64::getSVENonRevInstr(Opcode)) != -1)
552 Opcode = NewOpcode;
553 }
554
555 // Get the right MOVPRFX
556 uint64_t ElementSize = TII->getElementSizeForOpcode(Opcode);
557 unsigned MovPrfx, LSLZero, MovPrfxZero;
558 switch (ElementSize) {
561 MovPrfx = AArch64::MOVPRFX_ZZ;
562 LSLZero = AArch64::LSL_ZPmI_B;
563 MovPrfxZero = AArch64::MOVPRFX_ZPzZ_B;
564 break;
566 MovPrfx = AArch64::MOVPRFX_ZZ;
567 LSLZero = AArch64::LSL_ZPmI_H;
568 MovPrfxZero = AArch64::MOVPRFX_ZPzZ_H;
569 break;
571 MovPrfx = AArch64::MOVPRFX_ZZ;
572 LSLZero = AArch64::LSL_ZPmI_S;
573 MovPrfxZero = AArch64::MOVPRFX_ZPzZ_S;
574 break;
576 MovPrfx = AArch64::MOVPRFX_ZZ;
577 LSLZero = AArch64::LSL_ZPmI_D;
578 MovPrfxZero = AArch64::MOVPRFX_ZPzZ_D;
579 break;
580 default:
581 llvm_unreachable("Unsupported ElementSize");
582 }
583
584 //
585 // Create the destructive operation (if required)
586 //
587 MachineInstrBuilder PRFX, DOP;
588 if (FalseZero) {
589 // If we cannot prefix the requested instruction we'll instead emit a
590 // prefixed_zeroing_mov for DestructiveBinary.
591 assert((DOPRegIsUnique || DType == AArch64::DestructiveBinary ||
594 "The destructive operand should be unique");
595 assert(ElementSize != AArch64::ElementSizeNone &&
596 "This instruction is unpredicated");
597
598 // Merge source operand into destination register
599 PRFX = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MovPrfxZero))
600 .addReg(DstReg, RegState::Define)
601 .addReg(MI.getOperand(PredIdx).getReg())
602 .addReg(MI.getOperand(DOPIdx).getReg());
603
604 // After the movprfx, the destructive operand is same as Dst
605 DOPIdx = 0;
606
607 // Create the additional LSL to zero the lanes when the DstReg is not
608 // unique. Zeros the lanes in z0 that aren't active in p0 with sequence
609 // movprfx z0.b, p0/z, z0.b; lsl z0.b, p0/m, z0.b, #0;
610 if ((DType == AArch64::DestructiveBinary ||
613 !DOPRegIsUnique) {
614 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LSLZero))
615 .addReg(DstReg, RegState::Define)
616 .add(MI.getOperand(PredIdx))
617 .addReg(DstReg)
618 .addImm(0);
619 }
620 } else if (DstReg != MI.getOperand(DOPIdx).getReg()) {
621 assert(DOPRegIsUnique && "The destructive operand should be unique");
622 PRFX = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(MovPrfx))
623 .addReg(DstReg, RegState::Define)
624 .addReg(MI.getOperand(DOPIdx).getReg());
625 DOPIdx = 0;
626 }
627
628 //
629 // Create the destructive operation
630 //
631 DOP = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode))
632 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead));
633
634 switch (DType) {
636 DOP.addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill)
637 .add(MI.getOperand(PredIdx))
638 .add(MI.getOperand(SrcIdx));
639 break;
644 DOP.add(MI.getOperand(PredIdx))
645 .addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill)
646 .add(MI.getOperand(SrcIdx));
647 break;
649 DOP.add(MI.getOperand(PredIdx))
650 .addReg(MI.getOperand(DOPIdx).getReg(), RegState::Kill)
651 .add(MI.getOperand(SrcIdx))
652 .add(MI.getOperand(Src2Idx));
653 break;
654 }
655
656 if (PRFX) {
658 transferImpOps(MI, PRFX, DOP);
659 } else
660 transferImpOps(MI, DOP, DOP);
661
662 MI.eraseFromParent();
663 return true;
664}
665
666bool AArch64ExpandPseudo::expandSetTagLoop(
668 MachineBasicBlock::iterator &NextMBBI) {
669 MachineInstr &MI = *MBBI;
670 DebugLoc DL = MI.getDebugLoc();
671 Register SizeReg = MI.getOperand(0).getReg();
672 Register AddressReg = MI.getOperand(1).getReg();
673
675
676 bool ZeroData = MI.getOpcode() == AArch64::STZGloop_wback;
677 const unsigned OpCode1 =
678 ZeroData ? AArch64::STZGPostIndex : AArch64::STGPostIndex;
679 const unsigned OpCode2 =
680 ZeroData ? AArch64::STZ2GPostIndex : AArch64::ST2GPostIndex;
681
682 unsigned Size = MI.getOperand(2).getImm();
683 assert(Size > 0 && Size % 16 == 0);
684 if (Size % (16 * 2) != 0) {
685 BuildMI(MBB, MBBI, DL, TII->get(OpCode1), AddressReg)
686 .addReg(AddressReg)
687 .addReg(AddressReg)
688 .addImm(1);
689 Size -= 16;
690 }
692 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVi64imm), SizeReg)
693 .addImm(Size);
694 expandMOVImm(MBB, I, 64);
695
696 auto LoopBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
697 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
698
699 MF->insert(++MBB.getIterator(), LoopBB);
700 MF->insert(++LoopBB->getIterator(), DoneBB);
701
702 BuildMI(LoopBB, DL, TII->get(OpCode2))
703 .addDef(AddressReg)
704 .addReg(AddressReg)
705 .addReg(AddressReg)
706 .addImm(2)
708 .setMIFlags(MI.getFlags());
709 BuildMI(LoopBB, DL, TII->get(AArch64::SUBXri))
710 .addDef(SizeReg)
711 .addReg(SizeReg)
712 .addImm(16 * 2)
713 .addImm(0);
714 BuildMI(LoopBB, DL, TII->get(AArch64::CBNZX)).addUse(SizeReg).addMBB(LoopBB);
715
716 LoopBB->addSuccessor(LoopBB);
717 LoopBB->addSuccessor(DoneBB);
718
719 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
720 DoneBB->transferSuccessors(&MBB);
721
722 MBB.addSuccessor(LoopBB);
723
724 NextMBBI = MBB.end();
725 MI.eraseFromParent();
726 // Recompute liveness bottom up.
727 LivePhysRegs LiveRegs;
728 computeAndAddLiveIns(LiveRegs, *DoneBB);
729 computeAndAddLiveIns(LiveRegs, *LoopBB);
730 // Do an extra pass in the loop to get the loop carried dependencies right.
731 // FIXME: is this necessary?
732 LoopBB->clearLiveIns();
733 computeAndAddLiveIns(LiveRegs, *LoopBB);
734 DoneBB->clearLiveIns();
735 computeAndAddLiveIns(LiveRegs, *DoneBB);
736
737 return true;
738}
739
740bool AArch64ExpandPseudo::expandSVESpillFill(MachineBasicBlock &MBB,
742 unsigned Opc, unsigned N) {
743 const TargetRegisterInfo *TRI =
745 MachineInstr &MI = *MBBI;
746 for (unsigned Offset = 0; Offset < N; ++Offset) {
747 int ImmOffset = MI.getOperand(2).getImm() + Offset;
748 bool Kill = (Offset + 1 == N) ? MI.getOperand(1).isKill() : false;
749 assert(ImmOffset >= -256 && ImmOffset < 256 &&
750 "Immediate spill offset out of range");
751 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
752 .addReg(
753 TRI->getSubReg(MI.getOperand(0).getReg(), AArch64::zsub0 + Offset),
754 Opc == AArch64::LDR_ZXI ? RegState::Define : 0)
755 .addReg(MI.getOperand(1).getReg(), getKillRegState(Kill))
756 .addImm(ImmOffset);
757 }
758 MI.eraseFromParent();
759 return true;
760}
761
762bool AArch64ExpandPseudo::expandCALL_RVMARKER(
764 // Expand CALL_RVMARKER pseudo to:
765 // - a branch to the call target, followed by
766 // - the special `mov x29, x29` marker, and
767 // - another branch, to the runtime function
768 // Mark the sequence as bundle, to avoid passes moving other code in between.
769 MachineInstr &MI = *MBBI;
770
771 MachineInstr *OriginalCall;
772 MachineOperand &RVTarget = MI.getOperand(0);
773 MachineOperand &CallTarget = MI.getOperand(1);
774 assert((CallTarget.isGlobal() || CallTarget.isReg()) &&
775 "invalid operand for regular call");
776 assert(RVTarget.isGlobal() && "invalid operand for attached call");
777 unsigned Opc = CallTarget.isGlobal() ? AArch64::BL : AArch64::BLR;
778 OriginalCall = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)).getInstr();
779 OriginalCall->addOperand(CallTarget);
780
781 unsigned RegMaskStartIdx = 2;
782 // Skip register arguments. Those are added during ISel, but are not
783 // needed for the concrete branch.
784 while (!MI.getOperand(RegMaskStartIdx).isRegMask()) {
785 auto MOP = MI.getOperand(RegMaskStartIdx);
786 assert(MOP.isReg() && "can only add register operands");
788 MOP.getReg(), /*Def=*/false, /*Implicit=*/true));
789 RegMaskStartIdx++;
790 }
791 for (const MachineOperand &MO :
792 llvm::drop_begin(MI.operands(), RegMaskStartIdx))
793 OriginalCall->addOperand(MO);
794
795 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXrs))
796 .addReg(AArch64::FP, RegState::Define)
797 .addReg(AArch64::XZR)
798 .addReg(AArch64::FP)
799 .addImm(0);
800
801 auto *RVCall = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::BL))
802 .add(RVTarget)
803 .getInstr();
804
805 if (MI.shouldUpdateCallSiteInfo())
806 MBB.getParent()->moveCallSiteInfo(&MI, OriginalCall);
807
808 MI.eraseFromParent();
809 finalizeBundle(MBB, OriginalCall->getIterator(),
810 std::next(RVCall->getIterator()));
811 return true;
812}
813
814bool AArch64ExpandPseudo::expandCALL_BTI(MachineBasicBlock &MBB,
816 // Expand CALL_BTI pseudo to:
817 // - a branch to the call target
818 // - a BTI instruction
819 // Mark the sequence as a bundle, to avoid passes moving other code in
820 // between.
821
822 MachineInstr &MI = *MBBI;
823 MachineOperand &CallTarget = MI.getOperand(0);
824 assert((CallTarget.isGlobal() || CallTarget.isReg()) &&
825 "invalid operand for regular call");
826 unsigned Opc = CallTarget.isGlobal() ? AArch64::BL : AArch64::BLR;
828 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)).getInstr();
829 Call->addOperand(CallTarget);
830 Call->setCFIType(*MBB.getParent(), MI.getCFIType());
831
832 MachineInstr *BTI =
833 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::HINT))
834 // BTI J so that setjmp can to BR to this.
835 .addImm(36)
836 .getInstr();
837
838 if (MI.shouldUpdateCallSiteInfo())
839 MBB.getParent()->moveCallSiteInfo(&MI, Call);
840
841 MI.eraseFromParent();
842 finalizeBundle(MBB, Call->getIterator(), std::next(BTI->getIterator()));
843 return true;
844}
845
846bool AArch64ExpandPseudo::expandStoreSwiftAsyncContext(
848 Register CtxReg = MBBI->getOperand(0).getReg();
849 Register BaseReg = MBBI->getOperand(1).getReg();
850 int Offset = MBBI->getOperand(2).getImm();
851 DebugLoc DL(MBBI->getDebugLoc());
852 auto &STI = MBB.getParent()->getSubtarget<AArch64Subtarget>();
853
854 if (STI.getTargetTriple().getArchName() != "arm64e") {
855 BuildMI(MBB, MBBI, DL, TII->get(AArch64::STRXui))
856 .addUse(CtxReg)
857 .addUse(BaseReg)
858 .addImm(Offset / 8)
861 return true;
862 }
863
864 // We need to sign the context in an address-discriminated way. 0xc31a is a
865 // fixed random value, chosen as part of the ABI.
866 // add x16, xBase, #Offset
867 // movk x16, #0xc31a, lsl #48
868 // mov x17, x22/xzr
869 // pacdb x17, x16
870 // str x17, [xBase, #Offset]
871 unsigned Opc = Offset >= 0 ? AArch64::ADDXri : AArch64::SUBXri;
872 BuildMI(MBB, MBBI, DL, TII->get(Opc), AArch64::X16)
873 .addUse(BaseReg)
874 .addImm(abs(Offset))
875 .addImm(0)
877 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVKXi), AArch64::X16)
878 .addUse(AArch64::X16)
879 .addImm(0xc31a)
880 .addImm(48)
882 // We're not allowed to clobber X22 (and couldn't clobber XZR if we tried), so
883 // move it somewhere before signing.
884 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ORRXrs), AArch64::X17)
885 .addUse(AArch64::XZR)
886 .addUse(CtxReg)
887 .addImm(0)
889 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACDB), AArch64::X17)
890 .addUse(AArch64::X17)
891 .addUse(AArch64::X16)
893 BuildMI(MBB, MBBI, DL, TII->get(AArch64::STRXui))
894 .addUse(AArch64::X17)
895 .addUse(BaseReg)
896 .addImm(Offset / 8)
898
900 return true;
901}
902
904AArch64ExpandPseudo::expandRestoreZA(MachineBasicBlock &MBB,
906 MachineInstr &MI = *MBBI;
907 assert((std::next(MBBI) != MBB.end() ||
908 MI.getParent()->successors().begin() !=
909 MI.getParent()->successors().end()) &&
910 "Unexpected unreachable in block that restores ZA");
911
912 // Compare TPIDR2_EL0 value against 0.
913 DebugLoc DL = MI.getDebugLoc();
914 MachineInstrBuilder Cbz = BuildMI(MBB, MBBI, DL, TII->get(AArch64::CBZX))
915 .add(MI.getOperand(0));
916
917 // Split MBB and create two new blocks:
918 // - MBB now contains all instructions before RestoreZAPseudo.
919 // - SMBB contains the RestoreZAPseudo instruction only.
920 // - EndBB contains all instructions after RestoreZAPseudo.
921 MachineInstr &PrevMI = *std::prev(MBBI);
922 MachineBasicBlock *SMBB = MBB.splitAt(PrevMI, /*UpdateLiveIns*/ true);
923 MachineBasicBlock *EndBB = std::next(MI.getIterator()) == SMBB->end()
924 ? *SMBB->successors().begin()
925 : SMBB->splitAt(MI, /*UpdateLiveIns*/ true);
926
927 // Add the SMBB label to the TB[N]Z instruction & create a branch to EndBB.
928 Cbz.addMBB(SMBB);
929 BuildMI(&MBB, DL, TII->get(AArch64::B))
930 .addMBB(EndBB);
931 MBB.addSuccessor(EndBB);
932
933 // Replace the pseudo with a call (BL).
935 BuildMI(*SMBB, SMBB->end(), DL, TII->get(AArch64::BL));
936 MIB.addReg(MI.getOperand(1).getReg(), RegState::Implicit);
937 for (unsigned I = 2; I < MI.getNumOperands(); ++I)
938 MIB.add(MI.getOperand(I));
939 BuildMI(SMBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
940
941 MI.eraseFromParent();
942 return EndBB;
943}
944
946AArch64ExpandPseudo::expandCondSMToggle(MachineBasicBlock &MBB,
948 MachineInstr &MI = *MBBI;
949 // In the case of a smstart/smstop before a unreachable, just remove the pseudo.
950 // Exception handling code generated by Clang may introduce unreachables and it
951 // seems unnecessary to restore pstate.sm when that happens. Note that it is
952 // not just an optimisation, the code below expects a successor instruction/block
953 // in order to split the block at MBBI.
954 if (std::next(MBBI) == MBB.end() &&
955 MI.getParent()->successors().begin() ==
956 MI.getParent()->successors().end()) {
957 MI.eraseFromParent();
958 return &MBB;
959 }
960
961 // Expand the pseudo into smstart or smstop instruction. The pseudo has the
962 // following operands:
963 //
964 // MSRpstatePseudo <za|sm|both>, <0|1>, pstate.sm, expectedval, <regmask>
965 //
966 // The pseudo is expanded into a conditional smstart/smstop, with a
967 // check if pstate.sm (register) equals the expected value, and if not,
968 // invokes the smstart/smstop.
969 //
970 // As an example, the following block contains a normal call from a
971 // streaming-compatible function:
972 //
973 // OrigBB:
974 // MSRpstatePseudo 3, 0, %0, 0, <regmask> <- Conditional SMSTOP
975 // bl @normal_callee
976 // MSRpstatePseudo 3, 1, %0, 0, <regmask> <- Conditional SMSTART
977 //
978 // ...which will be transformed into:
979 //
980 // OrigBB:
981 // TBNZx %0:gpr64, 0, SMBB
982 // b EndBB
983 //
984 // SMBB:
985 // MSRpstatesvcrImm1 3, 0, <regmask> <- SMSTOP
986 //
987 // EndBB:
988 // bl @normal_callee
989 // MSRcond_pstatesvcrImm1 3, 1, <regmask> <- SMSTART
990 //
991 DebugLoc DL = MI.getDebugLoc();
992
993 // Create the conditional branch based on the third operand of the
994 // instruction, which tells us if we are wrapping a normal or streaming
995 // function.
996 // We test the live value of pstate.sm and toggle pstate.sm if this is not the
997 // expected value for the callee (0 for a normal callee and 1 for a streaming
998 // callee).
999 auto PStateSM = MI.getOperand(2).getReg();
1000 bool IsStreamingCallee = MI.getOperand(3).getImm();
1001 unsigned Opc = IsStreamingCallee ? AArch64::TBZX : AArch64::TBNZX;
1003 BuildMI(MBB, MBBI, DL, TII->get(Opc)).addReg(PStateSM).addImm(0);
1004
1005 // Split MBB and create two new blocks:
1006 // - MBB now contains all instructions before MSRcond_pstatesvcrImm1.
1007 // - SMBB contains the MSRcond_pstatesvcrImm1 instruction only.
1008 // - EndBB contains all instructions after MSRcond_pstatesvcrImm1.
1009 MachineInstr &PrevMI = *std::prev(MBBI);
1010 MachineBasicBlock *SMBB = MBB.splitAt(PrevMI, /*UpdateLiveIns*/ true);
1011 MachineBasicBlock *EndBB = std::next(MI.getIterator()) == SMBB->end()
1012 ? *SMBB->successors().begin()
1013 : SMBB->splitAt(MI, /*UpdateLiveIns*/ true);
1014
1015 // Add the SMBB label to the TB[N]Z instruction & create a branch to EndBB.
1016 Tbx.addMBB(SMBB);
1017 BuildMI(&MBB, DL, TII->get(AArch64::B))
1018 .addMBB(EndBB);
1019 MBB.addSuccessor(EndBB);
1020
1021 // Create the SMSTART/SMSTOP (MSRpstatesvcrImm1) instruction in SMBB.
1022 MachineInstrBuilder MIB = BuildMI(*SMBB, SMBB->begin(), MI.getDebugLoc(),
1023 TII->get(AArch64::MSRpstatesvcrImm1));
1024 // Copy all but the second and third operands of MSRcond_pstatesvcrImm1 (as
1025 // these contain the CopyFromReg for the first argument and the flag to
1026 // indicate whether the callee is streaming or normal).
1027 MIB.add(MI.getOperand(0));
1028 MIB.add(MI.getOperand(1));
1029 for (unsigned i = 4; i < MI.getNumOperands(); ++i)
1030 MIB.add(MI.getOperand(i));
1031
1032 BuildMI(SMBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
1033
1034 MI.eraseFromParent();
1035 return EndBB;
1036}
1037
1038/// If MBBI references a pseudo instruction that should be expanded here,
1039/// do the expansion and return true. Otherwise return false.
1040bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
1042 MachineBasicBlock::iterator &NextMBBI) {
1043 MachineInstr &MI = *MBBI;
1044 unsigned Opcode = MI.getOpcode();
1045
1046 // Check if we can expand the destructive op
1047 int OrigInstr = AArch64::getSVEPseudoMap(MI.getOpcode());
1048 if (OrigInstr != -1) {
1049 auto &Orig = TII->get(OrigInstr);
1050 if ((Orig.TSFlags & AArch64::DestructiveInstTypeMask) !=
1052 return expand_DestructiveOp(MI, MBB, MBBI);
1053 }
1054 }
1055
1056 switch (Opcode) {
1057 default:
1058 break;
1059
1060 case AArch64::BSPv8i8:
1061 case AArch64::BSPv16i8: {
1062 Register DstReg = MI.getOperand(0).getReg();
1063 if (DstReg == MI.getOperand(3).getReg()) {
1064 // Expand to BIT
1065 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1066 TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BITv8i8
1067 : AArch64::BITv16i8))
1068 .add(MI.getOperand(0))
1069 .add(MI.getOperand(3))
1070 .add(MI.getOperand(2))
1071 .add(MI.getOperand(1));
1072 } else if (DstReg == MI.getOperand(2).getReg()) {
1073 // Expand to BIF
1074 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1075 TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BIFv8i8
1076 : AArch64::BIFv16i8))
1077 .add(MI.getOperand(0))
1078 .add(MI.getOperand(2))
1079 .add(MI.getOperand(3))
1080 .add(MI.getOperand(1));
1081 } else {
1082 // Expand to BSL, use additional move if required
1083 if (DstReg == MI.getOperand(1).getReg()) {
1084 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1085 TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8
1086 : AArch64::BSLv16i8))
1087 .add(MI.getOperand(0))
1088 .add(MI.getOperand(1))
1089 .add(MI.getOperand(2))
1090 .add(MI.getOperand(3));
1091 } else {
1092 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1093 TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::ORRv8i8
1094 : AArch64::ORRv16i8))
1095 .addReg(DstReg,
1097 getRenamableRegState(MI.getOperand(0).isRenamable()))
1098 .add(MI.getOperand(1))
1099 .add(MI.getOperand(1));
1100 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1101 TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8
1102 : AArch64::BSLv16i8))
1103 .add(MI.getOperand(0))
1104 .addReg(DstReg,
1106 getRenamableRegState(MI.getOperand(0).isRenamable()))
1107 .add(MI.getOperand(2))
1108 .add(MI.getOperand(3));
1109 }
1110 }
1111 MI.eraseFromParent();
1112 return true;
1113 }
1114
1115 case AArch64::ADDWrr:
1116 case AArch64::SUBWrr:
1117 case AArch64::ADDXrr:
1118 case AArch64::SUBXrr:
1119 case AArch64::ADDSWrr:
1120 case AArch64::SUBSWrr:
1121 case AArch64::ADDSXrr:
1122 case AArch64::SUBSXrr:
1123 case AArch64::ANDWrr:
1124 case AArch64::ANDXrr:
1125 case AArch64::BICWrr:
1126 case AArch64::BICXrr:
1127 case AArch64::ANDSWrr:
1128 case AArch64::ANDSXrr:
1129 case AArch64::BICSWrr:
1130 case AArch64::BICSXrr:
1131 case AArch64::EONWrr:
1132 case AArch64::EONXrr:
1133 case AArch64::EORWrr:
1134 case AArch64::EORXrr:
1135 case AArch64::ORNWrr:
1136 case AArch64::ORNXrr:
1137 case AArch64::ORRWrr:
1138 case AArch64::ORRXrr: {
1139 unsigned Opcode;
1140 switch (MI.getOpcode()) {
1141 default:
1142 return false;
1143 case AArch64::ADDWrr: Opcode = AArch64::ADDWrs; break;
1144 case AArch64::SUBWrr: Opcode = AArch64::SUBWrs; break;
1145 case AArch64::ADDXrr: Opcode = AArch64::ADDXrs; break;
1146 case AArch64::SUBXrr: Opcode = AArch64::SUBXrs; break;
1147 case AArch64::ADDSWrr: Opcode = AArch64::ADDSWrs; break;
1148 case AArch64::SUBSWrr: Opcode = AArch64::SUBSWrs; break;
1149 case AArch64::ADDSXrr: Opcode = AArch64::ADDSXrs; break;
1150 case AArch64::SUBSXrr: Opcode = AArch64::SUBSXrs; break;
1151 case AArch64::ANDWrr: Opcode = AArch64::ANDWrs; break;
1152 case AArch64::ANDXrr: Opcode = AArch64::ANDXrs; break;
1153 case AArch64::BICWrr: Opcode = AArch64::BICWrs; break;
1154 case AArch64::BICXrr: Opcode = AArch64::BICXrs; break;
1155 case AArch64::ANDSWrr: Opcode = AArch64::ANDSWrs; break;
1156 case AArch64::ANDSXrr: Opcode = AArch64::ANDSXrs; break;
1157 case AArch64::BICSWrr: Opcode = AArch64::BICSWrs; break;
1158 case AArch64::BICSXrr: Opcode = AArch64::BICSXrs; break;
1159 case AArch64::EONWrr: Opcode = AArch64::EONWrs; break;
1160 case AArch64::EONXrr: Opcode = AArch64::EONXrs; break;
1161 case AArch64::EORWrr: Opcode = AArch64::EORWrs; break;
1162 case AArch64::EORXrr: Opcode = AArch64::EORXrs; break;
1163 case AArch64::ORNWrr: Opcode = AArch64::ORNWrs; break;
1164 case AArch64::ORNXrr: Opcode = AArch64::ORNXrs; break;
1165 case AArch64::ORRWrr: Opcode = AArch64::ORRWrs; break;
1166 case AArch64::ORRXrr: Opcode = AArch64::ORRXrs; break;
1167 }
1168 MachineFunction &MF = *MBB.getParent();
1169 // Try to create new inst without implicit operands added.
1170 MachineInstr *NewMI = MF.CreateMachineInstr(
1171 TII->get(Opcode), MI.getDebugLoc(), /*NoImplicit=*/true);
1172 MBB.insert(MBBI, NewMI);
1173 MachineInstrBuilder MIB1(MF, NewMI);
1174 MIB1->setPCSections(MF, MI.getPCSections());
1175 MIB1.addReg(MI.getOperand(0).getReg(), RegState::Define)
1176 .add(MI.getOperand(1))
1177 .add(MI.getOperand(2))
1179 transferImpOps(MI, MIB1, MIB1);
1180 if (auto DebugNumber = MI.peekDebugInstrNum())
1181 NewMI->setDebugInstrNum(DebugNumber);
1182 MI.eraseFromParent();
1183 return true;
1184 }
1185
1186 case AArch64::LOADgot: {
1188 Register DstReg = MI.getOperand(0).getReg();
1189 const MachineOperand &MO1 = MI.getOperand(1);
1190 unsigned Flags = MO1.getTargetFlags();
1191
1192 if (MF->getTarget().getCodeModel() == CodeModel::Tiny) {
1193 // Tiny codemodel expand to LDR
1194 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1195 TII->get(AArch64::LDRXl), DstReg);
1196
1197 if (MO1.isGlobal()) {
1198 MIB.addGlobalAddress(MO1.getGlobal(), 0, Flags);
1199 } else if (MO1.isSymbol()) {
1200 MIB.addExternalSymbol(MO1.getSymbolName(), Flags);
1201 } else {
1202 assert(MO1.isCPI() &&
1203 "Only expect globals, externalsymbols, or constant pools");
1204 MIB.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(), Flags);
1205 }
1206 } else {
1207 // Small codemodel expand into ADRP + LDR.
1208 MachineFunction &MF = *MI.getParent()->getParent();
1209 DebugLoc DL = MI.getDebugLoc();
1210 MachineInstrBuilder MIB1 =
1211 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg);
1212
1216 unsigned Reg32 = TRI->getSubReg(DstReg, AArch64::sub_32);
1217 unsigned DstFlags = MI.getOperand(0).getTargetFlags();
1218 MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::LDRWui))
1219 .addDef(Reg32)
1220 .addReg(DstReg, RegState::Kill)
1221 .addReg(DstReg, DstFlags | RegState::Implicit);
1222 } else {
1223 Register DstReg = MI.getOperand(0).getReg();
1224 MIB2 = BuildMI(MBB, MBBI, DL, TII->get(AArch64::LDRXui))
1225 .add(MI.getOperand(0))
1226 .addUse(DstReg, RegState::Kill);
1227 }
1228
1229 if (MO1.isGlobal()) {
1230 MIB1.addGlobalAddress(MO1.getGlobal(), 0, Flags | AArch64II::MO_PAGE);
1231 MIB2.addGlobalAddress(MO1.getGlobal(), 0,
1233 } else if (MO1.isSymbol()) {
1235 MIB2.addExternalSymbol(MO1.getSymbolName(), Flags |
1238 } else {
1239 assert(MO1.isCPI() &&
1240 "Only expect globals, externalsymbols, or constant pools");
1241 MIB1.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(),
1242 Flags | AArch64II::MO_PAGE);
1243 MIB2.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(),
1244 Flags | AArch64II::MO_PAGEOFF |
1246 }
1247
1248 transferImpOps(MI, MIB1, MIB2);
1249 }
1250 MI.eraseFromParent();
1251 return true;
1252 }
1253 case AArch64::MOVaddrBA: {
1254 MachineFunction &MF = *MI.getParent()->getParent();
1256 // blockaddress expressions have to come from a constant pool because the
1257 // largest addend (and hence offset within a function) allowed for ADRP is
1258 // only 8MB.
1259 const BlockAddress *BA = MI.getOperand(1).getBlockAddress();
1260 assert(MI.getOperand(1).getOffset() == 0 && "unexpected offset");
1261
1263 unsigned CPIdx = MCP->getConstantPoolIndex(BA, Align(8));
1264
1265 Register DstReg = MI.getOperand(0).getReg();
1266 auto MIB1 =
1267 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
1269 auto MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1270 TII->get(AArch64::LDRXui), DstReg)
1271 .addUse(DstReg)
1274 transferImpOps(MI, MIB1, MIB2);
1275 MI.eraseFromParent();
1276 return true;
1277 }
1278 }
1279 [[fallthrough]];
1280 case AArch64::MOVaddr:
1281 case AArch64::MOVaddrJT:
1282 case AArch64::MOVaddrCP:
1283 case AArch64::MOVaddrTLS:
1284 case AArch64::MOVaddrEXT: {
1285 // Expand into ADRP + ADD.
1286 Register DstReg = MI.getOperand(0).getReg();
1287 assert(DstReg != AArch64::XZR);
1288 MachineInstrBuilder MIB1 =
1289 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
1290 .add(MI.getOperand(1));
1291
1292 if (MI.getOperand(1).getTargetFlags() & AArch64II::MO_TAGGED) {
1293 // MO_TAGGED on the page indicates a tagged address. Set the tag now.
1294 // We do so by creating a MOVK that sets bits 48-63 of the register to
1295 // (global address + 0x100000000 - PC) >> 48. This assumes that we're in
1296 // the small code model so we can assume a binary size of <= 4GB, which
1297 // makes the untagged PC relative offset positive. The binary must also be
1298 // loaded into address range [0, 2^48). Both of these properties need to
1299 // be ensured at runtime when using tagged addresses.
1300 auto Tag = MI.getOperand(1);
1301 Tag.setTargetFlags(AArch64II::MO_PREL | AArch64II::MO_G3);
1302 Tag.setOffset(0x100000000);
1303 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi), DstReg)
1304 .addReg(DstReg)
1305 .add(Tag)
1306 .addImm(48);
1307 }
1308
1309 MachineInstrBuilder MIB2 =
1310 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
1311 .add(MI.getOperand(0))
1312 .addReg(DstReg)
1313 .add(MI.getOperand(2))
1314 .addImm(0);
1315
1316 transferImpOps(MI, MIB1, MIB2);
1317 MI.eraseFromParent();
1318 return true;
1319 }
1320 case AArch64::ADDlowTLS:
1321 // Produce a plain ADD
1322 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
1323 .add(MI.getOperand(0))
1324 .add(MI.getOperand(1))
1325 .add(MI.getOperand(2))
1326 .addImm(0);
1327 MI.eraseFromParent();
1328 return true;
1329
1330 case AArch64::MOVbaseTLS: {
1331 Register DstReg = MI.getOperand(0).getReg();
1332 auto SysReg = AArch64SysReg::TPIDR_EL0;
1334 if (MF->getSubtarget<AArch64Subtarget>().useEL3ForTP())
1335 SysReg = AArch64SysReg::TPIDR_EL3;
1336 else if (MF->getSubtarget<AArch64Subtarget>().useEL2ForTP())
1337 SysReg = AArch64SysReg::TPIDR_EL2;
1338 else if (MF->getSubtarget<AArch64Subtarget>().useEL1ForTP())
1339 SysReg = AArch64SysReg::TPIDR_EL1;
1340 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
1341 .addImm(SysReg);
1342 MI.eraseFromParent();
1343 return true;
1344 }
1345
1346 case AArch64::MOVi32imm:
1347 return expandMOVImm(MBB, MBBI, 32);
1348 case AArch64::MOVi64imm:
1349 return expandMOVImm(MBB, MBBI, 64);
1350 case AArch64::RET_ReallyLR: {
1351 // Hiding the LR use with RET_ReallyLR may lead to extra kills in the
1352 // function and missing live-ins. We are fine in practice because callee
1353 // saved register handling ensures the register value is restored before
1354 // RET, but we need the undef flag here to appease the MachineVerifier
1355 // liveness checks.
1357 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::RET))
1358 .addReg(AArch64::LR, RegState::Undef);
1359 transferImpOps(MI, MIB, MIB);
1360 MI.eraseFromParent();
1361 return true;
1362 }
1363 case AArch64::CMP_SWAP_8:
1364 return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRB, AArch64::STLXRB,
1365 AArch64::SUBSWrx,
1367 AArch64::WZR, NextMBBI);
1368 case AArch64::CMP_SWAP_16:
1369 return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRH, AArch64::STLXRH,
1370 AArch64::SUBSWrx,
1372 AArch64::WZR, NextMBBI);
1373 case AArch64::CMP_SWAP_32:
1374 return expandCMP_SWAP(MBB, MBBI, AArch64::LDAXRW, AArch64::STLXRW,
1375 AArch64::SUBSWrs,
1377 AArch64::WZR, NextMBBI);
1378 case AArch64::CMP_SWAP_64:
1379 return expandCMP_SWAP(MBB, MBBI,
1380 AArch64::LDAXRX, AArch64::STLXRX, AArch64::SUBSXrs,
1382 AArch64::XZR, NextMBBI);
1383 case AArch64::CMP_SWAP_128:
1384 case AArch64::CMP_SWAP_128_RELEASE:
1385 case AArch64::CMP_SWAP_128_ACQUIRE:
1386 case AArch64::CMP_SWAP_128_MONOTONIC:
1387 return expandCMP_SWAP_128(MBB, MBBI, NextMBBI);
1388
1389 case AArch64::AESMCrrTied:
1390 case AArch64::AESIMCrrTied: {
1392 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1393 TII->get(Opcode == AArch64::AESMCrrTied ? AArch64::AESMCrr :
1394 AArch64::AESIMCrr))
1395 .add(MI.getOperand(0))
1396 .add(MI.getOperand(1));
1397 transferImpOps(MI, MIB, MIB);
1398 MI.eraseFromParent();
1399 return true;
1400 }
1401 case AArch64::IRGstack: {
1402 MachineFunction &MF = *MBB.getParent();
1404 const AArch64FrameLowering *TFI =
1405 MF.getSubtarget<AArch64Subtarget>().getFrameLowering();
1406
1407 // IRG does not allow immediate offset. getTaggedBasePointerOffset should
1408 // almost always point to SP-after-prologue; if not, emit a longer
1409 // instruction sequence.
1410 int BaseOffset = -AFI->getTaggedBasePointerOffset();
1411 Register FrameReg;
1412 StackOffset FrameRegOffset = TFI->resolveFrameOffsetReference(
1413 MF, BaseOffset, false /*isFixed*/, false /*isSVE*/, FrameReg,
1414 /*PreferFP=*/false,
1415 /*ForSimm=*/true);
1416 Register SrcReg = FrameReg;
1417 if (FrameRegOffset) {
1418 // Use output register as temporary.
1419 SrcReg = MI.getOperand(0).getReg();
1420 emitFrameOffset(MBB, &MI, MI.getDebugLoc(), SrcReg, FrameReg,
1421 FrameRegOffset, TII);
1422 }
1423 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::IRG))
1424 .add(MI.getOperand(0))
1425 .addUse(SrcReg)
1426 .add(MI.getOperand(2));
1427 MI.eraseFromParent();
1428 return true;
1429 }
1430 case AArch64::TAGPstack: {
1431 int64_t Offset = MI.getOperand(2).getImm();
1432 BuildMI(MBB, MBBI, MI.getDebugLoc(),
1433 TII->get(Offset >= 0 ? AArch64::ADDG : AArch64::SUBG))
1434 .add(MI.getOperand(0))
1435 .add(MI.getOperand(1))
1436 .addImm(std::abs(Offset))
1437 .add(MI.getOperand(4));
1438 MI.eraseFromParent();
1439 return true;
1440 }
1441 case AArch64::STGloop_wback:
1442 case AArch64::STZGloop_wback:
1443 return expandSetTagLoop(MBB, MBBI, NextMBBI);
1444 case AArch64::STGloop:
1445 case AArch64::STZGloop:
1447 "Non-writeback variants of STGloop / STZGloop should not "
1448 "survive past PrologEpilogInserter.");
1449 case AArch64::STR_ZZZZXI:
1450 return expandSVESpillFill(MBB, MBBI, AArch64::STR_ZXI, 4);
1451 case AArch64::STR_ZZZXI:
1452 return expandSVESpillFill(MBB, MBBI, AArch64::STR_ZXI, 3);
1453 case AArch64::STR_ZZXI:
1454 return expandSVESpillFill(MBB, MBBI, AArch64::STR_ZXI, 2);
1455 case AArch64::LDR_ZZZZXI:
1456 return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 4);
1457 case AArch64::LDR_ZZZXI:
1458 return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 3);
1459 case AArch64::LDR_ZZXI:
1460 return expandSVESpillFill(MBB, MBBI, AArch64::LDR_ZXI, 2);
1461 case AArch64::BLR_RVMARKER:
1462 return expandCALL_RVMARKER(MBB, MBBI);
1463 case AArch64::BLR_BTI:
1464 return expandCALL_BTI(MBB, MBBI);
1465 case AArch64::StoreSwiftAsyncContext:
1466 return expandStoreSwiftAsyncContext(MBB, MBBI);
1467 case AArch64::RestoreZAPseudo: {
1468 auto *NewMBB = expandRestoreZA(MBB, MBBI);
1469 if (NewMBB != &MBB)
1470 NextMBBI = MBB.end(); // The NextMBBI iterator is invalidated.
1471 return true;
1472 }
1473 case AArch64::MSRpstatePseudo: {
1474 auto *NewMBB = expandCondSMToggle(MBB, MBBI);
1475 if (NewMBB != &MBB)
1476 NextMBBI = MBB.end(); // The NextMBBI iterator is invalidated.
1477 return true;
1478 }
1479 case AArch64::OBSCURE_COPY: {
1480 if (MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) {
1481 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXrs))
1482 .add(MI.getOperand(0))
1483 .addReg(AArch64::XZR)
1484 .add(MI.getOperand(1))
1485 .addImm(0);
1486 }
1487 MI.eraseFromParent();
1488 return true;
1489 }
1490 }
1491 return false;
1492}
1493
1494/// Iterate over the instructions in basic block MBB and expand any
1495/// pseudo instructions. Return true if anything was modified.
1496bool AArch64ExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
1497 bool Modified = false;
1498
1500 while (MBBI != E) {
1501 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
1502 Modified |= expandMI(MBB, MBBI, NMBBI);
1503 MBBI = NMBBI;
1504 }
1505
1506 return Modified;
1507}
1508
1509bool AArch64ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1510 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
1511
1512 bool Modified = false;
1513 for (auto &MBB : MF)
1514 Modified |= expandMBB(MBB);
1515 return Modified;
1516}
1517
1518/// Returns an instance of the pseudo instruction expansion pass.
1520 return new AArch64ExpandPseudo();
1521}
#define AARCH64_EXPAND_PSEUDO_NAME
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file defines the DenseMap class.
uint64_t Size
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
@ Flags
Definition: TextStubV5.cpp:93
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
The address of a basic block.
Definition: Constants.h:879
A debug info location.
Definition: DebugLoc.h:33
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
Set of metadata that should be preserved when using BuildMI().
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
MachineBasicBlock * splitAt(MachineInstr &SplitInst, bool UpdateLiveIns=true, LiveIntervals *LIS=nullptr)
Split a basic block into 2 pieces at SplitPoint.
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< succ_iterator > successors()
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
void moveCallSiteInfo(const MachineInstr *Old, const MachineInstr *New)
Move the call site info from Old to \New call site info.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
void setDebugInstrNum(unsigned Num)
Set instruction number of this MachineInstr.
Definition: MachineInstr.h:496
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
int64_t getOffset() const
Return the offset from the symbol in this operand.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:36
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
CodeModel::Model getCodeModel() const
Returns the code model.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
self_iterator getIterator()
Definition: ilist_node.h:82
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
@ MO_PREL
MO_PREL - Indicates that the bits of the symbol operand represented by MO_G0 etc are PC relative.
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_G3
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address,...
static unsigned getArithExtendImm(AArch64_AM::ShiftExtendType ET, unsigned Imm)
getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit...
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void expandMOVImm(uint64_t Imm, unsigned BitSize, SmallVectorImpl< ImmInsnModel > &Insn)
Expand a MOVi32imm or MOVi64imm pseudo instruction to one or more real move-immediate instructions to...
int getSVERevInstr(uint16_t Opcode)
int getSVEPseudoMap(uint16_t Opcode)
int getSVENonRevInstr(uint16_t Opcode)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Renamable
Register that may be renamed.
@ Define
Register definition.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:413
@ Offset
Definition: DWP.cpp:406
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1335
unsigned getDeadRegState(bool B)
void initializeAArch64ExpandPseudoPass(PassRegistry &)
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, StackOffset Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false, bool NeedsWinCFI=false, bool *HasWinCFI=nullptr, bool EmitCFAOffset=false, StackOffset InitialOffset={}, unsigned FrameReg=AArch64::SP)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
unsigned getKillRegState(bool B)
unsigned getRenamableRegState(bool B)
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39