LLVM 19.0.0git
AArch64BaseInfo.h
Go to the documentation of this file.
1//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone helper functions and enum definitions for
10// the AArch64 target useful for the compiler back-end and the MC libraries.
11// As such, it deliberately does not include references to LLVM core
12// code gen types, passes, etc..
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
17#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18
19// FIXME: Is it easiest to fix this layering violation by moving the .inc
20// #includes from AArch64MCTargetDesc.h to here?
21#include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
23#include "llvm/ADT/STLExtras.h"
27
28namespace llvm {
29
30inline static unsigned getWRegFromXReg(unsigned Reg) {
31 switch (Reg) {
32 case AArch64::X0: return AArch64::W0;
33 case AArch64::X1: return AArch64::W1;
34 case AArch64::X2: return AArch64::W2;
35 case AArch64::X3: return AArch64::W3;
36 case AArch64::X4: return AArch64::W4;
37 case AArch64::X5: return AArch64::W5;
38 case AArch64::X6: return AArch64::W6;
39 case AArch64::X7: return AArch64::W7;
40 case AArch64::X8: return AArch64::W8;
41 case AArch64::X9: return AArch64::W9;
42 case AArch64::X10: return AArch64::W10;
43 case AArch64::X11: return AArch64::W11;
44 case AArch64::X12: return AArch64::W12;
45 case AArch64::X13: return AArch64::W13;
46 case AArch64::X14: return AArch64::W14;
47 case AArch64::X15: return AArch64::W15;
48 case AArch64::X16: return AArch64::W16;
49 case AArch64::X17: return AArch64::W17;
50 case AArch64::X18: return AArch64::W18;
51 case AArch64::X19: return AArch64::W19;
52 case AArch64::X20: return AArch64::W20;
53 case AArch64::X21: return AArch64::W21;
54 case AArch64::X22: return AArch64::W22;
55 case AArch64::X23: return AArch64::W23;
56 case AArch64::X24: return AArch64::W24;
57 case AArch64::X25: return AArch64::W25;
58 case AArch64::X26: return AArch64::W26;
59 case AArch64::X27: return AArch64::W27;
60 case AArch64::X28: return AArch64::W28;
61 case AArch64::FP: return AArch64::W29;
62 case AArch64::LR: return AArch64::W30;
63 case AArch64::SP: return AArch64::WSP;
64 case AArch64::XZR: return AArch64::WZR;
65 }
66 // For anything else, return it unchanged.
67 return Reg;
68}
69
70inline static unsigned getXRegFromWReg(unsigned Reg) {
71 switch (Reg) {
72 case AArch64::W0: return AArch64::X0;
73 case AArch64::W1: return AArch64::X1;
74 case AArch64::W2: return AArch64::X2;
75 case AArch64::W3: return AArch64::X3;
76 case AArch64::W4: return AArch64::X4;
77 case AArch64::W5: return AArch64::X5;
78 case AArch64::W6: return AArch64::X6;
79 case AArch64::W7: return AArch64::X7;
80 case AArch64::W8: return AArch64::X8;
81 case AArch64::W9: return AArch64::X9;
82 case AArch64::W10: return AArch64::X10;
83 case AArch64::W11: return AArch64::X11;
84 case AArch64::W12: return AArch64::X12;
85 case AArch64::W13: return AArch64::X13;
86 case AArch64::W14: return AArch64::X14;
87 case AArch64::W15: return AArch64::X15;
88 case AArch64::W16: return AArch64::X16;
89 case AArch64::W17: return AArch64::X17;
90 case AArch64::W18: return AArch64::X18;
91 case AArch64::W19: return AArch64::X19;
92 case AArch64::W20: return AArch64::X20;
93 case AArch64::W21: return AArch64::X21;
94 case AArch64::W22: return AArch64::X22;
95 case AArch64::W23: return AArch64::X23;
96 case AArch64::W24: return AArch64::X24;
97 case AArch64::W25: return AArch64::X25;
98 case AArch64::W26: return AArch64::X26;
99 case AArch64::W27: return AArch64::X27;
100 case AArch64::W28: return AArch64::X28;
101 case AArch64::W29: return AArch64::FP;
102 case AArch64::W30: return AArch64::LR;
103 case AArch64::WSP: return AArch64::SP;
104 case AArch64::WZR: return AArch64::XZR;
105 }
106 // For anything else, return it unchanged.
107 return Reg;
108}
109
110inline static unsigned getXRegFromXRegTuple(unsigned RegTuple) {
111 switch (RegTuple) {
112 case AArch64::X0_X1_X2_X3_X4_X5_X6_X7: return AArch64::X0;
113 case AArch64::X2_X3_X4_X5_X6_X7_X8_X9: return AArch64::X2;
114 case AArch64::X4_X5_X6_X7_X8_X9_X10_X11: return AArch64::X4;
115 case AArch64::X6_X7_X8_X9_X10_X11_X12_X13: return AArch64::X6;
116 case AArch64::X8_X9_X10_X11_X12_X13_X14_X15: return AArch64::X8;
117 case AArch64::X10_X11_X12_X13_X14_X15_X16_X17: return AArch64::X10;
118 case AArch64::X12_X13_X14_X15_X16_X17_X18_X19: return AArch64::X12;
119 case AArch64::X14_X15_X16_X17_X18_X19_X20_X21: return AArch64::X14;
120 case AArch64::X16_X17_X18_X19_X20_X21_X22_X23: return AArch64::X16;
121 case AArch64::X18_X19_X20_X21_X22_X23_X24_X25: return AArch64::X18;
122 case AArch64::X20_X21_X22_X23_X24_X25_X26_X27: return AArch64::X20;
123 case AArch64::X22_X23_X24_X25_X26_X27_X28_FP: return AArch64::X22;
124 }
125 // For anything else, return it unchanged.
126 return RegTuple;
127}
128
129static inline unsigned getBRegFromDReg(unsigned Reg) {
130 switch (Reg) {
131 case AArch64::D0: return AArch64::B0;
132 case AArch64::D1: return AArch64::B1;
133 case AArch64::D2: return AArch64::B2;
134 case AArch64::D3: return AArch64::B3;
135 case AArch64::D4: return AArch64::B4;
136 case AArch64::D5: return AArch64::B5;
137 case AArch64::D6: return AArch64::B6;
138 case AArch64::D7: return AArch64::B7;
139 case AArch64::D8: return AArch64::B8;
140 case AArch64::D9: return AArch64::B9;
141 case AArch64::D10: return AArch64::B10;
142 case AArch64::D11: return AArch64::B11;
143 case AArch64::D12: return AArch64::B12;
144 case AArch64::D13: return AArch64::B13;
145 case AArch64::D14: return AArch64::B14;
146 case AArch64::D15: return AArch64::B15;
147 case AArch64::D16: return AArch64::B16;
148 case AArch64::D17: return AArch64::B17;
149 case AArch64::D18: return AArch64::B18;
150 case AArch64::D19: return AArch64::B19;
151 case AArch64::D20: return AArch64::B20;
152 case AArch64::D21: return AArch64::B21;
153 case AArch64::D22: return AArch64::B22;
154 case AArch64::D23: return AArch64::B23;
155 case AArch64::D24: return AArch64::B24;
156 case AArch64::D25: return AArch64::B25;
157 case AArch64::D26: return AArch64::B26;
158 case AArch64::D27: return AArch64::B27;
159 case AArch64::D28: return AArch64::B28;
160 case AArch64::D29: return AArch64::B29;
161 case AArch64::D30: return AArch64::B30;
162 case AArch64::D31: return AArch64::B31;
163 }
164 // For anything else, return it unchanged.
165 return Reg;
166}
167
168
169static inline unsigned getDRegFromBReg(unsigned Reg) {
170 switch (Reg) {
171 case AArch64::B0: return AArch64::D0;
172 case AArch64::B1: return AArch64::D1;
173 case AArch64::B2: return AArch64::D2;
174 case AArch64::B3: return AArch64::D3;
175 case AArch64::B4: return AArch64::D4;
176 case AArch64::B5: return AArch64::D5;
177 case AArch64::B6: return AArch64::D6;
178 case AArch64::B7: return AArch64::D7;
179 case AArch64::B8: return AArch64::D8;
180 case AArch64::B9: return AArch64::D9;
181 case AArch64::B10: return AArch64::D10;
182 case AArch64::B11: return AArch64::D11;
183 case AArch64::B12: return AArch64::D12;
184 case AArch64::B13: return AArch64::D13;
185 case AArch64::B14: return AArch64::D14;
186 case AArch64::B15: return AArch64::D15;
187 case AArch64::B16: return AArch64::D16;
188 case AArch64::B17: return AArch64::D17;
189 case AArch64::B18: return AArch64::D18;
190 case AArch64::B19: return AArch64::D19;
191 case AArch64::B20: return AArch64::D20;
192 case AArch64::B21: return AArch64::D21;
193 case AArch64::B22: return AArch64::D22;
194 case AArch64::B23: return AArch64::D23;
195 case AArch64::B24: return AArch64::D24;
196 case AArch64::B25: return AArch64::D25;
197 case AArch64::B26: return AArch64::D26;
198 case AArch64::B27: return AArch64::D27;
199 case AArch64::B28: return AArch64::D28;
200 case AArch64::B29: return AArch64::D29;
201 case AArch64::B30: return AArch64::D30;
202 case AArch64::B31: return AArch64::D31;
203 }
204 // For anything else, return it unchanged.
205 return Reg;
206}
207
208static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) {
209 switch (Opcode) {
210 case AArch64::LDADDAB: case AArch64::LDADDAH:
211 case AArch64::LDADDAW: case AArch64::LDADDAX:
212 case AArch64::LDADDALB: case AArch64::LDADDALH:
213 case AArch64::LDADDALW: case AArch64::LDADDALX:
214 case AArch64::LDCLRAB: case AArch64::LDCLRAH:
215 case AArch64::LDCLRAW: case AArch64::LDCLRAX:
216 case AArch64::LDCLRALB: case AArch64::LDCLRALH:
217 case AArch64::LDCLRALW: case AArch64::LDCLRALX:
218 case AArch64::LDEORAB: case AArch64::LDEORAH:
219 case AArch64::LDEORAW: case AArch64::LDEORAX:
220 case AArch64::LDEORALB: case AArch64::LDEORALH:
221 case AArch64::LDEORALW: case AArch64::LDEORALX:
222 case AArch64::LDSETAB: case AArch64::LDSETAH:
223 case AArch64::LDSETAW: case AArch64::LDSETAX:
224 case AArch64::LDSETALB: case AArch64::LDSETALH:
225 case AArch64::LDSETALW: case AArch64::LDSETALX:
226 case AArch64::LDSMAXAB: case AArch64::LDSMAXAH:
227 case AArch64::LDSMAXAW: case AArch64::LDSMAXAX:
228 case AArch64::LDSMAXALB: case AArch64::LDSMAXALH:
229 case AArch64::LDSMAXALW: case AArch64::LDSMAXALX:
230 case AArch64::LDSMINAB: case AArch64::LDSMINAH:
231 case AArch64::LDSMINAW: case AArch64::LDSMINAX:
232 case AArch64::LDSMINALB: case AArch64::LDSMINALH:
233 case AArch64::LDSMINALW: case AArch64::LDSMINALX:
234 case AArch64::LDUMAXAB: case AArch64::LDUMAXAH:
235 case AArch64::LDUMAXAW: case AArch64::LDUMAXAX:
236 case AArch64::LDUMAXALB: case AArch64::LDUMAXALH:
237 case AArch64::LDUMAXALW: case AArch64::LDUMAXALX:
238 case AArch64::LDUMINAB: case AArch64::LDUMINAH:
239 case AArch64::LDUMINAW: case AArch64::LDUMINAX:
240 case AArch64::LDUMINALB: case AArch64::LDUMINALH:
241 case AArch64::LDUMINALW: case AArch64::LDUMINALX:
242 case AArch64::SWPAB: case AArch64::SWPAH:
243 case AArch64::SWPAW: case AArch64::SWPAX:
244 case AArch64::SWPALB: case AArch64::SWPALH:
245 case AArch64::SWPALW: case AArch64::SWPALX:
246 return true;
247 }
248 return false;
249}
250
251namespace AArch64CC {
252
253// The CondCodes constants map directly to the 4-bit encoding of the condition
254// field for predicated instructions.
255enum CondCode { // Meaning (integer) Meaning (floating-point)
256 EQ = 0x0, // Equal Equal
257 NE = 0x1, // Not equal Not equal, or unordered
258 HS = 0x2, // Unsigned higher or same >, ==, or unordered
259 LO = 0x3, // Unsigned lower Less than
260 MI = 0x4, // Minus, negative Less than
261 PL = 0x5, // Plus, positive or zero >, ==, or unordered
262 VS = 0x6, // Overflow Unordered
263 VC = 0x7, // No overflow Not unordered
264 HI = 0x8, // Unsigned higher Greater than, or unordered
265 LS = 0x9, // Unsigned lower or same Less than or equal
266 GE = 0xa, // Greater than or equal Greater than or equal
267 LT = 0xb, // Less than Less than, or unordered
268 GT = 0xc, // Greater than Greater than
269 LE = 0xd, // Less than or equal <, ==, or unordered
270 AL = 0xe, // Always (unconditional) Always (unconditional)
271 NV = 0xf, // Always (unconditional) Always (unconditional)
272 // Note the NV exists purely to disassemble 0b1111. Execution is "always".
274
275 // Common aliases used for SVE.
276 ANY_ACTIVE = NE, // (!Z)
277 FIRST_ACTIVE = MI, // ( N)
278 LAST_ACTIVE = LO, // (!C)
279 NONE_ACTIVE = EQ // ( Z)
281
282inline static const char *getCondCodeName(CondCode Code) {
283 switch (Code) {
284 default: llvm_unreachable("Unknown condition code");
285 case EQ: return "eq";
286 case NE: return "ne";
287 case HS: return "hs";
288 case LO: return "lo";
289 case MI: return "mi";
290 case PL: return "pl";
291 case VS: return "vs";
292 case VC: return "vc";
293 case HI: return "hi";
294 case LS: return "ls";
295 case GE: return "ge";
296 case LT: return "lt";
297 case GT: return "gt";
298 case LE: return "le";
299 case AL: return "al";
300 case NV: return "nv";
301 }
302}
303
305 // To reverse a condition it's necessary to only invert the low bit:
306
307 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
308}
309
310/// Given a condition code, return NZCV flags that would satisfy that condition.
311/// The flag bits are in the format expected by the ccmp instructions.
312/// Note that many different flag settings can satisfy a given condition code,
313/// this function just returns one of them.
314inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
315 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
316 enum { N = 8, Z = 4, C = 2, V = 1 };
317 switch (Code) {
318 default: llvm_unreachable("Unknown condition code");
319 case EQ: return Z; // Z == 1
320 case NE: return 0; // Z == 0
321 case HS: return C; // C == 1
322 case LO: return 0; // C == 0
323 case MI: return N; // N == 1
324 case PL: return 0; // N == 0
325 case VS: return V; // V == 1
326 case VC: return 0; // V == 0
327 case HI: return C; // C == 1 && Z == 0
328 case LS: return 0; // C == 0 || Z == 1
329 case GE: return 0; // N == V
330 case LT: return N; // N != V
331 case GT: return 0; // Z == 0 && N == V
332 case LE: return Z; // Z == 1 || N != V
333 }
334}
335
336} // end namespace AArch64CC
337
338struct SysAlias {
339 const char *Name;
342
343 constexpr SysAlias(const char *N, uint16_t E) : Name(N), Encoding(E) {}
344 constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
346
347 bool haveFeatures(FeatureBitset ActiveFeatures) const {
348 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
349 (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
350 }
351
353};
354
357 constexpr SysAliasReg(const char *N, uint16_t E, bool R)
358 : SysAlias(N, E), NeedsReg(R) {}
359 constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
360 : SysAlias(N, E, F), NeedsReg(R) {}
361};
362
365 constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
366 : SysAlias(N, E), ImmValue(I) {}
367 constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
368 : SysAlias(N, E, F), ImmValue(I) {}
369};
370
371namespace AArch64SVCR {
372 struct SVCR : SysAlias{
373 using SysAlias::SysAlias;
374 };
375 #define GET_SVCR_DECL
376 #include "AArch64GenSystemOperands.inc"
377}
378
379namespace AArch64AT{
380 struct AT : SysAlias {
381 using SysAlias::SysAlias;
382 };
383 #define GET_AT_DECL
384 #include "AArch64GenSystemOperands.inc"
385}
386
387namespace AArch64DB {
388 struct DB : SysAlias {
389 using SysAlias::SysAlias;
390 };
391 #define GET_DB_DECL
392 #include "AArch64GenSystemOperands.inc"
393}
394
395namespace AArch64DBnXS {
398 };
399 #define GET_DBNXS_DECL
400 #include "AArch64GenSystemOperands.inc"
401}
402
403namespace AArch64DC {
404 struct DC : SysAlias {
405 using SysAlias::SysAlias;
406 };
407 #define GET_DC_DECL
408 #include "AArch64GenSystemOperands.inc"
409}
410
411namespace AArch64IC {
412 struct IC : SysAliasReg {
414 };
415 #define GET_IC_DECL
416 #include "AArch64GenSystemOperands.inc"
417}
418
419namespace AArch64ISB {
420 struct ISB : SysAlias {
421 using SysAlias::SysAlias;
422 };
423 #define GET_ISB_DECL
424 #include "AArch64GenSystemOperands.inc"
425}
426
427namespace AArch64TSB {
428 struct TSB : SysAlias {
429 using SysAlias::SysAlias;
430 };
431 #define GET_TSB_DECL
432 #include "AArch64GenSystemOperands.inc"
433}
434
435namespace AArch64PRFM {
436 struct PRFM : SysAlias {
437 using SysAlias::SysAlias;
438 };
439 #define GET_PRFM_DECL
440 #include "AArch64GenSystemOperands.inc"
441}
442
443namespace AArch64SVEPRFM {
444 struct SVEPRFM : SysAlias {
445 using SysAlias::SysAlias;
446 };
447#define GET_SVEPRFM_DECL
448#include "AArch64GenSystemOperands.inc"
449}
450
451namespace AArch64RPRFM {
452struct RPRFM : SysAlias {
453 using SysAlias::SysAlias;
454};
455#define GET_RPRFM_DECL
456#include "AArch64GenSystemOperands.inc"
457} // namespace AArch64RPRFM
458
459namespace AArch64SVEPredPattern {
460 struct SVEPREDPAT {
461 const char *Name;
463 };
464#define GET_SVEPREDPAT_DECL
465#include "AArch64GenSystemOperands.inc"
466}
467
468namespace AArch64SVEVecLenSpecifier {
470 const char *Name;
472 };
473#define GET_SVEVECLENSPECIFIER_DECL
474#include "AArch64GenSystemOperands.inc"
475} // namespace AArch64SVEVecLenSpecifier
476
477/// Return the number of active elements for VL1 to VL256 predicate pattern,
478/// zero for all other patterns.
479inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern) {
480 switch (Pattern) {
481 default:
482 return 0;
483 case AArch64SVEPredPattern::vl1:
484 case AArch64SVEPredPattern::vl2:
485 case AArch64SVEPredPattern::vl3:
486 case AArch64SVEPredPattern::vl4:
487 case AArch64SVEPredPattern::vl5:
488 case AArch64SVEPredPattern::vl6:
489 case AArch64SVEPredPattern::vl7:
490 case AArch64SVEPredPattern::vl8:
491 return Pattern;
492 case AArch64SVEPredPattern::vl16:
493 return 16;
494 case AArch64SVEPredPattern::vl32:
495 return 32;
496 case AArch64SVEPredPattern::vl64:
497 return 64;
498 case AArch64SVEPredPattern::vl128:
499 return 128;
500 case AArch64SVEPredPattern::vl256:
501 return 256;
502 }
503}
504
505/// Return specific VL predicate pattern based on the number of elements.
506inline std::optional<unsigned>
508 switch (MinNumElts) {
509 default:
510 return std::nullopt;
511 case 1:
512 case 2:
513 case 3:
514 case 4:
515 case 5:
516 case 6:
517 case 7:
518 case 8:
519 return MinNumElts;
520 case 16:
521 return AArch64SVEPredPattern::vl16;
522 case 32:
523 return AArch64SVEPredPattern::vl32;
524 case 64:
525 return AArch64SVEPredPattern::vl64;
526 case 128:
527 return AArch64SVEPredPattern::vl128;
528 case 256:
529 return AArch64SVEPredPattern::vl256;
530 }
531}
532
533/// An enum to describe what types of loops we should attempt to tail-fold:
534/// Disabled: None
535/// Reductions: Loops containing reductions
536/// Recurrences: Loops with first-order recurrences, i.e. that would
537/// require a SVE splice instruction
538/// Reverse: Reverse loops
539/// Simple: Loops that are not reversed and don't contain reductions
540/// or first-order recurrences.
541/// All: All
542enum class TailFoldingOpts : uint8_t {
543 Disabled = 0x00,
544 Simple = 0x01,
545 Reductions = 0x02,
546 Recurrences = 0x04,
547 Reverse = 0x08,
549};
550
552 /* LargestValue */ (long)TailFoldingOpts::Reverse);
553
554namespace AArch64ExactFPImm {
555 struct ExactFPImm {
556 const char *Name;
557 int Enum;
558 const char *Repr;
559 };
560#define GET_EXACTFPIMM_DECL
561#include "AArch64GenSystemOperands.inc"
562}
563
564namespace AArch64PState {
566 using SysAlias::SysAlias;
567 };
568 #define GET_PSTATEIMM0_15_DECL
569 #include "AArch64GenSystemOperands.inc"
570
572 using SysAlias::SysAlias;
573 };
574 #define GET_PSTATEIMM0_1_DECL
575 #include "AArch64GenSystemOperands.inc"
576}
577
578namespace AArch64PSBHint {
579 struct PSB : SysAlias {
580 using SysAlias::SysAlias;
581 };
582 #define GET_PSB_DECL
583 #include "AArch64GenSystemOperands.inc"
584}
585
586namespace AArch64BTIHint {
587 struct BTI : SysAlias {
588 using SysAlias::SysAlias;
589 };
590 #define GET_BTI_DECL
591 #include "AArch64GenSystemOperands.inc"
592}
593
594namespace AArch64SE {
602
607
611 SXTX
612 };
613}
614
615namespace AArch64Layout {
622
627
628 // Bare layout for the 128-bit vector
629 // (only show ".b", ".h", ".s", ".d" without vector number)
633 VL_D
634 };
635}
636
637inline static const char *
639 switch (Layout) {
640 case AArch64Layout::VL_8B: return ".8b";
641 case AArch64Layout::VL_4H: return ".4h";
642 case AArch64Layout::VL_2S: return ".2s";
643 case AArch64Layout::VL_1D: return ".1d";
644 case AArch64Layout::VL_16B: return ".16b";
645 case AArch64Layout::VL_8H: return ".8h";
646 case AArch64Layout::VL_4S: return ".4s";
647 case AArch64Layout::VL_2D: return ".2d";
648 case AArch64Layout::VL_B: return ".b";
649 case AArch64Layout::VL_H: return ".h";
650 case AArch64Layout::VL_S: return ".s";
651 case AArch64Layout::VL_D: return ".d";
652 default: llvm_unreachable("Unknown Vector Layout");
653 }
654}
655
656inline static AArch64Layout::VectorLayout
672}
673
674namespace AArch64SysReg {
675 struct SysReg {
676 const char *Name;
677 const char *AltName;
678 unsigned Encoding;
682
683 bool haveFeatures(FeatureBitset ActiveFeatures) const {
684 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
685 (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
686 }
687 };
688
689 #define GET_SYSREG_DECL
690 #include "AArch64GenSystemOperands.inc"
691
694
696 std::string genericRegisterString(uint32_t Bits);
697}
698
699namespace AArch64TLBI {
700 struct TLBI : SysAliasReg {
702 };
703 #define GET_TLBITable_DECL
704 #include "AArch64GenSystemOperands.inc"
705}
706
707namespace AArch64PRCTX {
710 };
711 #define GET_PRCTX_DECL
712 #include "AArch64GenSystemOperands.inc"
713}
714
715namespace AArch64II {
716/// Target Operand Flag enum.
717enum TOF {
718 //===------------------------------------------------------------------===//
719 // AArch64 Specific MachineOperand flags.
720
722
724
725 /// MO_PAGE - A symbol operand with this flag represents the pc-relative
726 /// offset of the 4K page containing the symbol. This is used with the
727 /// ADRP instruction.
729
730 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
731 /// that symbol within a 4K page. This offset is added to the page address
732 /// to produce the complete address.
734
735 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
736 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
737 MO_G3 = 3,
738
739 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
740 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
741 MO_G2 = 4,
742
743 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
744 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
745 MO_G1 = 5,
746
747 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
748 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
749 MO_G0 = 6,
750
751 /// MO_HI12 - This flag indicates that a symbol operand represents the bits
752 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
753 /// by-12-bits instruction.
755
756 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
757 /// reference is actually to the ".refptr.FOO" symbol. This is used for
758 /// stub symbols on windows.
760
761 /// MO_GOT - This flag indicates that a symbol operand represents the
762 /// address of the GOT entry for the symbol, rather than the address of
763 /// the symbol itself.
764 MO_GOT = 0x10,
765
766 /// MO_NC - Indicates whether the linker is expected to check the symbol
767 /// reference for overflow. For example in an ADRP/ADD pair of relocations
768 /// the ADRP usually does check, but not the ADD.
769 MO_NC = 0x20,
770
771 /// MO_TLS - Indicates that the operand being accessed is some kind of
772 /// thread-local symbol. On Darwin, only one type of thread-local access
773 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
774 /// referee will affect interpretation.
775 MO_TLS = 0x40,
776
777 /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
778 /// to the symbol is for an import stub. This is used for DLL import
779 /// storage class indication on Windows.
781
782 /// MO_S - Indicates that the bits of the symbol operand represented by
783 /// MO_G0 etc are signed.
784 MO_S = 0x100,
785
786 /// MO_PREL - Indicates that the bits of the symbol operand represented by
787 /// MO_G0 etc are PC relative.
788 MO_PREL = 0x200,
789
790 /// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag
791 /// in bits 56-63.
792 /// On a FrameIndex operand, indicates that the underlying memory is tagged
793 /// with an unknown tag value (MTE); this needs to be lowered either to an
794 /// SP-relative load or store instruction (which do not check tags), or to
795 /// an LDG instruction to obtain the tag value.
796 MO_TAGGED = 0x400,
797
798 /// MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version
799 /// of a symbol, not the original. For dllimport symbols, this means it
800 /// uses "__imp_aux". For other symbols, this means it uses the mangled
801 /// ("#" prefix for C) name.
803};
804} // end namespace AArch64II
805
806//===----------------------------------------------------------------------===//
807// v8.3a Pointer Authentication
808//
809
810namespace AArch64PACKey {
811enum ID : uint8_t {
812 IA = 0,
813 IB = 1,
814 DA = 2,
815 DB = 3,
816 LAST = DB
818} // namespace AArch64PACKey
819
820/// Return 2-letter identifier string for numeric key ID.
822 switch (KeyID) {
824 return StringRef("ia");
826 return StringRef("ib");
828 return StringRef("da");
830 return StringRef("db");
831 }
832 llvm_unreachable("Unhandled AArch64PACKey::ID enum");
833}
834
835/// Return numeric key ID for 2-letter identifier string.
836inline static std::optional<AArch64PACKey::ID>
838 if (Name == "ia")
839 return AArch64PACKey::IA;
840 if (Name == "ib")
841 return AArch64PACKey::IB;
842 if (Name == "da")
843 return AArch64PACKey::DA;
844 if (Name == "db")
845 return AArch64PACKey::DB;
846 return std::nullopt;
847}
848
849namespace AArch64 {
850// The number of bits in a SVE register is architecturally defined
851// to be a multiple of this value. If <M x t> has this number of bits,
852// a <n x M x t> vector can be stored in a SVE register without any
853// redundant bits. If <M x t> has this number of bits divided by P,
854// a <n x M x t> vector is stored in a SVE register by placing index i
855// in index i*P of a <n x (M*P) x t> vector. The other elements of the
856// <n x (M*P) x t> vector (such as index 1) are undefined.
857static constexpr unsigned SVEBitsPerBlock = 128;
858static constexpr unsigned SVEMaxBitsPerVector = 2048;
859} // end namespace AArch64
860} // end namespace llvm
861
862#endif
#define LLVM_DECLARE_ENUM_AS_BITMASK(Enum, LargestValue)
LLVM_DECLARE_ENUM_AS_BITMASK can be used to declare an enum type as a bit set, so that bitwise operat...
Definition: BitmaskEnum.h:66
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
std::string Name
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned Reg
This file contains some templates that are useful if you are working with the STL at all.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Container class for subtarget features.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const char * getCondCodeName(CondCode Code)
static CondCode getInvertedCondCode(CondCode Code)
static unsigned getNZCVToSatisfyCondCode(CondCode Code)
Given a condition code, return NZCV flags that would satisfy that condition.
TOF
Target Operand Flag enum.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_G1
MO_G1 - A symbol operand with this flag (granule 1) represents the bits 16-31 of a 64-bit address,...
@ MO_S
MO_S - Indicates that the bits of the symbol operand represented by MO_G0 etc are signed.
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_PREL
MO_PREL - Indicates that the bits of the symbol operand represented by MO_G0 etc are PC relative.
@ MO_G0
MO_G0 - A symbol operand with this flag (granule 0) represents the bits 0-15 of a 64-bit address,...
@ MO_ARM64EC_CALLMANGLE
MO_ARM64EC_CALLMANGLE - Operand refers to the Arm64EC-mangled version of a symbol,...
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
@ MO_HI12
MO_HI12 - This flag indicates that a symbol operand represents the bits 13-24 of a 64-bit address,...
@ MO_TLS
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
@ MO_G2
MO_G2 - A symbol operand with this flag (granule 2) represents the bits 32-47 of a 64-bit address,...
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_G3
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address,...
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
const SysReg * lookupSysRegByEncoding(uint16_t)
uint32_t parseGenericRegister(StringRef Name)
std::string genericRegisterString(uint32_t Bits)
const SysReg * lookupSysRegByName(StringRef)
static constexpr unsigned SVEMaxBitsPerVector
static constexpr unsigned SVEBitsPerBlock
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static std::optional< AArch64PACKey::ID > AArch64StringToPACKeyID(StringRef Name)
Return numeric key ID for 2-letter identifier string.
TailFoldingOpts
An enum to describe what types of loops we should attempt to tail-fold: Disabled: None Reductions: Lo...
static AArch64Layout::VectorLayout AArch64StringToVectorLayout(StringRef LayoutStr)
static const char * AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout)
std::optional< unsigned > getSVEPredPatternFromNumElements(unsigned MinNumElts)
Return specific VL predicate pattern based on the number of elements.
static unsigned getXRegFromWReg(unsigned Reg)
static unsigned getXRegFromXRegTuple(unsigned RegTuple)
static unsigned getDRegFromBReg(unsigned Reg)
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
static unsigned getWRegFromXReg(unsigned Reg)
unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
Return the number of active elements for VL1 to VL256 predicate pattern, zero for all other patterns.
static unsigned getBRegFromDReg(unsigned Reg)
static StringRef AArch64PACKeyIDToString(AArch64PACKey::ID KeyID)
Return 2-letter identifier string for numeric key ID.
#define N
bool haveFeatures(FeatureBitset ActiveFeatures) const
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
constexpr SysAliasReg(const char *N, uint16_t E, bool R)
bool haveFeatures(FeatureBitset ActiveFeatures) const
constexpr SysAlias(const char *N, uint16_t E)
FeatureBitset getRequiredFeatures() const
const char * Name
FeatureBitset FeaturesRequired
constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)