LLVM 17.0.0git
AArch64BaseInfo.h
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1//===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone helper functions and enum definitions for
10// the AArch64 target useful for the compiler back-end and the MC libraries.
11// As such, it deliberately does not include references to LLVM core
12// code gen types, passes, etc..
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
17#define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18
19// FIXME: Is it easiest to fix this layering violation by moving the .inc
20// #includes from AArch64MCTargetDesc.h to here?
21#include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
22#include "llvm/ADT/STLExtras.h"
26
27namespace llvm {
28
29inline static unsigned getWRegFromXReg(unsigned Reg) {
30 switch (Reg) {
31 case AArch64::X0: return AArch64::W0;
32 case AArch64::X1: return AArch64::W1;
33 case AArch64::X2: return AArch64::W2;
34 case AArch64::X3: return AArch64::W3;
35 case AArch64::X4: return AArch64::W4;
36 case AArch64::X5: return AArch64::W5;
37 case AArch64::X6: return AArch64::W6;
38 case AArch64::X7: return AArch64::W7;
39 case AArch64::X8: return AArch64::W8;
40 case AArch64::X9: return AArch64::W9;
41 case AArch64::X10: return AArch64::W10;
42 case AArch64::X11: return AArch64::W11;
43 case AArch64::X12: return AArch64::W12;
44 case AArch64::X13: return AArch64::W13;
45 case AArch64::X14: return AArch64::W14;
46 case AArch64::X15: return AArch64::W15;
47 case AArch64::X16: return AArch64::W16;
48 case AArch64::X17: return AArch64::W17;
49 case AArch64::X18: return AArch64::W18;
50 case AArch64::X19: return AArch64::W19;
51 case AArch64::X20: return AArch64::W20;
52 case AArch64::X21: return AArch64::W21;
53 case AArch64::X22: return AArch64::W22;
54 case AArch64::X23: return AArch64::W23;
55 case AArch64::X24: return AArch64::W24;
56 case AArch64::X25: return AArch64::W25;
57 case AArch64::X26: return AArch64::W26;
58 case AArch64::X27: return AArch64::W27;
59 case AArch64::X28: return AArch64::W28;
60 case AArch64::FP: return AArch64::W29;
61 case AArch64::LR: return AArch64::W30;
62 case AArch64::SP: return AArch64::WSP;
63 case AArch64::XZR: return AArch64::WZR;
64 }
65 // For anything else, return it unchanged.
66 return Reg;
67}
68
69inline static unsigned getXRegFromWReg(unsigned Reg) {
70 switch (Reg) {
71 case AArch64::W0: return AArch64::X0;
72 case AArch64::W1: return AArch64::X1;
73 case AArch64::W2: return AArch64::X2;
74 case AArch64::W3: return AArch64::X3;
75 case AArch64::W4: return AArch64::X4;
76 case AArch64::W5: return AArch64::X5;
77 case AArch64::W6: return AArch64::X6;
78 case AArch64::W7: return AArch64::X7;
79 case AArch64::W8: return AArch64::X8;
80 case AArch64::W9: return AArch64::X9;
81 case AArch64::W10: return AArch64::X10;
82 case AArch64::W11: return AArch64::X11;
83 case AArch64::W12: return AArch64::X12;
84 case AArch64::W13: return AArch64::X13;
85 case AArch64::W14: return AArch64::X14;
86 case AArch64::W15: return AArch64::X15;
87 case AArch64::W16: return AArch64::X16;
88 case AArch64::W17: return AArch64::X17;
89 case AArch64::W18: return AArch64::X18;
90 case AArch64::W19: return AArch64::X19;
91 case AArch64::W20: return AArch64::X20;
92 case AArch64::W21: return AArch64::X21;
93 case AArch64::W22: return AArch64::X22;
94 case AArch64::W23: return AArch64::X23;
95 case AArch64::W24: return AArch64::X24;
96 case AArch64::W25: return AArch64::X25;
97 case AArch64::W26: return AArch64::X26;
98 case AArch64::W27: return AArch64::X27;
99 case AArch64::W28: return AArch64::X28;
100 case AArch64::W29: return AArch64::FP;
101 case AArch64::W30: return AArch64::LR;
102 case AArch64::WSP: return AArch64::SP;
103 case AArch64::WZR: return AArch64::XZR;
104 }
105 // For anything else, return it unchanged.
106 return Reg;
107}
108
109inline static unsigned getXRegFromXRegTuple(unsigned RegTuple) {
110 switch (RegTuple) {
111 case AArch64::X0_X1_X2_X3_X4_X5_X6_X7: return AArch64::X0;
112 case AArch64::X2_X3_X4_X5_X6_X7_X8_X9: return AArch64::X2;
113 case AArch64::X4_X5_X6_X7_X8_X9_X10_X11: return AArch64::X4;
114 case AArch64::X6_X7_X8_X9_X10_X11_X12_X13: return AArch64::X6;
115 case AArch64::X8_X9_X10_X11_X12_X13_X14_X15: return AArch64::X8;
116 case AArch64::X10_X11_X12_X13_X14_X15_X16_X17: return AArch64::X10;
117 case AArch64::X12_X13_X14_X15_X16_X17_X18_X19: return AArch64::X12;
118 case AArch64::X14_X15_X16_X17_X18_X19_X20_X21: return AArch64::X14;
119 case AArch64::X16_X17_X18_X19_X20_X21_X22_X23: return AArch64::X16;
120 case AArch64::X18_X19_X20_X21_X22_X23_X24_X25: return AArch64::X18;
121 case AArch64::X20_X21_X22_X23_X24_X25_X26_X27: return AArch64::X20;
122 case AArch64::X22_X23_X24_X25_X26_X27_X28_FP: return AArch64::X22;
123 }
124 // For anything else, return it unchanged.
125 return RegTuple;
126}
127
128static inline unsigned getBRegFromDReg(unsigned Reg) {
129 switch (Reg) {
130 case AArch64::D0: return AArch64::B0;
131 case AArch64::D1: return AArch64::B1;
132 case AArch64::D2: return AArch64::B2;
133 case AArch64::D3: return AArch64::B3;
134 case AArch64::D4: return AArch64::B4;
135 case AArch64::D5: return AArch64::B5;
136 case AArch64::D6: return AArch64::B6;
137 case AArch64::D7: return AArch64::B7;
138 case AArch64::D8: return AArch64::B8;
139 case AArch64::D9: return AArch64::B9;
140 case AArch64::D10: return AArch64::B10;
141 case AArch64::D11: return AArch64::B11;
142 case AArch64::D12: return AArch64::B12;
143 case AArch64::D13: return AArch64::B13;
144 case AArch64::D14: return AArch64::B14;
145 case AArch64::D15: return AArch64::B15;
146 case AArch64::D16: return AArch64::B16;
147 case AArch64::D17: return AArch64::B17;
148 case AArch64::D18: return AArch64::B18;
149 case AArch64::D19: return AArch64::B19;
150 case AArch64::D20: return AArch64::B20;
151 case AArch64::D21: return AArch64::B21;
152 case AArch64::D22: return AArch64::B22;
153 case AArch64::D23: return AArch64::B23;
154 case AArch64::D24: return AArch64::B24;
155 case AArch64::D25: return AArch64::B25;
156 case AArch64::D26: return AArch64::B26;
157 case AArch64::D27: return AArch64::B27;
158 case AArch64::D28: return AArch64::B28;
159 case AArch64::D29: return AArch64::B29;
160 case AArch64::D30: return AArch64::B30;
161 case AArch64::D31: return AArch64::B31;
162 }
163 // For anything else, return it unchanged.
164 return Reg;
165}
166
167
168static inline unsigned getDRegFromBReg(unsigned Reg) {
169 switch (Reg) {
170 case AArch64::B0: return AArch64::D0;
171 case AArch64::B1: return AArch64::D1;
172 case AArch64::B2: return AArch64::D2;
173 case AArch64::B3: return AArch64::D3;
174 case AArch64::B4: return AArch64::D4;
175 case AArch64::B5: return AArch64::D5;
176 case AArch64::B6: return AArch64::D6;
177 case AArch64::B7: return AArch64::D7;
178 case AArch64::B8: return AArch64::D8;
179 case AArch64::B9: return AArch64::D9;
180 case AArch64::B10: return AArch64::D10;
181 case AArch64::B11: return AArch64::D11;
182 case AArch64::B12: return AArch64::D12;
183 case AArch64::B13: return AArch64::D13;
184 case AArch64::B14: return AArch64::D14;
185 case AArch64::B15: return AArch64::D15;
186 case AArch64::B16: return AArch64::D16;
187 case AArch64::B17: return AArch64::D17;
188 case AArch64::B18: return AArch64::D18;
189 case AArch64::B19: return AArch64::D19;
190 case AArch64::B20: return AArch64::D20;
191 case AArch64::B21: return AArch64::D21;
192 case AArch64::B22: return AArch64::D22;
193 case AArch64::B23: return AArch64::D23;
194 case AArch64::B24: return AArch64::D24;
195 case AArch64::B25: return AArch64::D25;
196 case AArch64::B26: return AArch64::D26;
197 case AArch64::B27: return AArch64::D27;
198 case AArch64::B28: return AArch64::D28;
199 case AArch64::B29: return AArch64::D29;
200 case AArch64::B30: return AArch64::D30;
201 case AArch64::B31: return AArch64::D31;
202 }
203 // For anything else, return it unchanged.
204 return Reg;
205}
206
207static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) {
208 switch (Opcode) {
209 case AArch64::LDADDAB: case AArch64::LDADDAH:
210 case AArch64::LDADDAW: case AArch64::LDADDAX:
211 case AArch64::LDADDALB: case AArch64::LDADDALH:
212 case AArch64::LDADDALW: case AArch64::LDADDALX:
213 case AArch64::LDCLRAB: case AArch64::LDCLRAH:
214 case AArch64::LDCLRAW: case AArch64::LDCLRAX:
215 case AArch64::LDCLRALB: case AArch64::LDCLRALH:
216 case AArch64::LDCLRALW: case AArch64::LDCLRALX:
217 case AArch64::LDEORAB: case AArch64::LDEORAH:
218 case AArch64::LDEORAW: case AArch64::LDEORAX:
219 case AArch64::LDEORALB: case AArch64::LDEORALH:
220 case AArch64::LDEORALW: case AArch64::LDEORALX:
221 case AArch64::LDSETAB: case AArch64::LDSETAH:
222 case AArch64::LDSETAW: case AArch64::LDSETAX:
223 case AArch64::LDSETALB: case AArch64::LDSETALH:
224 case AArch64::LDSETALW: case AArch64::LDSETALX:
225 case AArch64::LDSMAXAB: case AArch64::LDSMAXAH:
226 case AArch64::LDSMAXAW: case AArch64::LDSMAXAX:
227 case AArch64::LDSMAXALB: case AArch64::LDSMAXALH:
228 case AArch64::LDSMAXALW: case AArch64::LDSMAXALX:
229 case AArch64::LDSMINAB: case AArch64::LDSMINAH:
230 case AArch64::LDSMINAW: case AArch64::LDSMINAX:
231 case AArch64::LDSMINALB: case AArch64::LDSMINALH:
232 case AArch64::LDSMINALW: case AArch64::LDSMINALX:
233 case AArch64::LDUMAXAB: case AArch64::LDUMAXAH:
234 case AArch64::LDUMAXAW: case AArch64::LDUMAXAX:
235 case AArch64::LDUMAXALB: case AArch64::LDUMAXALH:
236 case AArch64::LDUMAXALW: case AArch64::LDUMAXALX:
237 case AArch64::LDUMINAB: case AArch64::LDUMINAH:
238 case AArch64::LDUMINAW: case AArch64::LDUMINAX:
239 case AArch64::LDUMINALB: case AArch64::LDUMINALH:
240 case AArch64::LDUMINALW: case AArch64::LDUMINALX:
241 case AArch64::SWPAB: case AArch64::SWPAH:
242 case AArch64::SWPAW: case AArch64::SWPAX:
243 case AArch64::SWPALB: case AArch64::SWPALH:
244 case AArch64::SWPALW: case AArch64::SWPALX:
245 return true;
246 }
247 return false;
248}
249
250namespace AArch64CC {
251
252// The CondCodes constants map directly to the 4-bit encoding of the condition
253// field for predicated instructions.
254enum CondCode { // Meaning (integer) Meaning (floating-point)
255 EQ = 0x0, // Equal Equal
256 NE = 0x1, // Not equal Not equal, or unordered
257 HS = 0x2, // Unsigned higher or same >, ==, or unordered
258 LO = 0x3, // Unsigned lower Less than
259 MI = 0x4, // Minus, negative Less than
260 PL = 0x5, // Plus, positive or zero >, ==, or unordered
261 VS = 0x6, // Overflow Unordered
262 VC = 0x7, // No overflow Not unordered
263 HI = 0x8, // Unsigned higher Greater than, or unordered
264 LS = 0x9, // Unsigned lower or same Less than or equal
265 GE = 0xa, // Greater than or equal Greater than or equal
266 LT = 0xb, // Less than Less than, or unordered
267 GT = 0xc, // Greater than Greater than
268 LE = 0xd, // Less than or equal <, ==, or unordered
269 AL = 0xe, // Always (unconditional) Always (unconditional)
270 NV = 0xf, // Always (unconditional) Always (unconditional)
271 // Note the NV exists purely to disassemble 0b1111. Execution is "always".
273
274 // Common aliases used for SVE.
275 ANY_ACTIVE = NE, // (!Z)
276 FIRST_ACTIVE = MI, // ( N)
277 LAST_ACTIVE = LO, // (!C)
278 NONE_ACTIVE = EQ // ( Z)
280
281inline static const char *getCondCodeName(CondCode Code) {
282 switch (Code) {
283 default: llvm_unreachable("Unknown condition code");
284 case EQ: return "eq";
285 case NE: return "ne";
286 case HS: return "hs";
287 case LO: return "lo";
288 case MI: return "mi";
289 case PL: return "pl";
290 case VS: return "vs";
291 case VC: return "vc";
292 case HI: return "hi";
293 case LS: return "ls";
294 case GE: return "ge";
295 case LT: return "lt";
296 case GT: return "gt";
297 case LE: return "le";
298 case AL: return "al";
299 case NV: return "nv";
300 }
301}
302
304 // To reverse a condition it's necessary to only invert the low bit:
305
306 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
307}
308
309/// Given a condition code, return NZCV flags that would satisfy that condition.
310/// The flag bits are in the format expected by the ccmp instructions.
311/// Note that many different flag settings can satisfy a given condition code,
312/// this function just returns one of them.
313inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
314 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
315 enum { N = 8, Z = 4, C = 2, V = 1 };
316 switch (Code) {
317 default: llvm_unreachable("Unknown condition code");
318 case EQ: return Z; // Z == 1
319 case NE: return 0; // Z == 0
320 case HS: return C; // C == 1
321 case LO: return 0; // C == 0
322 case MI: return N; // N == 1
323 case PL: return 0; // N == 0
324 case VS: return V; // V == 1
325 case VC: return 0; // V == 0
326 case HI: return C; // C == 1 && Z == 0
327 case LS: return 0; // C == 0 || Z == 1
328 case GE: return 0; // N == V
329 case LT: return N; // N != V
330 case GT: return 0; // Z == 0 && N == V
331 case LE: return Z; // Z == 1 || N != V
332 }
333}
334
335/// Return true if Code is a reflexive relationship:
336/// forall x. (CSET Code (CMP x x)) == 1
337inline static bool isReflexive(CondCode Code) {
338 switch (Code) {
339 case EQ:
340 case HS:
341 case PL:
342 case LS:
343 case GE:
344 case LE:
345 case AL:
346 case NV:
347 return true;
348 default:
349 return false;
350 }
351}
352
353/// Return true if Code is an irreflexive relationship:
354/// forall x. (CSET Code (CMP x x)) == 0
355inline static bool isIrreflexive(CondCode Code) {
356 switch (Code) {
357 case NE:
358 case LO:
359 case MI:
360 case HI:
361 case LT:
362 case GT:
363 return true;
364 default:
365 return false;
366 }
367}
368
369} // end namespace AArch64CC
370
371struct SysAlias {
372 const char *Name;
375
376 constexpr SysAlias(const char *N, uint16_t E) : Name(N), Encoding(E) {}
377 constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
379
380 bool haveFeatures(FeatureBitset ActiveFeatures) const {
381 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
382 (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
383 }
384
386};
387
390 constexpr SysAliasReg(const char *N, uint16_t E, bool R)
391 : SysAlias(N, E), NeedsReg(R) {}
392 constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
393 : SysAlias(N, E, F), NeedsReg(R) {}
394};
395
398 constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
399 : SysAlias(N, E), ImmValue(I) {}
400 constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
401 : SysAlias(N, E, F), ImmValue(I) {}
402};
403
404namespace AArch64SVCR {
405 struct SVCR : SysAlias{
406 using SysAlias::SysAlias;
407 };
408 #define GET_SVCR_DECL
409 #include "AArch64GenSystemOperands.inc"
410}
411
412namespace AArch64AT{
413 struct AT : SysAlias {
414 using SysAlias::SysAlias;
415 };
416 #define GET_AT_DECL
417 #include "AArch64GenSystemOperands.inc"
418}
419
420namespace AArch64DB {
421 struct DB : SysAlias {
422 using SysAlias::SysAlias;
423 };
424 #define GET_DB_DECL
425 #include "AArch64GenSystemOperands.inc"
426}
427
428namespace AArch64DBnXS {
431 };
432 #define GET_DBNXS_DECL
433 #include "AArch64GenSystemOperands.inc"
434}
435
436namespace AArch64DC {
437 struct DC : SysAlias {
438 using SysAlias::SysAlias;
439 };
440 #define GET_DC_DECL
441 #include "AArch64GenSystemOperands.inc"
442}
443
444namespace AArch64IC {
445 struct IC : SysAliasReg {
447 };
448 #define GET_IC_DECL
449 #include "AArch64GenSystemOperands.inc"
450}
451
452namespace AArch64ISB {
453 struct ISB : SysAlias {
454 using SysAlias::SysAlias;
455 };
456 #define GET_ISB_DECL
457 #include "AArch64GenSystemOperands.inc"
458}
459
460namespace AArch64TSB {
461 struct TSB : SysAlias {
462 using SysAlias::SysAlias;
463 };
464 #define GET_TSB_DECL
465 #include "AArch64GenSystemOperands.inc"
466}
467
468namespace AArch64PRFM {
469 struct PRFM : SysAlias {
470 using SysAlias::SysAlias;
471 };
472 #define GET_PRFM_DECL
473 #include "AArch64GenSystemOperands.inc"
474}
475
476namespace AArch64SVEPRFM {
477 struct SVEPRFM : SysAlias {
478 using SysAlias::SysAlias;
479 };
480#define GET_SVEPRFM_DECL
481#include "AArch64GenSystemOperands.inc"
482}
483
484namespace AArch64RPRFM {
485struct RPRFM : SysAlias {
486 using SysAlias::SysAlias;
487};
488#define GET_RPRFM_DECL
489#include "AArch64GenSystemOperands.inc"
490} // namespace AArch64RPRFM
491
492namespace AArch64SVEPredPattern {
493 struct SVEPREDPAT {
494 const char *Name;
496 };
497#define GET_SVEPREDPAT_DECL
498#include "AArch64GenSystemOperands.inc"
499}
500
501namespace AArch64SVEVecLenSpecifier {
503 const char *Name;
505 };
506#define GET_SVEVECLENSPECIFIER_DECL
507#include "AArch64GenSystemOperands.inc"
508} // namespace AArch64SVEVecLenSpecifier
509
510/// Return the number of active elements for VL1 to VL256 predicate pattern,
511/// zero for all other patterns.
512inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern) {
513 switch (Pattern) {
514 default:
515 return 0;
516 case AArch64SVEPredPattern::vl1:
517 case AArch64SVEPredPattern::vl2:
518 case AArch64SVEPredPattern::vl3:
519 case AArch64SVEPredPattern::vl4:
520 case AArch64SVEPredPattern::vl5:
521 case AArch64SVEPredPattern::vl6:
522 case AArch64SVEPredPattern::vl7:
523 case AArch64SVEPredPattern::vl8:
524 return Pattern;
525 case AArch64SVEPredPattern::vl16:
526 return 16;
527 case AArch64SVEPredPattern::vl32:
528 return 32;
529 case AArch64SVEPredPattern::vl64:
530 return 64;
531 case AArch64SVEPredPattern::vl128:
532 return 128;
533 case AArch64SVEPredPattern::vl256:
534 return 256;
535 }
536}
537
538/// Return specific VL predicate pattern based on the number of elements.
539inline std::optional<unsigned>
541 switch (MinNumElts) {
542 default:
543 return std::nullopt;
544 case 1:
545 case 2:
546 case 3:
547 case 4:
548 case 5:
549 case 6:
550 case 7:
551 case 8:
552 return MinNumElts;
553 case 16:
554 return AArch64SVEPredPattern::vl16;
555 case 32:
556 return AArch64SVEPredPattern::vl32;
557 case 64:
558 return AArch64SVEPredPattern::vl64;
559 case 128:
560 return AArch64SVEPredPattern::vl128;
561 case 256:
562 return AArch64SVEPredPattern::vl256;
563 }
564}
565
566namespace AArch64ExactFPImm {
567 struct ExactFPImm {
568 const char *Name;
569 int Enum;
570 const char *Repr;
571 };
572#define GET_EXACTFPIMM_DECL
573#include "AArch64GenSystemOperands.inc"
574}
575
576namespace AArch64PState {
578 using SysAlias::SysAlias;
579 };
580 #define GET_PSTATEIMM0_15_DECL
581 #include "AArch64GenSystemOperands.inc"
582
584 using SysAlias::SysAlias;
585 };
586 #define GET_PSTATEIMM0_1_DECL
587 #include "AArch64GenSystemOperands.inc"
588}
589
590namespace AArch64PSBHint {
591 struct PSB : SysAlias {
592 using SysAlias::SysAlias;
593 };
594 #define GET_PSB_DECL
595 #include "AArch64GenSystemOperands.inc"
596}
597
598namespace AArch64BTIHint {
599 struct BTI : SysAlias {
600 using SysAlias::SysAlias;
601 };
602 #define GET_BTI_DECL
603 #include "AArch64GenSystemOperands.inc"
604}
605
606namespace AArch64SE {
614
619
623 SXTX
624 };
625}
626
627namespace AArch64Layout {
634
639
640 // Bare layout for the 128-bit vector
641 // (only show ".b", ".h", ".s", ".d" without vector number)
645 VL_D
646 };
647}
648
649inline static const char *
651 switch (Layout) {
652 case AArch64Layout::VL_8B: return ".8b";
653 case AArch64Layout::VL_4H: return ".4h";
654 case AArch64Layout::VL_2S: return ".2s";
655 case AArch64Layout::VL_1D: return ".1d";
656 case AArch64Layout::VL_16B: return ".16b";
657 case AArch64Layout::VL_8H: return ".8h";
658 case AArch64Layout::VL_4S: return ".4s";
659 case AArch64Layout::VL_2D: return ".2d";
660 case AArch64Layout::VL_B: return ".b";
661 case AArch64Layout::VL_H: return ".h";
662 case AArch64Layout::VL_S: return ".s";
663 case AArch64Layout::VL_D: return ".d";
664 default: llvm_unreachable("Unknown Vector Layout");
665 }
666}
667
668inline static AArch64Layout::VectorLayout
684}
685
686namespace AArch64SysReg {
687 struct SysReg {
688 const char *Name;
689 const char *AltName;
690 unsigned Encoding;
694
695 bool haveFeatures(FeatureBitset ActiveFeatures) const {
696 return ActiveFeatures[llvm::AArch64::FeatureAll] ||
697 (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
698 }
699 };
700
701 #define GET_SYSREG_DECL
702 #include "AArch64GenSystemOperands.inc"
703
706
708 std::string genericRegisterString(uint32_t Bits);
709}
710
711namespace AArch64TLBI {
712 struct TLBI : SysAliasReg {
714 };
715 #define GET_TLBITable_DECL
716 #include "AArch64GenSystemOperands.inc"
717}
718
719namespace AArch64PRCTX {
722 };
723 #define GET_PRCTX_DECL
724 #include "AArch64GenSystemOperands.inc"
725}
726
727namespace AArch64II {
728 /// Target Operand Flag enum.
729 enum TOF {
730 //===------------------------------------------------------------------===//
731 // AArch64 Specific MachineOperand flags.
732
734
736
737 /// MO_PAGE - A symbol operand with this flag represents the pc-relative
738 /// offset of the 4K page containing the symbol. This is used with the
739 /// ADRP instruction.
741
742 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
743 /// that symbol within a 4K page. This offset is added to the page address
744 /// to produce the complete address.
746
747 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
748 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
749 MO_G3 = 3,
750
751 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
752 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
753 MO_G2 = 4,
754
755 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
756 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
757 MO_G1 = 5,
758
759 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
760 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
761 MO_G0 = 6,
762
763 /// MO_HI12 - This flag indicates that a symbol operand represents the bits
764 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
765 /// by-12-bits instruction.
767
768 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
769 /// reference is actually to the ".refptr.FOO" symbol. This is used for
770 /// stub symbols on windows.
772
773 /// MO_GOT - This flag indicates that a symbol operand represents the
774 /// address of the GOT entry for the symbol, rather than the address of
775 /// the symbol itself.
776 MO_GOT = 0x10,
777
778 /// MO_NC - Indicates whether the linker is expected to check the symbol
779 /// reference for overflow. For example in an ADRP/ADD pair of relocations
780 /// the ADRP usually does check, but not the ADD.
781 MO_NC = 0x20,
782
783 /// MO_TLS - Indicates that the operand being accessed is some kind of
784 /// thread-local symbol. On Darwin, only one type of thread-local access
785 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
786 /// referee will affect interpretation.
787 MO_TLS = 0x40,
788
789 /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
790 /// to the symbol is for an import stub. This is used for DLL import
791 /// storage class indication on Windows.
793
794 /// MO_S - Indicates that the bits of the symbol operand represented by
795 /// MO_G0 etc are signed.
796 MO_S = 0x100,
797
798 /// MO_PREL - Indicates that the bits of the symbol operand represented by
799 /// MO_G0 etc are PC relative.
800 MO_PREL = 0x200,
801
802 /// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag
803 /// in bits 56-63.
804 /// On a FrameIndex operand, indicates that the underlying memory is tagged
805 /// with an unknown tag value (MTE); this needs to be lowered either to an
806 /// SP-relative load or store instruction (which do not check tags), or to
807 /// an LDG instruction to obtain the tag value.
808 MO_TAGGED = 0x400,
809
810 /// MO_DLLIMPORTAUX - Symbol refers to "auxilliary" import stub. On
811 /// Arm64EC, there are two kinds of import stubs used for DLL import of
812 /// functions: MO_DLLIMPORT refers to natively callable Arm64 code, and
813 /// MO_DLLIMPORTAUX refers to the original address which can be compared
814 /// for equality.
816 };
817} // end namespace AArch64II
818
819//===----------------------------------------------------------------------===//
820// v8.3a Pointer Authentication
821//
822
823namespace AArch64PACKey {
824enum ID : uint8_t {
825 IA = 0,
826 IB = 1,
827 DA = 2,
828 DB = 3,
829 LAST = DB
831} // namespace AArch64PACKey
832
833/// Return 2-letter identifier string for numeric key ID.
835 switch (KeyID) {
837 return StringRef("ia");
839 return StringRef("ib");
841 return StringRef("da");
843 return StringRef("db");
844 }
845}
846
847/// Return numeric key ID for 2-letter identifier string.
848inline static std::optional<AArch64PACKey::ID>
850 if (Name == "ia")
851 return AArch64PACKey::IA;
852 if (Name == "ib")
853 return AArch64PACKey::IB;
854 if (Name == "da")
855 return AArch64PACKey::DA;
856 if (Name == "db")
857 return AArch64PACKey::DB;
858 return std::nullopt;
859}
860
861namespace AArch64 {
862// The number of bits in a SVE register is architecturally defined
863// to be a multiple of this value. If <M x t> has this number of bits,
864// a <n x M x t> vector can be stored in a SVE register without any
865// redundant bits. If <M x t> has this number of bits divided by P,
866// a <n x M x t> vector is stored in a SVE register by placing index i
867// in index i*P of a <n x (M*P) x t> vector. The other elements of the
868// <n x (M*P) x t> vector (such as index 1) are undefined.
869static constexpr unsigned SVEBitsPerBlock = 128;
870static constexpr unsigned SVEMaxBitsPerVector = 2048;
871} // end namespace AArch64
872} // end namespace llvm
873
874#endif
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
std::string Name
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned Reg
This file contains some templates that are useful if you are working with the STL at all.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Container class for subtarget features.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool isReflexive(CondCode Code)
Return true if Code is a reflexive relationship: forall x.
static const char * getCondCodeName(CondCode Code)
static bool isIrreflexive(CondCode Code)
Return true if Code is an irreflexive relationship: forall x.
static CondCode getInvertedCondCode(CondCode Code)
static unsigned getNZCVToSatisfyCondCode(CondCode Code)
Given a condition code, return NZCV flags that would satisfy that condition.
TOF
Target Operand Flag enum.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
@ MO_NC
MO_NC - Indicates whether the linker is expected to check the symbol reference for overflow.
@ MO_G1
MO_G1 - A symbol operand with this flag (granule 1) represents the bits 16-31 of a 64-bit address,...
@ MO_S
MO_S - Indicates that the bits of the symbol operand represented by MO_G0 etc are signed.
@ MO_PAGEOFF
MO_PAGEOFF - A symbol operand with this flag represents the offset of that symbol within a 4K page.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
@ MO_PREL
MO_PREL - Indicates that the bits of the symbol operand represented by MO_G0 etc are PC relative.
@ MO_G0
MO_G0 - A symbol operand with this flag (granule 0) represents the bits 0-15 of a 64-bit address,...
@ MO_PAGE
MO_PAGE - A symbol operand with this flag represents the pc-relative offset of the 4K page containing...
@ MO_DLLIMPORTAUX
MO_DLLIMPORTAUX - Symbol refers to "auxilliary" import stub.
@ MO_HI12
MO_HI12 - This flag indicates that a symbol operand represents the bits 13-24 of a 64-bit address,...
@ MO_TLS
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
@ MO_G2
MO_G2 - A symbol operand with this flag (granule 2) represents the bits 32-47 of a 64-bit address,...
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
@ MO_G3
MO_G3 - A symbol operand with this flag (granule 3) represents the high 16-bits of a 64-bit address,...
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
const SysReg * lookupSysRegByEncoding(uint16_t)
uint32_t parseGenericRegister(StringRef Name)
std::string genericRegisterString(uint32_t Bits)
const SysReg * lookupSysRegByName(StringRef)
static constexpr unsigned SVEMaxBitsPerVector
static constexpr unsigned SVEBitsPerBlock
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static std::optional< AArch64PACKey::ID > AArch64StringToPACKeyID(StringRef Name)
Return numeric key ID for 2-letter identifier string.
static AArch64Layout::VectorLayout AArch64StringToVectorLayout(StringRef LayoutStr)
static const char * AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout)
std::optional< unsigned > getSVEPredPatternFromNumElements(unsigned MinNumElts)
Return specific VL predicate pattern based on the number of elements.
static unsigned getXRegFromWReg(unsigned Reg)
static unsigned getXRegFromXRegTuple(unsigned RegTuple)
static unsigned getDRegFromBReg(unsigned Reg)
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
static unsigned getWRegFromXReg(unsigned Reg)
unsigned getNumElementsFromSVEPredPattern(unsigned Pattern)
Return the number of active elements for VL1 to VL256 predicate pattern, zero for all other patterns.
static unsigned getBRegFromDReg(unsigned Reg)
static StringRef AArch64PACKeyIDToString(AArch64PACKey::ID KeyID)
Return 2-letter identifier string for numeric key ID.
#define N
bool haveFeatures(FeatureBitset ActiveFeatures) const
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
constexpr SysAliasReg(const char *N, uint16_t E, bool R)
bool haveFeatures(FeatureBitset ActiveFeatures) const
constexpr SysAlias(const char *N, uint16_t E)
FeatureBitset getRequiredFeatures() const
const char * Name
FeatureBitset FeaturesRequired
constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)