LLVM  16.0.0git
AArch64BaseInfo.cpp
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1 //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides basic encoding and assembly information for AArch64.
10 //
11 //===----------------------------------------------------------------------===//
12 #include "AArch64BaseInfo.h"
13 #include "llvm/ADT/ArrayRef.h"
14 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Support/Regex.h"
17 
18 using namespace llvm;
19 
20 namespace llvm {
21  namespace AArch64AT {
22 #define GET_AT_IMPL
23 #include "AArch64GenSystemOperands.inc"
24  }
25 }
26 
27 
28 namespace llvm {
29  namespace AArch64DBnXS {
30 #define GET_DBNXS_IMPL
31 #include "AArch64GenSystemOperands.inc"
32  }
33 }
34 
35 namespace llvm {
36  namespace AArch64DB {
37 #define GET_DB_IMPL
38 #include "AArch64GenSystemOperands.inc"
39  }
40 }
41 
42 namespace llvm {
43  namespace AArch64DC {
44 #define GET_DC_IMPL
45 #include "AArch64GenSystemOperands.inc"
46  }
47 }
48 
49 namespace llvm {
50  namespace AArch64IC {
51 #define GET_IC_IMPL
52 #include "AArch64GenSystemOperands.inc"
53  }
54 }
55 
56 namespace llvm {
57  namespace AArch64ISB {
58 #define GET_ISB_IMPL
59 #include "AArch64GenSystemOperands.inc"
60  }
61 }
62 
63 namespace llvm {
64  namespace AArch64TSB {
65 #define GET_TSB_IMPL
66 #include "AArch64GenSystemOperands.inc"
67  }
68 }
69 
70 namespace llvm {
71  namespace AArch64PRCTX {
72 #define GET_PRCTX_IMPL
73 #include "AArch64GenSystemOperands.inc"
74  }
75 }
76 
77 namespace llvm {
78  namespace AArch64PRFM {
79 #define GET_PRFM_IMPL
80 #include "AArch64GenSystemOperands.inc"
81  }
82 }
83 
84 namespace llvm {
85  namespace AArch64SVEPRFM {
86 #define GET_SVEPRFM_IMPL
87 #include "AArch64GenSystemOperands.inc"
88  }
89 }
90 
91 namespace llvm {
92  namespace AArch64RPRFM {
93 #define GET_RPRFM_IMPL
94 #include "AArch64GenSystemOperands.inc"
95  } // namespace AArch64RPRFM
96 } // namespace llvm
97 
98 namespace llvm {
99  namespace AArch64SVEPredPattern {
100 #define GET_SVEPREDPAT_IMPL
101 #include "AArch64GenSystemOperands.inc"
102  }
103 }
104 
105 namespace llvm {
106 namespace AArch64SVEVecLenSpecifier {
107 #define GET_SVEVECLENSPECIFIER_IMPL
108 #include "AArch64GenSystemOperands.inc"
109 } // namespace AArch64SVEVecLenSpecifier
110 } // namespace llvm
111 
112 namespace llvm {
113  namespace AArch64ExactFPImm {
114 #define GET_EXACTFPIMM_IMPL
115 #include "AArch64GenSystemOperands.inc"
116  }
117 }
118 
119 namespace llvm {
120  namespace AArch64PState {
121 #define GET_PSTATE_IMPL
122 #include "AArch64GenSystemOperands.inc"
123  }
124 }
125 
126 namespace llvm {
127  namespace AArch64PSBHint {
128 #define GET_PSB_IMPL
129 #include "AArch64GenSystemOperands.inc"
130  }
131 }
132 
133 namespace llvm {
134  namespace AArch64BTIHint {
135 #define GET_BTI_IMPL
136 #include "AArch64GenSystemOperands.inc"
137  }
138 }
139 
140 namespace llvm {
141  namespace AArch64SysReg {
142 #define GET_SYSREG_IMPL
143 #include "AArch64GenSystemOperands.inc"
144  }
145 }
146 
148  // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
149  static const Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$");
150 
151  std::string UpperName = Name.upper();
153  if (!GenericRegPattern.match(UpperName, &Ops))
154  return -1;
155 
156  uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
157  uint32_t Bits;
158  Ops[1].getAsInteger(10, Op0);
159  Ops[2].getAsInteger(10, Op1);
160  Ops[3].getAsInteger(10, CRn);
161  Ops[4].getAsInteger(10, CRm);
162  Ops[5].getAsInteger(10, Op2);
163  Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
164 
165  return Bits;
166 }
167 
169  assert(Bits < 0x10000);
170  uint32_t Op0 = (Bits >> 14) & 0x3;
171  uint32_t Op1 = (Bits >> 11) & 0x7;
172  uint32_t CRn = (Bits >> 7) & 0xf;
173  uint32_t CRm = (Bits >> 3) & 0xf;
174  uint32_t Op2 = Bits & 0x7;
175 
176  return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
177  utostr(CRm) + "_" + utostr(Op2);
178 }
179 
180 namespace llvm {
181  namespace AArch64TLBI {
182 #define GET_TLBITable_IMPL
183 #include "AArch64GenSystemOperands.inc"
184  }
185 }
186 
187 namespace llvm {
188  namespace AArch64SVCR {
189 #define GET_SVCR_IMPL
190 #include "AArch64GenSystemOperands.inc"
191  }
192 }
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
AArch64BaseInfo.h
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::Regex::match
bool match(StringRef String, SmallVectorImpl< StringRef > *Matches=nullptr, std::string *Error=nullptr) const
matches - Match the regex against a given String.
Definition: Regex.cpp:86
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
StringExtras.h
ArrayRef.h
llvm::AArch64SysReg::parseGenericRegister
uint32_t parseGenericRegister(StringRef Name)
Definition: AArch64BaseInfo.cpp:147
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Regex.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
uint32_t
llvm::AArch64SysReg::genericRegisterString
std::string genericRegisterString(uint32_t Bits)
Definition: AArch64BaseInfo.cpp:168
SmallVector.h
llvm::Regex
Definition: Regex.h:28