LLVM 19.0.0git
MachineInstrBundle.cpp
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1//===-- lib/CodeGen/MachineInstrBundle.cpp --------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10#include "llvm/ADT/SmallSet.h"
14#include "llvm/CodeGen/Passes.h"
19#include "llvm/Pass.h"
20#include "llvm/PassRegistry.h"
21#include <utility>
22using namespace llvm;
23
24namespace {
25 class UnpackMachineBundles : public MachineFunctionPass {
26 public:
27 static char ID; // Pass identification
28 UnpackMachineBundles(
29 std::function<bool(const MachineFunction &)> Ftor = nullptr)
30 : MachineFunctionPass(ID), PredicateFtor(std::move(Ftor)) {
32 }
33
34 bool runOnMachineFunction(MachineFunction &MF) override;
35
36 private:
37 std::function<bool(const MachineFunction &)> PredicateFtor;
38 };
39} // end anonymous namespace
40
41char UnpackMachineBundles::ID = 0;
42char &llvm::UnpackMachineBundlesID = UnpackMachineBundles::ID;
43INITIALIZE_PASS(UnpackMachineBundles, "unpack-mi-bundles",
44 "Unpack machine instruction bundles", false, false)
45
46bool UnpackMachineBundles::runOnMachineFunction(MachineFunction &MF) {
47 if (PredicateFtor && !PredicateFtor(MF))
48 return false;
49
50 bool Changed = false;
51 for (MachineBasicBlock &MBB : MF) {
53 MIE = MBB.instr_end(); MII != MIE; ) {
54 MachineInstr *MI = &*MII;
55
56 // Remove BUNDLE instruction and the InsideBundle flags from bundled
57 // instructions.
58 if (MI->isBundle()) {
59 while (++MII != MIE && MII->isBundledWithPred()) {
60 MII->unbundleFromPred();
61 for (MachineOperand &MO : MII->operands()) {
62 if (MO.isReg() && MO.isInternalRead())
63 MO.setIsInternalRead(false);
64 }
65 }
66 MI->eraseFromParent();
67
68 Changed = true;
69 continue;
70 }
71
72 ++MII;
73 }
74 }
75
76 return Changed;
77}
78
81 std::function<bool(const MachineFunction &)> Ftor) {
82 return new UnpackMachineBundles(std::move(Ftor));
83}
84
85namespace {
86 class FinalizeMachineBundles : public MachineFunctionPass {
87 public:
88 static char ID; // Pass identification
89 FinalizeMachineBundles() : MachineFunctionPass(ID) {
91 }
92
93 bool runOnMachineFunction(MachineFunction &MF) override;
94 };
95} // end anonymous namespace
96
97char FinalizeMachineBundles::ID = 0;
98char &llvm::FinalizeMachineBundlesID = FinalizeMachineBundles::ID;
99INITIALIZE_PASS(FinalizeMachineBundles, "finalize-mi-bundles",
100 "Finalize machine instruction bundles", false, false)
101
102bool FinalizeMachineBundles::runOnMachineFunction(MachineFunction &MF) {
103 return llvm::finalizeBundles(MF);
104}
105
106/// Return the first found DebugLoc that has a DILocation, given a range of
107/// instructions. The search range is from FirstMI to LastMI (exclusive). If no
108/// DILocation is found, then an empty location is returned.
111 for (auto MII = FirstMI; MII != LastMI; ++MII)
112 if (MII->getDebugLoc())
113 return MII->getDebugLoc();
114 return DebugLoc();
115}
116
117/// finalizeBundle - Finalize a machine instruction bundle which includes
118/// a sequence of instructions starting from FirstMI to LastMI (exclusive).
119/// This routine adds a BUNDLE instruction to represent the bundle, it adds
120/// IsInternalRead markers to MachineOperands which are defined inside the
121/// bundle, and it copies externally visible defs and uses to the BUNDLE
122/// instruction.
126 assert(FirstMI != LastMI && "Empty bundle?");
127 MIBundleBuilder Bundle(MBB, FirstMI, LastMI);
128
132
134 BuildMI(MF, getDebugLoc(FirstMI, LastMI), TII->get(TargetOpcode::BUNDLE));
135 Bundle.prepend(MIB);
136
138 SmallSet<Register, 32> LocalDefSet;
139 SmallSet<Register, 8> DeadDefSet;
140 SmallSet<Register, 16> KilledDefSet;
141 SmallVector<Register, 8> ExternUses;
142 SmallSet<Register, 8> ExternUseSet;
143 SmallSet<Register, 8> KilledUseSet;
144 SmallSet<Register, 8> UndefUseSet;
146 for (auto MII = FirstMI; MII != LastMI; ++MII) {
147 // Debug instructions have no effects to track.
148 if (MII->isDebugInstr())
149 continue;
150
151 for (MachineOperand &MO : MII->operands()) {
152 if (!MO.isReg())
153 continue;
154 if (MO.isDef()) {
155 Defs.push_back(&MO);
156 continue;
157 }
158
159 Register Reg = MO.getReg();
160 if (!Reg)
161 continue;
162
163 if (LocalDefSet.count(Reg)) {
164 MO.setIsInternalRead();
165 if (MO.isKill())
166 // Internal def is now killed.
167 KilledDefSet.insert(Reg);
168 } else {
169 if (ExternUseSet.insert(Reg).second) {
170 ExternUses.push_back(Reg);
171 if (MO.isUndef())
172 UndefUseSet.insert(Reg);
173 }
174 if (MO.isKill())
175 // External def is now killed.
176 KilledUseSet.insert(Reg);
177 }
178 }
179
180 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
181 MachineOperand &MO = *Defs[i];
182 Register Reg = MO.getReg();
183 if (!Reg)
184 continue;
185
186 if (LocalDefSet.insert(Reg).second) {
187 LocalDefs.push_back(Reg);
188 if (MO.isDead()) {
189 DeadDefSet.insert(Reg);
190 }
191 } else {
192 // Re-defined inside the bundle, it's no longer killed.
193 KilledDefSet.erase(Reg);
194 if (!MO.isDead())
195 // Previously defined but dead.
196 DeadDefSet.erase(Reg);
197 }
198
199 if (!MO.isDead() && Reg.isPhysical()) {
200 for (MCPhysReg SubReg : TRI->subregs(Reg)) {
201 if (LocalDefSet.insert(SubReg).second)
202 LocalDefs.push_back(SubReg);
203 }
204 }
205 }
206
207 Defs.clear();
208 }
209
211 for (Register Reg : LocalDefs) {
212 if (Added.insert(Reg).second) {
213 // If it's not live beyond end of the bundle, mark it dead.
214 bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg);
215 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
216 getImplRegState(true));
217 }
218 }
219
220 for (Register Reg : ExternUses) {
221 bool isKill = KilledUseSet.count(Reg);
222 bool isUndef = UndefUseSet.count(Reg);
223 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
224 getImplRegState(true));
225 }
226
227 // Set FrameSetup/FrameDestroy for the bundle. If any of the instructions got
228 // the property, then also set it on the bundle.
229 for (auto MII = FirstMI; MII != LastMI; ++MII) {
230 if (MII->getFlag(MachineInstr::FrameSetup))
232 if (MII->getFlag(MachineInstr::FrameDestroy))
234 }
235}
236
237/// finalizeBundle - Same functionality as the previous finalizeBundle except
238/// the last instruction in the bundle is not provided as an input. This is
239/// used in cases where bundles are pre-determined by marking instructions
240/// with 'InsideBundle' marker. It returns the MBB instruction iterator that
241/// points to the end of the bundle.
246 MachineBasicBlock::instr_iterator LastMI = std::next(FirstMI);
247 while (LastMI != E && LastMI->isInsideBundle())
248 ++LastMI;
249 finalizeBundle(MBB, FirstMI, LastMI);
250 return LastMI;
251}
252
253/// finalizeBundles - Finalize instruction bundles in the specified
254/// MachineFunction. Return true if any bundles are finalized.
256 bool Changed = false;
257 for (MachineBasicBlock &MBB : MF) {
260 if (MII == MIE)
261 continue;
262 assert(!MII->isInsideBundle() &&
263 "First instr cannot be inside bundle before finalization!");
264
265 for (++MII; MII != MIE; ) {
266 if (!MII->isInsideBundle())
267 ++MII;
268 else {
269 MII = finalizeBundle(MBB, std::prev(MII));
270 Changed = true;
271 }
272 }
273 }
274
275 return Changed;
276}
277
280 SmallVectorImpl<std::pair<MachineInstr *, unsigned>> *Ops) {
281 VirtRegInfo RI = {false, false, false};
282 for (MIBundleOperands O(MI); O.isValid(); ++O) {
283 MachineOperand &MO = *O;
284 if (!MO.isReg() || MO.getReg() != Reg)
285 continue;
286
287 // Remember each (MI, OpNo) that refers to Reg.
288 if (Ops)
289 Ops->push_back(std::make_pair(MO.getParent(), O.getOperandNo()));
290
291 // Both defs and uses can read virtual registers.
292 if (MO.readsReg()) {
293 RI.Reads = true;
294 if (MO.isDef())
295 RI.Tied = true;
296 }
297
298 // Only defs can write.
299 if (MO.isDef())
300 RI.Writes = true;
301 else if (!RI.Tied &&
302 MO.getParent()->isRegTiedToDefOperand(O.getOperandNo()))
303 RI.Tied = true;
304 }
305 return RI;
306}
307
308std::pair<LaneBitmask, LaneBitmask>
311 const TargetRegisterInfo &TRI) {
312
313 LaneBitmask UseMask, DefMask;
314
315 for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
316 const MachineOperand &MO = *O;
317 if (!MO.isReg() || MO.getReg() != Reg)
318 continue;
319
320 unsigned SubReg = MO.getSubReg();
321 if (SubReg == 0 && MO.isUse() && !MO.isUndef())
322 UseMask |= MRI.getMaxLaneMaskForVReg(Reg);
323
324 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg);
325 if (MO.isDef()) {
326 if (!MO.isUndef())
327 UseMask |= ~SubRegMask;
328 DefMask |= SubRegMask;
329 } else if (!MO.isUndef())
330 UseMask |= SubRegMask;
331 }
332
333 return {UseMask, DefMask};
334}
335
337 const TargetRegisterInfo *TRI) {
338 bool AllDefsDead = true;
339 PhysRegInfo PRI = {false, false, false, false, false, false, false, false};
340
341 assert(Reg.isPhysical() && "analyzePhysReg not given a physical register!");
342 for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
343 const MachineOperand &MO = *O;
344
345 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) {
346 PRI.Clobbered = true;
347 continue;
348 }
349
350 if (!MO.isReg())
351 continue;
352
353 Register MOReg = MO.getReg();
354 if (!MOReg || !MOReg.isPhysical())
355 continue;
356
357 if (!TRI->regsOverlap(MOReg, Reg))
358 continue;
359
360 bool Covered = TRI->isSuperRegisterEq(Reg, MOReg);
361 if (MO.readsReg()) {
362 PRI.Read = true;
363 if (Covered) {
364 PRI.FullyRead = true;
365 if (MO.isKill())
366 PRI.Killed = true;
367 }
368 } else if (MO.isDef()) {
369 PRI.Defined = true;
370 if (Covered)
371 PRI.FullyDefined = true;
372 if (!MO.isDead())
373 AllDefsDead = false;
374 }
375 }
376
377 if (AllDefsDead) {
378 if (PRI.FullyDefined || PRI.Clobbered)
379 PRI.DeadDef = true;
380 else if (PRI.Defined)
381 PRI.PartialDeadDef = true;
382 }
383
384 return PRI;
385}
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const HexagonInstrInfo * TII
static bool isUndef(ArrayRef< int > Mask)
IRTranslator LLVM IR MI
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
This file defines the SmallVector class.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
A debug info location.
Definition: DebugLoc.h:33
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
Helper class for constructing bundles of MachineInstrs.
MIBundleBuilder & prepend(MachineInstr *MI)
Insert MI into MBB by prepending it to the instructions in the bundle.
MIBundleOperands - Iterate over all operands in a bundle of machine instructions.
instr_iterator instr_begin()
Instructions::iterator instr_iterator
instr_iterator instr_end()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:166
bool erase(const T &V)
Definition: SmallSet.h:207
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:179
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
char & FinalizeMachineBundlesID
FinalizeMachineBundles - This pass finalize machine instruction bundles (created earlier,...
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool finalizeBundles(MachineFunction &MF)
finalizeBundles - Finalize instruction bundles in the specified MachineFunction.
PhysRegInfo AnalyzePhysRegInBundle(const MachineInstr &MI, Register Reg, const TargetRegisterInfo *TRI)
AnalyzePhysRegInBundle - Analyze how the current instruction or bundle uses a physical register.
unsigned getDeadRegState(bool B)
void initializeFinalizeMachineBundlesPass(PassRegistry &)
void initializeUnpackMachineBundlesPass(PassRegistry &)
unsigned getImplRegState(bool B)
VirtRegInfo AnalyzeVirtRegInBundle(MachineInstr &MI, Register Reg, SmallVectorImpl< std::pair< MachineInstr *, unsigned > > *Ops=nullptr)
AnalyzeVirtRegInBundle - Analyze how the current instruction or bundle uses a virtual register.
unsigned getUndefRegState(bool B)
unsigned getDefRegState(bool B)
unsigned getKillRegState(bool B)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1858
char & UnpackMachineBundlesID
UnpackMachineBundles - This pass unpack machine instruction bundles.
std::pair< LaneBitmask, LaneBitmask > AnalyzeVirtRegLanesInBundle(const MachineInstr &MI, Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
Return a pair of lane masks (reads, writes) indicating which lanes this instruction uses with Reg.
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
Information about how a physical register Reg is used by a set of operands.
bool Read
Reg or one of its aliases is read.
bool Defined
Reg or one of its aliases is defined.
bool Killed
There is a use operand of reg or a super-register with kill flag set.
bool PartialDeadDef
Reg is Defined and all defs of reg or an overlapping register are dead.
bool Clobbered
There is a regmask operand indicating Reg is clobbered.
bool FullyRead
Reg or a super-register is read. The full register is read.
bool FullyDefined
Reg or a super-register is defined.
VirtRegInfo - Information about a virtual register used by a set of operands.
bool Reads
Reads - One of the operands read the virtual register.
bool Tied
Tied - Uses and defs must use the same register.
bool Writes
Writes - One of the operands writes the virtual register.