41char UnpackMachineBundles::ID = 0;
44 "Unpack machine instruction bundles",
false,
false)
47 if (PredicateFtor && !PredicateFtor(MF))
59 while (++MII != MIE && MII->isBundledWithPred()) {
60 MII->unbundleFromPred();
61 for (
unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
67 MI->eraseFromParent();
83 return new UnpackMachineBundles(std::move(Ftor));
98char FinalizeMachineBundles::ID = 0;
101 "Finalize machine instruction bundles",
false,
false)
112 for (
auto MII = FirstMI; MII != LastMI; ++MII)
113 if (MII->getDebugLoc())
114 return MII->getDebugLoc();
127 assert(FirstMI != LastMI &&
"Empty bundle?");
147 for (
auto MII = FirstMI; MII != LastMI; ++MII) {
149 if (MII->isDebugInstr())
152 for (
unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
165 if (LocalDefSet.
count(Reg)) {
171 if (ExternUseSet.
insert(Reg).second) {
182 for (
unsigned i = 0, e = Defs.
size(); i != e; ++i) {
188 if (LocalDefSet.
insert(Reg).second) {
195 KilledDefSet.
erase(Reg);
198 DeadDefSet.
erase(Reg);
201 if (!MO.
isDead() && Reg.isPhysical()) {
203 unsigned SubReg = *SubRegs;
214 for (
unsigned i = 0, e = LocalDefs.
size(); i != e; ++i) {
216 if (Added.insert(Reg).second) {
218 bool isDead = DeadDefSet.
count(Reg) || KilledDefSet.
count(Reg);
224 for (
unsigned i = 0, e = ExternUses.
size(); i != e; ++i) {
226 bool isKill = KilledUseSet.
count(Reg);
234 for (
auto MII = FirstMI; MII != LastMI; ++MII) {
252 while (LastMI !=
E && LastMI->isInsideBundle())
261 bool Changed =
false;
267 assert(!MII->isInsideBundle() &&
268 "First instr cannot be inside bundle before finalization!");
270 for (++MII; MII != MIE; ) {
271 if (!MII->isInsideBundle())
294 Ops->push_back(std::make_pair(MO.
getParent(), O.getOperandNo()));
315 bool AllDefsDead =
true;
316 PhysRegInfo PRI = {
false,
false,
false,
false,
false,
false,
false,
false};
318 assert(Reg.isPhysical() &&
"analyzePhysReg not given a physical register!");
334 if (!
TRI->regsOverlap(MOReg, Reg))
337 bool Covered =
TRI->isSuperRegisterEq(Reg, MOReg);
345 }
else if (MO.
isDef()) {
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const HexagonInstrInfo * TII
static bool isUndef(ArrayRef< int > Mask)
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
This file defines the SmallVector class.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
FunctionPass class - This class is used to implement most global optimizations.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
MCSubRegIterator enumerates all sub-registers of Reg.
Helper class for constructing bundles of MachineInstrs.
MIBundleBuilder & prepend(MachineInstr *MI)
Insert MI into MBB by prepending it to the instructions in the bundle.
MIBundleOperands - Iterate over all operands in a bundle of machine instructions.
instr_iterator instr_begin()
Instructions::iterator instr_iterator
instr_iterator instr_end()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
MachineOperand class - Representation of each machine instruction operand.
void setIsInternalRead(bool Val=true)
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
char & FinalizeMachineBundlesID
FinalizeMachineBundles - This pass finalize machine instruction bundles (created earlier,...
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool finalizeBundles(MachineFunction &MF)
finalizeBundles - Finalize instruction bundles in the specified MachineFunction.
PhysRegInfo AnalyzePhysRegInBundle(const MachineInstr &MI, Register Reg, const TargetRegisterInfo *TRI)
AnalyzePhysRegInBundle - Analyze how the current instruction or bundle uses a physical register.
unsigned getDeadRegState(bool B)
void initializeFinalizeMachineBundlesPass(PassRegistry &)
void initializeUnpackMachineBundlesPass(PassRegistry &)
unsigned getImplRegState(bool B)
VirtRegInfo AnalyzeVirtRegInBundle(MachineInstr &MI, Register Reg, SmallVectorImpl< std::pair< MachineInstr *, unsigned > > *Ops=nullptr)
AnalyzeVirtRegInBundle - Analyze how the current instruction or bundle uses a virtual register.
unsigned getUndefRegState(bool B)
unsigned getDefRegState(bool B)
unsigned getKillRegState(bool B)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
char & UnpackMachineBundlesID
UnpackMachineBundles - This pass unpack machine instruction bundles.
Information about how a physical register Reg is used by a set of operands.
bool Read
Reg or one of its aliases is read.
bool Defined
Reg or one of its aliases is defined.
bool Killed
There is a use operand of reg or a super-register with kill flag set.
bool PartialDeadDef
Reg is Defined and all defs of reg or an overlapping register are dead.
bool Clobbered
There is a regmask operand indicating Reg is clobbered.
bool FullyRead
Reg or a super-register is read. The full register is read.
bool FullyDefined
Reg or a super-register is defined.
VirtRegInfo - Information about a virtual register used by a set of operands.
bool Reads
Reads - One of the operands read the virtual register.
bool Tied
Tied - Uses and defs must use the same register.
bool Writes
Writes - One of the operands writes the virtual register.