LLVM  14.0.0git
MachineInstrBuilder.h
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1 //===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file exposes a function named BuildMI, which is useful for dramatically
10 // simplifying how MachineInstr's are created. It allows use of code like this:
11 //
12 // M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst)
13 // .addReg(argVal1)
14 // .addReg(argVal2);
15 //
16 //===----------------------------------------------------------------------===//
17 
18 #ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
19 #define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
20 
21 #include "llvm/ADT/ArrayRef.h"
29 #include "llvm/IR/InstrTypes.h"
30 #include "llvm/IR/Intrinsics.h"
32 #include <cassert>
33 #include <cstdint>
34 
35 namespace llvm {
36 
37 class MCInstrDesc;
38 class MDNode;
39 
40 namespace RegState {
41 
42 enum {
43  /// Register definition.
44  Define = 0x2,
45  /// Not emitted register (e.g. carry, or temporary result).
46  Implicit = 0x4,
47  /// The last use of a register.
48  Kill = 0x8,
49  /// Unused definition.
50  Dead = 0x10,
51  /// Value of the register doesn't matter.
52  Undef = 0x20,
53  /// Register definition happens before uses.
54  EarlyClobber = 0x40,
55  /// Register 'use' is for debugging purpose.
56  Debug = 0x80,
57  /// Register reads a value that is defined inside the same instruction or
58  /// bundle.
59  InternalRead = 0x100,
60  /// Register that may be renamed.
61  Renamable = 0x200,
65 };
66 
67 } // end namespace RegState
68 
70  MachineFunction *MF = nullptr;
71  MachineInstr *MI = nullptr;
72 
73 public:
74  MachineInstrBuilder() = default;
75 
76  /// Create a MachineInstrBuilder for manipulating an existing instruction.
77  /// F must be the machine function that was used to allocate I.
80  : MF(&F), MI(&*I) {}
81 
82  /// Allow automatic conversion to the machine instruction we are working on.
83  operator MachineInstr*() const { return MI; }
84  MachineInstr *operator->() const { return MI; }
85  operator MachineBasicBlock::iterator() const { return MI; }
86 
87  /// If conversion operators fail, use this method to get the MachineInstr
88  /// explicitly.
89  MachineInstr *getInstr() const { return MI; }
90 
91  /// Get the register for the operand index.
92  /// The operand at the index should be a register (asserted by
93  /// MachineOperand).
94  Register getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); }
95 
96  /// Add a new virtual register operand.
97  const MachineInstrBuilder &addReg(Register RegNo, unsigned flags = 0,
98  unsigned SubReg = 0) const {
99  assert((flags & 0x1) == 0 &&
100  "Passing in 'true' to addReg is forbidden! Use enums instead.");
101  MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
102  flags & RegState::Define,
103  flags & RegState::Implicit,
104  flags & RegState::Kill,
105  flags & RegState::Dead,
106  flags & RegState::Undef,
107  flags & RegState::EarlyClobber,
108  SubReg,
109  flags & RegState::Debug,
110  flags & RegState::InternalRead,
111  flags & RegState::Renamable));
112  return *this;
113  }
114 
115  /// Add a virtual register definition operand.
116  const MachineInstrBuilder &addDef(Register RegNo, unsigned Flags = 0,
117  unsigned SubReg = 0) const {
118  return addReg(RegNo, Flags | RegState::Define, SubReg);
119  }
120 
121  /// Add a virtual register use operand. It is an error for Flags to contain
122  /// `RegState::Define` when calling this function.
123  const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0,
124  unsigned SubReg = 0) const {
125  assert(!(Flags & RegState::Define) &&
126  "Misleading addUse defines register, use addReg instead.");
127  return addReg(RegNo, Flags, SubReg);
128  }
129 
130  /// Add a new immediate operand.
131  const MachineInstrBuilder &addImm(int64_t Val) const {
132  MI->addOperand(*MF, MachineOperand::CreateImm(Val));
133  return *this;
134  }
135 
136  const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
137  MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
138  return *this;
139  }
140 
141  const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
142  MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
143  return *this;
144  }
145 
147  unsigned TargetFlags = 0) const {
148  MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
149  return *this;
150  }
151 
152  const MachineInstrBuilder &addFrameIndex(int Idx) const {
153  MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
154  return *this;
155  }
156 
157  const MachineInstrBuilder &
158  addConstantPoolIndex(unsigned Idx, int Offset = 0,
159  unsigned TargetFlags = 0) const {
160  MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
161  return *this;
162  }
163 
164  const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0,
165  unsigned TargetFlags = 0) const {
166  MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
167  TargetFlags));
168  return *this;
169  }
170 
172  unsigned TargetFlags = 0) const {
173  MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
174  return *this;
175  }
176 
178  int64_t Offset = 0,
179  unsigned TargetFlags = 0) const {
180  MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
181  return *this;
182  }
183 
184  const MachineInstrBuilder &addExternalSymbol(const char *FnName,
185  unsigned TargetFlags = 0) const {
186  MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags));
187  return *this;
188  }
189 
191  int64_t Offset = 0,
192  unsigned TargetFlags = 0) const {
193  MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags));
194  return *this;
195  }
196 
198  MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask));
199  return *this;
200  }
201 
203  MI->addMemOperand(*MF, MMO);
204  return *this;
205  }
206 
207  const MachineInstrBuilder &
209  MI->setMemRefs(*MF, MMOs);
210  return *this;
211  }
212 
213  const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const {
214  MI->cloneMemRefs(*MF, OtherMI);
215  return *this;
216  }
217 
218  const MachineInstrBuilder &
220  MI->cloneMergedMemRefs(*MF, OtherMIs);
221  return *this;
222  }
223 
224  const MachineInstrBuilder &add(const MachineOperand &MO) const {
225  MI->addOperand(*MF, MO);
226  return *this;
227  }
228 
230  for (const MachineOperand &MO : MOs) {
231  MI->addOperand(*MF, MO);
232  }
233  return *this;
234  }
235 
236  const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
237  MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
238  assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())
239  : true) &&
240  "first MDNode argument of a DBG_VALUE not a variable");
241  assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())
242  : true) &&
243  "first MDNode argument of a DBG_LABEL not a label");
244  return *this;
245  }
246 
247  const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
248  MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));
249  return *this;
250  }
251 
253  MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID));
254  return *this;
255  }
256 
258  MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred));
259  return *this;
260  }
261 
263  MI->addOperand(*MF, MachineOperand::CreateShuffleMask(Val));
264  return *this;
265  }
266 
268  unsigned char TargetFlags = 0) const {
269  MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags));
270  return *this;
271  }
272 
273  const MachineInstrBuilder &setMIFlags(unsigned Flags) const {
274  MI->setFlags(Flags);
275  return *this;
276  }
277 
279  MI->setFlag(Flag);
280  return *this;
281  }
282 
283  // Add a displacement from an existing MachineOperand with an added offset.
284  const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
285  unsigned char TargetFlags = 0) const {
286  // If caller specifies new TargetFlags then use it, otherwise the
287  // default behavior is to copy the target flags from the existing
288  // MachineOperand. This means if the caller wants to clear the
289  // target flags it needs to do so explicitly.
290  if (0 == TargetFlags)
291  TargetFlags = Disp.getTargetFlags();
292 
293  switch (Disp.getType()) {
294  default:
295  llvm_unreachable("Unhandled operand type in addDisp()");
297  return addImm(Disp.getImm() + off);
299  return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off,
300  TargetFlags);
302  return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
303  TargetFlags);
305  return addBlockAddress(Disp.getBlockAddress(), Disp.getOffset() + off,
306  TargetFlags);
308  assert(off == 0 && "cannot create offset into jump tables");
309  return addJumpTableIndex(Disp.getIndex(), TargetFlags);
310  }
311  }
312 
313  /// Copy all the implicit operands from OtherMI onto this one.
314  const MachineInstrBuilder &
315  copyImplicitOps(const MachineInstr &OtherMI) const {
316  MI->copyImplicitOps(*MF, OtherMI);
317  return *this;
318  }
319 
321  const TargetRegisterInfo &TRI,
322  const RegisterBankInfo &RBI) const {
323  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
324  }
325 };
326 
327 /// Builder interface. Specify how to create the initial instruction itself.
329  const MCInstrDesc &MCID) {
330  return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
331 }
332 
333 /// This version of the builder sets up the first operand as a
334 /// destination virtual register.
336  const MCInstrDesc &MCID, Register DestReg) {
337  return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
338  .addReg(DestReg, RegState::Define);
339 }
340 
341 /// This version of the builder inserts the newly-built instruction before
342 /// the given position in the given MachineBasicBlock, and sets up the first
343 /// operand as a destination virtual register.
346  const DebugLoc &DL, const MCInstrDesc &MCID,
347  Register DestReg) {
348  MachineFunction &MF = *BB.getParent();
349  MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
350  BB.insert(I, MI);
351  return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
352 }
353 
354 /// This version of the builder inserts the newly-built instruction before
355 /// the given position in the given MachineBasicBlock, and sets up the first
356 /// operand as a destination virtual register.
357 ///
358 /// If \c I is inside a bundle, then the newly inserted \a MachineInstr is
359 /// added to the same bundle.
362  const DebugLoc &DL, const MCInstrDesc &MCID,
363  Register DestReg) {
364  MachineFunction &MF = *BB.getParent();
365  MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
366  BB.insert(I, MI);
367  return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
368 }
369 
371  const DebugLoc &DL, const MCInstrDesc &MCID,
372  Register DestReg) {
373  // Calling the overload for instr_iterator is always correct. However, the
374  // definition is not available in headers, so inline the check.
375  if (I.isInsideBundle())
376  return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg);
377  return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg);
378 }
379 
381  const DebugLoc &DL, const MCInstrDesc &MCID,
382  Register DestReg) {
383  return BuildMI(BB, *I, DL, MCID, DestReg);
384 }
385 
386 /// This version of the builder inserts the newly-built instruction before the
387 /// given position in the given MachineBasicBlock, and does NOT take a
388 /// destination register.
391  const DebugLoc &DL,
392  const MCInstrDesc &MCID) {
393  MachineFunction &MF = *BB.getParent();
394  MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
395  BB.insert(I, MI);
396  return MachineInstrBuilder(MF, MI);
397 }
398 
401  const DebugLoc &DL,
402  const MCInstrDesc &MCID) {
403  MachineFunction &MF = *BB.getParent();
404  MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
405  BB.insert(I, MI);
406  return MachineInstrBuilder(MF, MI);
407 }
408 
410  const DebugLoc &DL,
411  const MCInstrDesc &MCID) {
412  // Calling the overload for instr_iterator is always correct. However, the
413  // definition is not available in headers, so inline the check.
414  if (I.isInsideBundle())
416  return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID);
417 }
418 
420  const DebugLoc &DL,
421  const MCInstrDesc &MCID) {
422  return BuildMI(BB, *I, DL, MCID);
423 }
424 
425 /// This version of the builder inserts the newly-built instruction at the end
426 /// of the given MachineBasicBlock, and does NOT take a destination register.
428  const MCInstrDesc &MCID) {
429  return BuildMI(*BB, BB->end(), DL, MCID);
430 }
431 
432 /// This version of the builder inserts the newly-built instruction at the
433 /// end of the given MachineBasicBlock, and sets up the first operand as a
434 /// destination virtual register.
436  const MCInstrDesc &MCID, Register DestReg) {
437  return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
438 }
439 
440 /// This version of the builder builds a DBG_VALUE intrinsic
441 /// for either a value in a register or a register-indirect
442 /// address. The convention is that a DBG_VALUE is indirect iff the
443 /// second operand is an immediate.
444 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
445  const MCInstrDesc &MCID, bool IsIndirect,
446  Register Reg, const MDNode *Variable,
447  const MDNode *Expr);
448 
449 /// This version of the builder builds a DBG_VALUE intrinsic
450 /// for a MachineOperand.
451 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
452  const MCInstrDesc &MCID, bool IsIndirect,
453  const MachineOperand &MO, const MDNode *Variable,
454  const MDNode *Expr);
455 
456 /// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
457 /// for a MachineOperand.
458 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
459  const MCInstrDesc &MCID, bool IsIndirect,
460  ArrayRef<MachineOperand> MOs,
461  const MDNode *Variable, const MDNode *Expr);
462 
463 /// This version of the builder builds a DBG_VALUE intrinsic
464 /// for either a value in a register or a register-indirect
465 /// address and inserts it at position I.
466 MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
467  MachineBasicBlock::iterator I, const DebugLoc &DL,
468  const MCInstrDesc &MCID, bool IsIndirect,
469  Register Reg, const MDNode *Variable,
470  const MDNode *Expr);
471 
472 /// This version of the builder builds a DBG_VALUE intrinsic
473 /// for a machine operand and inserts it at position I.
474 MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
475  MachineBasicBlock::iterator I, const DebugLoc &DL,
476  const MCInstrDesc &MCID, bool IsIndirect,
477  MachineOperand &MO, const MDNode *Variable,
478  const MDNode *Expr);
479 
480 /// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
481 /// for a machine operand and inserts it at position I.
482 MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
483  MachineBasicBlock::iterator I, const DebugLoc &DL,
484  const MCInstrDesc &MCID, bool IsIndirect,
485  ArrayRef<MachineOperand> MOs,
486  const MDNode *Variable, const MDNode *Expr);
487 
488 /// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
489 MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
491  const MachineInstr &Orig, int FrameIndex,
492  Register SpillReg);
493 MachineInstr *
495  const MachineInstr &Orig, int FrameIndex,
496  SmallVectorImpl<const MachineOperand *> &SpilledOperands);
497 
498 /// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when
499 /// modifying an instruction in place while iterating over a basic block.
500 void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg);
501 
502 inline unsigned getDefRegState(bool B) {
503  return B ? RegState::Define : 0;
504 }
505 inline unsigned getImplRegState(bool B) {
506  return B ? RegState::Implicit : 0;
507 }
508 inline unsigned getKillRegState(bool B) {
509  return B ? RegState::Kill : 0;
510 }
511 inline unsigned getDeadRegState(bool B) {
512  return B ? RegState::Dead : 0;
513 }
514 inline unsigned getUndefRegState(bool B) {
515  return B ? RegState::Undef : 0;
516 }
517 inline unsigned getInternalReadRegState(bool B) {
518  return B ? RegState::InternalRead : 0;
519 }
520 inline unsigned getDebugRegState(bool B) {
521  return B ? RegState::Debug : 0;
522 }
523 inline unsigned getRenamableRegState(bool B) {
524  return B ? RegState::Renamable : 0;
525 }
526 
527 /// Get all register state flags from machine operand \p RegOp.
528 inline unsigned getRegState(const MachineOperand &RegOp) {
529  assert(RegOp.isReg() && "Not a register operand");
530  return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) |
531  getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) |
532  getUndefRegState(RegOp.isUndef()) |
534  getDebugRegState(RegOp.isDebug()) |
536  RegOp.isRenamable());
537 }
538 
539 /// Helper class for constructing bundles of MachineInstrs.
540 ///
541 /// MIBundleBuilder can create a bundle from scratch by inserting new
542 /// MachineInstrs one at a time, or it can create a bundle from a sequence of
543 /// existing MachineInstrs in a basic block.
545  MachineBasicBlock &MBB;
548 
549 public:
550  /// Create an MIBundleBuilder that inserts instructions into a new bundle in
551  /// BB above the bundle or instruction at Pos.
553  : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {}
554 
555  /// Create a bundle from the sequence of instructions between B and E.
558  : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) {
559  assert(B != E && "No instructions to bundle");
560  ++B;
561  while (B != E) {
562  MachineInstr &MI = *B;
563  ++B;
564  MI.bundleWithPred();
565  }
566  }
567 
568  /// Create an MIBundleBuilder representing an existing instruction or bundle
569  /// that has MI as its head.
571  : MBB(*MI->getParent()), Begin(MI),
572  End(getBundleEnd(MI->getIterator())) {}
573 
574  /// Return a reference to the basic block containing this bundle.
575  MachineBasicBlock &getMBB() const { return MBB; }
576 
577  /// Return true if no instructions have been inserted in this bundle yet.
578  /// Empty bundles aren't representable in a MachineBasicBlock.
579  bool empty() const { return Begin == End; }
580 
581  /// Return an iterator to the first bundled instruction.
582  MachineBasicBlock::instr_iterator begin() const { return Begin; }
583 
584  /// Return an iterator beyond the last bundled instruction.
585  MachineBasicBlock::instr_iterator end() const { return End; }
586 
587  /// Insert MI into this bundle before I which must point to an instruction in
588  /// the bundle, or end().
590  MachineInstr *MI) {
591  MBB.insert(I, MI);
592  if (I == Begin) {
593  if (!empty())
594  MI->bundleWithSucc();
595  Begin = MI->getIterator();
596  return *this;
597  }
598  if (I == End) {
599  MI->bundleWithPred();
600  return *this;
601  }
602  // MI was inserted in the middle of the bundle, so its neighbors' flags are
603  // already fine. Update MI's bundle flags manually.
604  MI->setFlag(MachineInstr::BundledPred);
605  MI->setFlag(MachineInstr::BundledSucc);
606  return *this;
607  }
608 
609  /// Insert MI into MBB by prepending it to the instructions in the bundle.
610  /// MI will become the first instruction in the bundle.
612  return insert(begin(), MI);
613  }
614 
615  /// Insert MI into MBB by appending it to the instructions in the bundle.
616  /// MI will become the last instruction in the bundle.
618  return insert(end(), MI);
619  }
620 };
621 
622 } // end namespace llvm
623 
624 #endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H
llvm::MachineInstrBuilder::operator->
MachineInstr * operator->() const
Definition: MachineInstrBuilder.h:84
llvm::MachineOperand::CreateCPI
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:828
llvm::MachineOperand::CreateJTI
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
Definition: MachineOperand.h:844
llvm::MachineInstrBuilder::addCImm
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
Definition: MachineInstrBuilder.h:136
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:63
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
MachineInstr.h
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::MachineInstrBuilder::copyImplicitOps
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
Definition: MachineInstrBuilder.h:315
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MachineInstrBuilder::addFPImm
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Definition: MachineInstrBuilder.h:141
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
llvm::MIBundleBuilder::begin
MachineBasicBlock::instr_iterator begin() const
Return an iterator to the first bundled instruction.
Definition: MachineInstrBuilder.h:582
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:563
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::MIBundleBuilder::end
MachineBasicBlock::instr_iterator end() const
Return an iterator beyond the last bundled instruction.
Definition: MachineInstrBuilder.h:585
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:568
llvm::MIBundleBuilder::MIBundleBuilder
MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B, MachineBasicBlock::iterator E)
Create a bundle from the sequence of instructions between B and E.
Definition: MachineInstrBuilder.h:556
ErrorHandling.h
MachineBasicBlock.h
llvm::MIBundleBuilder::MIBundleBuilder
MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos)
Create an MIBundleBuilder that inserts instructions into a new bundle in BB above the bundle or instr...
Definition: MachineInstrBuilder.h:552
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::MachineOperand::CreateMetadata
static MachineOperand CreateMetadata(const MDNode *Meta)
Definition: MachineOperand.h:898
llvm::MachineOperand::CreateCFIIndex
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
Definition: MachineOperand.h:913
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::getDeadRegState
unsigned getDeadRegState(bool B)
Definition: MachineInstrBuilder.h:511
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:600
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:135
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::getUndefRegState
unsigned getUndefRegState(bool B)
Definition: MachineInstrBuilder.h:514
llvm::MachineOperand::CreateES
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
Definition: MachineOperand.h:858
llvm::getBundleEnd
MachineBasicBlock::instr_iterator getBundleEnd(MachineBasicBlock::instr_iterator I)
Returns an iterator pointing beyond the bundle containing I.
Definition: MachineInstrBundle.h:60
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:118
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:502
llvm::MIBundleBuilder::insert
MIBundleBuilder & insert(MachineBasicBlock::instr_iterator I, MachineInstr *MI)
Insert MI into this bundle before I which must point to an instruction in the bundle,...
Definition: MachineInstrBuilder.h:589
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::getRenamableRegState
unsigned getRenamableRegState(bool B)
Definition: MachineInstrBuilder.h:523
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MIBundleBuilder::getMBB
MachineBasicBlock & getMBB() const
Return a reference to the basic block containing this bundle.
Definition: MachineInstrBuilder.h:575
llvm::RegState::Renamable
@ Renamable
Register that may be renamed.
Definition: MachineInstrBuilder.h:61
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:773
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:62
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
Intrinsics.h
llvm::buildDbgValueForSpill
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2228
InstrTypes.h
llvm::RegState::Debug
@ Debug
Register 'use' is for debugging purpose.
Definition: MachineInstrBuilder.h:56
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
Utils.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
MachineInstrBundle.h
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::MachineOperand::CreateFI
static MachineOperand CreateFI(int Idx)
Definition: MachineOperand.h:823
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
llvm::MachineOperand::CreateShuffleMask
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
Definition: MachineOperand.h:931
llvm::getRegState
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
Definition: MachineInstrBuilder.h:528
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:221
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineOperand::CreateMBB
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
Definition: MachineOperand.h:816
llvm::MachineInstrBuilder::addShuffleMask
const MachineInstrBuilder & addShuffleMask(ArrayRef< int > Val) const
Definition: MachineInstrBuilder.h:262
llvm::updateDbgValueForSpill
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
Definition: MachineInstr.cpp:2271
llvm::MIBundleBuilder::empty
bool empty() const
Return true if no instructions have been inserted in this bundle yet.
Definition: MachineInstrBuilder.h:579
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:385
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MachineInstrBuilder::addDisp
const MachineInstrBuilder & addDisp(const MachineOperand &Disp, int64_t off, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:284
ArrayRef.h
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:219
llvm::MachineInstrBuilder::addIntrinsicID
const MachineInstrBuilder & addIntrinsicID(Intrinsic::ID ID) const
Definition: MachineInstrBuilder.h:252
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MachineOperand::CreateBA
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:866
llvm::MachineInstrBuilder::MachineInstrBuilder
MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I)
Definition: MachineInstrBuilder.h:79
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MDNode
Metadata node.
Definition: Metadata.h:906
llvm::MachineOperand::CreateMCSymbol
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
Definition: MachineOperand.h:904
llvm::RegState::InternalRead
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
Definition: MachineInstrBuilder.h:59
llvm::MachineInstrBuilder::constrainAllUses
bool constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Definition: MachineInstrBuilder.h:320
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:80
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineOperand::MO_JumpTableIndex
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
Definition: MachineOperand.h:60
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:848
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::MachineOperand::CreateIntrinsicID
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
Definition: MachineOperand.h:919
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(ArrayRef< MachineOperand > MOs) const
Definition: MachineInstrBuilder.h:229
llvm::MachineOperand::CreateGA
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:850
llvm::RegState::EarlyClobber
@ EarlyClobber
Register definition happens before uses.
Definition: MachineInstrBuilder.h:54
llvm::MachineInstrBuilder::addJumpTableIndex
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:171
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:776
uint32_t
llvm::RegState::DefineNoRead
@ DefineNoRead
Definition: MachineInstrBuilder.h:62
llvm::MIBundleBuilder
Helper class for constructing bundles of MachineInstrs.
Definition: MachineInstrBuilder.h:544
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RegState::ImplicitKill
@ ImplicitKill
Definition: MachineInstrBuilder.h:64
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::MachineInstrBuilder::addPredicate
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
Definition: MachineInstrBuilder.h:257
llvm::MachineInstrBuilder::addBlockAddress
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:190
llvm::MachineOperand::CreateCImm
static MachineOperand CreateCImm(const ConstantInt *CI)
Definition: MachineOperand.h:779
llvm::MachineInstrBuilder::cloneMergedMemRefs
const MachineInstrBuilder & cloneMergedMemRefs(ArrayRef< const MachineInstr * > OtherMIs) const
Definition: MachineInstrBuilder.h:219
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MIBundleBuilder::prepend
MIBundleBuilder & prepend(MachineInstr *MI)
Insert MI into MBB by prepending it to the instructions in the bundle.
Definition: MachineInstrBuilder.h:611
llvm::getDebugRegState
unsigned getDebugRegState(bool B)
Definition: MachineInstrBuilder.h:520
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:557
llvm::MachineInstrBuilder::addConstantPoolIndex
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:158
llvm::MachineBasicBlock::instr_iterator
Instructions::iterator instr_iterator
Definition: MachineBasicBlock.h:228
llvm::MIBundleBuilder::MIBundleBuilder
MIBundleBuilder(MachineInstr *MI)
Create an MIBundleBuilder representing an existing instruction or bundle that has MI as its head.
Definition: MachineInstrBuilder.h:570
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition: MachineInstrBuilder.h:208
llvm::MachineInstrBuilder::addTargetIndex
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:164
llvm::MIBundleBuilder::append
MIBundleBuilder & append(MachineInstr *MI)
Insert MI into MBB by appending it to the instructions in the bundle.
Definition: MachineInstrBuilder.h:617
llvm::MachineOperand::isDebug
bool isDebug() const
Definition: MachineOperand.h:446
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:177
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:267
llvm::MachineOperand::CreateRegMask
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
Definition: MachineOperand.h:886
llvm::MachineInstrBuilder::setMIFlags
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Definition: MachineInstrBuilder.h:273
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineInstr::BundledSucc
@ BundledSucc
Definition: MachineInstr.h:87
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::MachineInstrBuilder::MachineInstrBuilder
MachineInstrBuilder()=default
llvm::MachineOperand::isInternalRead
bool isInternalRead() const
Definition: MachineOperand.h:431
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
MachineOperand.h
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::MachineFunction::CreateMachineInstr
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
Definition: MachineFunction.cpp:348
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::getInternalReadRegState
unsigned getInternalReadRegState(bool B)
Definition: MachineInstrBuilder.h:517
MachineFunction.h
llvm::MachineInstr::BundledPred
@ BundledPred
Definition: MachineInstr.h:86
llvm::MachineInstrBuilder::MachineInstrBuilder
MachineInstrBuilder(MachineFunction &F, MachineInstr *I)
Create a MachineInstrBuilder for manipulating an existing instruction.
Definition: MachineInstrBuilder.h:78
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::getImplRegState
unsigned getImplRegState(bool B)
Definition: MachineInstrBuilder.h:505
llvm::MachineOperand::CreatePredicate
static MachineOperand CreatePredicate(unsigned Pred)
Definition: MachineOperand.h:925
TargetRegisterInfo.h
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::MachineOperand::CreateFPImm
static MachineOperand CreateFPImm(const ConstantFP *CFP)
Definition: MachineOperand.h:785
llvm::MachineOperand::CreateTargetIndex
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:836
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:58