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18 #ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
19 #define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
98 unsigned SubReg = 0)
const {
99 assert((flags & 0x1) == 0 &&
100 "Passing in 'true' to addReg is forbidden! Use enums instead.");
117 unsigned SubReg = 0)
const {
124 unsigned SubReg = 0)
const {
126 "Misleading addUse defines register, use addReg instead.");
147 unsigned TargetFlags = 0)
const {
159 unsigned TargetFlags = 0)
const {
165 unsigned TargetFlags = 0)
const {
172 unsigned TargetFlags = 0)
const {
179 unsigned TargetFlags = 0)
const {
185 unsigned TargetFlags = 0)
const {
192 unsigned TargetFlags = 0)
const {
203 MI->addMemOperand(*MF, MMO);
209 MI->setMemRefs(*MF, MMOs);
214 MI->cloneMemRefs(*MF, OtherMI);
220 MI->cloneMergedMemRefs(*MF, OtherMIs);
225 MI->addOperand(*MF, MO);
231 MI->addOperand(*MF, MO);
238 assert((
MI->isDebugValueLike() ?
static_cast<bool>(
MI->getDebugVariable())
240 "first MDNode argument of a DBG_VALUE not a variable");
241 assert((
MI->isDebugLabel() ?
static_cast<bool>(
MI->getDebugLabel())
243 "first MDNode argument of a DBG_LABEL not a label");
268 unsigned char TargetFlags = 0)
const {
285 unsigned char TargetFlags = 0)
const {
290 if (0 == TargetFlags)
308 assert(off == 0 &&
"cannot create offset into jump tables");
315 MI->setPCSections(*MF, MD);
322 MI->copyImplicitOps(*MF, OtherMI);
341 : DL(DI), PCSections(PCSections) {}
353 MDNode *PCSections =
nullptr;
410 if (
I.isInsideBundle())
450 if (
I.isInsideBundle())
475 return BuildMI(*
BB,
BB->end(), MIMD, MCID, DestReg);
482 MachineInstrBuilder
BuildMI(MachineFunction &MF,
const DebugLoc &
DL,
483 const MCInstrDesc &MCID,
bool IsIndirect,
484 Register
Reg,
const MDNode *Variable,
489 MachineInstrBuilder
BuildMI(MachineFunction &MF,
const DebugLoc &
DL,
490 const MCInstrDesc &MCID,
bool IsIndirect,
491 ArrayRef<MachineOperand> MOs,
492 const MDNode *Variable,
const MDNode *Expr);
497 MachineInstrBuilder
BuildMI(MachineBasicBlock &
BB,
499 const MCInstrDesc &MCID,
bool IsIndirect,
500 Register
Reg,
const MDNode *Variable,
505 MachineInstrBuilder
BuildMI(MachineBasicBlock &
BB,
507 const MCInstrDesc &MCID,
bool IsIndirect,
508 ArrayRef<MachineOperand> MOs,
509 const MDNode *Variable,
const MDNode *Expr);
519 SmallVectorImpl<const MachineOperand *> &SpilledOperands);
576 :
MBB(
BB), Begin(Pos.getInstrIterator()), End(Begin) {}
581 :
MBB(
BB), Begin(
B.getInstrIterator()), End(
E.getInstrIterator()) {
582 assert(
B !=
E &&
"No instructions to bundle");
602 bool empty()
const {
return Begin == End; }
617 MI->bundleWithSucc();
618 Begin =
MI->getIterator();
622 MI->bundleWithPred();
647 #endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H
MachineInstr * operator->() const
@ Undef
Value of the register doesn't matter.
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
@ MO_BlockAddress
Address of a basic block.
@ MO_Immediate
Immediate operand.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineBasicBlock::instr_iterator begin() const
Return an iterator to the first bundled instruction.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
const GlobalValue * getGlobal() const
const MachineInstrBuilder & add(const MachineOperand &MO) const
MachineBasicBlock::instr_iterator end() const
Return an iterator beyond the last bundled instruction.
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const BlockAddress * getBlockAddress() const
MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B, MachineBasicBlock::iterator E)
Create a bundle from the sequence of instructions between B and E.
Reg
All possible values of the reg field in the ModR/M byte.
MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos)
Create an MIBundleBuilder that inserts instructions into a new bundle in BB above the bundle or instr...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
static MachineOperand CreateMetadata(const MDNode *Meta)
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
A description of a memory reference used in the backend.
unsigned getDeadRegState(bool B)
int64_t getOffset() const
Return the offset from the symbol in this operand.
unsigned const TargetRegisterInfo * TRI
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
unsigned getUndefRegState(bool B)
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
MachineBasicBlock::instr_iterator getBundleEnd(MachineBasicBlock::instr_iterator I)
Returns an iterator pointing beyond the bundle containing I.
@ Debug
Register 'use' is for debugging purpose.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
This is the shared class of boolean and integer constants.
unsigned getDefRegState(bool B)
MIBundleBuilder & insert(MachineBasicBlock::instr_iterator I, MachineInstr *MI)
Insert MI into this bundle before I which must point to an instruction in the bundle,...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getRenamableRegState(bool B)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
MachineBasicBlock & getMBB() const
Return a reference to the basic block containing this bundle.
static MachineOperand CreateImm(int64_t Val)
@ MO_GlobalAddress
Address of a global value.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
@ Renamable
Register that may be renamed.
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
ConstantFP - Floating Point Values [float, double].
static MachineOperand CreateFI(int Idx)
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
Holds all the information related to register banks.
unsigned getTargetFlags() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
const MachineInstrBuilder & addShuffleMask(ArrayRef< int > Val) const
@ EarlyClobber
Register definition happens before uses.
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
bool empty() const
Return true if no instructions have been inserted in this bundle yet.
This is an important class for using LLVM in a threaded context.
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
const MachineInstrBuilder & addDisp(const MachineOperand &Disp, int64_t off, unsigned char TargetFlags=0) const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const MachineInstrBuilder & addIntrinsicID(Intrinsic::ID ID) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I)
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
bool constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
The address of a basic block.
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
MachineInstrBundleIterator< MachineInstr > iterator
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
const MachineInstrBuilder & add(ArrayRef< MachineOperand > MOs) const
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const Function * getParent(const Value *V)
Helper class for constructing bundles of MachineInstrs.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
static MachineOperand CreateCImm(const ConstantInt *CI)
const MachineInstrBuilder & cloneMergedMemRefs(ArrayRef< const MachineInstr * > OtherMIs) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Wrapper class representing virtual and physical registers.
MIBundleBuilder & prepend(MachineInstr *MI)
Insert MI into MBB by prepending it to the instructions in the bundle.
unsigned getDebugRegState(bool B)
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Instructions::iterator instr_iterator
MIBundleBuilder(MachineInstr *MI)
Create an MIBundleBuilder representing an existing instruction or bundle that has MI as its head.
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned TargetFlags=0) const
MIBundleBuilder & append(MachineInstr *MI)
Insert MI into MBB by appending it to the instructions in the bundle.
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
@ Kill
The last use of a register.
unsigned getKillRegState(bool B)
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
MachineInstrBuilder()=default
bool isInternalRead() const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
const MachineInstrBuilder & setPCSections(MDNode *MD) const
BlockVerifier::State From
unsigned getInternalReadRegState(bool B)
MachineInstrBuilder(MachineFunction &F, MachineInstr *I)
Create a MachineInstrBuilder for manipulating an existing instruction.
unsigned getImplRegState(bool B)
@ Define
Register definition.
static MachineOperand CreatePredicate(unsigned Pred)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.