LLVM 17.0.0git
Utils.cpp
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1//===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file This file implements the utility functions used by the GlobalISel
9/// pipeline.
10//===----------------------------------------------------------------------===//
11
13#include "llvm/ADT/APFloat.h"
14#include "llvm/ADT/APInt.h"
32#include "llvm/IR/Constants.h"
35#include <numeric>
36#include <optional>
37
38#define DEBUG_TYPE "globalisel-utils"
39
40using namespace llvm;
41using namespace MIPatternMatch;
42
44 const TargetInstrInfo &TII,
45 const RegisterBankInfo &RBI, Register Reg,
46 const TargetRegisterClass &RegClass) {
47 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
48 return MRI.createVirtualRegister(&RegClass);
49
50 return Reg;
51}
52
54 const MachineFunction &MF, const TargetRegisterInfo &TRI,
56 const RegisterBankInfo &RBI, MachineInstr &InsertPt,
57 const TargetRegisterClass &RegClass, MachineOperand &RegMO) {
58 Register Reg = RegMO.getReg();
59 // Assume physical registers are properly constrained.
60 assert(Reg.isVirtual() && "PhysReg not implemented");
61
62 // Save the old register class to check whether
63 // the change notifications will be required.
64 // TODO: A better approach would be to pass
65 // the observers to constrainRegToClass().
66 auto *OldRegClass = MRI.getRegClassOrNull(Reg);
67 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
68 // If we created a new virtual register because the class is not compatible
69 // then create a copy between the new and the old register.
70 if (ConstrainedReg != Reg) {
71 MachineBasicBlock::iterator InsertIt(&InsertPt);
72 MachineBasicBlock &MBB = *InsertPt.getParent();
73 // FIXME: The copy needs to have the classes constrained for its operands.
74 // Use operand's regbank to get the class for old register (Reg).
75 if (RegMO.isUse()) {
76 BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
77 TII.get(TargetOpcode::COPY), ConstrainedReg)
78 .addReg(Reg);
79 } else {
80 assert(RegMO.isDef() && "Must be a definition");
81 BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
82 TII.get(TargetOpcode::COPY), Reg)
83 .addReg(ConstrainedReg);
84 }
85 if (GISelChangeObserver *Observer = MF.getObserver()) {
86 Observer->changingInstr(*RegMO.getParent());
87 }
88 RegMO.setReg(ConstrainedReg);
89 if (GISelChangeObserver *Observer = MF.getObserver()) {
90 Observer->changedInstr(*RegMO.getParent());
91 }
92 } else if (OldRegClass != MRI.getRegClassOrNull(Reg)) {
93 if (GISelChangeObserver *Observer = MF.getObserver()) {
94 if (!RegMO.isDef()) {
95 MachineInstr *RegDef = MRI.getVRegDef(Reg);
96 Observer->changedInstr(*RegDef);
97 }
98 Observer->changingAllUsesOfReg(MRI, Reg);
99 Observer->finishedChangingAllUsesOfReg();
100 }
101 }
102 return ConstrainedReg;
103}
104
106 const MachineFunction &MF, const TargetRegisterInfo &TRI,
108 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
109 MachineOperand &RegMO, unsigned OpIdx) {
110 Register Reg = RegMO.getReg();
111 // Assume physical registers are properly constrained.
112 assert(Reg.isVirtual() && "PhysReg not implemented");
113
114 const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI, MF);
115 // Some of the target independent instructions, like COPY, may not impose any
116 // register class constraints on some of their operands: If it's a use, we can
117 // skip constraining as the instruction defining the register would constrain
118 // it.
119
120 if (OpRC) {
121 // Obtain the RC from incoming regbank if it is a proper sub-class. Operands
122 // can have multiple regbanks for a superclass that combine different
123 // register types (E.g., AMDGPU's VGPR and AGPR). The regbank ambiguity
124 // resolved by targets during regbankselect should not be overridden.
125 if (const auto *SubRC = TRI.getCommonSubClass(
126 OpRC, TRI.getConstrainedRegClassForOperand(RegMO, MRI)))
127 OpRC = SubRC;
128
129 OpRC = TRI.getAllocatableClass(OpRC);
130 }
131
132 if (!OpRC) {
133 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
134 "Register class constraint is required unless either the "
135 "instruction is target independent or the operand is a use");
136 // FIXME: Just bailing out like this here could be not enough, unless we
137 // expect the users of this function to do the right thing for PHIs and
138 // COPY:
139 // v1 = COPY v0
140 // v2 = COPY v1
141 // v1 here may end up not being constrained at all. Please notice that to
142 // reproduce the issue we likely need a destination pattern of a selection
143 // rule producing such extra copies, not just an input GMIR with them as
144 // every existing target using selectImpl handles copies before calling it
145 // and they never reach this function.
146 return Reg;
147 }
148 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC,
149 RegMO);
150}
151
153 const TargetInstrInfo &TII,
154 const TargetRegisterInfo &TRI,
155 const RegisterBankInfo &RBI) {
156 assert(!isPreISelGenericOpcode(I.getOpcode()) &&
157 "A selected instruction is expected");
158 MachineBasicBlock &MBB = *I.getParent();
161
162 for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
163 MachineOperand &MO = I.getOperand(OpI);
164
165 // There's nothing to be done on non-register operands.
166 if (!MO.isReg())
167 continue;
168
169 LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
170 assert(MO.isReg() && "Unsupported non-reg operand");
171
172 Register Reg = MO.getReg();
173 // Physical registers don't need to be constrained.
174 if (Reg.isPhysical())
175 continue;
176
177 // Register operands with a value of 0 (e.g. predicate operands) don't need
178 // to be constrained.
179 if (Reg == 0)
180 continue;
181
182 // If the operand is a vreg, we should constrain its regclass, and only
183 // insert COPYs if that's impossible.
184 // constrainOperandRegClass does that for us.
185 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI);
186
187 // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
188 // done.
189 if (MO.isUse()) {
190 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
191 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
192 I.tieOperands(DefIdx, OpI);
193 }
194 }
195 return true;
196}
197
200 // Give up if either DstReg or SrcReg is a physical register.
201 if (DstReg.isPhysical() || SrcReg.isPhysical())
202 return false;
203 // Give up if the types don't match.
204 if (MRI.getType(DstReg) != MRI.getType(SrcReg))
205 return false;
206 // Replace if either DstReg has no constraints or the register
207 // constraints match.
208 return !MRI.getRegClassOrRegBank(DstReg) ||
209 MRI.getRegClassOrRegBank(DstReg) == MRI.getRegClassOrRegBank(SrcReg);
210}
211
213 const MachineRegisterInfo &MRI) {
214 // FIXME: This logical is mostly duplicated with
215 // DeadMachineInstructionElim::isDead. Why is LOCAL_ESCAPE not considered in
216 // MachineInstr::isLabel?
217
218 // Don't delete frame allocation labels.
219 if (MI.getOpcode() == TargetOpcode::LOCAL_ESCAPE)
220 return false;
221 // LIFETIME markers should be preserved even if they seem dead.
222 if (MI.getOpcode() == TargetOpcode::LIFETIME_START ||
223 MI.getOpcode() == TargetOpcode::LIFETIME_END)
224 return false;
225
226 // If we can move an instruction, we can remove it. Otherwise, it has
227 // a side-effect of some sort.
228 bool SawStore = false;
229 if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI())
230 return false;
231
232 // Instructions without side-effects are dead iff they only define dead vregs.
233 for (const auto &MO : MI.operands()) {
234 if (!MO.isReg() || !MO.isDef())
235 continue;
236
237 Register Reg = MO.getReg();
238 if (Reg.isPhysical() || !MRI.use_nodbg_empty(Reg))
239 return false;
240 }
241 return true;
242}
243
245 MachineFunction &MF,
246 const TargetPassConfig &TPC,
249 bool IsFatal = Severity == DS_Error &&
251 // Print the function name explicitly if we don't have a debug location (which
252 // makes the diagnostic less useful) or if we're going to emit a raw error.
253 if (!R.getLocation().isValid() || IsFatal)
254 R << (" (in function: " + MF.getName() + ")").str();
255
256 if (IsFatal)
257 report_fatal_error(Twine(R.getMsg()));
258 else
259 MORE.emit(R);
260}
261
266}
267
271 MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
272 reportGISelDiagnostic(DS_Error, MF, TPC, MORE, R);
273}
274
277 const char *PassName, StringRef Msg,
278 const MachineInstr &MI) {
279 MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
280 MI.getDebugLoc(), MI.getParent());
281 R << Msg;
282 // Printing MI is expensive; only do it if expensive remarks are enabled.
283 if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
284 R << ": " << ore::MNV("Inst", MI);
285 reportGISelFailure(MF, TPC, MORE, R);
286}
287
288std::optional<APInt> llvm::getIConstantVRegVal(Register VReg,
289 const MachineRegisterInfo &MRI) {
290 std::optional<ValueAndVReg> ValAndVReg = getIConstantVRegValWithLookThrough(
291 VReg, MRI, /*LookThroughInstrs*/ false);
292 assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
293 "Value found while looking through instrs");
294 if (!ValAndVReg)
295 return std::nullopt;
296 return ValAndVReg->Value;
297}
298
299std::optional<int64_t>
301 std::optional<APInt> Val = getIConstantVRegVal(VReg, MRI);
302 if (Val && Val->getBitWidth() <= 64)
303 return Val->getSExtValue();
304 return std::nullopt;
305}
306
307namespace {
308
309typedef std::function<bool(const MachineInstr *)> IsOpcodeFn;
310typedef std::function<std::optional<APInt>(const MachineInstr *MI)> GetAPCstFn;
311
312std::optional<ValueAndVReg> getConstantVRegValWithLookThrough(
313 Register VReg, const MachineRegisterInfo &MRI, IsOpcodeFn IsConstantOpcode,
314 GetAPCstFn getAPCstValue, bool LookThroughInstrs = true,
315 bool LookThroughAnyExt = false) {
318
319 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI) &&
320 LookThroughInstrs) {
321 switch (MI->getOpcode()) {
322 case TargetOpcode::G_ANYEXT:
323 if (!LookThroughAnyExt)
324 return std::nullopt;
325 [[fallthrough]];
326 case TargetOpcode::G_TRUNC:
327 case TargetOpcode::G_SEXT:
328 case TargetOpcode::G_ZEXT:
329 SeenOpcodes.push_back(std::make_pair(
330 MI->getOpcode(),
331 MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
332 VReg = MI->getOperand(1).getReg();
333 break;
334 case TargetOpcode::COPY:
335 VReg = MI->getOperand(1).getReg();
336 if (VReg.isPhysical())
337 return std::nullopt;
338 break;
339 case TargetOpcode::G_INTTOPTR:
340 VReg = MI->getOperand(1).getReg();
341 break;
342 default:
343 return std::nullopt;
344 }
345 }
346 if (!MI || !IsConstantOpcode(MI))
347 return std::nullopt;
348
349 std::optional<APInt> MaybeVal = getAPCstValue(MI);
350 if (!MaybeVal)
351 return std::nullopt;
352 APInt &Val = *MaybeVal;
353 while (!SeenOpcodes.empty()) {
354 std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val();
355 switch (OpcodeAndSize.first) {
356 case TargetOpcode::G_TRUNC:
357 Val = Val.trunc(OpcodeAndSize.second);
358 break;
359 case TargetOpcode::G_ANYEXT:
360 case TargetOpcode::G_SEXT:
361 Val = Val.sext(OpcodeAndSize.second);
362 break;
363 case TargetOpcode::G_ZEXT:
364 Val = Val.zext(OpcodeAndSize.second);
365 break;
366 }
367 }
368
369 return ValueAndVReg{Val, VReg};
370}
371
372bool isIConstant(const MachineInstr *MI) {
373 if (!MI)
374 return false;
375 return MI->getOpcode() == TargetOpcode::G_CONSTANT;
376}
377
378bool isFConstant(const MachineInstr *MI) {
379 if (!MI)
380 return false;
381 return MI->getOpcode() == TargetOpcode::G_FCONSTANT;
382}
383
384bool isAnyConstant(const MachineInstr *MI) {
385 if (!MI)
386 return false;
387 unsigned Opc = MI->getOpcode();
388 return Opc == TargetOpcode::G_CONSTANT || Opc == TargetOpcode::G_FCONSTANT;
389}
390
391std::optional<APInt> getCImmAsAPInt(const MachineInstr *MI) {
392 const MachineOperand &CstVal = MI->getOperand(1);
393 if (CstVal.isCImm())
394 return CstVal.getCImm()->getValue();
395 return std::nullopt;
396}
397
398std::optional<APInt> getCImmOrFPImmAsAPInt(const MachineInstr *MI) {
399 const MachineOperand &CstVal = MI->getOperand(1);
400 if (CstVal.isCImm())
401 return CstVal.getCImm()->getValue();
402 if (CstVal.isFPImm())
403 return CstVal.getFPImm()->getValueAPF().bitcastToAPInt();
404 return std::nullopt;
405}
406
407} // end anonymous namespace
408
410 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
411 return getConstantVRegValWithLookThrough(VReg, MRI, isIConstant,
412 getCImmAsAPInt, LookThroughInstrs);
413}
414
416 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
417 bool LookThroughAnyExt) {
418 return getConstantVRegValWithLookThrough(
419 VReg, MRI, isAnyConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs,
420 LookThroughAnyExt);
421}
422
423std::optional<FPValueAndVReg> llvm::getFConstantVRegValWithLookThrough(
424 Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
425 auto Reg = getConstantVRegValWithLookThrough(
426 VReg, MRI, isFConstant, getCImmOrFPImmAsAPInt, LookThroughInstrs);
427 if (!Reg)
428 return std::nullopt;
430 Reg->VReg};
431}
432
433const ConstantFP *
435 MachineInstr *MI = MRI.getVRegDef(VReg);
436 if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
437 return nullptr;
438 return MI->getOperand(1).getFPImm();
439}
440
441std::optional<DefinitionAndSourceRegister>
443 Register DefSrcReg = Reg;
444 auto *DefMI = MRI.getVRegDef(Reg);
445 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
446 if (!DstTy.isValid())
447 return std::nullopt;
448 unsigned Opc = DefMI->getOpcode();
449 while (Opc == TargetOpcode::COPY || isPreISelGenericOptimizationHint(Opc)) {
450 Register SrcReg = DefMI->getOperand(1).getReg();
451 auto SrcTy = MRI.getType(SrcReg);
452 if (!SrcTy.isValid())
453 break;
454 DefMI = MRI.getVRegDef(SrcReg);
455 DefSrcReg = SrcReg;
456 Opc = DefMI->getOpcode();
457 }
458 return DefinitionAndSourceRegister{DefMI, DefSrcReg};
459}
460
462 const MachineRegisterInfo &MRI) {
463 std::optional<DefinitionAndSourceRegister> DefSrcReg =
465 return DefSrcReg ? DefSrcReg->MI : nullptr;
466}
467
469 const MachineRegisterInfo &MRI) {
470 std::optional<DefinitionAndSourceRegister> DefSrcReg =
472 return DefSrcReg ? DefSrcReg->Reg : Register();
473}
474
476 const MachineRegisterInfo &MRI) {
478 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr;
479}
480
481APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
482 if (Size == 32)
483 return APFloat(float(Val));
484 if (Size == 64)
485 return APFloat(Val);
486 if (Size != 16)
487 llvm_unreachable("Unsupported FPConstant size");
488 bool Ignored;
489 APFloat APF(Val);
490 APF.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored);
491 return APF;
492}
493
494std::optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode,
495 const Register Op1,
496 const Register Op2,
497 const MachineRegisterInfo &MRI) {
498 auto MaybeOp2Cst = getAnyConstantVRegValWithLookThrough(Op2, MRI, false);
499 if (!MaybeOp2Cst)
500 return std::nullopt;
501
502 auto MaybeOp1Cst = getAnyConstantVRegValWithLookThrough(Op1, MRI, false);
503 if (!MaybeOp1Cst)
504 return std::nullopt;
505
506 const APInt &C1 = MaybeOp1Cst->Value;
507 const APInt &C2 = MaybeOp2Cst->Value;
508 switch (Opcode) {
509 default:
510 break;
511 case TargetOpcode::G_ADD:
512 case TargetOpcode::G_PTR_ADD:
513 return C1 + C2;
514 case TargetOpcode::G_AND:
515 return C1 & C2;
516 case TargetOpcode::G_ASHR:
517 return C1.ashr(C2);
518 case TargetOpcode::G_LSHR:
519 return C1.lshr(C2);
520 case TargetOpcode::G_MUL:
521 return C1 * C2;
522 case TargetOpcode::G_OR:
523 return C1 | C2;
524 case TargetOpcode::G_SHL:
525 return C1 << C2;
526 case TargetOpcode::G_SUB:
527 return C1 - C2;
528 case TargetOpcode::G_XOR:
529 return C1 ^ C2;
530 case TargetOpcode::G_UDIV:
531 if (!C2.getBoolValue())
532 break;
533 return C1.udiv(C2);
534 case TargetOpcode::G_SDIV:
535 if (!C2.getBoolValue())
536 break;
537 return C1.sdiv(C2);
538 case TargetOpcode::G_UREM:
539 if (!C2.getBoolValue())
540 break;
541 return C1.urem(C2);
542 case TargetOpcode::G_SREM:
543 if (!C2.getBoolValue())
544 break;
545 return C1.srem(C2);
546 case TargetOpcode::G_SMIN:
547 return APIntOps::smin(C1, C2);
548 case TargetOpcode::G_SMAX:
549 return APIntOps::smax(C1, C2);
550 case TargetOpcode::G_UMIN:
551 return APIntOps::umin(C1, C2);
552 case TargetOpcode::G_UMAX:
553 return APIntOps::umax(C1, C2);
554 }
555
556 return std::nullopt;
557}
558
559std::optional<APFloat>
560llvm::ConstantFoldFPBinOp(unsigned Opcode, const Register Op1,
561 const Register Op2, const MachineRegisterInfo &MRI) {
562 const ConstantFP *Op2Cst = getConstantFPVRegVal(Op2, MRI);
563 if (!Op2Cst)
564 return std::nullopt;
565
566 const ConstantFP *Op1Cst = getConstantFPVRegVal(Op1, MRI);
567 if (!Op1Cst)
568 return std::nullopt;
569
570 APFloat C1 = Op1Cst->getValueAPF();
571 const APFloat &C2 = Op2Cst->getValueAPF();
572 switch (Opcode) {
573 case TargetOpcode::G_FADD:
574 C1.add(C2, APFloat::rmNearestTiesToEven);
575 return C1;
576 case TargetOpcode::G_FSUB:
577 C1.subtract(C2, APFloat::rmNearestTiesToEven);
578 return C1;
579 case TargetOpcode::G_FMUL:
580 C1.multiply(C2, APFloat::rmNearestTiesToEven);
581 return C1;
582 case TargetOpcode::G_FDIV:
583 C1.divide(C2, APFloat::rmNearestTiesToEven);
584 return C1;
585 case TargetOpcode::G_FREM:
586 C1.mod(C2);
587 return C1;
588 case TargetOpcode::G_FCOPYSIGN:
589 C1.copySign(C2);
590 return C1;
591 case TargetOpcode::G_FMINNUM:
592 return minnum(C1, C2);
593 case TargetOpcode::G_FMAXNUM:
594 return maxnum(C1, C2);
595 case TargetOpcode::G_FMINIMUM:
596 return minimum(C1, C2);
597 case TargetOpcode::G_FMAXIMUM:
598 return maximum(C1, C2);
599 case TargetOpcode::G_FMINNUM_IEEE:
600 case TargetOpcode::G_FMAXNUM_IEEE:
601 // FIXME: These operations were unfortunately named. fminnum/fmaxnum do not
602 // follow the IEEE behavior for signaling nans and follow libm's fmin/fmax,
603 // and currently there isn't a nice wrapper in APFloat for the version with
604 // correct snan handling.
605 break;
606 default:
607 break;
608 }
609
610 return std::nullopt;
611}
612
614llvm::ConstantFoldVectorBinop(unsigned Opcode, const Register Op1,
615 const Register Op2,
616 const MachineRegisterInfo &MRI) {
617 auto *SrcVec2 = getOpcodeDef<GBuildVector>(Op2, MRI);
618 if (!SrcVec2)
619 return SmallVector<APInt>();
620
621 auto *SrcVec1 = getOpcodeDef<GBuildVector>(Op1, MRI);
622 if (!SrcVec1)
623 return SmallVector<APInt>();
624
625 SmallVector<APInt> FoldedElements;
626 for (unsigned Idx = 0, E = SrcVec1->getNumSources(); Idx < E; ++Idx) {
627 auto MaybeCst = ConstantFoldBinOp(Opcode, SrcVec1->getSourceReg(Idx),
628 SrcVec2->getSourceReg(Idx), MRI);
629 if (!MaybeCst)
630 return SmallVector<APInt>();
631 FoldedElements.push_back(*MaybeCst);
632 }
633 return FoldedElements;
634}
635
637 bool SNaN) {
638 const MachineInstr *DefMI = MRI.getVRegDef(Val);
639 if (!DefMI)
640 return false;
641
642 const TargetMachine& TM = DefMI->getMF()->getTarget();
643 if (DefMI->getFlag(MachineInstr::FmNoNans) || TM.Options.NoNaNsFPMath)
644 return true;
645
646 // If the value is a constant, we can obviously see if it is a NaN or not.
647 if (const ConstantFP *FPVal = getConstantFPVRegVal(Val, MRI)) {
648 return !FPVal->getValueAPF().isNaN() ||
649 (SNaN && !FPVal->getValueAPF().isSignaling());
650 }
651
652 if (DefMI->getOpcode() == TargetOpcode::G_BUILD_VECTOR) {
653 for (const auto &Op : DefMI->uses())
654 if (!isKnownNeverNaN(Op.getReg(), MRI, SNaN))
655 return false;
656 return true;
657 }
658
659 switch (DefMI->getOpcode()) {
660 default:
661 break;
662 case TargetOpcode::G_FADD:
663 case TargetOpcode::G_FSUB:
664 case TargetOpcode::G_FMUL:
665 case TargetOpcode::G_FDIV:
666 case TargetOpcode::G_FREM:
667 case TargetOpcode::G_FSIN:
668 case TargetOpcode::G_FCOS:
669 case TargetOpcode::G_FMA:
670 case TargetOpcode::G_FMAD:
671 if (SNaN)
672 return true;
673
674 // TODO: Need isKnownNeverInfinity
675 return false;
676 case TargetOpcode::G_FMINNUM_IEEE:
677 case TargetOpcode::G_FMAXNUM_IEEE: {
678 if (SNaN)
679 return true;
680 // This can return a NaN if either operand is an sNaN, or if both operands
681 // are NaN.
682 return (isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI) &&
686 }
687 case TargetOpcode::G_FMINNUM:
688 case TargetOpcode::G_FMAXNUM: {
689 // Only one needs to be known not-nan, since it will be returned if the
690 // other ends up being one.
691 return isKnownNeverNaN(DefMI->getOperand(1).getReg(), MRI, SNaN) ||
693 }
694 }
695
696 if (SNaN) {
697 // FP operations quiet. For now, just handle the ones inserted during
698 // legalization.
699 switch (DefMI->getOpcode()) {
700 case TargetOpcode::G_FPEXT:
701 case TargetOpcode::G_FPTRUNC:
702 case TargetOpcode::G_FCANONICALIZE:
703 return true;
704 default:
705 return false;
706 }
707 }
708
709 return false;
710}
711
713 const MachinePointerInfo &MPO) {
714 auto PSV = MPO.V.dyn_cast<const PseudoSourceValue *>();
715 if (auto FSPV = dyn_cast_or_null<FixedStackPseudoSourceValue>(PSV)) {
716 MachineFrameInfo &MFI = MF.getFrameInfo();
717 return commonAlignment(MFI.getObjectAlign(FSPV->getFrameIndex()),
718 MPO.Offset);
719 }
720
721 if (const Value *V = MPO.V.dyn_cast<const Value *>()) {
722 const Module *M = MF.getFunction().getParent();
723 return V->getPointerAlignment(M->getDataLayout());
724 }
725
726 return Align(1);
727}
728
730 const TargetInstrInfo &TII,
731 MCRegister PhysReg,
732 const TargetRegisterClass &RC,
733 const DebugLoc &DL, LLT RegTy) {
734 MachineBasicBlock &EntryMBB = MF.front();
736 Register LiveIn = MRI.getLiveInVirtReg(PhysReg);
737 if (LiveIn) {
738 MachineInstr *Def = MRI.getVRegDef(LiveIn);
739 if (Def) {
740 // FIXME: Should the verifier check this is in the entry block?
741 assert(Def->getParent() == &EntryMBB && "live-in copy not in entry block");
742 return LiveIn;
743 }
744
745 // It's possible the incoming argument register and copy was added during
746 // lowering, but later deleted due to being/becoming dead. If this happens,
747 // re-insert the copy.
748 } else {
749 // The live in register was not present, so add it.
750 LiveIn = MF.addLiveIn(PhysReg, &RC);
751 if (RegTy.isValid())
752 MRI.setType(LiveIn, RegTy);
753 }
754
755 BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(TargetOpcode::COPY), LiveIn)
756 .addReg(PhysReg);
757 if (!EntryMBB.isLiveIn(PhysReg))
758 EntryMBB.addLiveIn(PhysReg);
759 return LiveIn;
760}
761
762std::optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode,
763 const Register Op1, uint64_t Imm,
764 const MachineRegisterInfo &MRI) {
765 auto MaybeOp1Cst = getIConstantVRegVal(Op1, MRI);
766 if (MaybeOp1Cst) {
767 switch (Opcode) {
768 default:
769 break;
770 case TargetOpcode::G_SEXT_INREG: {
771 LLT Ty = MRI.getType(Op1);
772 return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits());
773 }
774 }
775 }
776 return std::nullopt;
777}
778
779std::optional<APFloat>
780llvm::ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src,
781 const MachineRegisterInfo &MRI) {
782 assert(Opcode == TargetOpcode::G_SITOFP || Opcode == TargetOpcode::G_UITOFP);
783 if (auto MaybeSrcVal = getIConstantVRegVal(Src, MRI)) {
784 APFloat DstVal(getFltSemanticForLLT(DstTy));
785 DstVal.convertFromAPInt(*MaybeSrcVal, Opcode == TargetOpcode::G_SITOFP,
786 APFloat::rmNearestTiesToEven);
787 return DstVal;
788 }
789 return std::nullopt;
790}
791
792std::optional<SmallVector<unsigned>>
794 LLT Ty = MRI.getType(Src);
795 SmallVector<unsigned> FoldedCTLZs;
796 auto tryFoldScalar = [&](Register R) -> std::optional<unsigned> {
797 auto MaybeCst = getIConstantVRegVal(R, MRI);
798 if (!MaybeCst)
799 return std::nullopt;
800 return MaybeCst->countl_zero();
801 };
802 if (Ty.isVector()) {
803 // Try to constant fold each element.
804 auto *BV = getOpcodeDef<GBuildVector>(Src, MRI);
805 if (!BV)
806 return std::nullopt;
807 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
808 if (auto MaybeFold = tryFoldScalar(BV->getSourceReg(SrcIdx))) {
809 FoldedCTLZs.emplace_back(*MaybeFold);
810 continue;
811 }
812 return std::nullopt;
813 }
814 return FoldedCTLZs;
815 }
816 if (auto MaybeCst = tryFoldScalar(Src)) {
817 FoldedCTLZs.emplace_back(*MaybeCst);
818 return FoldedCTLZs;
819 }
820 return std::nullopt;
821}
822
824 GISelKnownBits *KB) {
825 std::optional<DefinitionAndSourceRegister> DefSrcReg =
827 if (!DefSrcReg)
828 return false;
829
830 const MachineInstr &MI = *DefSrcReg->MI;
831 const LLT Ty = MRI.getType(Reg);
832
833 switch (MI.getOpcode()) {
834 case TargetOpcode::G_CONSTANT: {
835 unsigned BitWidth = Ty.getScalarSizeInBits();
836 const ConstantInt *CI = MI.getOperand(1).getCImm();
837 return CI->getValue().zextOrTrunc(BitWidth).isPowerOf2();
838 }
839 case TargetOpcode::G_SHL: {
840 // A left-shift of a constant one will have exactly one bit set because
841 // shifting the bit off the end is undefined.
842
843 // TODO: Constant splat
844 if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
845 if (*ConstLHS == 1)
846 return true;
847 }
848
849 break;
850 }
851 case TargetOpcode::G_LSHR: {
852 if (auto ConstLHS = getIConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
853 if (ConstLHS->isSignMask())
854 return true;
855 }
856
857 break;
858 }
859 case TargetOpcode::G_BUILD_VECTOR: {
860 // TODO: Probably should have a recursion depth guard since you could have
861 // bitcasted vector elements.
862 for (const MachineOperand &MO : llvm::drop_begin(MI.operands()))
863 if (!isKnownToBeAPowerOfTwo(MO.getReg(), MRI, KB))
864 return false;
865
866 return true;
867 }
868 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
869 // Only handle constants since we would need to know if number of leading
870 // zeros is greater than the truncation amount.
871 const unsigned BitWidth = Ty.getScalarSizeInBits();
872 for (const MachineOperand &MO : llvm::drop_begin(MI.operands())) {
873 auto Const = getIConstantVRegVal(MO.getReg(), MRI);
874 if (!Const || !Const->zextOrTrunc(BitWidth).isPowerOf2())
875 return false;
876 }
877
878 return true;
879 }
880 default:
881 break;
882 }
883
884 if (!KB)
885 return false;
886
887 // More could be done here, though the above checks are enough
888 // to handle some common cases.
889
890 // Fall back to computeKnownBits to catch other known cases.
891 KnownBits Known = KB->getKnownBits(Reg);
892 return (Known.countMaxPopulation() == 1) && (Known.countMinPopulation() == 1);
893}
894
897}
898
899LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) {
900 const unsigned OrigSize = OrigTy.getSizeInBits();
901 const unsigned TargetSize = TargetTy.getSizeInBits();
902
903 if (OrigSize == TargetSize)
904 return OrigTy;
905
906 if (OrigTy.isVector()) {
907 const LLT OrigElt = OrigTy.getElementType();
908
909 if (TargetTy.isVector()) {
910 const LLT TargetElt = TargetTy.getElementType();
911
912 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
913 int GCDElts =
914 std::gcd(OrigTy.getNumElements(), TargetTy.getNumElements());
915 // Prefer the original element type.
916 ElementCount Mul = OrigTy.getElementCount() * TargetTy.getNumElements();
917 return LLT::vector(Mul.divideCoefficientBy(GCDElts),
918 OrigTy.getElementType());
919 }
920 } else {
921 if (OrigElt.getSizeInBits() == TargetSize)
922 return OrigTy;
923 }
924
925 unsigned LCMSize = std::lcm(OrigSize, TargetSize);
926 return LLT::fixed_vector(LCMSize / OrigElt.getSizeInBits(), OrigElt);
927 }
928
929 if (TargetTy.isVector()) {
930 unsigned LCMSize = std::lcm(OrigSize, TargetSize);
931 return LLT::fixed_vector(LCMSize / OrigSize, OrigTy);
932 }
933
934 unsigned LCMSize = std::lcm(OrigSize, TargetSize);
935
936 // Preserve pointer types.
937 if (LCMSize == OrigSize)
938 return OrigTy;
939 if (LCMSize == TargetSize)
940 return TargetTy;
941
942 return LLT::scalar(LCMSize);
943}
944
945LLT llvm::getCoverTy(LLT OrigTy, LLT TargetTy) {
946 if (!OrigTy.isVector() || !TargetTy.isVector() || OrigTy == TargetTy ||
947 (OrigTy.getScalarSizeInBits() != TargetTy.getScalarSizeInBits()))
948 return getLCMType(OrigTy, TargetTy);
949
950 unsigned OrigTyNumElts = OrigTy.getNumElements();
951 unsigned TargetTyNumElts = TargetTy.getNumElements();
952 if (OrigTyNumElts % TargetTyNumElts == 0)
953 return OrigTy;
954
955 unsigned NumElts = alignTo(OrigTyNumElts, TargetTyNumElts);
957 OrigTy.getElementType());
958}
959
960LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) {
961 const unsigned OrigSize = OrigTy.getSizeInBits();
962 const unsigned TargetSize = TargetTy.getSizeInBits();
963
964 if (OrigSize == TargetSize)
965 return OrigTy;
966
967 if (OrigTy.isVector()) {
968 LLT OrigElt = OrigTy.getElementType();
969 if (TargetTy.isVector()) {
970 LLT TargetElt = TargetTy.getElementType();
971 if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
972 int GCD = std::gcd(OrigTy.getNumElements(), TargetTy.getNumElements());
973 return LLT::scalarOrVector(ElementCount::getFixed(GCD), OrigElt);
974 }
975 } else {
976 // If the source is a vector of pointers, return a pointer element.
977 if (OrigElt.getSizeInBits() == TargetSize)
978 return OrigElt;
979 }
980
981 unsigned GCD = std::gcd(OrigSize, TargetSize);
982 if (GCD == OrigElt.getSizeInBits())
983 return OrigElt;
984
985 // If we can't produce the original element type, we have to use a smaller
986 // scalar.
987 if (GCD < OrigElt.getSizeInBits())
988 return LLT::scalar(GCD);
989 return LLT::fixed_vector(GCD / OrigElt.getSizeInBits(), OrigElt);
990 }
991
992 if (TargetTy.isVector()) {
993 // Try to preserve the original element type.
994 LLT TargetElt = TargetTy.getElementType();
995 if (TargetElt.getSizeInBits() == OrigSize)
996 return OrigTy;
997 }
998
999 unsigned GCD = std::gcd(OrigSize, TargetSize);
1000 return LLT::scalar(GCD);
1001}
1002
1004 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
1005 "Only G_SHUFFLE_VECTOR can have a splat index!");
1006 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
1007 auto FirstDefinedIdx = find_if(Mask, [](int Elt) { return Elt >= 0; });
1008
1009 // If all elements are undefined, this shuffle can be considered a splat.
1010 // Return 0 for better potential for callers to simplify.
1011 if (FirstDefinedIdx == Mask.end())
1012 return 0;
1013
1014 // Make sure all remaining elements are either undef or the same
1015 // as the first non-undef value.
1016 int SplatValue = *FirstDefinedIdx;
1017 if (any_of(make_range(std::next(FirstDefinedIdx), Mask.end()),
1018 [&SplatValue](int Elt) { return Elt >= 0 && Elt != SplatValue; }))
1019 return std::nullopt;
1020
1021 return SplatValue;
1022}
1023
1024static bool isBuildVectorOp(unsigned Opcode) {
1025 return Opcode == TargetOpcode::G_BUILD_VECTOR ||
1026 Opcode == TargetOpcode::G_BUILD_VECTOR_TRUNC;
1027}
1028
1029namespace {
1030
1031std::optional<ValueAndVReg> getAnyConstantSplat(Register VReg,
1032 const MachineRegisterInfo &MRI,
1033 bool AllowUndef) {
1035 if (!MI)
1036 return std::nullopt;
1037
1038 bool isConcatVectorsOp = MI->getOpcode() == TargetOpcode::G_CONCAT_VECTORS;
1039 if (!isBuildVectorOp(MI->getOpcode()) && !isConcatVectorsOp)
1040 return std::nullopt;
1041
1042 std::optional<ValueAndVReg> SplatValAndReg;
1043 for (MachineOperand &Op : MI->uses()) {
1044 Register Element = Op.getReg();
1045 // If we have a G_CONCAT_VECTOR, we recursively look into the
1046 // vectors that we're concatenating to see if they're splats.
1047 auto ElementValAndReg =
1048 isConcatVectorsOp
1049 ? getAnyConstantSplat(Element, MRI, AllowUndef)
1051
1052 // If AllowUndef, treat undef as value that will result in a constant splat.
1053 if (!ElementValAndReg) {
1054 if (AllowUndef && isa<GImplicitDef>(MRI.getVRegDef(Element)))
1055 continue;
1056 return std::nullopt;
1057 }
1058
1059 // Record splat value
1060 if (!SplatValAndReg)
1061 SplatValAndReg = ElementValAndReg;
1062
1063 // Different constant than the one already recorded, not a constant splat.
1064 if (SplatValAndReg->Value != ElementValAndReg->Value)
1065 return std::nullopt;
1066 }
1067
1068 return SplatValAndReg;
1069}
1070
1071} // end anonymous namespace
1072
1074 const MachineRegisterInfo &MRI,
1075 int64_t SplatValue, bool AllowUndef) {
1076 if (auto SplatValAndReg = getAnyConstantSplat(Reg, MRI, AllowUndef))
1077 return mi_match(SplatValAndReg->VReg, MRI, m_SpecificICst(SplatValue));
1078 return false;
1079}
1080
1082 const MachineRegisterInfo &MRI,
1083 int64_t SplatValue, bool AllowUndef) {
1084 return isBuildVectorConstantSplat(MI.getOperand(0).getReg(), MRI, SplatValue,
1085 AllowUndef);
1086}
1087
1088std::optional<APInt>
1090 if (auto SplatValAndReg =
1091 getAnyConstantSplat(Reg, MRI, /* AllowUndef */ false)) {
1092 std::optional<ValueAndVReg> ValAndVReg =
1093 getIConstantVRegValWithLookThrough(SplatValAndReg->VReg, MRI);
1094 return ValAndVReg->Value;
1095 }
1096
1097 return std::nullopt;
1098}
1099
1100std::optional<APInt>
1102 const MachineRegisterInfo &MRI) {
1103 return getIConstantSplatVal(MI.getOperand(0).getReg(), MRI);
1104}
1105
1106std::optional<int64_t>
1108 const MachineRegisterInfo &MRI) {
1109 if (auto SplatValAndReg =
1110 getAnyConstantSplat(Reg, MRI, /* AllowUndef */ false))
1111 return getIConstantVRegSExtVal(SplatValAndReg->VReg, MRI);
1112 return std::nullopt;
1113}
1114
1115std::optional<int64_t>
1117 const MachineRegisterInfo &MRI) {
1118 return getIConstantSplatSExtVal(MI.getOperand(0).getReg(), MRI);
1119}
1120
1121std::optional<FPValueAndVReg>
1123 bool AllowUndef) {
1124 if (auto SplatValAndReg = getAnyConstantSplat(VReg, MRI, AllowUndef))
1125 return getFConstantVRegValWithLookThrough(SplatValAndReg->VReg, MRI);
1126 return std::nullopt;
1127}
1128
1130 const MachineRegisterInfo &MRI,
1131 bool AllowUndef) {
1132 return isBuildVectorConstantSplat(MI, MRI, 0, AllowUndef);
1133}
1134
1136 const MachineRegisterInfo &MRI,
1137 bool AllowUndef) {
1138 return isBuildVectorConstantSplat(MI, MRI, -1, AllowUndef);
1139}
1140
1141std::optional<RegOrConstant>
1143 unsigned Opc = MI.getOpcode();
1144 if (!isBuildVectorOp(Opc))
1145 return std::nullopt;
1146 if (auto Splat = getIConstantSplatSExtVal(MI, MRI))
1147 return RegOrConstant(*Splat);
1148 auto Reg = MI.getOperand(1).getReg();
1149 if (any_of(make_range(MI.operands_begin() + 2, MI.operands_end()),
1150 [&Reg](const MachineOperand &Op) { return Op.getReg() != Reg; }))
1151 return std::nullopt;
1152 return RegOrConstant(Reg);
1153}
1154
1156 const MachineRegisterInfo &MRI,
1157 bool AllowFP = true,
1158 bool AllowOpaqueConstants = true) {
1159 switch (MI.getOpcode()) {
1160 case TargetOpcode::G_CONSTANT:
1161 case TargetOpcode::G_IMPLICIT_DEF:
1162 return true;
1163 case TargetOpcode::G_FCONSTANT:
1164 return AllowFP;
1165 case TargetOpcode::G_GLOBAL_VALUE:
1166 case TargetOpcode::G_FRAME_INDEX:
1167 case TargetOpcode::G_BLOCK_ADDR:
1168 case TargetOpcode::G_JUMP_TABLE:
1169 return AllowOpaqueConstants;
1170 default:
1171 return false;
1172 }
1173}
1174
1176 const MachineRegisterInfo &MRI) {
1177 Register Def = MI.getOperand(0).getReg();
1178 if (auto C = getIConstantVRegValWithLookThrough(Def, MRI))
1179 return true;
1180 GBuildVector *BV = dyn_cast<GBuildVector>(&MI);
1181 if (!BV)
1182 return false;
1183 for (unsigned SrcIdx = 0; SrcIdx < BV->getNumSources(); ++SrcIdx) {
1185 getOpcodeDef<GImplicitDef>(BV->getSourceReg(SrcIdx), MRI))
1186 continue;
1187 return false;
1188 }
1189 return true;
1190}
1191
1193 const MachineRegisterInfo &MRI,
1194 bool AllowFP, bool AllowOpaqueConstants) {
1195 if (isConstantScalar(MI, MRI, AllowFP, AllowOpaqueConstants))
1196 return true;
1197
1198 if (!isBuildVectorOp(MI.getOpcode()))
1199 return false;
1200
1201 const unsigned NumOps = MI.getNumOperands();
1202 for (unsigned I = 1; I != NumOps; ++I) {
1203 const MachineInstr *ElementDef = MRI.getVRegDef(MI.getOperand(I).getReg());
1204 if (!isConstantScalar(*ElementDef, MRI, AllowFP, AllowOpaqueConstants))
1205 return false;
1206 }
1207
1208 return true;
1209}
1210
1211std::optional<APInt>
1213 const MachineRegisterInfo &MRI) {
1214 Register Def = MI.getOperand(0).getReg();
1215 if (auto C = getIConstantVRegValWithLookThrough(Def, MRI))
1216 return C->Value;
1217 auto MaybeCst = getIConstantSplatSExtVal(MI, MRI);
1218 if (!MaybeCst)
1219 return std::nullopt;
1220 const unsigned ScalarSize = MRI.getType(Def).getScalarSizeInBits();
1221 return APInt(ScalarSize, *MaybeCst, true);
1222}
1223
1225 const MachineRegisterInfo &MRI, bool AllowUndefs) {
1226 switch (MI.getOpcode()) {
1227 case TargetOpcode::G_IMPLICIT_DEF:
1228 return AllowUndefs;
1229 case TargetOpcode::G_CONSTANT:
1230 return MI.getOperand(1).getCImm()->isNullValue();
1231 case TargetOpcode::G_FCONSTANT: {
1232 const ConstantFP *FPImm = MI.getOperand(1).getFPImm();
1233 return FPImm->isZero() && !FPImm->isNegative();
1234 }
1235 default:
1236 if (!AllowUndefs) // TODO: isBuildVectorAllZeros assumes undef is OK already
1237 return false;
1238 return isBuildVectorAllZeros(MI, MRI);
1239 }
1240}
1241
1243 const MachineRegisterInfo &MRI,
1244 bool AllowUndefs) {
1245 switch (MI.getOpcode()) {
1246 case TargetOpcode::G_IMPLICIT_DEF:
1247 return AllowUndefs;
1248 case TargetOpcode::G_CONSTANT:
1249 return MI.getOperand(1).getCImm()->isAllOnesValue();
1250 default:
1251 if (!AllowUndefs) // TODO: isBuildVectorAllOnes assumes undef is OK already
1252 return false;
1253 return isBuildVectorAllOnes(MI, MRI);
1254 }
1255}
1256
1258 const MachineRegisterInfo &MRI, Register Reg,
1259 std::function<bool(const Constant *ConstVal)> Match, bool AllowUndefs) {
1260
1261 const MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
1262 if (AllowUndefs && Def->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
1263 return Match(nullptr);
1264
1265 // TODO: Also handle fconstant
1266 if (Def->getOpcode() == TargetOpcode::G_CONSTANT)
1267 return Match(Def->getOperand(1).getCImm());
1268
1269 if (Def->getOpcode() != TargetOpcode::G_BUILD_VECTOR)
1270 return false;
1271
1272 for (unsigned I = 1, E = Def->getNumOperands(); I != E; ++I) {
1273 Register SrcElt = Def->getOperand(I).getReg();
1274 const MachineInstr *SrcDef = getDefIgnoringCopies(SrcElt, MRI);
1275 if (AllowUndefs && SrcDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) {
1276 if (!Match(nullptr))
1277 return false;
1278 continue;
1279 }
1280
1281 if (SrcDef->getOpcode() != TargetOpcode::G_CONSTANT ||
1282 !Match(SrcDef->getOperand(1).getCImm()))
1283 return false;
1284 }
1285
1286 return true;
1287}
1288
1289bool llvm::isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
1290 bool IsFP) {
1291 switch (TLI.getBooleanContents(IsVector, IsFP)) {
1292 case TargetLowering::UndefinedBooleanContent:
1293 return Val & 0x1;
1294 case TargetLowering::ZeroOrOneBooleanContent:
1295 return Val == 1;
1296 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1297 return Val == -1;
1298 }
1299 llvm_unreachable("Invalid boolean contents");
1300}
1301
1302bool llvm::isConstFalseVal(const TargetLowering &TLI, int64_t Val,
1303 bool IsVector, bool IsFP) {
1304 switch (TLI.getBooleanContents(IsVector, IsFP)) {
1305 case TargetLowering::UndefinedBooleanContent:
1306 return ~Val & 0x1;
1307 case TargetLowering::ZeroOrOneBooleanContent:
1308 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1309 return Val == 0;
1310 }
1311 llvm_unreachable("Invalid boolean contents");
1312}
1313
1314int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector,
1315 bool IsFP) {
1316 switch (TLI.getBooleanContents(IsVector, IsFP)) {
1317 case TargetLowering::UndefinedBooleanContent:
1318 case TargetLowering::ZeroOrOneBooleanContent:
1319 return 1;
1320 case TargetLowering::ZeroOrNegativeOneBooleanContent:
1321 return -1;
1322 }
1323 llvm_unreachable("Invalid boolean contents");
1324}
1325
1328 const auto &F = MBB.getParent()->getFunction();
1329 return F.hasOptSize() || F.hasMinSize() ||
1331}
1332
1334 LostDebugLocObserver *LocObserver,
1335 SmallInstListTy &DeadInstChain) {
1336 for (MachineOperand &Op : MI.uses()) {
1337 if (Op.isReg() && Op.getReg().isVirtual())
1338 DeadInstChain.insert(MRI.getVRegDef(Op.getReg()));
1339 }
1340 LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n");
1341 DeadInstChain.remove(&MI);
1342 MI.eraseFromParent();
1343 if (LocObserver)
1344 LocObserver->checkpoint(false);
1345}
1346
1349 LostDebugLocObserver *LocObserver) {
1350 SmallInstListTy DeadInstChain;
1351 for (MachineInstr *MI : DeadInstrs)
1352 saveUsesAndErase(*MI, MRI, LocObserver, DeadInstChain);
1353
1354 while (!DeadInstChain.empty()) {
1355 MachineInstr *Inst = DeadInstChain.pop_back_val();
1356 if (!isTriviallyDead(*Inst, MRI))
1357 continue;
1358 saveUsesAndErase(*Inst, MRI, LocObserver, DeadInstChain);
1359 }
1360}
1361
1363 LostDebugLocObserver *LocObserver) {
1364 return eraseInstrs({&MI}, MRI, LocObserver);
1365}
1366
1368 for (auto &Def : MI.defs()) {
1369 assert(Def.isReg() && "Must be a reg");
1370
1372 for (auto &MOUse : MRI.use_operands(Def.getReg())) {
1373 MachineInstr *DbgValue = MOUse.getParent();
1374 // Ignore partially formed DBG_VALUEs.
1375 if (DbgValue->isNonListDebugValue() && DbgValue->getNumOperands() == 4) {
1376 DbgUsers.push_back(&MOUse);
1377 }
1378 }
1379
1380 if (!DbgUsers.empty()) {
1382 }
1383 }
1384}
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
basic Basic Alias true
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static void reportGISelDiagnostic(DiagnosticSeverity Severity, MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Definition: Utils.cpp:244
static bool isBuildVectorOp(unsigned Opcode)
Definition: Utils.cpp:1024
static bool isConstantScalar(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Definition: Utils.cpp:1155
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Size
This contains common code to allow clients to notify changes to machine instr.
Provides analysis for querying information about KnownBits during GISel passes.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Tracks DebugLocs between checkpoints and verifies that they are transferred.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
Contains matchers for matching SSA Machine Instructions.
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
Target-Independent Code Generator Pass Configuration Options pass.
static const char PassName[]
BinaryOperator * Mul
Class recording the (high level) value of a variable.
opStatus divide(const APFloat &RHS, roundingMode RM)
Definition: APFloat.h:1033
void copySign(const APFloat &RHS)
Definition: APFloat.h:1127
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:5377
opStatus subtract(const APFloat &RHS, roundingMode RM)
Definition: APFloat.h:1015
opStatus add(const APFloat &RHS, roundingMode RM)
Definition: APFloat.h:1006
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
Definition: APFloat.h:1157
opStatus multiply(const APFloat &RHS, roundingMode RM)
Definition: APFloat.h:1024
APInt bitcastToAPInt() const
Definition: APFloat.h:1174
opStatus mod(const APFloat &RHS)
Definition: APFloat.h:1051
Class for arbitrary precision integers.
Definition: APInt.h:75
APInt udiv(const APInt &RHS) const
Unsigned division operation.
Definition: APInt.cpp:1571
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:973
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:994
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:898
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
Definition: APInt.cpp:1664
APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
Definition: APInt.cpp:1642
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition: APInt.h:815
APInt srem(const APInt &RHS) const
Function for signed remainder operation.
Definition: APInt.cpp:1734
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:946
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
Definition: APInt.h:432
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:839
Represent the analysis usage information of a pass.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:256
const APFloat & getValueAPF() const
Definition: Constants.h:297
bool isNegative() const
Return true if the sign bit is set.
Definition: Constants.h:304
bool isZero() const
Return true if the value is positive or negative zero.
Definition: Constants.h:301
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:132
This is an important base class in LLVM.
Definition: Constant.h:41
A debug info location.
Definition: DebugLoc.h:33
static constexpr ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:291
Represents a G_BUILD_VECTOR.
Abstract class that contains various methods for clients to notify about changes.
KnownBits getKnownBits(Register R)
void insert(MachineInstr *I)
Add the specified instruction to the worklist if it isn't already in it.
Definition: GISelWorkList.h:74
MachineInstr * pop_back_val()
bool empty() const
Definition: GISelWorkList.h:38
void remove(const MachineInstr *I)
Remove I from the worklist if it exists.
Definition: GISelWorkList.h:83
Register getSourceReg(unsigned I) const
Returns the I'th source register.
unsigned getNumSources() const
Returns the number of source registers.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
constexpr unsigned getScalarSizeInBits() const
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
static constexpr LLT scalarOrVector(ElementCount EC, LLT ScalarTy)
void checkpoint(bool CheckDebugLocs=true)
Call this to indicate that it's a good point to assess whether locations have been lost.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:230
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
MachineFunctionProperties & set(Property P)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
GISelChangeObserver * getObserver() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:313
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:357
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:689
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:445
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
MachineOperand class - Representation of each machine instruction operand.
const ConstantInt * getCImm() const
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
const ConstantFP * getFPImm() const
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Diagnostic information for missed-optimization remarks.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Definition: PointerUnion.h:162
Analysis providing profile information.
Special value supplied for machine level alias analysis.
Represents a value which can be a Register or a constant.
Definition: Utils.h:352
Holds all the information related to register banks.
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
bool empty() const
Definition: SmallVector.h:94
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:941
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
Target-Independent Code Generator Pass Configuration Options.
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const APInt & smin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be signed.
Definition: APInt.h:2182
const APInt & smax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be signed.
Definition: APInt.h:2187
const APInt & umin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be unsigned.
Definition: APInt.h:2192
const APInt & umax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be unsigned.
Definition: APInt.h:2197
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
SpecificConstantMatch m_SpecificICst(int64_t RequestedValue)
Matches a constant equal to RequestedValue.
bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P)
DiagnosticInfoMIROptimization::MachineArgument MNV
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition: Utils.cpp:729
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:397
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1129
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:53
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:475
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:434
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
std::optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition: Utils.cpp:288
std::optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:780
std::optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1089
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
Definition: Utils.cpp:1242
const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)
Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.
std::optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:560
void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Definition: Utils.cpp:1367
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:152
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Definition: TargetOpcodes.h:30
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
std::optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:762
std::optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1142
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 maximum semantics.
Definition: APFloat.h:1384
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
std::optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
Definition: Utils.cpp:1212
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
Definition: Utils.cpp:1224
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:461
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition: Utils.cpp:1257
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition: Utils.cpp:1289
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:899
std::optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:300
std::optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:494
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1326
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1789
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE maxNum semantics.
Definition: APFloat.h:1360
bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Return true if the specified instruction is known to be a constant, or a vector of constants.
Definition: Utils.cpp:1192
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:198
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
Definition: Utils.cpp:1333
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:268
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
std::optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
Definition: Utils.cpp:415
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1135
SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
Definition: Utils.cpp:614
std::optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
Definition: Utils.cpp:1122
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:895
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition: Utils.cpp:945
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE minNum semantics.
Definition: APFloat.h:1349
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:36
std::optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
Definition: Utils.cpp:423
bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Definition: Utils.cpp:1302
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:184
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:481
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
Definition: Utils.cpp:1073
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1362
DiagnosticSeverity
Defines the different supported severity of a diagnostic.
@ DS_Warning
@ DS_Error
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:43
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition: Utils.cpp:1314
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:409
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1809
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:301
std::optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition: Utils.cpp:442
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:212
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1347
void salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI, MachineInstr &MI, ArrayRef< MachineOperand * > DbgUsers)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:468
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:960
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2018 minimum semantics.
Definition: APFloat.h:1371
std::optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1107
std::optional< SmallVector< unsigned > > ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI)
Tries to constant fold a G_CTLZ operation on Src.
Definition: Utils.cpp:793
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:212
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:712
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:262
#define MORE()
Definition: regcomp.c:252
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Simple struct used to hold a Register value and the instruction which defines it.
Definition: Utils.h:219
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
Definition: KnownBits.h:280
unsigned countMinPopulation() const
Returns the number of bits known to be one.
Definition: KnownBits.h:277
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:178