LLVM  10.0.0svn
Utils.cpp
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1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file This file implements the utility functions used by the GlobalISel
9 /// pipeline.
10 //===----------------------------------------------------------------------===//
11 
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/Twine.h"
24 #include "llvm/IR/Constants.h"
25 
26 #define DEBUG_TYPE "globalisel-utils"
27 
28 using namespace llvm;
29 
31  const TargetInstrInfo &TII,
32  const RegisterBankInfo &RBI, unsigned Reg,
33  const TargetRegisterClass &RegClass) {
34  if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
35  return MRI.createVirtualRegister(&RegClass);
36 
37  return Reg;
38 }
39 
41  const MachineFunction &MF, const TargetRegisterInfo &TRI,
43  const RegisterBankInfo &RBI, MachineInstr &InsertPt,
44  const TargetRegisterClass &RegClass, const MachineOperand &RegMO,
45  unsigned OpIdx) {
46  Register Reg = RegMO.getReg();
47  // Assume physical registers are properly constrained.
48  assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
49 
50  unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
51  // If we created a new virtual register because the class is not compatible
52  // then create a copy between the new and the old register.
53  if (ConstrainedReg != Reg) {
54  MachineBasicBlock::iterator InsertIt(&InsertPt);
55  MachineBasicBlock &MBB = *InsertPt.getParent();
56  if (RegMO.isUse()) {
57  BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
58  TII.get(TargetOpcode::COPY), ConstrainedReg)
59  .addReg(Reg);
60  } else {
61  assert(RegMO.isDef() && "Must be a definition");
62  BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
63  TII.get(TargetOpcode::COPY), Reg)
64  .addReg(ConstrainedReg);
65  }
66  }
67  return ConstrainedReg;
68 }
69 
71  const MachineFunction &MF, const TargetRegisterInfo &TRI,
73  const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
74  const MachineOperand &RegMO, unsigned OpIdx) {
75  Register Reg = RegMO.getReg();
76  // Assume physical registers are properly constrained.
77  assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
78 
79  const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
80  // Some of the target independent instructions, like COPY, may not impose any
81  // register class constraints on some of their operands: If it's a use, we can
82  // skip constraining as the instruction defining the register would constrain
83  // it.
84 
85  // We can't constrain unallocatable register classes, because we can't create
86  // virtual registers for these classes, so we need to let targets handled this
87  // case.
88  if (RegClass && !RegClass->isAllocatable())
89  RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI);
90 
91  if (!RegClass) {
92  assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
93  "Register class constraint is required unless either the "
94  "instruction is target independent or the operand is a use");
95  // FIXME: Just bailing out like this here could be not enough, unless we
96  // expect the users of this function to do the right thing for PHIs and
97  // COPY:
98  // v1 = COPY v0
99  // v2 = COPY v1
100  // v1 here may end up not being constrained at all. Please notice that to
101  // reproduce the issue we likely need a destination pattern of a selection
102  // rule producing such extra copies, not just an input GMIR with them as
103  // every existing target using selectImpl handles copies before calling it
104  // and they never reach this function.
105  return Reg;
106  }
107  return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass,
108  RegMO, OpIdx);
109 }
110 
112  const TargetInstrInfo &TII,
113  const TargetRegisterInfo &TRI,
114  const RegisterBankInfo &RBI) {
116  "A selected instruction is expected");
117  MachineBasicBlock &MBB = *I.getParent();
118  MachineFunction &MF = *MBB.getParent();
120 
121  for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
122  MachineOperand &MO = I.getOperand(OpI);
123 
124  // There's nothing to be done on non-register operands.
125  if (!MO.isReg())
126  continue;
127 
128  LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
129  assert(MO.isReg() && "Unsupported non-reg operand");
130 
131  Register Reg = MO.getReg();
132  // Physical registers don't need to be constrained.
134  continue;
135 
136  // Register operands with a value of 0 (e.g. predicate operands) don't need
137  // to be constrained.
138  if (Reg == 0)
139  continue;
140 
141  // If the operand is a vreg, we should constrain its regclass, and only
142  // insert COPYs if that's impossible.
143  // constrainOperandRegClass does that for us.
144  MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
145  MO, OpI));
146 
147  // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
148  // done.
149  if (MO.isUse()) {
150  int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
151  if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
152  I.tieOperands(DefIdx, OpI);
153  }
154  }
155  return true;
156 }
157 
159  const MachineRegisterInfo &MRI) {
160  // If we can move an instruction, we can remove it. Otherwise, it has
161  // a side-effect of some sort.
162  bool SawStore = false;
163  if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI())
164  return false;
165 
166  // Instructions without side-effects are dead iff they only define dead vregs.
167  for (auto &MO : MI.operands()) {
168  if (!MO.isReg() || !MO.isDef())
169  continue;
170 
171  Register Reg = MO.getReg();
172  if (Register::isPhysicalRegister(Reg) || !MRI.use_nodbg_empty(Reg))
173  return false;
174  }
175  return true;
176 }
177 
182 
183  // Print the function name explicitly if we don't have a debug location (which
184  // makes the diagnostic less useful) or if we're going to emit a raw error.
185  if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
186  R << (" (in function: " + MF.getName() + ")").str();
187 
188  if (TPC.isGlobalISelAbortEnabled())
190  else
191  MORE.emit(R);
192 }
193 
196  const char *PassName, StringRef Msg,
197  const MachineInstr &MI) {
198  MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
199  MI.getDebugLoc(), MI.getParent());
200  R << Msg;
201  // Printing MI is expensive; only do it if expensive remarks are enabled.
202  if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
203  R << ": " << ore::MNV("Inst", MI);
204  reportGISelFailure(MF, TPC, MORE, R);
205 }
206 
208  const MachineRegisterInfo &MRI) {
209  Optional<ValueAndVReg> ValAndVReg =
210  getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false);
211  assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
212  "Value found while looking through instrs");
213  if (!ValAndVReg)
214  return None;
215  return ValAndVReg->Value;
216 }
217 
219  unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
220  bool HandleFConstant) {
222  MachineInstr *MI;
223  auto IsConstantOpcode = [HandleFConstant](unsigned Opcode) {
224  return Opcode == TargetOpcode::G_CONSTANT ||
225  (HandleFConstant && Opcode == TargetOpcode::G_FCONSTANT);
226  };
227  auto GetImmediateValue = [HandleFConstant,
228  &MRI](const MachineInstr &MI) -> Optional<APInt> {
229  const MachineOperand &CstVal = MI.getOperand(1);
230  if (!CstVal.isImm() && !CstVal.isCImm() &&
231  (!HandleFConstant || !CstVal.isFPImm()))
232  return None;
233  if (!CstVal.isFPImm()) {
234  unsigned BitWidth =
235  MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
236  APInt Val = CstVal.isImm() ? APInt(BitWidth, CstVal.getImm())
237  : CstVal.getCImm()->getValue();
238  assert(Val.getBitWidth() == BitWidth &&
239  "Value bitwidth doesn't match definition type");
240  return Val;
241  }
242  return CstVal.getFPImm()->getValueAPF().bitcastToAPInt();
243  };
244  while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI->getOpcode()) &&
245  LookThroughInstrs) {
246  switch (MI->getOpcode()) {
247  case TargetOpcode::G_TRUNC:
248  case TargetOpcode::G_SEXT:
249  case TargetOpcode::G_ZEXT:
250  SeenOpcodes.push_back(std::make_pair(
251  MI->getOpcode(),
252  MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
253  VReg = MI->getOperand(1).getReg();
254  break;
255  case TargetOpcode::COPY:
256  VReg = MI->getOperand(1).getReg();
258  return None;
259  break;
260  case TargetOpcode::G_INTTOPTR:
261  VReg = MI->getOperand(1).getReg();
262  break;
263  default:
264  return None;
265  }
266  }
267  if (!MI || !IsConstantOpcode(MI->getOpcode()))
268  return None;
269 
270  Optional<APInt> MaybeVal = GetImmediateValue(*MI);
271  if (!MaybeVal)
272  return None;
273  APInt &Val = *MaybeVal;
274  while (!SeenOpcodes.empty()) {
275  std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val();
276  switch (OpcodeAndSize.first) {
277  case TargetOpcode::G_TRUNC:
278  Val = Val.trunc(OpcodeAndSize.second);
279  break;
280  case TargetOpcode::G_SEXT:
281  Val = Val.sext(OpcodeAndSize.second);
282  break;
283  case TargetOpcode::G_ZEXT:
284  Val = Val.zext(OpcodeAndSize.second);
285  break;
286  }
287  }
288 
289  if (Val.getBitWidth() > 64)
290  return None;
291 
292  return ValueAndVReg{Val.getSExtValue(), VReg};
293 }
294 
296  const MachineRegisterInfo &MRI) {
297  MachineInstr *MI = MRI.getVRegDef(VReg);
298  if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
299  return nullptr;
300  return MI->getOperand(1).getFPImm();
301 }
302 
304  const MachineRegisterInfo &MRI) {
305  auto *DefMI = MRI.getVRegDef(Reg);
306  auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
307  if (!DstTy.isValid())
308  return nullptr;
309  while (DefMI->getOpcode() == TargetOpcode::COPY) {
310  Register SrcReg = DefMI->getOperand(1).getReg();
311  auto SrcTy = MRI.getType(SrcReg);
312  if (!SrcTy.isValid() || SrcTy != DstTy)
313  break;
314  DefMI = MRI.getVRegDef(SrcReg);
315  }
316  return DefMI;
317 }
318 
320  const MachineRegisterInfo &MRI) {
322  return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr;
323 }
324 
325 APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
326  if (Size == 32)
327  return APFloat(float(Val));
328  if (Size == 64)
329  return APFloat(Val);
330  if (Size != 16)
331  llvm_unreachable("Unsupported FPConstant size");
332  bool Ignored;
333  APFloat APF(Val);
335  return APF;
336 }
337 
338 Optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode, const unsigned Op1,
339  const unsigned Op2,
340  const MachineRegisterInfo &MRI) {
341  auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI);
342  auto MaybeOp2Cst = getConstantVRegVal(Op2, MRI);
343  if (MaybeOp1Cst && MaybeOp2Cst) {
344  LLT Ty = MRI.getType(Op1);
345  APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true);
346  APInt C2(Ty.getSizeInBits(), *MaybeOp2Cst, true);
347  switch (Opcode) {
348  default:
349  break;
350  case TargetOpcode::G_ADD:
351  return C1 + C2;
352  case TargetOpcode::G_AND:
353  return C1 & C2;
354  case TargetOpcode::G_ASHR:
355  return C1.ashr(C2);
356  case TargetOpcode::G_LSHR:
357  return C1.lshr(C2);
358  case TargetOpcode::G_MUL:
359  return C1 * C2;
360  case TargetOpcode::G_OR:
361  return C1 | C2;
362  case TargetOpcode::G_SHL:
363  return C1 << C2;
364  case TargetOpcode::G_SUB:
365  return C1 - C2;
366  case TargetOpcode::G_XOR:
367  return C1 ^ C2;
368  case TargetOpcode::G_UDIV:
369  if (!C2.getBoolValue())
370  break;
371  return C1.udiv(C2);
372  case TargetOpcode::G_SDIV:
373  if (!C2.getBoolValue())
374  break;
375  return C1.sdiv(C2);
376  case TargetOpcode::G_UREM:
377  if (!C2.getBoolValue())
378  break;
379  return C1.urem(C2);
380  case TargetOpcode::G_SREM:
381  if (!C2.getBoolValue())
382  break;
383  return C1.srem(C2);
384  }
385  }
386  return None;
387 }
388 
390  bool SNaN) {
391  const MachineInstr *DefMI = MRI.getVRegDef(Val);
392  if (!DefMI)
393  return false;
394 
395  if (DefMI->getFlag(MachineInstr::FmNoNans))
396  return true;
397 
398  if (SNaN) {
399  // FP operations quiet. For now, just handle the ones inserted during
400  // legalization.
401  switch (DefMI->getOpcode()) {
402  case TargetOpcode::G_FPEXT:
403  case TargetOpcode::G_FPTRUNC:
404  case TargetOpcode::G_FCANONICALIZE:
405  return true;
406  default:
407  return false;
408  }
409  }
410 
411  return false;
412 }
413 
414 Optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode, const unsigned Op1,
415  uint64_t Imm,
416  const MachineRegisterInfo &MRI) {
417  auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI);
418  if (MaybeOp1Cst) {
419  LLT Ty = MRI.getType(Op1);
420  APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true);
421  switch (Opcode) {
422  default:
423  break;
424  case TargetOpcode::G_SEXT_INREG:
425  return C1.trunc(Imm).sext(C1.getBitWidth());
426  }
427  }
428  return None;
429 }
430 
433 }
434 
436  if (!Ty.isVector())
437  return MVT::getIntegerVT(Ty.getSizeInBits());
438 
439  return MVT::getVectorVT(
441  Ty.getNumElements());
442 }
443 
445  if (!Ty.isVector())
446  return LLT::scalar(Ty.getSizeInBits());
447 
448  return LLT::vector(Ty.getVectorNumElements(),
450 }
const NoneType None
Definition: None.h:23
static MVT getIntegerVT(unsigned BitWidth)
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:117
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:888
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:431
static MVT getVectorVT(MVT VT, unsigned NumElements)
APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
Definition: APInt.cpp:1647
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isVector() const
Return true if this is a vector value type.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const MachineFunctionProperties & getProperties() const
Get the function properties.
const ConstantFP * getConstantFPVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:295
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:179
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:912
APInt udiv(const APInt &RHS) const
Unsigned division operation.
Definition: APInt.cpp:1576
unsigned Reg
unsigned getVectorNumElements() const
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:865
unsigned const TargetRegisterInfo * TRI
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:476
bool isPHI() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:303
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1517
int64_t Value
Definition: Utils.h:118
bool isVector() const
void emit(DiagnosticInfoOptimizationBase &OptDiag)
Emit an optimization remark.
Holds all the information related to register banks.
const HexagonInstrInfo * TII
const ConstantFP * getFPImm() const
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const unsigned Op1, const unsigned Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:338
unsigned constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, unsigned Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:30
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
Target-Independent Code Generator Pass Configuration Options.
LLT getElementType() const
Returns the vector&#39;s element type. Only valid for vector types.
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:325
unsigned getSizeInBits() const
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1583
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:4483
bool allowExtraAnalysis(StringRef PassName) const
Whether we allow for extra compile-time budget to perform more analysis to be more informative...
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:137
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
MVT getVectorElementType() const
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
TargetInstrInfo - Interface to description of machine instruction set.
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
MVT getMVTForLLT(LLT Ty)
Get a rough equivalent of an MVT for a given LLT.
Definition: Utils.cpp:435
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
Definition: APInt.cpp:1669
Machine Value Type.
LLT getLLTForMVT(MVT Ty)
Get a rough equivalent of an LLT for a given MVT.
Definition: Utils.cpp:444
This file contains the declarations for the subclasses of Constant, which represent the different fla...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Represent the analysis usage information of a pass.
This file declares a class to represent arbitrary precision floating point values and provide a varie...
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:36
unsigned VReg
Definition: Utils.h:119
Optional< ValueAndVReg > getConstantVRegValWithLookThrough(unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool HandleFConstants=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_F/CONSTANT (LookThro...
Definition: Utils.cpp:218
void getLocation(StringRef &RelativePath, unsigned &Line, unsigned &Column) const
Return location information for this diagnostic in three parts: the relative source file path...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:319
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:970
const APFloat & getValueAPF() const
Definition: Constants.h:302
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:203
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition: APInt.h:946
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
static const fltSemantics & IEEEhalf() LLVM_READNONE
Definition: APFloat.cpp:152
The optimization diagnostic interface.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:374
#define MORE()
Definition: regcomp.c:252
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:111
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Class for arbitrary precision integers.
Definition: APInt.h:69
Optional< int64_t > getConstantVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:207
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:255
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:158
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const unsigned Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:414
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
APInt srem(const APInt &RHS) const
Function for signed remainder operation.
Definition: APInt.cpp:1739
#define I(x, y, z)
Definition: MD5.cpp:58
uint32_t Size
Definition: Profile.cpp:46
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Diagnostic information for missed-optimization remarks.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:30
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:219
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
APInt bitcastToAPInt() const
Definition: APFloat.h:1109
static LLT vector(uint16_t NumElements, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
const ConstantInt * getCImm() const
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:178
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:296
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.