LLVM  10.0.0svn
Utils.cpp
Go to the documentation of this file.
1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file This file implements the utility functions used by the GlobalISel
9 /// pipeline.
10 //===----------------------------------------------------------------------===//
11 
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/Twine.h"
24 #include "llvm/IR/Constants.h"
25 
26 #define DEBUG_TYPE "globalisel-utils"
27 
28 using namespace llvm;
29 
31  const TargetInstrInfo &TII,
32  const RegisterBankInfo &RBI, unsigned Reg,
33  const TargetRegisterClass &RegClass) {
34  if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
35  return MRI.createVirtualRegister(&RegClass);
36 
37  return Reg;
38 }
39 
41  const MachineFunction &MF, const TargetRegisterInfo &TRI,
43  const RegisterBankInfo &RBI, MachineInstr &InsertPt,
44  const TargetRegisterClass &RegClass, const MachineOperand &RegMO,
45  unsigned OpIdx) {
46  Register Reg = RegMO.getReg();
47  // Assume physical registers are properly constrained.
48  assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
49 
50  unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
51  // If we created a new virtual register because the class is not compatible
52  // then create a copy between the new and the old register.
53  if (ConstrainedReg != Reg) {
54  MachineBasicBlock::iterator InsertIt(&InsertPt);
55  MachineBasicBlock &MBB = *InsertPt.getParent();
56  if (RegMO.isUse()) {
57  BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
58  TII.get(TargetOpcode::COPY), ConstrainedReg)
59  .addReg(Reg);
60  } else {
61  assert(RegMO.isDef() && "Must be a definition");
62  BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
63  TII.get(TargetOpcode::COPY), Reg)
64  .addReg(ConstrainedReg);
65  }
66  }
67  return ConstrainedReg;
68 }
69 
71  const MachineFunction &MF, const TargetRegisterInfo &TRI,
73  const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
74  const MachineOperand &RegMO, unsigned OpIdx) {
75  Register Reg = RegMO.getReg();
76  // Assume physical registers are properly constrained.
77  assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
78 
79  const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
80  // Some of the target independent instructions, like COPY, may not impose any
81  // register class constraints on some of their operands: If it's a use, we can
82  // skip constraining as the instruction defining the register would constrain
83  // it.
84 
85  // We can't constrain unallocatable register classes, because we can't create
86  // virtual registers for these classes, so we need to let targets handled this
87  // case.
88  if (RegClass && !RegClass->isAllocatable())
89  RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI);
90 
91  if (!RegClass) {
92  assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
93  "Register class constraint is required unless either the "
94  "instruction is target independent or the operand is a use");
95  // FIXME: Just bailing out like this here could be not enough, unless we
96  // expect the users of this function to do the right thing for PHIs and
97  // COPY:
98  // v1 = COPY v0
99  // v2 = COPY v1
100  // v1 here may end up not being constrained at all. Please notice that to
101  // reproduce the issue we likely need a destination pattern of a selection
102  // rule producing such extra copies, not just an input GMIR with them as
103  // every existing target using selectImpl handles copies before calling it
104  // and they never reach this function.
105  return Reg;
106  }
107  return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass,
108  RegMO, OpIdx);
109 }
110 
112  const TargetInstrInfo &TII,
113  const TargetRegisterInfo &TRI,
114  const RegisterBankInfo &RBI) {
116  "A selected instruction is expected");
117  MachineBasicBlock &MBB = *I.getParent();
118  MachineFunction &MF = *MBB.getParent();
120 
121  for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
122  MachineOperand &MO = I.getOperand(OpI);
123 
124  // There's nothing to be done on non-register operands.
125  if (!MO.isReg())
126  continue;
127 
128  LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
129  assert(MO.isReg() && "Unsupported non-reg operand");
130 
131  Register Reg = MO.getReg();
132  // Physical registers don't need to be constrained.
134  continue;
135 
136  // Register operands with a value of 0 (e.g. predicate operands) don't need
137  // to be constrained.
138  if (Reg == 0)
139  continue;
140 
141  // If the operand is a vreg, we should constrain its regclass, and only
142  // insert COPYs if that's impossible.
143  // constrainOperandRegClass does that for us.
144  MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
145  MO, OpI));
146 
147  // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
148  // done.
149  if (MO.isUse()) {
150  int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
151  if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
152  I.tieOperands(DefIdx, OpI);
153  }
154  }
155  return true;
156 }
157 
159  const MachineRegisterInfo &MRI) {
160  // If we can move an instruction, we can remove it. Otherwise, it has
161  // a side-effect of some sort.
162  bool SawStore = false;
163  if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI())
164  return false;
165 
166  // Instructions without side-effects are dead iff they only define dead vregs.
167  for (auto &MO : MI.operands()) {
168  if (!MO.isReg() || !MO.isDef())
169  continue;
170 
171  Register Reg = MO.getReg();
172  if (Register::isPhysicalRegister(Reg) || !MRI.use_nodbg_empty(Reg))
173  return false;
174  }
175  return true;
176 }
177 
182 
183  // Print the function name explicitly if we don't have a debug location (which
184  // makes the diagnostic less useful) or if we're going to emit a raw error.
185  if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
186  R << (" (in function: " + MF.getName() + ")").str();
187 
188  if (TPC.isGlobalISelAbortEnabled())
190  else
191  MORE.emit(R);
192 }
193 
196  const char *PassName, StringRef Msg,
197  const MachineInstr &MI) {
198  MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
199  MI.getDebugLoc(), MI.getParent());
200  R << Msg;
201  // Printing MI is expensive; only do it if expensive remarks are enabled.
202  if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
203  R << ": " << ore::MNV("Inst", MI);
204  reportGISelFailure(MF, TPC, MORE, R);
205 }
206 
208  const MachineRegisterInfo &MRI) {
209  Optional<ValueAndVReg> ValAndVReg =
210  getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false);
211  assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
212  "Value found while looking through instrs");
213  if (!ValAndVReg)
214  return None;
215  return ValAndVReg->Value;
216 }
217 
219  unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
221  MachineInstr *MI;
222  while ((MI = MRI.getVRegDef(VReg)) &&
223  MI->getOpcode() != TargetOpcode::G_CONSTANT && LookThroughInstrs) {
224  switch (MI->getOpcode()) {
225  case TargetOpcode::G_TRUNC:
226  case TargetOpcode::G_SEXT:
227  case TargetOpcode::G_ZEXT:
228  SeenOpcodes.push_back(std::make_pair(
229  MI->getOpcode(),
230  MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
231  VReg = MI->getOperand(1).getReg();
232  break;
233  case TargetOpcode::COPY:
234  VReg = MI->getOperand(1).getReg();
236  return None;
237  break;
238  case TargetOpcode::G_INTTOPTR:
239  VReg = MI->getOperand(1).getReg();
240  break;
241  default:
242  return None;
243  }
244  }
245  if (!MI || MI->getOpcode() != TargetOpcode::G_CONSTANT ||
246  (!MI->getOperand(1).isImm() && !MI->getOperand(1).isCImm()))
247  return None;
248 
249  const MachineOperand &CstVal = MI->getOperand(1);
250  unsigned BitWidth = MRI.getType(MI->getOperand(0).getReg()).getSizeInBits();
251  APInt Val = CstVal.isImm() ? APInt(BitWidth, CstVal.getImm())
252  : CstVal.getCImm()->getValue();
253  assert(Val.getBitWidth() == BitWidth &&
254  "Value bitwidth doesn't match definition type");
255  while (!SeenOpcodes.empty()) {
256  std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val();
257  switch (OpcodeAndSize.first) {
258  case TargetOpcode::G_TRUNC:
259  Val = Val.trunc(OpcodeAndSize.second);
260  break;
261  case TargetOpcode::G_SEXT:
262  Val = Val.sext(OpcodeAndSize.second);
263  break;
264  case TargetOpcode::G_ZEXT:
265  Val = Val.zext(OpcodeAndSize.second);
266  break;
267  }
268  }
269 
270  if (Val.getBitWidth() > 64)
271  return None;
272 
273  return ValueAndVReg{Val.getSExtValue(), VReg};
274 }
275 
277  const MachineRegisterInfo &MRI) {
278  MachineInstr *MI = MRI.getVRegDef(VReg);
279  if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
280  return nullptr;
281  return MI->getOperand(1).getFPImm();
282 }
283 
285  const MachineRegisterInfo &MRI) {
286  auto *DefMI = MRI.getVRegDef(Reg);
287  auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
288  if (!DstTy.isValid())
289  return nullptr;
290  while (DefMI->getOpcode() == TargetOpcode::COPY) {
291  Register SrcReg = DefMI->getOperand(1).getReg();
292  auto SrcTy = MRI.getType(SrcReg);
293  if (!SrcTy.isValid() || SrcTy != DstTy)
294  break;
295  DefMI = MRI.getVRegDef(SrcReg);
296  }
297  return DefMI;
298 }
299 
301  const MachineRegisterInfo &MRI) {
303  return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr;
304 }
305 
306 APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
307  if (Size == 32)
308  return APFloat(float(Val));
309  if (Size == 64)
310  return APFloat(Val);
311  if (Size != 16)
312  llvm_unreachable("Unsupported FPConstant size");
313  bool Ignored;
314  APFloat APF(Val);
316  return APF;
317 }
318 
319 Optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode, const unsigned Op1,
320  const unsigned Op2,
321  const MachineRegisterInfo &MRI) {
322  auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI);
323  auto MaybeOp2Cst = getConstantVRegVal(Op2, MRI);
324  if (MaybeOp1Cst && MaybeOp2Cst) {
325  LLT Ty = MRI.getType(Op1);
326  APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true);
327  APInt C2(Ty.getSizeInBits(), *MaybeOp2Cst, true);
328  switch (Opcode) {
329  default:
330  break;
331  case TargetOpcode::G_ADD:
332  return C1 + C2;
333  case TargetOpcode::G_AND:
334  return C1 & C2;
335  case TargetOpcode::G_ASHR:
336  return C1.ashr(C2);
337  case TargetOpcode::G_LSHR:
338  return C1.lshr(C2);
339  case TargetOpcode::G_MUL:
340  return C1 * C2;
341  case TargetOpcode::G_OR:
342  return C1 | C2;
343  case TargetOpcode::G_SHL:
344  return C1 << C2;
345  case TargetOpcode::G_SUB:
346  return C1 - C2;
347  case TargetOpcode::G_XOR:
348  return C1 ^ C2;
349  case TargetOpcode::G_UDIV:
350  if (!C2.getBoolValue())
351  break;
352  return C1.udiv(C2);
353  case TargetOpcode::G_SDIV:
354  if (!C2.getBoolValue())
355  break;
356  return C1.sdiv(C2);
357  case TargetOpcode::G_UREM:
358  if (!C2.getBoolValue())
359  break;
360  return C1.urem(C2);
361  case TargetOpcode::G_SREM:
362  if (!C2.getBoolValue())
363  break;
364  return C1.srem(C2);
365  }
366  }
367  return None;
368 }
369 
371  bool SNaN) {
372  const MachineInstr *DefMI = MRI.getVRegDef(Val);
373  if (!DefMI)
374  return false;
375 
376  if (DefMI->getFlag(MachineInstr::FmNoNans))
377  return true;
378 
379  if (SNaN) {
380  // FP operations quiet. For now, just handle the ones inserted during
381  // legalization.
382  switch (DefMI->getOpcode()) {
383  case TargetOpcode::G_FPEXT:
384  case TargetOpcode::G_FPTRUNC:
385  case TargetOpcode::G_FCANONICALIZE:
386  return true;
387  default:
388  return false;
389  }
390  }
391 
392  return false;
393 }
394 
395 Optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode, const unsigned Op1,
396  uint64_t Imm,
397  const MachineRegisterInfo &MRI) {
398  auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI);
399  if (MaybeOp1Cst) {
400  LLT Ty = MRI.getType(Op1);
401  APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true);
402  switch (Opcode) {
403  default:
404  break;
405  case TargetOpcode::G_SEXT_INREG:
406  return C1.trunc(Imm).sext(C1.getBitWidth());
407  }
408  }
409  return None;
410 }
411 
414 }
415 
417  if (!Ty.isVector())
418  return MVT::getIntegerVT(Ty.getSizeInBits());
419 
420  return MVT::getVectorVT(
422  Ty.getNumElements());
423 }
424 
426  if (!Ty.isVector())
427  return LLT::scalar(Ty.getSizeInBits());
428 
429  return LLT::vector(Ty.getVectorNumElements(),
431 }
const NoneType None
Definition: None.h:23
static MVT getIntegerVT(unsigned BitWidth)
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:117
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:836
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:412
static MVT getVectorVT(MVT VT, unsigned NumElements)
APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
Definition: APInt.cpp:1595
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isVector() const
Return true if this is a vector value type.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
const MachineFunctionProperties & getProperties() const
Get the function properties.
const ConstantFP * getConstantFPVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:276
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:178
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:860
APInt udiv(const APInt &RHS) const
Unsigned division operation.
Definition: APInt.cpp:1524
unsigned Reg
unsigned getVectorNumElements() const
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:813
unsigned const TargetRegisterInfo * TRI
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:477
bool isPHI() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:284
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1515
int64_t Value
Definition: Utils.h:118
bool isVector() const
void emit(DiagnosticInfoOptimizationBase &OptDiag)
Emit an optimization remark.
Holds all the information related to register banks.
const HexagonInstrInfo * TII
const ConstantFP * getFPImm() const
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const unsigned Op1, const unsigned Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:319
unsigned constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, unsigned Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:30
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
Target-Independent Code Generator Pass Configuration Options.
LLT getElementType() const
Returns the vector&#39;s element type. Only valid for vector types.
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:306
unsigned getSizeInBits() const
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1581
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:4483
bool allowExtraAnalysis(StringRef PassName) const
Whether we allow for extra compile-time budget to perform more analysis to be more informative...
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:137
void setReg(Register Reg)
Change the register this operand corresponds to.
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
MVT getVectorElementType() const
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
TargetInstrInfo - Interface to description of machine instruction set.
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
MVT getMVTForLLT(LLT Ty)
Get a rough equivalent of an MVT for a given LLT.
Definition: Utils.cpp:416
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
Definition: APInt.cpp:1617
Machine Value Type.
LLT getLLTForMVT(MVT Ty)
Get a rough equivalent of an LLT for a given MVT.
Definition: Utils.cpp:425
This file contains the declarations for the subclasses of Constant, which represent the different fla...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
bool isCImm() const
isCImm - Test if this is a MO_CImmediate operand.
Represent the analysis usage information of a pass.
This file declares a class to represent arbitrary precision floating point values and provide a varie...
bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:36
unsigned VReg
Definition: Utils.h:119
void getLocation(StringRef &RelativePath, unsigned &Line, unsigned &Column) const
Return location information for this diagnostic in three parts: the relative source file path...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:300
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:970
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:202
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition: APInt.h:946
Optional< ValueAndVReg > getConstantVRegValWithLookThrough(unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT (LookThroug...
Definition: Utils.cpp:218
bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
static const fltSemantics & IEEEhalf() LLVM_READNONE
Definition: APFloat.cpp:152
The optimization diagnostic interface.
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:374
#define MORE()
Definition: regcomp.c:252
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:111
int64_t getImm() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Class for arbitrary precision integers.
Definition: APInt.h:69
Optional< int64_t > getConstantVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:207
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:256
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:158
Representation of each machine instruction.
Definition: MachineInstr.h:64
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const unsigned Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:395
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
APInt srem(const APInt &RHS) const
Function for signed remainder operation.
Definition: APInt.cpp:1687
#define I(x, y, z)
Definition: MD5.cpp:58
uint32_t Size
Definition: Profile.cpp:46
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Diagnostic information for missed-optimization remarks.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:30
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:218
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
static LLT vector(uint16_t NumElements, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
const ConstantInt * getCImm() const
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:178
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:297
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.