LLVM  9.0.0svn
MachineIRBuilder.cpp
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the MachineIRBuidler class.
10 //===----------------------------------------------------------------------===//
13 
22 #include "llvm/IR/DebugInfo.h"
23 
24 using namespace llvm;
25 
27  State.MF = &MF;
28  State.MBB = nullptr;
29  State.MRI = &MF.getRegInfo();
30  State.TII = MF.getSubtarget().getInstrInfo();
31  State.DL = DebugLoc();
33  State.Observer = nullptr;
34 }
35 
37  State.MBB = &MBB;
38  State.II = MBB.end();
39  assert(&getMF() == MBB.getParent() &&
40  "Basic block is in a different function");
41 }
42 
44  assert(MI.getParent() && "Instruction is not part of a basic block");
45  setMBB(*MI.getParent());
46  State.II = MI.getIterator();
47 }
48 
50 
53  assert(MBB.getParent() == &getMF() &&
54  "Basic block is in a different function");
55  State.MBB = &MBB;
56  State.II = II;
57 }
58 
59 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {
60  if (State.Observer)
61  State.Observer->createdInstr(*InsertedInstr);
62 }
63 
65  State.Observer = &Observer;
66 }
67 
69 
70 //------------------------------------------------------------------------------
71 // Build instruction variants.
72 //------------------------------------------------------------------------------
73 
75  return insertInstr(buildInstrNoInsert(Opcode));
76 }
77 
79  MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
80  return MIB;
81 }
82 
84  getMBB().insert(getInsertPt(), MIB);
85  recordInsertion(MIB);
86  return MIB;
87 }
88 
91  const MDNode *Expr) {
92  assert(isa<DILocalVariable>(Variable) && "not a variable");
93  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
94  assert(
95  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
96  "Expected inlined-at fields to agree");
97  return insertInstr(BuildMI(getMF(), getDL(),
98  getTII().get(TargetOpcode::DBG_VALUE),
99  /*IsIndirect*/ false, Reg, Variable, Expr));
100 }
101 
104  const MDNode *Expr) {
105  assert(isa<DILocalVariable>(Variable) && "not a variable");
106  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
107  assert(
108  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
109  "Expected inlined-at fields to agree");
110  return insertInstr(BuildMI(getMF(), getDL(),
111  getTII().get(TargetOpcode::DBG_VALUE),
112  /*IsIndirect*/ true, Reg, Variable, Expr));
113 }
114 
116  const MDNode *Variable,
117  const MDNode *Expr) {
118  assert(isa<DILocalVariable>(Variable) && "not a variable");
119  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
120  assert(
121  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
122  "Expected inlined-at fields to agree");
123  return buildInstr(TargetOpcode::DBG_VALUE)
124  .addFrameIndex(FI)
125  .addImm(0)
126  .addMetadata(Variable)
127  .addMetadata(Expr);
128 }
129 
131  const MDNode *Variable,
132  const MDNode *Expr) {
133  assert(isa<DILocalVariable>(Variable) && "not a variable");
134  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
135  assert(
136  cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(getDL()) &&
137  "Expected inlined-at fields to agree");
138  auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
139  if (auto *CI = dyn_cast<ConstantInt>(&C)) {
140  if (CI->getBitWidth() > 64)
141  MIB.addCImm(CI);
142  else
143  MIB.addImm(CI->getZExtValue());
144  } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
145  MIB.addFPImm(CFP);
146  } else {
147  // Insert %noreg if we didn't find a usable constant and had to drop it.
148  MIB.addReg(0U);
149  }
150 
151  return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
152 }
153 
155  assert(isa<DILabel>(Label) && "not a label");
156  assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.DL) &&
157  "Expected inlined-at fields to agree");
158  auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
159 
160  return MIB.addMetadata(Label);
161 }
162 
164  assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
165  return buildInstr(TargetOpcode::G_FRAME_INDEX)
166  .addDef(Res)
167  .addFrameIndex(Idx);
168 }
169 
171  const GlobalValue *GV) {
172  assert(getMRI()->getType(Res).isPointer() && "invalid operand type");
173  assert(getMRI()->getType(Res).getAddressSpace() ==
174  GV->getType()->getAddressSpace() &&
175  "address space mismatch");
176 
177  return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
178  .addDef(Res)
179  .addGlobalAddress(GV);
180 }
181 
182 void MachineIRBuilder::validateBinaryOp(const LLT &Res, const LLT &Op0,
183  const LLT &Op1) {
184  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
185  assert((Res == Op0 && Res == Op1) && "type mismatch");
186 }
187 
188 void MachineIRBuilder::validateShiftOp(const LLT &Res, const LLT &Op0,
189  const LLT &Op1) {
190  assert((Res.isScalar() || Res.isVector()) && "invalid operand type");
191  assert((Res == Op0) && "type mismatch");
192 }
193 
195  unsigned Op1) {
196  assert(getMRI()->getType(Res).isPointer() &&
197  getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
198  assert(getMRI()->getType(Op1).isScalar() && "invalid offset type");
199 
200  return buildInstr(TargetOpcode::G_GEP)
201  .addDef(Res)
202  .addUse(Op0)
203  .addUse(Op1);
204 }
205 
207 MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
208  const LLT &ValueTy, uint64_t Value) {
209  assert(Res == 0 && "Res is a result argument");
210  assert(ValueTy.isScalar() && "invalid offset type");
211 
212  if (Value == 0) {
213  Res = Op0;
214  return None;
215  }
216 
218  auto Cst = buildConstant(ValueTy, Value);
219  return buildGEP(Res, Op0, Cst.getReg(0));
220 }
221 
223  uint32_t NumBits) {
224  assert(getMRI()->getType(Res).isPointer() &&
225  getMRI()->getType(Res) == getMRI()->getType(Op0) && "type mismatch");
226 
227  return buildInstr(TargetOpcode::G_PTR_MASK)
228  .addDef(Res)
229  .addUse(Op0)
230  .addImm(NumBits);
231 }
232 
234  return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
235 }
236 
238  assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");
239  return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
240 }
241 
243  const SrcOp &Op) {
244  return buildInstr(TargetOpcode::COPY, Res, Op);
245 }
246 
248  const ConstantInt &Val) {
249  LLT Ty = Res.getLLTTy(*getMRI());
250  LLT EltTy = Ty.getScalarType();
251  assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
252  "creating constant with the wrong size");
253 
254  if (Ty.isVector()) {
255  auto Const = buildInstr(TargetOpcode::G_CONSTANT)
256  .addDef(getMRI()->createGenericVirtualRegister(EltTy))
257  .addCImm(&Val);
258  return buildSplatVector(Res, Const);
259  }
260 
261  auto Const = buildInstr(TargetOpcode::G_CONSTANT);
262  Res.addDefToMIB(*getMRI(), Const);
263  Const.addCImm(&Val);
264  return Const;
265 }
266 
268  int64_t Val) {
269  auto IntN = IntegerType::get(getMF().getFunction().getContext(),
271  ConstantInt *CI = ConstantInt::get(IntN, Val, true);
272  return buildConstant(Res, *CI);
273 }
274 
276  const ConstantFP &Val) {
277  LLT Ty = Res.getLLTTy(*getMRI());
278  LLT EltTy = Ty.getScalarType();
279 
281  == EltTy.getSizeInBits() &&
282  "creating fconstant with the wrong size");
283 
284  assert(!Ty.isPointer() && "invalid operand type");
285 
286  if (Ty.isVector()) {
287  auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
288  .addDef(getMRI()->createGenericVirtualRegister(EltTy))
289  .addFPImm(&Val);
290 
291  return buildSplatVector(Res, Const);
292  }
293 
294  auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
295  Res.addDefToMIB(*getMRI(), Const);
296  Const.addFPImm(&Val);
297  return Const;
298 }
299 
301  const APInt &Val) {
302  ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Val);
303  return buildConstant(Res, *CI);
304 }
305 
307  double Val) {
308  LLT DstTy = Res.getLLTTy(*getMRI());
309  auto &Ctx = getMF().getFunction().getContext();
310  auto *CFP =
312  return buildFConstant(Res, *CFP);
313 }
314 
316  const APFloat &Val) {
317  auto &Ctx = getMF().getFunction().getContext();
318  auto *CFP = ConstantFP::get(Ctx, Val);
319  return buildFConstant(Res, *CFP);
320 }
321 
323  MachineBasicBlock &Dest) {
324  assert(getMRI()->getType(Tst).isScalar() && "invalid operand type");
325 
326  return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
327 }
328 
330  MachineMemOperand &MMO) {
331  return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
332 }
333 
335  unsigned Res,
336  unsigned Addr,
337  MachineMemOperand &MMO) {
338  assert(getMRI()->getType(Res).isValid() && "invalid operand type");
339  assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
340 
341  return buildInstr(Opcode)
342  .addDef(Res)
343  .addUse(Addr)
344  .addMemOperand(&MMO);
345 }
346 
348  MachineMemOperand &MMO) {
349  assert(getMRI()->getType(Val).isValid() && "invalid operand type");
350  assert(getMRI()->getType(Addr).isPointer() && "invalid operand type");
351 
352  return buildInstr(TargetOpcode::G_STORE)
353  .addUse(Val)
354  .addUse(Addr)
355  .addMemOperand(&MMO);
356 }
357 
359  const DstOp &CarryOut,
360  const SrcOp &Op0,
361  const SrcOp &Op1) {
362  return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
363 }
364 
366  const DstOp &CarryOut,
367  const SrcOp &Op0,
368  const SrcOp &Op1,
369  const SrcOp &CarryIn) {
370  return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
371  {Op0, Op1, CarryIn});
372 }
373 
375  const SrcOp &Op) {
376  return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);
377 }
378 
380  const SrcOp &Op) {
381  return buildInstr(TargetOpcode::G_SEXT, Res, Op);
382 }
383 
385  const SrcOp &Op) {
386  return buildInstr(TargetOpcode::G_ZEXT, Res, Op);
387 }
388 
389 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const {
390  const auto *TLI = getMF().getSubtarget().getTargetLowering();
391  switch (TLI->getBooleanContents(IsVec, IsFP)) {
393  return TargetOpcode::G_SEXT;
395  return TargetOpcode::G_ZEXT;
396  default:
397  return TargetOpcode::G_ANYEXT;
398  }
399 }
400 
402  const SrcOp &Op,
403  bool IsFP) {
404  unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP);
405  return buildInstr(ExtOp, Res, Op);
406 }
407 
409  const DstOp &Res,
410  const SrcOp &Op) {
411  assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
412  TargetOpcode::G_SEXT == ExtOpc) &&
413  "Expecting Extending Opc");
414  assert(Res.getLLTTy(*getMRI()).isScalar() ||
415  Res.getLLTTy(*getMRI()).isVector());
416  assert(Res.getLLTTy(*getMRI()).isScalar() ==
417  Op.getLLTTy(*getMRI()).isScalar());
418 
419  unsigned Opcode = TargetOpcode::COPY;
420  if (Res.getLLTTy(*getMRI()).getSizeInBits() >
421  Op.getLLTTy(*getMRI()).getSizeInBits())
422  Opcode = ExtOpc;
423  else if (Res.getLLTTy(*getMRI()).getSizeInBits() <
424  Op.getLLTTy(*getMRI()).getSizeInBits())
425  Opcode = TargetOpcode::G_TRUNC;
426  else
427  assert(Res.getLLTTy(*getMRI()) == Op.getLLTTy(*getMRI()));
428 
429  return buildInstr(Opcode, Res, Op);
430 }
431 
433  const SrcOp &Op) {
434  return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op);
435 }
436 
438  const SrcOp &Op) {
439  return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op);
440 }
441 
443  const SrcOp &Op) {
444  return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op);
445 }
446 
448  const SrcOp &Src) {
449  LLT SrcTy = Src.getLLTTy(*getMRI());
450  LLT DstTy = Dst.getLLTTy(*getMRI());
451  if (SrcTy == DstTy)
452  return buildCopy(Dst, Src);
453 
454  unsigned Opcode;
455  if (SrcTy.isPointer() && DstTy.isScalar())
456  Opcode = TargetOpcode::G_PTRTOINT;
457  else if (DstTy.isPointer() && SrcTy.isScalar())
458  Opcode = TargetOpcode::G_INTTOPTR;
459  else {
460  assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
461  Opcode = TargetOpcode::G_BITCAST;
462  }
463 
464  return buildInstr(Opcode, Dst, Src);
465 }
466 
468  const SrcOp &Src,
469  uint64_t Index) {
470  LLT SrcTy = Src.getLLTTy(*getMRI());
471  LLT DstTy = Dst.getLLTTy(*getMRI());
472 
473 #ifndef NDEBUG
474  assert(SrcTy.isValid() && "invalid operand type");
475  assert(DstTy.isValid() && "invalid operand type");
476  assert(Index + DstTy.getSizeInBits() <= SrcTy.getSizeInBits() &&
477  "extracting off end of register");
478 #endif
479 
480  if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {
481  assert(Index == 0 && "insertion past the end of a register");
482  return buildCast(Dst, Src);
483  }
484 
485  auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
486  Dst.addDefToMIB(*getMRI(), Extract);
487  Src.addSrcToMIB(Extract);
488  Extract.addImm(Index);
489  return Extract;
490 }
491 
493  ArrayRef<uint64_t> Indices) {
494 #ifndef NDEBUG
495  assert(Ops.size() == Indices.size() && "incompatible args");
496  assert(!Ops.empty() && "invalid trivial sequence");
497  assert(std::is_sorted(Indices.begin(), Indices.end()) &&
498  "sequence offsets must be in ascending order");
499 
500  assert(getMRI()->getType(Res).isValid() && "invalid operand type");
501  for (auto Op : Ops)
502  assert(getMRI()->getType(Op).isValid() && "invalid operand type");
503 #endif
504 
505  LLT ResTy = getMRI()->getType(Res);
506  LLT OpTy = getMRI()->getType(Ops[0]);
507  unsigned OpSize = OpTy.getSizeInBits();
508  bool MaybeMerge = true;
509  for (unsigned i = 0; i < Ops.size(); ++i) {
510  if (getMRI()->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
511  MaybeMerge = false;
512  break;
513  }
514  }
515 
516  if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
517  buildMerge(Res, Ops);
518  return;
519  }
520 
521  unsigned ResIn = getMRI()->createGenericVirtualRegister(ResTy);
522  buildUndef(ResIn);
523 
524  for (unsigned i = 0; i < Ops.size(); ++i) {
525  unsigned ResOut = i + 1 == Ops.size()
526  ? Res
528  buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
529  ResIn = ResOut;
530  }
531 }
532 
534  return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
535 }
536 
538  ArrayRef<unsigned> Ops) {
539  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<SrcOp>,
540  // we need some temporary storage for the DstOp objects. Here we use a
541  // sufficiently large SmallVector to not go through the heap.
542  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
543  return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
544 }
545 
547  const SrcOp &Op) {
548  // Unfortunately to convert from ArrayRef<LLT> to ArrayRef<DstOp>,
549  // we need some temporary storage for the DstOp objects. Here we use a
550  // sufficiently large SmallVector to not go through the heap.
551  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
552  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
553 }
554 
556  const SrcOp &Op) {
557  unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
559  for (unsigned I = 0; I != NumReg; ++I)
560  TmpVec.push_back(getMRI()->createGenericVirtualRegister(Res));
561  return buildUnmerge(TmpVec, Op);
562 }
563 
565  const SrcOp &Op) {
566  // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<DstOp>,
567  // we need some temporary storage for the DstOp objects. Here we use a
568  // sufficiently large SmallVector to not go through the heap.
569  SmallVector<DstOp, 8> TmpVec(Res.begin(), Res.end());
570  return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);
571 }
572 
574  ArrayRef<unsigned> Ops) {
575  // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
576  // we need some temporary storage for the DstOp objects. Here we use a
577  // sufficiently large SmallVector to not go through the heap.
578  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
579  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
580 }
581 
583  const SrcOp &Src) {
584  SmallVector<SrcOp, 8> TmpVec(Res.getLLTTy(*getMRI()).getNumElements(), Src);
585  return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
586 }
587 
590  ArrayRef<unsigned> Ops) {
591  // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
592  // we need some temporary storage for the DstOp objects. Here we use a
593  // sufficiently large SmallVector to not go through the heap.
594  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
595  return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
596 }
597 
600  // Unfortunately to convert from ArrayRef<unsigned> to ArrayRef<SrcOp>,
601  // we need some temporary storage for the DstOp objects. Here we use a
602  // sufficiently large SmallVector to not go through the heap.
603  SmallVector<SrcOp, 8> TmpVec(Ops.begin(), Ops.end());
604  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
605 }
606 
608  unsigned Op, unsigned Index) {
609  assert(Index + getMRI()->getType(Op).getSizeInBits() <=
610  getMRI()->getType(Res).getSizeInBits() &&
611  "insertion past the end of a register");
612 
613  if (getMRI()->getType(Res).getSizeInBits() ==
614  getMRI()->getType(Op).getSizeInBits()) {
615  return buildCast(Res, Op);
616  }
617 
618  return buildInstr(TargetOpcode::G_INSERT)
619  .addDef(Res)
620  .addUse(Src)
621  .addUse(Op)
622  .addImm(Index);
623 }
624 
626  ArrayRef<unsigned> ResultRegs,
627  bool HasSideEffects) {
628  auto MIB =
629  buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
630  : TargetOpcode::G_INTRINSIC);
631  for (unsigned ResultReg : ResultRegs)
632  MIB.addDef(ResultReg);
633  MIB.addIntrinsicID(ID);
634  return MIB;
635 }
636 
639  bool HasSideEffects) {
640  auto MIB =
641  buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
642  : TargetOpcode::G_INTRINSIC);
643  for (DstOp Result : Results)
644  Result.addDefToMIB(*getMRI(), MIB);
645  MIB.addIntrinsicID(ID);
646  return MIB;
647 }
648 
650  const SrcOp &Op) {
651  return buildInstr(TargetOpcode::G_TRUNC, Res, Op);
652 }
653 
655  const SrcOp &Op) {
656  return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op);
657 }
658 
660  const DstOp &Res,
661  const SrcOp &Op0,
662  const SrcOp &Op1) {
663  return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
664 }
665 
667  const DstOp &Res,
668  const SrcOp &Op0,
669  const SrcOp &Op1) {
670 
671  return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1});
672 }
673 
675  const SrcOp &Tst,
676  const SrcOp &Op0,
677  const SrcOp &Op1) {
678 
679  return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1});
680 }
681 
684  const SrcOp &Elt, const SrcOp &Idx) {
685  return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});
686 }
687 
690  const SrcOp &Idx) {
691  return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});
692 }
693 
695  unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal,
696  unsigned NewVal, MachineMemOperand &MMO) {
697 #ifndef NDEBUG
698  LLT OldValResTy = getMRI()->getType(OldValRes);
699  LLT SuccessResTy = getMRI()->getType(SuccessRes);
700  LLT AddrTy = getMRI()->getType(Addr);
701  LLT CmpValTy = getMRI()->getType(CmpVal);
702  LLT NewValTy = getMRI()->getType(NewVal);
703  assert(OldValResTy.isScalar() && "invalid operand type");
704  assert(SuccessResTy.isScalar() && "invalid operand type");
705  assert(AddrTy.isPointer() && "invalid operand type");
706  assert(CmpValTy.isValid() && "invalid operand type");
707  assert(NewValTy.isValid() && "invalid operand type");
708  assert(OldValResTy == CmpValTy && "type mismatch");
709  assert(OldValResTy == NewValTy && "type mismatch");
710 #endif
711 
712  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
713  .addDef(OldValRes)
714  .addDef(SuccessRes)
715  .addUse(Addr)
716  .addUse(CmpVal)
717  .addUse(NewVal)
718  .addMemOperand(&MMO);
719 }
720 
722 MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
723  unsigned CmpVal, unsigned NewVal,
724  MachineMemOperand &MMO) {
725 #ifndef NDEBUG
726  LLT OldValResTy = getMRI()->getType(OldValRes);
727  LLT AddrTy = getMRI()->getType(Addr);
728  LLT CmpValTy = getMRI()->getType(CmpVal);
729  LLT NewValTy = getMRI()->getType(NewVal);
730  assert(OldValResTy.isScalar() && "invalid operand type");
731  assert(AddrTy.isPointer() && "invalid operand type");
732  assert(CmpValTy.isValid() && "invalid operand type");
733  assert(NewValTy.isValid() && "invalid operand type");
734  assert(OldValResTy == CmpValTy && "type mismatch");
735  assert(OldValResTy == NewValTy && "type mismatch");
736 #endif
737 
738  return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
739  .addDef(OldValRes)
740  .addUse(Addr)
741  .addUse(CmpVal)
742  .addUse(NewVal)
743  .addMemOperand(&MMO);
744 }
745 
747  unsigned OldValRes,
748  unsigned Addr,
749  unsigned Val,
750  MachineMemOperand &MMO) {
751 #ifndef NDEBUG
752  LLT OldValResTy = getMRI()->getType(OldValRes);
753  LLT AddrTy = getMRI()->getType(Addr);
754  LLT ValTy = getMRI()->getType(Val);
755  assert(OldValResTy.isScalar() && "invalid operand type");
756  assert(AddrTy.isPointer() && "invalid operand type");
757  assert(ValTy.isValid() && "invalid operand type");
758  assert(OldValResTy == ValTy && "type mismatch");
759 #endif
760 
761  return buildInstr(Opcode)
762  .addDef(OldValRes)
763  .addUse(Addr)
764  .addUse(Val)
765  .addMemOperand(&MMO);
766 }
767 
769 MachineIRBuilder::buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
770  unsigned Val, MachineMemOperand &MMO) {
771  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
772  MMO);
773 }
775 MachineIRBuilder::buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
776  unsigned Val, MachineMemOperand &MMO) {
777  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
778  MMO);
779 }
781 MachineIRBuilder::buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
782  unsigned Val, MachineMemOperand &MMO) {
783  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
784  MMO);
785 }
787 MachineIRBuilder::buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
788  unsigned Val, MachineMemOperand &MMO) {
789  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
790  MMO);
791 }
793 MachineIRBuilder::buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
794  unsigned Val, MachineMemOperand &MMO) {
795  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
796  MMO);
797 }
799  unsigned Addr,
800  unsigned Val,
801  MachineMemOperand &MMO) {
802  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
803  MMO);
804 }
806 MachineIRBuilder::buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
807  unsigned Val, MachineMemOperand &MMO) {
808  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
809  MMO);
810 }
812 MachineIRBuilder::buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
813  unsigned Val, MachineMemOperand &MMO) {
814  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
815  MMO);
816 }
818 MachineIRBuilder::buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
819  unsigned Val, MachineMemOperand &MMO) {
820  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
821  MMO);
822 }
824 MachineIRBuilder::buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
825  unsigned Val, MachineMemOperand &MMO) {
826  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
827  MMO);
828 }
830 MachineIRBuilder::buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
831  unsigned Val, MachineMemOperand &MMO) {
832  return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
833  MMO);
834 }
835 
838 #ifndef NDEBUG
839  assert(getMRI()->getType(Res).isPointer() && "invalid res type");
840 #endif
841 
842  return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
843 }
844 
845 void MachineIRBuilder::validateTruncExt(const LLT &DstTy, const LLT &SrcTy,
846  bool IsExtend) {
847 #ifndef NDEBUG
848  if (DstTy.isVector()) {
849  assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");
850  assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
851  "different number of elements in a trunc/ext");
852  } else
853  assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
854 
855  if (IsExtend)
856  assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
857  "invalid narrowing extend");
858  else
859  assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
860  "invalid widening trunc");
861 #endif
862 }
863 
864 void MachineIRBuilder::validateSelectOp(const LLT &ResTy, const LLT &TstTy,
865  const LLT &Op0Ty, const LLT &Op1Ty) {
866 #ifndef NDEBUG
867  assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
868  "invalid operand type");
869  assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");
870  if (ResTy.isScalar() || ResTy.isPointer())
871  assert(TstTy.isScalar() && "type mismatch");
872  else
873  assert((TstTy.isScalar() ||
874  (TstTy.isVector() &&
875  TstTy.getNumElements() == Op0Ty.getNumElements())) &&
876  "type mismatch");
877 #endif
878 }
879 
881  ArrayRef<DstOp> DstOps,
882  ArrayRef<SrcOp> SrcOps,
883  Optional<unsigned> Flags) {
884  switch (Opc) {
885  default:
886  break;
887  case TargetOpcode::G_SELECT: {
888  assert(DstOps.size() == 1 && "Invalid select");
889  assert(SrcOps.size() == 3 && "Invalid select");
891  DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),
892  SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));
893  break;
894  }
895  case TargetOpcode::G_ADD:
896  case TargetOpcode::G_AND:
897  case TargetOpcode::G_MUL:
898  case TargetOpcode::G_OR:
899  case TargetOpcode::G_SUB:
900  case TargetOpcode::G_XOR:
901  case TargetOpcode::G_UDIV:
902  case TargetOpcode::G_SDIV:
903  case TargetOpcode::G_UREM:
904  case TargetOpcode::G_SREM:
905  case TargetOpcode::G_SMIN:
906  case TargetOpcode::G_SMAX:
907  case TargetOpcode::G_UMIN:
908  case TargetOpcode::G_UMAX: {
909  // All these are binary ops.
910  assert(DstOps.size() == 1 && "Invalid Dst");
911  assert(SrcOps.size() == 2 && "Invalid Srcs");
912  validateBinaryOp(DstOps[0].getLLTTy(*getMRI()),
913  SrcOps[0].getLLTTy(*getMRI()),
914  SrcOps[1].getLLTTy(*getMRI()));
915  break;
916  }
917  case TargetOpcode::G_SHL:
918  case TargetOpcode::G_ASHR:
919  case TargetOpcode::G_LSHR: {
920  assert(DstOps.size() == 1 && "Invalid Dst");
921  assert(SrcOps.size() == 2 && "Invalid Srcs");
922  validateShiftOp(DstOps[0].getLLTTy(*getMRI()),
923  SrcOps[0].getLLTTy(*getMRI()),
924  SrcOps[1].getLLTTy(*getMRI()));
925  break;
926  }
927  case TargetOpcode::G_SEXT:
928  case TargetOpcode::G_ZEXT:
929  case TargetOpcode::G_ANYEXT:
930  assert(DstOps.size() == 1 && "Invalid Dst");
931  assert(SrcOps.size() == 1 && "Invalid Srcs");
932  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
933  SrcOps[0].getLLTTy(*getMRI()), true);
934  break;
935  case TargetOpcode::G_TRUNC:
936  case TargetOpcode::G_FPTRUNC: {
937  assert(DstOps.size() == 1 && "Invalid Dst");
938  assert(SrcOps.size() == 1 && "Invalid Srcs");
939  validateTruncExt(DstOps[0].getLLTTy(*getMRI()),
940  SrcOps[0].getLLTTy(*getMRI()), false);
941  break;
942  }
943  case TargetOpcode::COPY:
944  assert(DstOps.size() == 1 && "Invalid Dst");
945  // If the caller wants to add a subreg source it has to be done separately
946  // so we may not have any SrcOps at this point yet.
947  break;
948  case TargetOpcode::G_FCMP:
949  case TargetOpcode::G_ICMP: {
950  assert(DstOps.size() == 1 && "Invalid Dst Operands");
951  assert(SrcOps.size() == 3 && "Invalid Src Operands");
952  // For F/ICMP, the first src operand is the predicate, followed by
953  // the two comparands.
954  assert(SrcOps[0].getSrcOpKind() == SrcOp::SrcType::Ty_Predicate &&
955  "Expecting predicate");
956  assert([&]() -> bool {
957  CmpInst::Predicate Pred = SrcOps[0].getPredicate();
958  return Opc == TargetOpcode::G_ICMP ? CmpInst::isIntPredicate(Pred)
959  : CmpInst::isFPPredicate(Pred);
960  }() && "Invalid predicate");
961  assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
962  "Type mismatch");
963  assert([&]() -> bool {
964  LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());
965  LLT DstTy = DstOps[0].getLLTTy(*getMRI());
966  if (Op0Ty.isScalar() || Op0Ty.isPointer())
967  return DstTy.isScalar();
968  else
969  return DstTy.isVector() &&
970  DstTy.getNumElements() == Op0Ty.getNumElements();
971  }() && "Type Mismatch");
972  break;
973  }
974  case TargetOpcode::G_UNMERGE_VALUES: {
975  assert(!DstOps.empty() && "Invalid trivial sequence");
976  assert(SrcOps.size() == 1 && "Invalid src for Unmerge");
977  assert(std::all_of(DstOps.begin(), DstOps.end(),
978  [&, this](const DstOp &Op) {
979  return Op.getLLTTy(*getMRI()) ==
980  DstOps[0].getLLTTy(*getMRI());
981  }) &&
982  "type mismatch in output list");
983  assert(DstOps.size() * DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
984  SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
985  "input operands do not cover output register");
986  break;
987  }
988  case TargetOpcode::G_MERGE_VALUES: {
989  assert(!SrcOps.empty() && "invalid trivial sequence");
990  assert(DstOps.size() == 1 && "Invalid Dst");
991  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
992  [&, this](const SrcOp &Op) {
993  return Op.getLLTTy(*getMRI()) ==
994  SrcOps[0].getLLTTy(*getMRI());
995  }) &&
996  "type mismatch in input list");
997  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
998  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
999  "input operands do not cover output register");
1000  if (SrcOps.size() == 1)
1001  return buildCast(DstOps[0], SrcOps[0]);
1002  if (DstOps[0].getLLTTy(*getMRI()).isVector())
1003  return buildInstr(TargetOpcode::G_CONCAT_VECTORS, DstOps, SrcOps);
1004  break;
1005  }
1006  case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1007  assert(DstOps.size() == 1 && "Invalid Dst size");
1008  assert(SrcOps.size() == 2 && "Invalid Src size");
1009  assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1010  assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||
1011  DstOps[0].getLLTTy(*getMRI()).isPointer()) &&
1012  "Invalid operand type");
1013  assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");
1014  assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==
1015  DstOps[0].getLLTTy(*getMRI()) &&
1016  "Type mismatch");
1017  break;
1018  }
1019  case TargetOpcode::G_INSERT_VECTOR_ELT: {
1020  assert(DstOps.size() == 1 && "Invalid dst size");
1021  assert(SrcOps.size() == 3 && "Invalid src size");
1022  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1023  SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");
1024  assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==
1025  SrcOps[1].getLLTTy(*getMRI()) &&
1026  "Type mismatch");
1027  assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");
1028  assert(DstOps[0].getLLTTy(*getMRI()).getNumElements() ==
1029  SrcOps[0].getLLTTy(*getMRI()).getNumElements() &&
1030  "Type mismatch");
1031  break;
1032  }
1033  case TargetOpcode::G_BUILD_VECTOR: {
1034  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1035  "Must have at least 2 operands");
1036  assert(DstOps.size() == 1 && "Invalid DstOps");
1037  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1038  "Res type must be a vector");
1039  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1040  [&, this](const SrcOp &Op) {
1041  return Op.getLLTTy(*getMRI()) ==
1042  SrcOps[0].getLLTTy(*getMRI());
1043  }) &&
1044  "type mismatch in input list");
1045  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1046  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1047  "input scalars do not exactly cover the output vector register");
1048  break;
1049  }
1050  case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1051  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1052  "Must have at least 2 operands");
1053  assert(DstOps.size() == 1 && "Invalid DstOps");
1054  assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&
1055  "Res type must be a vector");
1056  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1057  [&, this](const SrcOp &Op) {
1058  return Op.getLLTTy(*getMRI()) ==
1059  SrcOps[0].getLLTTy(*getMRI());
1060  }) &&
1061  "type mismatch in input list");
1062  if (SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1063  DstOps[0].getLLTTy(*getMRI()).getElementType().getSizeInBits())
1064  return buildInstr(TargetOpcode::G_BUILD_VECTOR, DstOps, SrcOps);
1065  break;
1066  }
1067  case TargetOpcode::G_CONCAT_VECTORS: {
1068  assert(DstOps.size() == 1 && "Invalid DstOps");
1069  assert((!SrcOps.empty() || SrcOps.size() < 2) &&
1070  "Must have at least 2 operands");
1071  assert(std::all_of(SrcOps.begin(), SrcOps.end(),
1072  [&, this](const SrcOp &Op) {
1073  return (Op.getLLTTy(*getMRI()).isVector() &&
1074  Op.getLLTTy(*getMRI()) ==
1075  SrcOps[0].getLLTTy(*getMRI()));
1076  }) &&
1077  "type mismatch in input list");
1078  assert(SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1079  DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1080  "input vectors do not exactly cover the output vector register");
1081  break;
1082  }
1083  case TargetOpcode::G_UADDE: {
1084  assert(DstOps.size() == 2 && "Invalid no of dst operands");
1085  assert(SrcOps.size() == 3 && "Invalid no of src operands");
1086  assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1087  assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&
1088  (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&
1089  "Invalid operand");
1090  assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");
1091  assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&
1092  "type mismatch");
1093  break;
1094  }
1095  }
1096 
1097  auto MIB = buildInstr(Opc);
1098  for (const DstOp &Op : DstOps)
1099  Op.addDefToMIB(*getMRI(), MIB);
1100  for (const SrcOp &Op : SrcOps)
1101  Op.addSrcToMIB(MIB);
1102  if (Flags)
1103  MIB->setFlags(*Flags);
1104  return MIB;
1105 }
bool isFPPredicate() const
Definition: InstrTypes.h:801
uint64_t CallInst * C
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
The CSE Analysis object.
Definition: CSEInfo.h:71
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_GEP Op0, Op1.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MachineInstrBuilder buildIndirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
iterator begin() const
Definition: ArrayRef.h:136
unsigned getScalarSizeInBits() const
void push_back(const T &Elt)
Definition: SmallVector.h:211
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< unsigned > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
bool isScalar() const
MachineInstrBuilder buildAtomicRMWSub(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
GISelChangeObserver * Observer
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
unsigned Reg
virtual const TargetLowering * getTargetLowering() const
MachineInstrBuilder buildAtomicRMWXor(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
LLT getScalarType() const
Function Alias Analysis Results
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void addSrcToMIB(MachineInstrBuilder &MIB) const
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
Definition: APFloat.cpp:169
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1185
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
const fltSemantics & getSemantics() const
Definition: APFloat.h:1154
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty, const LLT &Op1Ty)
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
Definition: Constants.h:142
LegalityPredicate isPointer(unsigned TypeIdx)
True iff the specified type index is a pointer (with any address space).
LegalityPredicate isVector(unsigned TypeIdx)
True iff the specified type index is a vector.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert `Res0, ...
MachineInstrBuilder buildAtomicRMWNand(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
bool isVector() const
void setMF(MachineFunction &MF)
The address of a basic block.
Definition: Constants.h:839
MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
A description of a memory reference used in the backend.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend)
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineBasicBlock::iterator II
void recordInsertion(MachineInstr *MI) const
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:300
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1)
MachineFunction & getMF()
Getter for the function we currently build.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
virtual const TargetInstrInfo * getInstrInfo() const
MachineInstrBuilder buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
static Function * getFunction(Constant *C)
Definition: Evaluator.cpp:258
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
void setChangeObserver(GISelChangeObserver &Observer)
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBundleIterator< MachineInstr > iterator
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
void validateShiftOp(const LLT &Res, const LLT &Op0, const LLT &Op1)
MachineRegisterInfo * getMRI()
Getter for MRI.
Abstract class that contains various methods for clients to notify about changes. ...
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_FPTRUNC Op.
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned char TargetFlags=0) const
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
unsigned getReg() const
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
This is an important base class in LLVM.
Definition: Constant.h:41
MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0, uint32_t NumBits)
Build and insert Res = G_PTR_MASK Op0, NumBits.
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
MachineInstrBuilder buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
bool isValid() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:709
MachineInstrBuilder buildInsert(unsigned Res, unsigned Src, unsigned Op, unsigned Index)
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Definition: DerivedTypes.h:526
DebugLoc DL
Debug location to be set to any instruction we create.
self_iterator getIterator()
Definition: ilist_node.h:81
const MachineInstrBuilder & addFrameIndex(int Idx) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:196
MachineInstrBuilder buildBrIndirect(unsigned Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
static wasm::ValType getType(const TargetRegisterClass *RC)
MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
const APFloat & getValueAPF() const
Definition: Constants.h:302
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:239
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
void buildSequence(unsigned Res, ArrayRef< unsigned > Ops, ArrayRef< uint64_t > Indices)
Build and insert instructions to put Ops together at the specified p Indices to form a larger registe...
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
iterator end() const
Definition: ArrayRef.h:137
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
const TargetInstrInfo & getTII()
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:631
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
LegalityPredicate isScalar(unsigned TypeIdx)
True iff the specified type index is a scalar.
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
Definition: Constants.cpp:694
LLT getLLTTy(const MachineRegisterInfo &MRI) const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
MachineInstrBuilder buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
void setCSEInfo(GISelCSEInfo *Info)
This file declares the MachineIRBuilder class.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
bool isIntPredicate() const
Definition: InstrTypes.h:802
Class for arbitrary precision integers.
Definition: APInt.h:69
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal, unsigned NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO.
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
bool isPointer() const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
#define I(x, y, z)
Definition: MD5.cpp:58
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< unsigned > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
Optional< MachineInstrBuilder > materializeGEP(unsigned &Res, unsigned Op0, const LLT &ValueTy, uint64_t Value)
Materialize and insert Res = G_GEP Op0, (G_CONSTANT Value)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
LLVM Value Representation.
Definition: Value.h:72
unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
MachineInstrBuilder buildAtomicRMWMin(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr, unsigned CmpVal, unsigned NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
MachineFunction * MF
MachineFunction under construction.
MachineInstrBuilder buildAtomicRMWOr(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildAtomicRMWMax(unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
PointerType * getType() const
Global values are always pointers.
Definition: GlobalValue.h:273
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
This file describes how to lower LLVM code to machine code.
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.