52 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
53 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
55 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
56 "Expected inlined-at fields to agree");
59 false, Reg, Variable, Expr));
65 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
66 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
68 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
69 "Expected inlined-at fields to agree");
72 true, Reg, Variable, Expr));
78 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
79 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
81 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
82 "Expected inlined-at fields to agree");
86 .addMetadata(Variable)
93 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
94 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
96 cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
getDL()) &&
97 "Expected inlined-at fields to agree");
100 auto *NumericConstant = [&] () ->
const Constant* {
101 if (
const auto *CE = dyn_cast<ConstantExpr>(&
C))
102 if (CE->getOpcode() == Instruction::IntToPtr)
103 return CE->getOperand(0);
107 if (
auto *CI = dyn_cast<ConstantInt>(NumericConstant)) {
108 if (CI->getBitWidth() > 64)
111 MIB.addImm(CI->getZExtValue());
112 }
else if (
auto *CFP = dyn_cast<ConstantFP>(NumericConstant)) {
114 }
else if (isa<ConstantPointerNull>(NumericConstant)) {
121 MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
126 assert(isa<DILabel>(Label) &&
"not a label");
127 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(State.
DL) &&
128 "Expected inlined-at fields to agree");
129 auto MIB =
buildInstr(TargetOpcode::DBG_LABEL);
131 return MIB.addMetadata(Label);
138 auto MIB =
buildInstr(TargetOpcode::G_DYN_STACKALLOC);
140 Size.addSrcToMIB(MIB);
141 MIB.addImm(Alignment.
value());
148 auto MIB =
buildInstr(TargetOpcode::G_FRAME_INDEX);
150 MIB.addFrameIndex(
Idx);
159 "address space mismatch");
161 auto MIB =
buildInstr(TargetOpcode::G_GLOBAL_VALUE);
163 MIB.addGlobalAddress(GV);
170 auto MIB =
buildInstr(TargetOpcode::G_CONSTANT_POOL);
172 MIB.addConstantPoolIndex(
Idx);
178 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})
179 .addJumpTableIndex(JTI);
184 assert((Res == Op0) &&
"type mismatch");
190 assert((Res == Op0 && Res == Op1) &&
"type mismatch");
196 assert((Res == Op0) &&
"type mismatch");
201 const SrcOp &Op1, std::optional<unsigned> Flags) {
206 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1}, Flags);
209std::optional<MachineInstrBuilder>
212 assert(Res == 0 &&
"Res is a result argument");
231 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits));
246 "Different vector element types");
248 "Op0 has more elements");
251 for (
auto Op : Unmerge.getInstr()->defs())
255 "Op0 has more size");
261 for (
unsigned i = 0; i < NumberOfPadElts; ++i)
274 "Different vector element types");
276 "Op0 has fewer elements");
298 "Table reg must be a pointer");
315 "creating constant with the wrong size");
318 auto Const =
buildInstr(TargetOpcode::G_CONSTANT)
324 auto Const =
buildInstr(TargetOpcode::G_CONSTANT);
346 "creating fconstant with the wrong size");
351 auto Const =
buildInstr(TargetOpcode::G_FCONSTANT)
358 auto Const =
buildInstr(TargetOpcode::G_FCONSTANT);
361 Const.addFPImm(&Val);
391 auto MIB =
buildInstr(TargetOpcode::G_BRCOND);
420 Addr.addSrcToMIB(MIB);
421 MIB.addMemOperand(&MMO);
433 return buildLoad(Dst, BasePtr, *OffsetMMO);
450 Addr.addSrcToMIB(MIB);
451 MIB.addMemOperand(&MMO);
486 switch (TLI->getBooleanContents(IsVec, IsFP)) {
488 return TargetOpcode::G_SEXT;
490 return TargetOpcode::G_ZEXT;
492 return TargetOpcode::G_ANYEXT;
508 switch (TLI->getBooleanContents(IsVector, IsFP)) {
523 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||
524 TargetOpcode::G_SEXT == ExtOpc) &&
525 "Expecting Extending Opc");
531 unsigned Opcode = TargetOpcode::COPY;
533 Op.getLLTTy(*
getMRI()).getSizeInBits())
536 Op.getLLTTy(*
getMRI()).getSizeInBits())
537 Opcode = TargetOpcode::G_TRUNC;
577 Opcode = TargetOpcode::G_PTRTOINT;
579 Opcode = TargetOpcode::G_INTTOPTR;
582 Opcode = TargetOpcode::G_BITCAST;
598 "extracting off end of register");
602 assert(
Index == 0 &&
"insertion past the end of a register");
606 auto Extract =
buildInstr(TargetOpcode::G_EXTRACT);
607 Dst.addDefToMIB(*
getMRI(), Extract);
608 Src.addSrcToMIB(Extract);
609 Extract.addImm(
Index);
614 return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});
624 return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);
635 return buildInstr(getOpcodeForMerge(Res, TmpVec), Res, TmpVec);
640 std::initializer_list<SrcOp> Ops) {
642 return buildInstr(getOpcodeForMerge(Res, Ops), Res, Ops);
645unsigned MachineIRBuilder::getOpcodeForMerge(
const DstOp &
DstOp,
648 if (SrcOps[0].getLLTTy(*
getMRI()).isVector())
649 return TargetOpcode::G_CONCAT_VECTORS;
650 return TargetOpcode::G_BUILD_VECTOR;
653 return TargetOpcode::G_MERGE_VALUES;
663 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec,
Op);
670 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec,
Op);
680 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec,
Op);
689 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
698 for (
const auto &
Op : Ops)
700 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
706 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
716 if (TmpVec[0].getLLTTy(*
getMRI()).getSizeInBits() ==
718 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);
719 return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);
726 "Expected Src to match Dst elt ty");
749 return buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {Res}, {Src1, Src2})
750 .addShuffleMask(MaskAlloc);
759 return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);
768 "insertion past the end of a register");
771 Op.getLLTTy(*
getMRI()).getSizeInBits()) {
779 if (HasSideEffects && IsConvergent)
780 return TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS;
782 return TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;
784 return TargetOpcode::G_INTRINSIC_CONVERGENT;
785 return TargetOpcode::G_INTRINSIC;
791 bool HasSideEffects,
bool isConvergent) {
793 for (
unsigned ResultReg : ResultRegs)
794 MIB.addDef(ResultReg);
795 MIB.addIntrinsicID(
ID);
803 bool HasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory();
804 bool isConvergent = Attrs.hasFnAttr(Attribute::Convergent);
814 Result.addDefToMIB(*
getMRI(), MIB);
815 MIB.addIntrinsicID(
ID);
822 bool HasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory();
823 bool isConvergent = Attrs.hasFnAttr(Attribute::Convergent);
834 std::optional<unsigned> Flags) {
835 return buildInstr(TargetOpcode::G_FPTRUNC, Res,
Op, Flags);
842 return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1});
849 std::optional<unsigned> Flags) {
851 return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
857 std::optional<unsigned> Flags) {
859 return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);
865 return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt,
Idx});
871 return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val,
Idx});
888 assert(OldValResTy == CmpValTy &&
"type mismatch");
889 assert(OldValResTy == NewValTy &&
"type mismatch");
892 return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS)
914 assert(OldValResTy == CmpValTy &&
"type mismatch");
915 assert(OldValResTy == NewValTy &&
"type mismatch");
918 return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG)
927 unsigned Opcode,
const DstOp &OldValRes,
938 assert(OldValResTy == ValTy &&
"type mismatch");
944 Addr.addSrcToMIB(MIB);
946 MIB.addMemOperand(&MMO);
1067 assert(SrcTy.
isVector() &&
"mismatched cast between vector and non-vector");
1069 "different number of elements in a trunc/ext");
1075 "invalid narrowing extend");
1078 "invalid widening trunc");
1083 const LLT Op0Ty,
const LLT Op1Ty) {
1086 "invalid operand type");
1087 assert((ResTy == Op0Ty && ResTy == Op1Ty) &&
"type mismatch");
1101 std::optional<unsigned> Flags) {
1105 case TargetOpcode::G_SELECT: {
1106 assert(DstOps.
size() == 1 &&
"Invalid select");
1107 assert(SrcOps.
size() == 3 &&
"Invalid select");
1109 DstOps[0].getLLTTy(*
getMRI()), SrcOps[0].getLLTTy(*
getMRI()),
1110 SrcOps[1].getLLTTy(*
getMRI()), SrcOps[2].getLLTTy(*
getMRI()));
1113 case TargetOpcode::G_FNEG:
1114 case TargetOpcode::G_ABS:
1117 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1119 SrcOps[0].getLLTTy(*
getMRI()));
1121 case TargetOpcode::G_ADD:
1122 case TargetOpcode::G_AND:
1123 case TargetOpcode::G_MUL:
1124 case TargetOpcode::G_OR:
1125 case TargetOpcode::G_SUB:
1126 case TargetOpcode::G_XOR:
1127 case TargetOpcode::G_UDIV:
1128 case TargetOpcode::G_SDIV:
1129 case TargetOpcode::G_UREM:
1130 case TargetOpcode::G_SREM:
1131 case TargetOpcode::G_SMIN:
1132 case TargetOpcode::G_SMAX:
1133 case TargetOpcode::G_UMIN:
1134 case TargetOpcode::G_UMAX:
1135 case TargetOpcode::G_UADDSAT:
1136 case TargetOpcode::G_SADDSAT:
1137 case TargetOpcode::G_USUBSAT:
1138 case TargetOpcode::G_SSUBSAT: {
1141 assert(SrcOps.
size() == 2 &&
"Invalid Srcs");
1143 SrcOps[0].getLLTTy(*
getMRI()),
1144 SrcOps[1].getLLTTy(*
getMRI()));
1147 case TargetOpcode::G_SHL:
1148 case TargetOpcode::G_ASHR:
1149 case TargetOpcode::G_LSHR:
1150 case TargetOpcode::G_USHLSAT:
1151 case TargetOpcode::G_SSHLSAT: {
1153 assert(SrcOps.
size() == 2 &&
"Invalid Srcs");
1155 SrcOps[0].getLLTTy(*
getMRI()),
1156 SrcOps[1].getLLTTy(*
getMRI()));
1159 case TargetOpcode::G_SEXT:
1160 case TargetOpcode::G_ZEXT:
1161 case TargetOpcode::G_ANYEXT:
1163 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1165 SrcOps[0].getLLTTy(*
getMRI()),
true);
1167 case TargetOpcode::G_TRUNC:
1168 case TargetOpcode::G_FPTRUNC: {
1170 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1172 SrcOps[0].getLLTTy(*
getMRI()),
false);
1175 case TargetOpcode::G_BITCAST: {
1177 assert(SrcOps.
size() == 1 &&
"Invalid Srcs");
1178 assert(DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1179 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
"invalid bitcast");
1182 case TargetOpcode::COPY:
1187 case TargetOpcode::G_FCMP:
1188 case TargetOpcode::G_ICMP: {
1189 assert(DstOps.
size() == 1 &&
"Invalid Dst Operands");
1190 assert(SrcOps.
size() == 3 &&
"Invalid Src Operands");
1194 "Expecting predicate");
1199 }() &&
"Invalid predicate");
1203 LLT Op0Ty = SrcOps[1].getLLTTy(*
getMRI());
1204 LLT DstTy = DstOps[0].getLLTTy(*
getMRI());
1210 }() &&
"Type Mismatch");
1213 case TargetOpcode::G_UNMERGE_VALUES: {
1214 assert(!DstOps.
empty() &&
"Invalid trivial sequence");
1215 assert(SrcOps.
size() == 1 &&
"Invalid src for Unmerge");
1219 DstOps[0].getLLTTy(*
getMRI());
1221 "type mismatch in output list");
1223 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1224 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1225 "input operands do not cover output register");
1228 case TargetOpcode::G_MERGE_VALUES: {
1229 assert(SrcOps.
size() >= 2 &&
"invalid trivial sequence");
1234 SrcOps[0].getLLTTy(*
getMRI());
1236 "type mismatch in input list");
1238 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1239 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1240 "input operands do not cover output register");
1242 "vectors should be built with G_CONCAT_VECTOR or G_BUILD_VECTOR");
1245 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1246 assert(DstOps.
size() == 1 &&
"Invalid Dst size");
1247 assert(SrcOps.
size() == 2 &&
"Invalid Src size");
1248 assert(SrcOps[0].getLLTTy(*
getMRI()).isVector() &&
"Invalid operand type");
1250 DstOps[0].getLLTTy(*
getMRI()).isPointer()) &&
1251 "Invalid operand type");
1252 assert(SrcOps[1].getLLTTy(*
getMRI()).isScalar() &&
"Invalid operand type");
1253 assert(SrcOps[0].getLLTTy(*
getMRI()).getElementType() ==
1254 DstOps[0].getLLTTy(*
getMRI()) &&
1258 case TargetOpcode::G_INSERT_VECTOR_ELT: {
1259 assert(DstOps.
size() == 1 &&
"Invalid dst size");
1260 assert(SrcOps.
size() == 3 &&
"Invalid src size");
1262 SrcOps[0].getLLTTy(*
getMRI()).isVector() &&
"Invalid operand type");
1263 assert(DstOps[0].getLLTTy(*
getMRI()).getElementType() ==
1264 SrcOps[1].getLLTTy(*
getMRI()) &&
1266 assert(SrcOps[2].getLLTTy(*
getMRI()).isScalar() &&
"Invalid index");
1267 assert(DstOps[0].getLLTTy(*
getMRI()).getNumElements() ==
1268 SrcOps[0].getLLTTy(*
getMRI()).getNumElements() &&
1272 case TargetOpcode::G_BUILD_VECTOR: {
1274 "Must have at least 2 operands");
1275 assert(DstOps.
size() == 1 &&
"Invalid DstOps");
1277 "Res type must be a vector");
1281 SrcOps[0].getLLTTy(*
getMRI());
1283 "type mismatch in input list");
1285 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1286 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1287 "input scalars do not exactly cover the output vector register");
1290 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1292 "Must have at least 2 operands");
1293 assert(DstOps.
size() == 1 &&
"Invalid DstOps");
1295 "Res type must be a vector");
1299 SrcOps[0].getLLTTy(*
getMRI());
1301 "type mismatch in input list");
1304 case TargetOpcode::G_CONCAT_VECTORS: {
1305 assert(DstOps.
size() == 1 &&
"Invalid DstOps");
1307 "Must have at least 2 operands");
1310 return (
Op.getLLTTy(*
getMRI()).isVector() &&
1312 SrcOps[0].getLLTTy(*
getMRI()));
1314 "type mismatch in input list");
1316 SrcOps[0].getLLTTy(*
getMRI()).getSizeInBits() ==
1317 DstOps[0].getLLTTy(*
getMRI()).getSizeInBits() &&
1318 "input vectors do not exactly cover the output vector register");
1321 case TargetOpcode::G_UADDE: {
1322 assert(DstOps.
size() == 2 &&
"Invalid no of dst operands");
1323 assert(SrcOps.
size() == 3 &&
"Invalid no of src operands");
1324 assert(DstOps[0].getLLTTy(*
getMRI()).isScalar() &&
"Invalid operand");
1326 (DstOps[0].getLLTTy(*
getMRI()) == SrcOps[1].getLLTTy(*
getMRI())) &&
1328 assert(DstOps[1].getLLTTy(*
getMRI()).isScalar() &&
"Invalid operand");
1336 for (
const DstOp &
Op : DstOps)
1338 for (
const SrcOp &
Op : SrcOps)
1339 Op.addSrcToMIB(MIB);
1341 MIB->setFlags(*Flags);
Function Alias Analysis Results
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static Function * getFunction(Constant *C)
static unsigned getIntrinsicOpcode(bool HasSideEffects, bool IsConvergent)
This file declares the MachineIRBuilder class.
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SymbolRef::Type getType(const Symbol *Sym)
This file describes how to lower LLVM code to machine code.
const fltSemantics & getSemantics() const
Class for arbitrary precision integers.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
The address of a basic block.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
bool isFPPredicate() const
bool isIntPredicate() const
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
This is the shared class of boolean and integer constants.
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
unsigned getBitWidth() const
getBitWidth - Return the bitwidth of this constant.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
PointerType * getType() const
Global values are always pointers.
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr LLT getScalarType() const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstrBundleIterator< MachineInstr > iterator
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
ArrayRef< int > allocateShuffleMask(ArrayRef< int > Mask)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
MachineInstrBuilder buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO.
MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
LLVMContext & getContext() const
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx)
Build and insert Res = G_CONSTANT_POOL Idx.
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
const TargetInstrInfo & getTII()
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)
Build and insert a G_INTRINSIC instruction.
MDNode * getPCSections()
Get the current instruction's PC sections metadata.
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
void recordInsertion(MachineInstr *InsertedInstr) const
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ... where each OpN is built with G_CONSTANT.
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
MachineInstrBuilder buildMergeValues(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
MachineInstrBuilder buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO.
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPTRUNC Op.
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
void validateUnaryOp(const LLT Res, const LLT Op0)
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
void setMF(MachineFunction &MF)
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
A description of a memory reference used in the backend.
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
Flags
Flags values. These may be or'd together.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Wrapper class representing virtual and physical registers.
void reserve(size_type N)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
LLT getLLTTy(const MachineRegisterInfo &MRI) const
void addSrcToMIB(MachineInstrBuilder &MIB) const
@ ZeroOrOneBooleanContent
@ UndefinedBooleanContent
@ ZeroOrNegativeOneBooleanContent
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetLowering * getTargetLowering() const
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
DWARFExpression::Operation Op
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
MachineFunction * MF
MachineFunction under construction.
DebugLoc DL
Debug location to be set to any instruction we create.
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
MDNode * PCSections
PC sections metadata to be set to any instruction we create.
MachineBasicBlock::iterator II
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
GISelChangeObserver * Observer
This class contains a discriminated union of information about pointers in memory operands,...