LLVM 18.0.0git
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TargetSubtargetInfo - Generic base class for all target subtargets. More...
#include "llvm/CodeGen/TargetSubtargetInfo.h"
Public Types | |
using | AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } |
using | RegClassVector = SmallVectorImpl< const TargetRegisterClass * > |
Public Member Functions | |
TargetSubtargetInfo ()=delete | |
TargetSubtargetInfo (const TargetSubtargetInfo &)=delete | |
TargetSubtargetInfo & | operator= (const TargetSubtargetInfo &)=delete |
~TargetSubtargetInfo () override | |
virtual bool | isXRaySupported () const |
virtual const TargetInstrInfo * | getInstrInfo () const |
virtual const TargetFrameLowering * | getFrameLowering () const |
virtual const TargetLowering * | getTargetLowering () const |
virtual const SelectionDAGTargetInfo * | getSelectionDAGInfo () const |
virtual const CallLowering * | getCallLowering () const |
virtual const InlineAsmLowering * | getInlineAsmLowering () const |
virtual InstructionSelector * | getInstructionSelector () const |
virtual RegisterScheduler::FunctionPassCtor | getDAGScheduler (CodeGenOptLevel) const |
Target can subclass this hook to select a different DAG scheduler. | |
virtual const LegalizerInfo * | getLegalizerInfo () const |
virtual const TargetRegisterInfo * | getRegisterInfo () const |
getRegisterInfo - If register information is available, return it. | |
virtual const RegisterBankInfo * | getRegBankInfo () const |
If the information for the register banks is available, return it. | |
virtual const InstrItineraryData * | getInstrItineraryData () const |
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget. | |
virtual unsigned | resolveSchedClass (unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const |
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant property. | |
virtual bool | isZeroIdiom (const MachineInstr *MI, APInt &Mask) const |
Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget. | |
virtual bool | isDependencyBreaking (const MachineInstr *MI, APInt &Mask) const |
Returns true if MI is a dependency breaking instruction for the subtarget. | |
virtual bool | isOptimizableRegisterMove (const MachineInstr *MI) const |
Returns true if MI is a candidate for move elimination. | |
virtual bool | enableMachineScheduler () const |
True if the subtarget should run MachineScheduler after aggressive coalescing. | |
virtual bool | enableMachineSchedDefaultSched () const |
True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler. | |
virtual bool | enableMachinePipeliner () const |
True if the subtarget should run MachinePipeliner. | |
virtual bool | enableJoinGlobalCopies () const |
True if the subtarget should enable joining global copies. | |
virtual bool | enablePostRAScheduler () const |
True if the subtarget should run a scheduler after register allocation. | |
virtual bool | enablePostRAMachineScheduler () const |
True if the subtarget should run a machine scheduler after register allocation. | |
virtual bool | enableAtomicExpand () const |
True if the subtarget should run the atomic expansion pass. | |
virtual bool | enableIndirectBrExpand () const |
True if the subtarget should run the indirectbr expansion pass. | |
virtual void | overrideSchedPolicy (MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const |
Override generic scheduling policy within a region. | |
virtual void | adjustSchedDependency (SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const |
virtual AntiDepBreakMode | getAntiDepBreakMode () const |
virtual void | getCriticalPathRCs (RegClassVector &CriticalPathRCs) const |
virtual void | getPostRAMutations (std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const |
virtual void | getSMSMutations (std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const |
virtual bool | useDFAforSMS () const |
Default to DFA for resource management, return false when target will use ProcResource in InstrSchedModel instead. | |
virtual CodeGenOptLevel | getOptLevelToEnablePostRAScheduler () const |
virtual bool | enableRALocalReassignment (CodeGenOptLevel OptLevel) const |
True if the subtarget should run the local reassignment heuristic of the register allocator. | |
virtual bool | useAA () const |
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.). | |
virtual bool | addrSinkUsingGEPs () const |
Sink addresses into blocks using GEP instructions rather than pointer casts and arithmetic. | |
virtual bool | enableEarlyIfConversion () const |
Enable the use of the early if conversion pass. | |
virtual std::unique_ptr< PBQPRAConstraint > | getCustomPBQPConstraints () const |
Return PBQPConstraint(s) for the target. | |
virtual bool | enableSubRegLiveness () const |
Enable tracking of subregister liveness in register allocator. | |
virtual void | mirFileLoaded (MachineFunction &MF) const |
This is called after a .mir file was loaded. | |
virtual bool | ignoreCSRForAllocationOrder (const MachineFunction &MF, unsigned PhysReg) const |
True if the register allocator should use the allocation orders exactly as written in the tablegen descriptions, false if it should allocate the specified physical register later if is it callee-saved. | |
virtual unsigned char | classifyGlobalFunctionReference (const GlobalValue *GV) const |
Classify a global function reference. | |
virtual bool | enableSpillageCopyElimination () const |
Enable spillage copy elimination in MachineCopyPropagation pass. | |
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MCSubtargetInfo (const MCSubtargetInfo &)=default | |
MCSubtargetInfo (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) | |
MCSubtargetInfo ()=delete | |
MCSubtargetInfo & | operator= (const MCSubtargetInfo &)=delete |
MCSubtargetInfo & | operator= (MCSubtargetInfo &&)=delete |
virtual | ~MCSubtargetInfo ()=default |
const Triple & | getTargetTriple () const |
StringRef | getCPU () const |
StringRef | getTuneCPU () const |
const FeatureBitset & | getFeatureBits () const |
void | setFeatureBits (const FeatureBitset &FeatureBits_) |
StringRef | getFeatureString () const |
bool | hasFeature (unsigned Feature) const |
void | setDefaultFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS) |
Set the features to the default for the given CPU and TuneCPU, with ano appended feature string. | |
FeatureBitset | ToggleFeature (uint64_t FB) |
Toggle a feature and return the re-computed feature bits. | |
FeatureBitset | ToggleFeature (const FeatureBitset &FB) |
Toggle a feature and return the re-computed feature bits. | |
FeatureBitset | ToggleFeature (StringRef FS) |
Toggle a set of features and return the re-computed feature bits. | |
FeatureBitset | ApplyFeatureFlag (StringRef FS) |
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag. | |
FeatureBitset | SetFeatureBitsTransitively (const FeatureBitset &FB) |
Set/clear additional feature bits, including all other bits they imply. | |
FeatureBitset | ClearFeatureBitsTransitively (const FeatureBitset &FB) |
bool | checkFeatures (StringRef FS) const |
Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features. | |
const MCSchedModel & | getSchedModelForCPU (StringRef CPU) const |
Get the machine model of a CPU. | |
const MCSchedModel & | getSchedModel () const |
Get the machine model for this subtarget's CPU. | |
const MCWriteProcResEntry * | getWriteProcResBegin (const MCSchedClassDesc *SC) const |
Return an iterator at the first process resource consumed by the given scheduling class. | |
const MCWriteProcResEntry * | getWriteProcResEnd (const MCSchedClassDesc *SC) const |
const MCWriteLatencyEntry * | getWriteLatencyEntry (const MCSchedClassDesc *SC, unsigned DefIdx) const |
int | getReadAdvanceCycles (const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const |
ArrayRef< MCReadAdvanceEntry > | getReadAdvanceEntries (const MCSchedClassDesc &SC) const |
Return the set of ReadAdvance entries declared by the scheduling class descriptor in input. | |
InstrItineraryData | getInstrItineraryForCPU (StringRef CPU) const |
Get scheduling itinerary of a CPU. | |
void | initInstrItins (InstrItineraryData &InstrItins) const |
Initialize an InstrItineraryData instance. | |
virtual unsigned | resolveVariantSchedClass (unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const |
Resolve a variant scheduling class for the given MCInst and CPU. | |
bool | isCPUStringValid (StringRef CPU) const |
Check whether the CPU string is valid. | |
ArrayRef< SubtargetSubTypeKV > | getAllProcessorDescriptions () const |
Return processor descriptions. | |
ArrayRef< SubtargetFeatureKV > | getAllProcessorFeatures () const |
Return processor features. | |
virtual unsigned | getHwMode () const |
virtual std::optional< unsigned > | getCacheSize (unsigned Level) const |
Return the cache size in bytes for the given level of cache. | |
virtual std::optional< unsigned > | getCacheAssociativity (unsigned Level) const |
Return the cache associatvity for the given level of cache. | |
virtual std::optional< unsigned > | getCacheLineSize (unsigned Level) const |
Return the target cache line size in bytes at a given level. | |
virtual unsigned | getCacheLineSize () const |
Return the target cache line size in bytes. | |
virtual unsigned | getPrefetchDistance () const |
Return the preferred prefetch distance in terms of instructions. | |
virtual unsigned | getMaxPrefetchIterationsAhead () const |
Return the maximum prefetch distance in terms of loop iterations. | |
virtual bool | enableWritePrefetching () const |
virtual unsigned | getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const |
Return the minimum stride necessary to trigger software prefetching. | |
virtual bool | shouldPrefetchAddressSpace (unsigned AS) const |
Protected Member Functions | |
TargetSubtargetInfo (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) | |
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void | InitMCProcessorInfo (StringRef CPU, StringRef TuneCPU, StringRef FS) |
Initialize the scheduling model and feature bits. | |
TargetSubtargetInfo - Generic base class for all target subtargets.
All Target-specific options that control code generation and printing should be exposed through a TargetSubtargetInfo-derived class.
Definition at line 62 of file TargetSubtargetInfo.h.
using llvm::TargetSubtargetInfo::AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } |
Definition at line 75 of file TargetSubtargetInfo.h.
Definition at line 76 of file TargetSubtargetInfo.h.
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Definition at line 17 of file TargetSubtargetInfo.cpp.
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Sink addresses into blocks using GEP instructions rather than pointer casts and arithmetic.
Definition at line 284 of file TargetSubtargetInfo.h.
References useAA().
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Definition at line 236 of file TargetSubtargetInfo.h.
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Classify a global function reference.
This mainly used to fetch target special flags for lowering a function address. For example mark a function call should be plt or pc-related addressing.
Definition at line 318 of file TargetSubtargetInfo.h.
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True if the subtarget should run the atomic expansion pass.
Definition at line 27 of file TargetSubtargetInfo.cpp.
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Enable the use of the early if conversion pass.
Definition at line 289 of file TargetSubtargetInfo.h.
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True if the subtarget should run the indirectbr expansion pass.
Definition at line 31 of file TargetSubtargetInfo.cpp.
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True if the subtarget should enable joining global copies.
By default this is enabled if the machine scheduler is enabled, but can be overridden.
Definition at line 39 of file TargetSubtargetInfo.cpp.
References enableMachineScheduler().
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True if the subtarget should run MachinePipeliner.
Definition at line 199 of file TargetSubtargetInfo.h.
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True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler.
Definition at line 196 of file TargetSubtargetInfo.h.
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True if the subtarget should run MachineScheduler after aggressive coalescing.
This currently replaces the SelectionDAG scheduler with the "source" order scheduler (though see below for an option to turn this off and use the TargetLowering preference). It does not yet disable the postRA scheduler.
Definition at line 35 of file TargetSubtargetInfo.cpp.
Referenced by enableJoinGlobalCopies(), and enablePostRAMachineScheduler().
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True if the subtarget should run a machine scheduler after register allocation.
Definition at line 52 of file TargetSubtargetInfo.cpp.
References enableMachineScheduler(), and enablePostRAScheduler().
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True if the subtarget should run a scheduler after register allocation.
By default this queries the PostRAScheduling bit in the scheduling model which is the preferred way to influence this.
Definition at line 48 of file TargetSubtargetInfo.cpp.
References llvm::MCSubtargetInfo::getSchedModel(), and llvm::MCSchedModel::PostRAScheduler.
Referenced by enablePostRAMachineScheduler().
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True if the subtarget should run the local reassignment heuristic of the register allocator.
This heuristic may be compile time intensive, OptLevel
provides a finer grain to tune the register allocator.
Definition at line 43 of file TargetSubtargetInfo.cpp.
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Enable spillage copy elimination in MachineCopyPropagation pass.
This helps removing redundant copies generated by register allocator when handling complex eviction chains.
Definition at line 325 of file TargetSubtargetInfo.h.
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Enable tracking of subregister liveness in register allocator.
Please use MachineRegisterInfo::subRegLivenessEnabled() instead where possible.
Definition at line 301 of file TargetSubtargetInfo.h.
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Definition at line 241 of file TargetSubtargetInfo.h.
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Definition at line 103 of file TargetSubtargetInfo.h.
Referenced by llvm::createLibcall(), llvm::createMemLibcall(), and llvm::IRTranslator::runOnMachineFunction().
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Definition at line 246 of file TargetSubtargetInfo.h.
References llvm::SmallVectorImpl< T >::clear().
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Return PBQPConstraint(s) for the target.
Override to provide custom PBQP constraints.
Definition at line 294 of file TargetSubtargetInfo.h.
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Target can subclass this hook to select a different DAG scheduler.
Definition at line 119 of file TargetSubtargetInfo.h.
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Definition at line 96 of file TargetSubtargetInfo.h.
Referenced by llvm::CodeViewDebug::beginFunctionImpl(), checkNumAlignedDPRCS2Regs(), llvm::SelectionDAG::CreateStackTemporary(), llvm::TargetOptions::DisableFramePointerElim(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::LoongArchRegisterInfo::eliminateFrameIndex(), emitDebugValueComment(), llvm::MachineFrameInfo::estimateStackSize(), getFnStackAlignment(), llvm::AVRRegisterInfo::getFrameRegister(), llvm::M68kRegisterInfo::getFrameRegister(), llvm::SelectionDAG::getReducedAlign(), llvm::MipsRegisterInfo::getRegPressureLimit(), llvm::TargetInstrInfo::getSPAdjust(), llvm::X86InstrInfo::getSPAdjust(), llvm::MIRParserImpl::initializeFrameInfo(), insertCSRRestores(), insertCSRSaves(), llvm::MipsCallLowering::lowerCall(), mayCombineMisaligned(), llvm::MachineFrameInfo::print(), llvm::CFIFixup::runOnMachineFunction(), llvm::FunctionLoweringInfo::set(), llvm::TargetRegisterInfo::shouldRealignStack(), and llvm::DwarfCompileUnit::updateSubprogramScopeDIE().
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Definition at line 105 of file TargetSubtargetInfo.h.
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Definition at line 95 of file TargetSubtargetInfo.h.
Referenced by llvm::MachineBasicBlock::addLiveIn(), llvm::ARMFrameLowering::adjustForSegmentedStacks(), llvm::ARMBasicBlockUtils::ARMBasicBlockUtils(), attemptDebugCopyProp(), llvm::avoidZeroOffsetLandingPad(), llvm::DwarfDebug::beginInstruction(), llvm::calculateRegAllocScore(), llvm::MachineBasicBlock::canSplitCriticalEdge(), combineFPFusedMultiply(), llvm::MachineFrameInfo::computeMaxCallFrameSize(), llvm::createBURRListDAGScheduler(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::VLIWResourceModel::createPacketizer(), createPHIsForCMOVsInSinkBB(), createPHIsForSelects(), llvm::createSourceListDAGScheduler(), llvm::TargetInstrInfo::describeLoadedValue(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::BPFRegisterInfo::eliminateFrameIndex(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), emitBuildPairF64Pseudo(), emitCalleeSavedRestores(), emitComments(), llvm::ARMFrameLowering::emitEpilogue(), llvm::MSP430FrameLowering::emitEpilogue(), llvm::SparcFrameLowering::emitEpilogue(), llvm::SystemZELFFrameLowering::emitEpilogue(), llvm::AsmPrinter::emitFunctionBody(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMBaseRegisterInfo::emitLoadConstPool(), llvm::AsmPrinter::emitNops(), llvm::MSP430FrameLowering::emitPrologue(), llvm::NVPTXFrameLowering::emitPrologue(), emitQuietFCMP(), emitReadCycleWidePseudo(), emitSelectPseudo(), emitSplitF64Pseudo(), emitThumb2LoadConstPool(), emitVFROUND_NOEXCEPT_MASK(), estimateRSStackSizeLimit(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::finalizeBundle(), llvm::MachineFunction::finalizeDebugInstrRefs(), findJumpTableIndex(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), genIndexedMultiply(), getBBAddrMapMetadata(), llvm::getEHScopeMembership(), llvm::MachineBasicBlock::getFallThrough(), llvm::ARMHazardRecognizerFPMLx::getHazardType(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::MSP430InstrInfo::getInstSizeInBytes(), getOrCreateFrameHelper(), getSchedRegions(), getTargetIndexName(), llvm::TargetSchedModel::init(), llvm::PreRARematStage::initGCNSchedStage(), llvm::MipsFunctionInfo::initGlobalBaseReg(), llvm::GenericScheduler::initialize(), llvm::PostGenericScheduler::initialize(), llvm::ConvergingVLIWScheduler::initialize(), llvm::TailDuplicator::initMF(), llvm::SystemZELFFrameLowering::inlineStackProbe(), llvm::SystemZXPLINKFrameLowering::inlineStackProbe(), insertCSRRestores(), insertCSRSaves(), insertDivByZeroTrap(), llvm::insertMultibyteShift(), interpretValues(), isColdBlock(), jumpTableHasOtherUses(), AMDGPUMCInstLower::lower(), llvm::X86CallLowering::lowerCall(), llvm::RISCVRegisterInfo::lowerVRELOAD(), llvm::RISCVRegisterInfo::lowerVSPILL(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), llvm::RISCVRegisterInfo::materializeFrameBaseRegister(), llvm::MachineInstr::mayAlias(), llvm::MachineInstr::print(), llvm::MachineBasicBlock::print(), llvm::MachineOperand::printTargetFlags(), llvm::AArch64FrameLowering::processFunctionBeforeFrameFinalized(), llvm::SwiftErrorValueTracking::propagateVRegs(), llvm::TargetInstrInfo::reassociateOps(), llvm::MachineRegisterInfo::recomputeRegClass(), replaceFI(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::SystemZELFFrameLowering::restoreCalleeSavedRegisters(), llvm::AArch64FrameLowering::restoreCalleeSavedRegisters(), llvm::CSKYFrameLowering::restoreCalleeSavedRegisters(), llvm::MSP430FrameLowering::restoreCalleeSavedRegisters(), llvm::RISCVFrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::LiveIntervals::runOnMachineFunction(), llvm::CFIFixup::runOnMachineFunction(), llvm::ExecutionDomainFix::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::BreakFalseDeps::runOnMachineFunction(), llvm::CSKYAsmPrinter::runOnMachineFunction(), llvm::Mips16RegisterInfo::saveScavengerRegister(), llvm::FunctionLoweringInfo::set(), setCallTargetReg(), llvm::SwiftErrorValueTracking::setFunction(), llvm::MachineIRBuilder::setMF(), llvm::TargetRegisterInfo::shouldRegionSplitForVirtReg(), llvm::MachineBasicBlock::SkipPHIsAndLabels(), llvm::MachineBasicBlock::SkipPHIsLabelsAndDebug(), llvm::SystemZELFFrameLowering::spillCalleeSavedRegisters(), llvm::AArch64FrameLowering::spillCalleeSavedRegisters(), llvm::CSKYFrameLowering::spillCalleeSavedRegisters(), llvm::LoongArchFrameLowering::spillCalleeSavedRegisters(), llvm::MSP430FrameLowering::spillCalleeSavedRegisters(), llvm::RISCVFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), llvm::MachineBasicBlock::SplitCriticalEdge(), UpdateOperandRegClass(), llvm::MachineBasicBlock::updateTerminator(), and llvm::VirtRegAuxInfo::weightCalcHelper().
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getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
Definition at line 135 of file TargetSubtargetInfo.h.
Referenced by llvm::R600InstrInfo::CreateTargetScheduleState(), and llvm::HexagonInstrInfo::CreateTargetScheduleState().
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Definition at line 113 of file TargetSubtargetInfo.h.
Referenced by llvm::InstructionSelect::runOnMachineFunction().
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Definition at line 123 of file TargetSubtargetInfo.h.
Referenced by llvm::MipsRegisterBankInfo::applyMappingImpl(), llvm::machineFunctionIsIllegal(), and llvm::Legalizer::runOnMachineFunction().
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Definition at line 268 of file TargetSubtargetInfo.h.
References llvm::Default.
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Definition at line 252 of file TargetSubtargetInfo.h.
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If the information for the register banks is available, return it.
Otherwise return nullptr.
Definition at line 131 of file TargetSubtargetInfo.h.
Referenced by llvm::RegBankSelect::init(), llvm::X86CallLowering::lowerCall(), and llvm::RegisterBankInfo::InstructionMapping::verify().
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getRegisterInfo - If register information is available, return it.
If not, return null.
Definition at line 127 of file TargetSubtargetInfo.h.
Referenced by llvm::DwarfCompileUnit::addAddress(), llvm::DwarfCompileUnit::addComplexAddress(), addLiveInRegs(), addSavedGPR(), llvm::MachineFunction::allocateRegMask(), llvm::TargetFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(), analyzeCompressibleUses(), llvm::A57ChainingConstraint::apply(), llvm::HexagonSubtarget::CallMutation::apply(), llvm::DebugHandlerBase::beginFunction(), llvm::CodeViewDebug::beginFunctionImpl(), buildAnyextOrCopy(), llvm::AArch64InstrInfo::buildOutlinedFrame(), llvm::HexagonPacketizerList::canPromoteToDotCur(), CC_X86_64_VectorCall(), checkNumAlignedDPRCS2Regs(), computeLiveOuts(), llvm::TargetSchedModel::computeOutputLatency(), llvm::MIRPrinter::convertCallSiteObjects(), llvm::MIRPrinter::convertEntryValueObjects(), llvm::MIRPrinter::convertStackObjects(), llvm::createBURRListDAGScheduler(), llvm::MipsFunctionInfo::createEhDataRegsFI(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::MipsFunctionInfo::createISRRegFI(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::createSourceListDAGScheduler(), createTuple(), llvm::TargetInstrInfo::describeLoadedValue(), llvm::AArch64InstrInfo::describeLoadedValue(), llvm::MipsInstrInfo::describeLoadedValue(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::CSKYFrameLowering::determineCalleeSaves(), llvm::MipsSEFrameLowering::determineCalleeSaves(), llvm::SystemZELFFrameLowering::determineCalleeSaves(), llvm::TargetFrameLowering::determineCalleeSaves(), emitBuildPairF64Pseudo(), emitCalleeSavedRestores(), llvm::DwarfDebug::emitDebugLocValue(), emitDebugValueComment(), llvm::ARMFrameLowering::emitEpilogue(), llvm::MipsAsmPrinter::emitFrameDirective(), emitFrameOffsetAdj(), llvm::AsmPrinter::emitImplicitDef(), llvm::AMDGPUAsmPrinter::emitImplicitDef(), emitKill(), llvm::AArch64FrameLowering::emitPrologue(), llvm::CSKYFrameLowering::emitPrologue(), llvm::XCoreFrameLowering::emitPrologue(), emitSplitF64Pseudo(), emitVFROUND_NOEXCEPT_MASK(), estimateRSStackSizeLimit(), llvm::MachineFrameInfo::estimateStackSize(), llvm::finalizeBundle(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::TargetFrameLowering::getCalleeSaves(), llvm::TargetFrameLowering::getDwarfFrameBase(), llvm::X86FrameLowering::getDwarfFrameBase(), llvm::TargetFrameLowering::getFrameIndexReference(), llvm::CSKYFrameLowering::getFrameIndexReference(), llvm::LoongArchFrameLowering::getFrameIndexReference(), llvm::RISCVFrameLowering::getFrameIndexReference(), llvm::AArch64FrameLowering::getFrameIndexReferencePreferSP(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::PPCRegisterBankInfo::getInstrMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::AVRRegisterInfo::getLargestLegalSuperClass(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), llvm::RISCVInstrInfo::getOutliningTypeImpl(), llvm::MachineFrameInfo::getPristineRegs(), getRegistersForValue(), getRegTy(), llvm::AArch64FrameLowering::getSEHFrameIndexOffset(), llvm::TargetInstrInfo::getStackSlotRange(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), llvm::AArch64FrameLowering::hasFP(), llvm::ARCFrameLowering::hasFP(), llvm::ARMFrameLowering::hasFP(), llvm::CSKYFrameLowering::hasFP(), llvm::LoongArchFrameLowering::hasFP(), llvm::RISCVFrameLowering::hasFP(), llvm::SparcFrameLowering::hasFP(), llvm::VEFrameLowering::hasFP(), llvm::RegPressureTracker::init(), llvm::RegBankSelect::init(), llvm::TailDuplicator::initMF(), insertCSRRestores(), insertCSRSaves(), llvm::LoongArchInstrInfo::insertIndirectBranch(), llvm::RISCVInstrInfo::insertIndirectBranch(), interpretValues(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), isNonFoldablePartialRegisterLoad(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::MipsCallLowering::lowerCall(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::RISCVRegisterInfo::lowerVRELOAD(), llvm::RISCVRegisterInfo::lowerVSPILL(), patchMatchingInput(), llvm::SystemZInstrInfo::prepareCompareSwapOperands(), llvm::MIRPrinter::print(), llvm::PhysicalRegisterUsageInfo::print(), llvm::MachineFunction::print(), llvm::MachineBasicBlock::print(), llvm::AMDGPUAsmPrinter::PrintAsmOperand(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printSavedRegsBitmask(), llvm::ARCFrameLowering::processFunctionBeforeFrameFinalized(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), llvm::TargetInstrInfo::reassociateOps(), reduceDbgValsForwardScan(), replaceFrameIndex(), llvm::ARMFrameLowering::ResolveFrameIndexReference(), llvm::AArch64FrameLowering::resolveFrameOffsetReference(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters(), llvm::LiveIntervals::runOnMachineFunction(), llvm::LiveStacks::runOnMachineFunction(), llvm::ExecutionDomainFix::runOnMachineFunction(), llvm::InstructionSelect::runOnMachineFunction(), llvm::LiveVariables::runOnMachineFunction(), llvm::ReachingDefAnalysis::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::BreakFalseDeps::runOnMachineFunction(), llvm::FunctionLoweringInfo::set(), setAliasRegs(), llvm::X86MachineFunctionInfo::setRestoreBasePointer(), llvm::MIRParserImpl::setupRegisterInfo(), shouldUseFrameHelper(), llvm::Thumb1FrameLowering::spillCalleeSavedRegisters(), llvm::MachineBasicBlock::splitAt(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::X86InstrInfo::unfoldMemoryOperand(), updateLiveIn(), UpdateOperandRegClass(), llvm::RegisterBankInfo::InstructionMapping::verify(), and llvm::VirtRegAuxInfo::weightCalcHelper().
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Definition at line 100 of file TargetSubtargetInfo.h.
Referenced by llvm::SelectionDAG::init().
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Definition at line 258 of file TargetSubtargetInfo.h.
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Definition at line 99 of file TargetSubtargetInfo.h.
Referenced by llvm::CCState::analyzeMustTailForwardedRegisters(), llvm::MachineIRBuilder::buildBoolExtInReg(), llvm::calculateDbgEntityHistory(), llvm::createLibcall(), llvm::createMemLibcall(), llvm::XCoreFrameLowering::emitEpilogue(), llvm::AsmPrinter::emitJumpTableInfo(), llvm::SystemZELFFrameLowering::emitPrologue(), llvm::XCoreFrameLowering::emitPrologue(), llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::MachineIRBuilder::getBoolExtOp(), llvm::SystemZELFRegisters::getCalleeSavedRegs(), llvm::SystemZELFRegisters::getCallPreservedMask(), llvm::AsmPrinter::getCodeViewJumpTableInfo(), getRegistersForValue(), llvm::CombinerHelper::getTargetLowering(), llvm::CCState::HandleByVal(), llvm::SelectionDAG::init(), llvm::GenericScheduler::initPolicy(), interpretValues(), isRegOtherThanSPAndFP(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::MachineBasicBlock::liveout_begin(), llvm::CombinerHelper::matchNotCmp(), llvm::ExpandLargeDivRemPass::run(), llvm::ExpandLargeFpConvertPass::run(), llvm::StackProtector::runOnFunction(), llvm::InstructionSelect::runOnMachineFunction(), llvm::IRTranslator::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::FunctionLoweringInfo::set(), llvm::SwiftErrorValueTracking::setFunction(), TransferTracker::TransferTracker(), and llvm::AArch64GISelUtils::tryEmitBZero().
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True if the register allocator should use the allocation orders exactly as written in the tablegen descriptions, false if it should allocate the specified physical register later if is it callee-saved.
Definition at line 309 of file TargetSubtargetInfo.h.
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Returns true if MI is a dependency breaking instruction for the subtarget.
Similar in behavior to isZeroIdiom
. However, it knows how to identify all dependency breaking instructions (i.e. not just zero-idioms).
As for isZeroIdiom
, this method returns a mask of "broken" dependencies. (See method isZeroIdiom
for a detailed description of Mask).
Definition at line 169 of file TargetSubtargetInfo.h.
References isZeroIdiom(), and MI.
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Returns true if MI is a candidate for move elimination.
A candidate for move elimination may be optimized out at register renaming stage. Subtargets can specify the set of optimizable moves by instantiating tablegen class IsOptimizableRegisterMove
(see llvm/Target/TargetInstrPredicate.td).
SubtargetEmitter is responsible for processing all the definitions of class IsOptimizableRegisterMove, and auto-generate an override for this method.
Definition at line 182 of file TargetSubtargetInfo.h.
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Definition at line 83 of file TargetSubtargetInfo.h.
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Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget.
This function also sets bits in Mask related to input operands that are not in a data dependency relationship. There is one bit for each machine operand; implicit operands follow explicit operands in the bit representation used for Mask. An empty (i.e. a mask with all bits cleared) means: data dependencies are "broken" for all the explicit input machine operands of MI.
Definition at line 158 of file TargetSubtargetInfo.h.
Referenced by isDependencyBreaking().
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This is called after a .mir file was loaded.
Definition at line 60 of file TargetSubtargetInfo.cpp.
Referenced by llvm::MIRParserImpl::initializeMachineFunction().
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Override generic scheduling policy within a region.
This is a convenient way for targets that don't provide any custom scheduling heuristics (no custom MachineSchedStrategy) to make changes to the generic scheduling policy.
Definition at line 228 of file TargetSubtargetInfo.h.
Referenced by llvm::GenericScheduler::initPolicy().
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Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant property.
This may return the ID of another variant SchedClass, but repeated invocation must quickly terminate in a nonvariant SchedClass.
Definition at line 143 of file TargetSubtargetInfo.h.
Referenced by llvm::TargetSchedModel::resolveSchedClass().
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Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
Definition at line 56 of file TargetSubtargetInfo.cpp.
Referenced by addrSinkUsingGEPs(), and llvm::BasicTTIImplBase< T >::useAA().
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Default to DFA for resource management, return false when target will use ProcResource in InstrSchedModel instead.
Definition at line 264 of file TargetSubtargetInfo.h.