Go to the documentation of this file.
29 #define GET_REGINFO_TARGET_DESC
30 #include "SparcGenRegisterInfo.inc"
34 cl::desc(
"Reserve application registers (%g2-%g4)"));
90 if (!Subtarget.
isV9()) {
91 for (
unsigned n = 0;
n != 16; ++
n) {
98 for (
unsigned n = 0;
n < 31;
n++)
106 unsigned Kind)
const {
108 return Subtarget.
is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
113 unsigned FIOperandNum,
int Offset,
unsigned FramePtr) {
118 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr,
false);
119 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(
Offset);
132 BuildMI(*
MI.getParent(), II, dl,
TII.get(SP::SETHIi), SP::G1)
140 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1,
false);
141 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(
LO10(
Offset));
150 BuildMI(*
MI.getParent(), II, dl,
TII.get(SP::SETHIi), SP::G1)
152 BuildMI(*
MI.getParent(), II, dl,
TII.get(SP::XORri), SP::G1)
158 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1,
false);
159 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
165 int SPAdj,
unsigned FIOperandNum,
167 assert(SPAdj == 0 &&
"Unexpected");
171 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
180 Offset +=
MI.getOperand(FIOperandNum + 1).getImm();
183 if (
MI.getOpcode() == SP::STQFri) {
186 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
187 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
192 MI.setDesc(
TII.get(SP::STDFri));
193 MI.getOperand(2).setReg(SrcOddReg);
195 }
else if (
MI.getOpcode() == SP::LDQFri) {
198 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64);
199 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64);
201 BuildMI(*
MI.getParent(), II, dl,
TII.get(SP::LDDFri), DestEvenReg)
205 MI.setDesc(
TII.get(SP::LDDFri));
206 MI.getOperand(0).setReg(DestOddReg);
234 if (getFrameLowering(MF)->hasReservedCallFrame(MF))
static unsigned HI22(int64_t imm)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II, MachineInstr &MI, const DebugLoc &dl, unsigned FIOperandNum, int Offset, unsigned FramePtr)
virtual const TargetInstrInfo * getInstrInfo() const
const uint32_t * getRTCallPreservedMask(CallingConv::ID CC) const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind) const override
static cl::opt< bool > ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false), cl::desc("Reserve application registers (%g2-%g4)"))
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
TargetInstrInfo - Interface to description of machine instruction set.
const HexagonInstrInfo * TII
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
initializer< Ty > init(const Ty &Val)
static unsigned HIX22(int64_t imm)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const SparcInstrInfo * getInstrInfo() const override
bool canRealignStack(const MachineFunction &MF) const override
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Wrapper class representing virtual and physical registers.
Register getFrameRegister(const MachineFunction &MF) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static unsigned LOX10(int64_t imm)
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
static unsigned LO10(int64_t imm)
MCRegAliasIterator enumerates all registers aliasing Reg.