95#define DEBUG_TYPE "x86-disassembler"
97#define debug(s) LLVM_DEBUG(dbgs() << __LINE__ << ": " << s);
122#include "X86GenDisassemblerTables.inc"
130 dec = &
ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
133 dec = &
TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
136 dec = &
THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
139 dec = &
THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
142 dec = &
XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
145 dec = &
XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
148 dec = &
XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
155 dec = &
MAP4_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
158 dec = &
MAP5_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
161 dec = &
MAP6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
164 dec = &
MAP7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
180 return modRMTable[dec->
instructionIDs + ((modRM & 0x38) >> 3) + 8];
182 case MODRM_SPLITMISC:
195 byte = insn->
bytes[offset];
200 auto r = insn->
bytes;
202 if (offset +
sizeof(
T) > r.size())
210 return insn->
mode ==
MODE_64BIT && prefix >= 0x40 && prefix <= 0x4f;
240 if ((
byte == 0xf2 ||
byte == 0xf3) && !
peek(insn,
nextByte)) {
249 if (!(
byte == 0xf3 &&
nextByte == 0x90))
267 if (
peek(insn, nnextByte))
333 if (
isREX(insn,
byte)) {
354 if (
peek(insn, byte2)) {
395 "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
399 }
else if (
byte == 0xc4) {
401 if (
peek(insn, byte1)) {
430 }
else if (
byte == 0xc5) {
432 if (
peek(insn, byte1)) {
462 }
else if (
byte == 0x8f) {
464 if (
peek(insn, byte1)) {
469 if ((byte1 & 0x38) != 0x0)
501 }
else if (
isREX2(insn,
byte)) {
503 if (
peek(insn, byte1)) {
560 sibBaseBase = SIB_BASE_EAX;
564 sibBaseBase = SIB_BASE_RAX;
689 EABase eaBaseBase = EA_BASE_BX_SI;
758 insn->
eaBase = EA_BASE_sib;
781#define GENERIC_FIXUP_FUNC(name, base, prefix) \
782 static uint16_t name(struct InternalInstruction *insn, OperandType type, \
783 uint8_t index, uint8_t *valid) { \
787 debug("Unhandled register type"); \
791 return base + index; \
793 if (insn->rexPrefix && index >= 4 && index <= 7) \
794 return prefix##_SPL + (index - 4); \
796 return prefix##_AL + index; \
798 return prefix##_AX + index; \
800 return prefix##_EAX + index; \
802 return prefix##_RAX + index; \
804 return prefix##_ZMM0 + index; \
806 return prefix##_YMM0 + index; \
808 return prefix##_XMM0 + index; \
812 return prefix##_TMM0 + index; \
813 case TYPE_TMM_PAIR: \
816 return prefix##_TMM0_TMM1 + (index / 2); \
821 return prefix##_K0 + index; \
825 return prefix##_K0_K1 + (index / 2); \
827 return prefix##_MM0 + (index & 0x7); \
828 case TYPE_SEGMENTREG: \
829 if ((index & 7) > 5) \
831 return prefix##_ES + (index & 7); \
832 case TYPE_DEBUGREG: \
835 return prefix##_DR0 + index; \
836 case TYPE_CONTROLREG: \
839 return prefix##_CR0 + index; \
841 return prefix##_XMM0 + index; \
843 return prefix##_YMM0 + index; \
845 return prefix##_ZMM0 + index; \
876 debug(
"Expected a REG or R/M encoding in fixupReg");
886 insn->reg - insn->regBase, &valid);
915 if (insn->eaBase >= insn->eaRegBase) {
916 insn->eaBase = (
EABase)fixupRMValue(
917 insn, (
OperandType)
op->type, insn->eaBase - insn->eaRegBase, &valid);
938 dbgs() <<
format(
"Unhandled mmm field for instruction (0x%hhx)",
967 dbgs() <<
format(
"Unhandled m-mmmm field for instruction (0x%hhx)",
996 dbgs() <<
format(
"Unhandled m-mmmm field for instruction (0x%hhx)",
1018 if (current == 0x0f) {
1020 dbgs() <<
format(
"Found a two-byte escape prefix (0x%hhx)", current));
1024 if (current == 0x38) {
1031 }
else if (current == 0x3a) {
1038 }
else if (current == 0x0f) {
1040 dbgs() <<
format(
"Found a 3dnow escape prefix (0x%hhx)", current));
1068 for (
int i = 0;; i++) {
1069 if (orig[i] ==
'\0' && equiv[i] ==
'\0')
1071 if (orig[i] ==
'\0' || equiv[i] ==
'\0')
1073 if (orig[i] != equiv[i]) {
1074 if ((orig[i] ==
'Q' || orig[i] ==
'L') && equiv[i] ==
'W')
1076 if ((orig[i] ==
'6' || orig[i] ==
'3') && equiv[i] ==
'1')
1078 if ((orig[i] ==
'4' || orig[i] ==
'2') && equiv[i] ==
'6')
1087 for (
int i = 0;; ++i) {
1088 if (
name[i] ==
'\0')
1090 if (
name[i] ==
'6' &&
name[i + 1] ==
'4')
1160 switch (insn->
opcode & 0xfe) {
1333 attrMask &= ~ATTR_ADSIZE;
1338 (insn->
opcode == 0xA1 || (insn->
opcode & 0xf0) == 0x50))
1383 auto SpecName = mii->
getName(instructionIDWithREXW);
1385 if (!
is64Bit(SpecName.data())) {
1447 specName = mii->
getName(instructionID);
1448 specWithOpSizeName = mii->
getName(instructionIDWithOpsize);
1466 uint16_t instructionIDWithNewOpcode;
1489 insn->
spec = specWithNewOpcode;
1514 auto setOpcodeRegister = [&](
unsigned base) {
1523 setOpcodeRegister(MODRM_REG_AL);
1532 setOpcodeRegister(MODRM_REG_AX);
1535 setOpcodeRegister(MODRM_REG_EAX);
1538 setOpcodeRegister(MODRM_REG_RAX);
1615 insn->
vvvv =
static_cast<Reg>(vvvv);
1637 int hasVVVV, needVVVV;
1644 needVVVV = hasVVVV && (insn->
vvvv != 0);
1647 switch (
Op.encoding) {
1655 needVVVV = hasVVVV & ((insn->
vvvv & 0xf) != 0);
1660 if (insn->
eaBase != EA_BASE_sib && insn->
eaBase != EA_BASE_sib64)
1675 debug(
"Unhandled VSIB index type");
1697 if (insn->
eaBase != EA_BASE_sib && insn->
eaBase != EA_BASE_sib64)
1725 if (
Op.type == TYPE_XMM ||
Op.type == TYPE_YMM)
1793 case ENCODING_WRITEMASK:
1800 LLVM_DEBUG(
dbgs() <<
"Encountered an operand with an unknown encoding.");
1840 std::unique_ptr<const MCInstrInfo> MII;
1843 std::unique_ptr<const MCInstrInfo> MII);
1855X86GenericDisassembler::X86GenericDisassembler(
1858 std::unique_ptr<const MCInstrInfo> MII)
1861 if (FB[X86::Is16Bit]) {
1864 }
else if (FB[X86::Is32Bit]) {
1867 }
else if (FB[X86::Is64Bit]) {
1878 CommentStream = &CStream;
1917 Instr.setFlags(Flags);
1932#define ENTRY(x) X86::x,
1936 MCPhysReg llvmRegnum = llvmRegnums[reg];
1958 baseRegNo = insn.
hasAdSize ? X86::ESI : X86::RSI;
1960 baseRegNo = insn.
hasAdSize ? X86::SI : X86::ESI;
1963 baseRegNo = insn.
hasAdSize ? X86::ESI : X86::SI;
1983 baseRegNo = insn.
hasAdSize ? X86::EDI : X86::RDI;
1985 baseRegNo = insn.
hasAdSize ? X86::DI : X86::EDI;
1988 baseRegNo = insn.
hasAdSize ? X86::EDI : X86::DI;
2011 if (type == TYPE_REL) {
2022 if(immediate & 0x80)
2023 immediate |= ~(0xffull);
2026 if(immediate & 0x8000)
2027 immediate |= ~(0xffffull);
2030 if(immediate & 0x80000000)
2031 immediate |= ~(0xffffffffull);
2038 if(immediate & 0x80)
2039 immediate |= ~(0xffull);
2042 if(immediate & 0x8000)
2043 immediate |= ~(0xffffull);
2046 if(immediate & 0x80000000)
2047 immediate |= ~(0xffffffffull);
2052 else if (type == TYPE_IMM) {
2057 if(immediate & 0x80)
2058 immediate |= ~(0xffull);
2061 if(immediate & 0x8000)
2062 immediate |= ~(0xffffull);
2065 if(immediate & 0x80000000)
2066 immediate |= ~(0xffffffffull);
2093 if (type == TYPE_MOFFS) {
2108 if (insn.
eaBase == EA_BASE_sib || insn.
eaBase == EA_BASE_sib64) {
2109 debug(
"A R/M register operand may not have a SIB byte");
2115 debug(
"Unexpected EA base register");
2118 debug(
"EA_BASE_NONE for ModR/M base");
2120#define ENTRY(x) case EA_BASE_##x:
2123 debug(
"A R/M register operand may not have a base; "
2124 "the operand must be a register.");
2128 mcInst.addOperand(MCOperand::createReg(X86::x)); break;
2147 bool ForceSIB =
false) {
2167 if (insn.
eaBase == EA_BASE_sib || insn.
eaBase == EA_BASE_sib64) {
2171 debug(
"Unexpected sibBase");
2174 case SIB_BASE_##x: \
2175 baseReg = MCOperand::createReg(X86::x); break;
2186 debug(
"Unexpected sibIndex");
2189 case SIB_INDEX_##x: \
2190 indexReg = MCOperand::createReg(X86::x); break;
2211 insn.
sibBase != SIB_BASE_R12D && insn.
sibBase != SIB_BASE_R12))) {
2223 debug(
"EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
2260 debug(
"Unexpected eaBase");
2268 baseReg = MCOperand::createReg(X86::x); break;
2271#define ENTRY(x) case EA_REG_##x:
2274 debug(
"A R/M memory operand may not be a register; "
2275 "the base field must be a base.");
2312 switch (operand.
type) {
2314 debug(
"Unexpected type for a R/M operand");
2330 case TYPE_CONTROLREG:
2361 if (maskRegNum >= 8) {
2362 debug(
"Invalid mask register number");
2382 debug(
"Unhandled operand encoding during translation");
2387 case ENCODING_WRITEMASK:
2450 debug(
"Instruction has no specification");
2460 if(mcInst.
getOpcode() == X86::REP_PREFIX)
2462 else if(mcInst.
getOpcode() == X86::REPNE_PREFIX)
2469 if (
Op.encoding != ENCODING_NONE) {
2482 std::unique_ptr<const MCInstrInfo> MII(
T.createMCInstrInfo());
2483 return new X86GenericDisassembler(STI, Ctx, std::move(MII));
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static bool isBranch(unsigned Opcode)
#define LLVM_C_ABI
LLVM_C_ABI is the export/visibility macro used to mark symbols declared in llvm-c as exported when bu...
static uint8_t readOpcode(WasmObjectFile::ReadContext &Ctx)
static int nextByte(ArrayRef< uint8_t > Bytes, uint64_t &Size)
static bool isPrefix(unsigned Opcode, const MCInstrInfo &MCII)
Check if the instruction is a prefix.
#define CASE_ENCODING_VSIB
#define THREEDNOW_MAP_SYM
#define rFromEVEX2of4(evex)
#define lFromEVEX4of4(evex)
#define l2FromEVEX4of4(evex)
#define rFromVEX2of3(vex)
#define zFromEVEX4of4(evex)
#define bFromXOP2of3(xop)
#define xFromVEX2of3(vex)
#define mmmmmFromVEX2of3(vex)
#define rmFromModRM(modRM)
#define bFromEVEX4of4(evex)
#define rFromVEX2of2(vex)
#define ppFromEVEX3of4(evex)
#define v2FromEVEX4of4(evex)
#define modFromModRM(modRM)
#define rFromXOP2of3(xop)
#define lFromXOP3of3(xop)
#define lFromVEX2of2(vex)
#define scFromEVEX4of4(evex)
#define scaleFromSIB(sib)
#define regFromModRM(modRM)
#define b2FromEVEX2of4(evex)
#define vvvvFromVEX2of2(vex)
#define nfFromEVEX4of4(evex)
#define ppFromXOP3of3(xop)
#define vvvvFromVEX3of3(vex)
#define r2FromEVEX2of4(evex)
#define uFromEVEX3of4(evex)
#define xFromXOP2of3(xop)
#define wFromEVEX3of4(evex)
#define bFromVEX2of3(vex)
#define wFromVEX3of3(vex)
#define mmmmmFromXOP2of3(xop)
#define aaaFromEVEX4of4(evex)
#define lFromVEX3of3(vex)
#define mmmFromEVEX2of4(evex)
#define ppFromVEX3of3(vex)
#define bFromEVEX2of4(evex)
#define xFromEVEX2of4(evex)
#define ppFromVEX2of2(vex)
#define indexFromSIB(sib)
#define vvvvFromXOP3of3(xop)
#define wFromXOP3of3(xop)
#define oszcFromEVEX3of4(evex)
#define vvvvFromEVEX3of4(evex)
static void translateRegister(MCInst &mcInst, Reg reg)
translateRegister - Translates an internal register to the appropriate LLVM register,...
static bool isREX2(struct InternalInstruction *insn, uint8_t prefix)
static int getInstructionID(struct InternalInstruction *insn, const MCInstrInfo *mii)
static bool readOpcode(struct InternalInstruction *insn)
static MCDisassembler * createX86Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static bool translateMaskRegister(MCInst &mcInst, uint8_t maskRegNum)
translateMaskRegister - Translates a 3-bit mask register number to LLVM form, and appends it to an MC...
static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn)
translateDstIndex - Appends a destination index operand to an MCInst.
static void translateImmediate(MCInst &mcInst, uint64_t immediate, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateImmediate - Appends an immediate operand to an MCInst.
static int readOperands(struct InternalInstruction *insn)
static void translateFPRegister(MCInst &mcInst, uint8_t stackPos)
translateFPRegister - Translates a stack position on the FPU stack to its LLVM form,...
static bool is64Bit(const char *name)
static const uint8_t segmentRegnums[SEG_OVERRIDE_max]
static int readImmediate(struct InternalInstruction *insn, uint8_t size)
static int getInstructionIDWithAttrMask(uint16_t *instructionID, struct InternalInstruction *insn, uint16_t attrMask)
static int readSIB(struct InternalInstruction *insn)
static bool isREX(struct InternalInstruction *insn, uint8_t prefix)
static int readVVVV(struct InternalInstruction *insn)
static bool isNF(InternalInstruction *insn)
static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn)
translateSrcIndex - Appends a source index operand to an MCInst.
#define GENERIC_FIXUP_FUNC(name, base, prefix)
static int readMaskRegister(struct InternalInstruction *insn)
static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateRM - Translates an operand stored in the R/M (and possibly SIB) byte of an instruction to LL...
static InstrUID decode(OpcodeType type, InstructionContext insnContext, uint8_t opcode, uint8_t modRM)
static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size)
static int readDisplacement(struct InternalInstruction *insn)
static bool isCCMPOrCTEST(InternalInstruction *insn)
LLVM_C_ABI void LLVMInitializeX86Disassembler()
static int fixupReg(struct InternalInstruction *insn, const struct OperandSpecifier *op)
static int readModRM(struct InternalInstruction *insn)
static bool is16BitEquivalent(const char *orig, const char *equiv)
static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis, bool ForceSIB=false)
translateRMMemory - Translates a memory operand stored in the Mod and R/M fields of an internal instr...
static bool translateInstruction(MCInst &target, InternalInstruction &source, const MCDisassembler *Dis)
translateInstruction - Translates an internal instruction and all its operands to an MCInst.
static bool translateRMRegister(MCInst &mcInst, InternalInstruction &insn)
translateRMRegister - Translates a register stored in the R/M field of the ModR/M byte to its LLVM eq...
static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateOperand - Translates an operand stored in an internal instruction to LLVM's format and appen...
static int readPrefixes(struct InternalInstruction *insn)
static bool peek(struct InternalInstruction *insn, uint8_t &byte)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
This class represents an Operation in the Expression.
Container class for subtarget features.
Context object for machine code objects.
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
Interface to description of machine instruction set.
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(MCRegister Reg)
static MCOperand createImm(int64_t Val)
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
StringRef - Represent a constant reference to a string, i.e.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ X86
Windows x64, Windows Itanium (IA-64)
EABase
All possible values of the base field for effective-address computations, a.k.a.
Reg
All possible values of the reg field in the ModR/M byte.
DisassemblerMode
Decoding mode for the Intel disassembler.
SIBBase
All possible values of the SIB base field.
SIBIndex
All possible values of the SIB index field.
NodeAddr< InstrNode * > Instr
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ATTRIBUTE_ALWAYS_INLINE DynamicAPInt mod(const DynamicAPInt &LHS, const DynamicAPInt &RHS)
is always non-negative.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Target & getTheX86_32Target()
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
@ Success
The lock was released successfully.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Target & getTheX86_64Target()
Implement std::hash so that hash_code can be used in STL containers.
OpcodeDecision opcodeDecisions[IC_max]
ModRMDecision modRMDecisions[256]
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
The specification for how to extract and interpret a full instruction and its operands.
The x86 internal instruction, which is produced by the decoder.
ArrayRef< OperandSpecifier > operands
EADisplacement eaDisplacement
uint8_t rex2ExtensionPrefix[2]
uint8_t vectorExtensionPrefix[4]
SegmentOverride segmentOverride
uint8_t numImmediatesConsumed
llvm::ArrayRef< uint8_t > bytes
uint8_t numImmediatesTranslated
const InstructionSpecifier * spec
VectorExtensionType vectorExtensionType
uint8_t displacementOffset
The specification for how to extract and interpret one operand.