93 #define DEBUG_TYPE "x86-disassembler" 97 dbgs() << file <<
":" << line <<
": " << s;
106 #define debug(s) LLVM_DEBUG(Debug(__FILE__, __LINE__, s)); 136 std::unique_ptr<const MCInstrInfo> MII;
139 std::unique_ptr<const MCInstrInfo> MII);
152 X86GenericDisassembler::X86GenericDisassembler(
155 std::unique_ptr<const MCInstrInfo> MII)
158 if (FB[X86::Mode16Bit]) {
161 }
else if (FB[X86::Mode32Bit]) {
164 }
else if (FB[X86::Mode64Bit]) {
187 auto *R =
static_cast<const Region *
>(
Arg);
189 unsigned Index = Address - R->Base;
192 *Byte = Bytes[
Index];
202 static void logger(
void* arg,
const char* log) {
207 vStream << log <<
"\n";
217 CommentStream = &CStream;
222 if (&VStream == &
nulls())
228 LoggerFn, (
void *)&VStream,
229 (
const void *)MII.get(), Address, fMode);
235 Size = InternalInstr.
length;
248 InternalInstr.
opcode != 0x90)
269 #define ENTRY(x) X86::x, 297 uint64_t Address, uint64_t
Offset,
312 const void *Decoder) {
388 if (type == TYPE_REL) {
401 immediate |= ~(0xffull);
404 if(immediate & 0x8000)
405 immediate |= ~(0xffffull);
408 if(immediate & 0x80000000)
409 immediate |= ~(0xffffffffull);
417 immediate |= ~(0xffull);
420 if(immediate & 0x8000)
421 immediate |= ~(0xffffull);
424 if(immediate & 0x80000000)
425 immediate |= ~(0xffffffffull);
430 else if (type == TYPE_IMM) {
436 immediate |= ~(0xffull);
439 if(immediate & 0x8000)
440 immediate |= ~(0xffffull);
443 if(immediate & 0x80000000)
444 immediate |= ~(0xffffffffull);
471 if (type == TYPE_MOFFS) {
486 if (insn.
eaBase == EA_BASE_sib || insn.
eaBase == EA_BASE_sib64) {
487 debug(
"A R/M register operand may not have a SIB byte");
493 debug(
"Unexpected EA base register");
496 debug(
"EA_BASE_NONE for ModR/M base");
498 #define ENTRY(x) case EA_BASE_##x: 501 debug(
"A R/M register operand may not have a base; " 502 "the operand must be a register.");
506 mcInst.addOperand(MCOperand::createReg(X86::x)); break; 543 if (insn.
eaBase == EA_BASE_sib || insn.
eaBase == EA_BASE_sib64) {
547 debug(
"Unexpected sibBase");
551 baseReg = MCOperand::createReg(X86::x); break; 562 debug(
"Unexpected sibIndex");
565 case SIB_INDEX_##x: \ 566 indexReg = MCOperand::createReg(X86::x); break; 598 debug(
"EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
636 debug(
"Unexpected eaBase");
644 baseReg = MCOperand::createReg(X86::x); break; 647 #define ENTRY(x) case EA_REG_##x: 650 debug(
"A R/M memory operand may not be a register; " 651 "the base field must be a base.");
684 switch (operand.
type) {
686 debug(
"Unexpected type for a R/M operand");
700 case TYPE_CONTROLREG:
728 uint8_t maskRegNum) {
729 if (maskRegNum >= 8) {
730 debug(
"Invalid mask register number");
750 debug(
"Unhandled operand encoding during translation");
755 case ENCODING_WRITEMASK:
811 debug(
"Instruction has no specification");
821 if(mcInst.
getOpcode() == X86::REP_PREFIX)
823 else if(mcInst.
getOpcode() == X86::REPNE_PREFIX)
830 if (
Op.encoding != ENCODING_NONE) {
844 return new X86GenericDisassembler(STI, Ctx, std::move(MII));
*ViewGraph Emit a dot run run gv on the postscript file
void(* dlog_t)(void *arg, const char *log)
Type for the logging function that the consumer can provide to get debugging output from the decoder...
This class represents lattice values for constants.
DecodeStatus
Ternary decode status.
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
static void translateImmediate(MCInst &mcInst, uint64_t immediate, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateImmediate - Appends an immediate operand to an MCInst.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static MCOperand createReg(unsigned Reg)
const FeatureBitset & getFeatureBits() const
Reg
All possible values of the reg field in the ModR/M byte.
static bool translateInstruction(MCInst &target, InternalInstruction &source, const MCDisassembler *Dis)
translateInstruction - Translates an internal instruction and all its operands to an MCInst...
static void translateFPRegister(MCInst &mcInst, uint8_t stackPos)
translateFPRegister - Translates a stack position on the FPU stack to its LLVM form, and appends it to an MCInst.
Context object for machine code objects.
static void translateRegister(MCInst &mcInst, Reg reg)
translateRegister - Translates an internal register to the appropriate LLVM register, and appends it as an operand to an MCInst.
uint8_t numImmediatesTranslated
SegmentOverride segmentOverride
static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value, const void *Decoder)
tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateOperand - Translates an operand stored in an internal instruction to LLVM's format and appen...
Instances of this class represent a single low-level machine instruction.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
The specification for how to extract and interpret one operand.
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn)
translateSrcIndex - Appends a source index operand to an MCInst.
Container class for subtarget features.
static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address)
A callback function that wraps the readByte method from Region.
size_t size() const
size - Get the array size.
Interface to description of machine instruction set.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static const uint8_t segmentRegnums[SEG_OVERRIDE_max]
void Debug(const char *file, unsigned line, const char *s)
Print a message to debugs()
The x86 internal instruction, which is produced by the decoder.
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
StringRef GetInstrName(unsigned Opcode, const void *mii)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EADisplacement eaDisplacement
void setFlags(unsigned F)
void setOpcode(unsigned Op)
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateRM - Translates an operand stored in the R/M (and possibly SIB) byte of an instruction to LL...
ArrayRef< OperandSpecifier > operands
const InstructionSpecifier * spec
static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis)
translateRMMemory - Translates a memory operand stored in the Mod and R/M fields of an internal instr...
#define CASE_ENCODING_VSIB
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void LLVMInitializeX86Disassembler()
Target - Wrapper for Target specific information.
uint8_t displacementOffset
static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn)
translateDstIndex - Appends a destination index operand to an MCInst.
static bool translateRMRegister(MCInst &mcInst, InternalInstruction &insn)
translateRMRegister - Translates a register stored in the R/M field of the ModR/M byte to its LLVM eq...
static MCDisassembler * createX86Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Generic base class for all target subtargets.
static void logger(void *arg, const char *log)
logger - a callback function that wraps the operator<< method from raw_ostream.
Target & getTheX86_32Target()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
LLVM Value Representation.
raw_ostream & nulls()
This returns a reference to a raw_ostream which simply discards output.
This class implements an extremely fast bulk output stream that can only output to a stream...
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const MCDisassembler *Dis)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
unsigned getOpcode() const
Instances of this class represent operands of the MCInst class.
Target & getTheX86_64Target()
static MCOperand createImm(int64_t Val)
static bool translateMaskRegister(MCInst &mcInst, uint8_t maskRegNum)
translateMaskRegister - Translates a 3-bit mask register number to LLVM form, and appends it to an MC...
DisassemblerMode
Decoding mode for the Intel disassembler.